MIMXRT1166_cm4.h File Reference

CMSIS Peripheral Access Layer for MIMXRT1166_cm4. More...

#include "core_cm4.h"
#include "system_MIMXRT1166_cm4.h"

Go to the source code of this file.

Data Structures
struct	ADC_Type
struct	ADC_ETC_Type
struct	ANADIG_LDO_SNVS_Type
struct	ANADIG_LDO_SNVS_DIG_Type
struct	ANADIG_MISC_Type
struct	ANADIG_OSC_Type
struct	ANADIG_PLL_Type
struct	ANADIG_PMU_Type
struct	ANADIG_TEMPSENSOR_Type
struct	AOI_Type
struct	ASRC_Type
struct	AUDIO_PLL_Type
struct	CAAM_Type
struct	CAN_Type
struct	CAN_WRAPPER_Type
struct	CCM_Type
struct	CCM_OBS_Type
struct	CDOG_Type
struct	CMP_Type
struct	CSI_Type
struct	DAC_Type
struct	DCDC_Type
struct	DCIC_Type
struct	DMA_Type
struct	DMAMUX_Type
struct	DSI_HOST_Type
struct	DSI_HOST_APB_PKT_IF_Type
struct	DSI_HOST_DPI_INTFC_Type
struct	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type
struct	EMVSIM_Type
struct	ENC_Type
struct	ENET_Type
struct	ETHERNET_PLL_Type
struct	EWM_Type
struct	FLEXIO_Type
struct	FLEXRAM_Type
struct	FLEXSPI_Type
struct	GPC_CPU_MODE_CTRL_Type
struct	GPC_SET_POINT_CTRL_Type
struct	GPC_STBY_CTRL_Type
struct	GPIO_Type
struct	GPT_Type
struct	I2S_Type
struct	IEE_Type
struct	IEE_APC_Type
struct	IOMUXC_Type
struct	IOMUXC_GPR_Type
struct	IOMUXC_LPSR_Type
struct	IOMUXC_LPSR_GPR_Type
struct	IOMUXC_SNVS_Type
struct	IOMUXC_SNVS_GPR_Type
struct	IPS_DOMAIN_Type
struct	KEY_MANAGER_Type
struct	KPP_Type
struct	LCDIF_Type
struct	LCDIFV2_Type
struct	LMEM_Type
struct	LPI2C_Type
struct	LPSPI_Type
struct	LPUART_Type
struct	MCM_Type
struct	MECC_Type
struct	MIPI_CSI2RX_Type
struct	MMCAU_Type
struct	MU_Type
struct	OCOTP_Type
struct	OSC_RC_400M_Type
struct	OTFAD_Type
struct	PDM_Type
struct	PGMC_BPC_Type
struct	PGMC_CPC_Type
struct	PGMC_MIF_Type
struct	PGMC_PPC_Type
struct	PHY_LDO_Type
struct	PIT_Type
struct	PUF_Type
struct	PWM_Type
struct	PXP_Type
struct	RDC_Type
struct	RDC_SEMAPHORE_Type
struct	RTWDOG_Type
struct	SEMA4_Type
struct	SEMC_Type
struct	SNVS_Type
struct	SPDIF_Type
struct	SRAM_Type
struct	SRC_Type
struct	SSARC_HP_Type
struct	SSARC_LP_Type
struct	TMPSNS_Type
struct	TMR_Type
struct	USB_Type
struct	USBHSDCD_Type
struct	USBNC_Type
struct	USBPHY_Type
struct	USDHC_Type
struct	VIDEO_MUX_Type
struct	VIDEO_PLL_Type
struct	VMBANDGAP_Type
struct	WDOG_Type
struct	XBARA_Type
struct	XBARB_Type
struct	XECC_Type
struct	XRDC2_Type

Macros
#define	_MIMXRT1166_CM4_H_
#define	MCU_MEM_MAP_VERSION   0x0000U
#define	MCU_MEM_MAP_VERSION_MINOR   0x0001U
#define	XRDC2_MAKE_MEM(mrc, mrgd)
#define	XRDC2_GET_MRC(mem)
#define	XRDC2_GET_MRGD(mem)
#define	XRDC2_MAKE_PERIPH(pac, pdac)
#define	XRDC2_GET_PAC(periph)
#define	XRDC2_GET_PDAC(periph)
#define	NUMBER_OF_INT_VECTORS   234
#define	__MPU_PRESENT   1
#define	__NVIC_PRIO_BITS   4
#define	__Vendor_SysTickConfig   0
#define	__FPU_PRESENT   1
#define	ADC_TCTRL_COUNT   (8U)
#define	ADC_CMDL_COUNT   (15U)
#define	ADC_CMDH_COUNT   (15U)
#define	ADC_CV_COUNT   (4U)
#define	LPADC1_BASE   (0x40050000u)
#define	LPADC1   ((ADC_Type *)LPADC1_BASE)
#define	LPADC2_BASE   (0x40054000u)
#define	LPADC2   ((ADC_Type *)LPADC2_BASE)
#define	ADC_BASE_ADDRS   { 0u, LPADC1_BASE, LPADC2_BASE }
#define	ADC_BASE_PTRS   { (ADC_Type *)0u, LPADC1, LPADC2 }
#define	ADC_IRQS   { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
#define	ADC_ETC_TRIGn_CTRL_COUNT   (8U)
#define	ADC_ETC_TRIGn_COUNTER_COUNT   (8U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_COUNT   (8U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_COUNT   (8U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_COUNT   (8U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_COUNT   (8U)
#define	ADC_ETC_TRIGn_RESULT_1_0_COUNT   (8U)
#define	ADC_ETC_TRIGn_RESULT_3_2_COUNT   (8U)
#define	ADC_ETC_TRIGn_RESULT_5_4_COUNT   (8U)
#define	ADC_ETC_TRIGn_RESULT_7_6_COUNT   (8U)
#define	ADC_ETC_BASE   (0x40048000u)
#define	ADC_ETC   ((ADC_ETC_Type *)ADC_ETC_BASE)
#define	ADC_ETC_BASE_ADDRS   { ADC_ETC_BASE }
#define	ADC_ETC_BASE_PTRS   { ADC_ETC }
#define	ADC_ETC_IRQS   { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
#define	ADC_ETC_FAULT_IRQS   { ADC_ETC_ERROR_IRQ_IRQn }
#define	ANADIG_LDO_SNVS_BASE   (0x40C84000u)
#define	ANADIG_LDO_SNVS   ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE)
#define	ANADIG_LDO_SNVS_BASE_ADDRS   { ANADIG_LDO_SNVS_BASE }
#define	ANADIG_LDO_SNVS_BASE_PTRS   { ANADIG_LDO_SNVS }
#define	ANADIG_LDO_SNVS_DIG_BASE   (0x40C84000u)
#define	ANADIG_LDO_SNVS_DIG   ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE)
#define	ANADIG_LDO_SNVS_DIG_BASE_ADDRS   { ANADIG_LDO_SNVS_DIG_BASE }
#define	ANADIG_LDO_SNVS_DIG_BASE_PTRS   { ANADIG_LDO_SNVS_DIG }
#define	ANADIG_MISC_BASE   (0x40C84000u)
#define	ANADIG_MISC   ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
#define	ANADIG_MISC_BASE_ADDRS   { ANADIG_MISC_BASE }
#define	ANADIG_MISC_BASE_PTRS   { ANADIG_MISC }
#define	ANADIG_OSC_BASE   (0x40C84000u)
#define	ANADIG_OSC   ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
#define	ANADIG_OSC_BASE_ADDRS   { ANADIG_OSC_BASE }
#define	ANADIG_OSC_BASE_PTRS   { ANADIG_OSC }
#define	ANADIG_PLL_BASE   (0x40C84000u)
#define	ANADIG_PLL   ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
#define	ANADIG_PLL_BASE_ADDRS   { ANADIG_PLL_BASE }
#define	ANADIG_PLL_BASE_PTRS   { ANADIG_PLL }
#define	ANADIG_PMU_BASE   (0x40C84000u)
#define	ANADIG_PMU   ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
#define	ANADIG_PMU_BASE_ADDRS   { ANADIG_PMU_BASE }
#define	ANADIG_PMU_BASE_PTRS   { ANADIG_PMU }
#define	ANADIG_TEMPSENSOR_BASE   (0x40C84000u)
#define	ANADIG_TEMPSENSOR   ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
#define	ANADIG_TEMPSENSOR_BASE_ADDRS   { ANADIG_TEMPSENSOR_BASE }
#define	ANADIG_TEMPSENSOR_BASE_PTRS   { ANADIG_TEMPSENSOR }
#define	AOI_BFCRT01_COUNT   (4U)
#define	AOI_BFCRT23_COUNT   (4U)
#define	AOI1_BASE   (0x400B8000u)
#define	AOI1   ((AOI_Type *)AOI1_BASE)
#define	AOI2_BASE   (0x400BC000u)
#define	AOI2   ((AOI_Type *)AOI2_BASE)
#define	AOI_BASE_ADDRS   { 0u, AOI1_BASE, AOI2_BASE }
#define	AOI_BASE_PTRS   { (AOI_Type *)0u, AOI1, AOI2 }
#define	ASRC_ASRPM_COUNT   (5U)
#define	ASRC_ASRMCR1_COUNT   (3U)
#define	ASRC_BASE   (0x40414000u)
#define	ASRC   ((ASRC_Type *)ASRC_BASE)
#define	ASRC_BASE_ADDRS   { ASRC_BASE }
#define	ASRC_BASE_PTRS   { ASRC }
#define	ASRC_IRQS   { ASRC_IRQn }
#define	AUDIO_PLL_BASE   (0u)
#define	AUDIO_PLL   ((AUDIO_PLL_Type *)AUDIO_PLL_BASE)
#define	AUDIO_PLL_BASE_ADDRS   { AUDIO_PLL_BASE }
#define	AUDIO_PLL_BASE_PTRS   { AUDIO_PLL }
#define	CAAM_JRDID_MS_COUNT   (4U)
#define	CAAM_JRDID_LS_COUNT   (4U)
#define	CAAM_RTIC_DID_COUNT   (4U)
#define	CAAM_DECODID_MS_COUNT   (1U)
#define	CAAM_DECODID_LS_COUNT   (1U)
#define	CAAM_JRSMVBAR_COUNT   (4U)
#define	CAAM_DMA_AIDL_MAP_MS_COUNT   (1U)
#define	CAAM_DMA_AIDL_MAP_LS_COUNT   (1U)
#define	CAAM_DMA_AIDM_MAP_MS_COUNT   (1U)
#define	CAAM_DMA_AIDM_MAP_LS_COUNT   (1U)
#define	CAAM_MPPKR_COUNT   (64U)
#define	CAAM_MPMR_COUNT   (32U)
#define	CAAM_MPTESTR_COUNT   (32U)
#define	CAAM_JDKEKR_COUNT   (8U)
#define	CAAM_TDKEKR_COUNT   (8U)
#define	CAAM_TDSKR_COUNT   (8U)
#define	CAAM_RTENT_COUNT   (16U)
#define	CAAM_PX_SDID_PG0_COUNT   (16U)
#define	CAAM_PX_SMAPR_PG0_COUNT   (16U)
#define	CAAM_PX_SMAG2_PG0_COUNT   (16U)
#define	CAAM_PX_SMAG1_PG0_COUNT   (16U)
#define	CAAM_SMWPJRR_COUNT   (4U)
#define	CAAM_HT_JD_ADDR_COUNT   (1U)
#define	CAAM_HT_SD_ADDR_COUNT   (1U)
#define	CAAM_HT_JQ_CTRL_MS_COUNT   (1U)
#define	CAAM_HT_JQ_CTRL_LS_COUNT   (1U)
#define	CAAM_HT_STATUS_COUNT   (1U)
#define	CAAM_JRJDDA_COUNT   (1U)
#define	CAAM_IRBAR_JR_COUNT   (4U)
#define	CAAM_IRSR_JR_COUNT   (4U)
#define	CAAM_IRSAR_JR_COUNT   (4U)
#define	CAAM_IRJAR_JR_COUNT   (4U)
#define	CAAM_ORBAR_JR_COUNT   (4U)
#define	CAAM_ORSR_JR_COUNT   (4U)
#define	CAAM_ORJRR_JR_COUNT   (4U)
#define	CAAM_ORSFR_JR_COUNT   (4U)
#define	CAAM_JRSTAR_JR_COUNT   (4U)
#define	CAAM_JRINTR_JR_COUNT   (4U)
#define	CAAM_JRCFGR_JR_MS_COUNT   (4U)
#define	CAAM_JRCFGR_JR_LS_COUNT   (4U)
#define	CAAM_IRRIR_JR_COUNT   (4U)
#define	CAAM_ORWIR_JR_COUNT   (4U)
#define	CAAM_JRCR_JR_COUNT   (4U)
#define	CAAM_JRAAV_COUNT   (4U)
#define	CAAM_JRAAA_COUNT   (4U)
#define	CAAM_JRAAA_COUNT2   (4U)
#define	CAAM_PX_SDID_JR_COUNT   (4U)
#define	CAAM_PX_SDID_JR_COUNT2   (16U)
#define	CAAM_PX_SMAPR_JR_COUNT   (4U)
#define	CAAM_PX_SMAPR_JR_COUNT2   (16U)
#define	CAAM_PX_SMAG2_JR_COUNT   (4U)
#define	CAAM_PX_SMAG2_JR_COUNT2   (16U)
#define	CAAM_PX_SMAG1_JR_COUNT   (4U)
#define	CAAM_PX_SMAG1_JR_COUNT2   (16U)
#define	CAAM_SMCR_JR_COUNT   (4U)
#define	CAAM_SMCSR_JR_COUNT   (4U)
#define	CAAM_REIR0JR_COUNT   (4U)
#define	CAAM_REIR2JR_COUNT   (4U)
#define	CAAM_REIR4JR_COUNT   (4U)
#define	CAAM_REIR5JR_COUNT   (4U)
#define	CAAM_RMA_COUNT   (4U)
#define	CAAM_RMA_COUNT2   (2U)
#define	CAAM_RML_COUNT   (4U)
#define	CAAM_RML_COUNT2   (2U)
#define	CAAM_RMD_COUNT   (4U)
#define	CAAM_RMD_COUNT2   (2U)
#define	CAAM_RMD_COUNT3   (32U)
#define	CAAM_CC1MR_COUNT   (1U)
#define	CAAM_CC1MR_PK_COUNT   (1U)
#define	CAAM_CC1MR_RNG_COUNT   (1U)
#define	CAAM_CC1KSR_COUNT   (1U)
#define	CAAM_CC1DSR_COUNT   (1U)
#define	CAAM_CC1ICVSR_COUNT   (1U)
#define	CAAM_CCCTRL_COUNT   (1U)
#define	CAAM_CICTL_COUNT   (1U)
#define	CAAM_CCWR_COUNT   (1U)
#define	CAAM_CCSTA_MS_COUNT   (1U)
#define	CAAM_CCSTA_LS_COUNT   (1U)
#define	CAAM_CC1AADSZR_COUNT   (1U)
#define	CAAM_CC1IVSZR_COUNT   (1U)
#define	CAAM_CPKASZR_COUNT   (1U)
#define	CAAM_CPKBSZR_COUNT   (1U)
#define	CAAM_CPKNSZR_COUNT   (1U)
#define	CAAM_CPKESZR_COUNT   (1U)
#define	CAAM_CC1CTXR_COUNT   (1U)
#define	CAAM_CC1CTXR_COUNT2   (16U)
#define	CAAM_CC1KR_COUNT   (1U)
#define	CAAM_CC1KR_COUNT2   (8U)
#define	CAAM_CC2MR_COUNT   (1U)
#define	CAAM_CC2KSR_COUNT   (1U)
#define	CAAM_CC2DSR_COUNT   (1U)
#define	CAAM_CC2ICVSZR_COUNT   (1U)
#define	CAAM_CC2CTXR_COUNT   (1U)
#define	CAAM_CC2CTXR_COUNT2   (18U)
#define	CAAM_CC2KEYR_COUNT   (1U)
#define	CAAM_CC2KEYR_COUNT2   (32U)
#define	CAAM_CFIFOSTA_COUNT   (1U)
#define	CAAM_CNFIFO_COUNT   (1U)
#define	CAAM_CNFIFO_2_COUNT   (1U)
#define	CAAM_CIFIFO_COUNT   (1U)
#define	CAAM_COFIFO_COUNT   (1U)
#define	CAAM_DJQCR_MS_COUNT   (1U)
#define	CAAM_DJQCR_LS_COUNT   (1U)
#define	CAAM_DDAR_COUNT   (1U)
#define	CAAM_DOPSTA_MS_COUNT   (1U)
#define	CAAM_DOPSTA_LS_COUNT   (1U)
#define	CAAM_DPDIDSR_COUNT   (1U)
#define	CAAM_DODIDSR_COUNT   (1U)
#define	CAAM_DMTH_MS_COUNT   (1U)
#define	CAAM_DMTH_MS_COUNT2   (4U)
#define	CAAM_DMTH_LS_COUNT   (1U)
#define	CAAM_DMTH_LS_COUNT2   (4U)
#define	CAAM_DGTR_0_COUNT   (1U)
#define	CAAM_DGTR_0_COUNT2   (1U)
#define	CAAM_DGTR_1_COUNT   (1U)
#define	CAAM_DGTR_1_COUNT2   (1U)
#define	CAAM_DGTR_2_COUNT   (1U)
#define	CAAM_DGTR_2_COUNT2   (1U)
#define	CAAM_DGTR_3_COUNT   (1U)
#define	CAAM_DGTR_3_COUNT2   (1U)
#define	CAAM_DSTR_0_COUNT   (1U)
#define	CAAM_DSTR_0_COUNT2   (1U)
#define	CAAM_DSTR_1_COUNT   (1U)
#define	CAAM_DSTR_1_COUNT2   (1U)
#define	CAAM_DSTR_2_COUNT   (1U)
#define	CAAM_DSTR_2_COUNT2   (1U)
#define	CAAM_DSTR_3_COUNT   (1U)
#define	CAAM_DSTR_3_COUNT2   (1U)
#define	CAAM_DDESB_COUNT   (1U)
#define	CAAM_DDESB_COUNT2   (64U)
#define	CAAM_DDJR_COUNT   (1U)
#define	CAAM_DDDR_COUNT   (1U)
#define	CAAM_DDJP_COUNT   (1U)
#define	CAAM_DSDP_COUNT   (1U)
#define	CAAM_DDDR_MS_COUNT   (1U)
#define	CAAM_DDDR_LS_COUNT   (1U)
#define	CAAM_SOL_COUNT   (1U)
#define	CAAM_VSOL_COUNT   (1U)
#define	CAAM_SIL_COUNT   (1U)
#define	CAAM_VSIL_COUNT   (1U)
#define	CAAM_DPOVRD_COUNT   (1U)
#define	CAAM_UVSOL_COUNT   (1U)
#define	CAAM_UVSIL_COUNT   (1U)
#define	CAAM_BASE   (0x40440000u)
#define	CAAM   ((CAAM_Type *)CAAM_BASE)
#define	CAAM_BASE_ADDRS   { CAAM_BASE }
#define	CAAM_BASE_PTRS   { CAAM }
#define	CAN_CS_COUNT_MB8B   (64U)
#define	CAN_ID_COUNT_MB8B   (64U)
#define	CAN_WORD_COUNT_MB8B   (64U)
#define	CAN_WORD_COUNT_MB8B2   (2U)
#define	CAN_CS_COUNT_MB16B_L   (21U)
#define	CAN_ID_COUNT_MB16B_L   (21U)
#define	CAN_WORD_COUNT_MB16B_L   (21U)
#define	CAN_WORD_COUNT_MB16B_L2   (4U)
#define	CAN_CS_COUNT_MB16B_H   (21U)
#define	CAN_ID_COUNT_MB16B_H   (21U)
#define	CAN_WORD_COUNT_MB16B_H   (21U)
#define	CAN_WORD_COUNT_MB16B_H2   (4U)
#define	CAN_CS_COUNT_MB32B_L   (12U)
#define	CAN_ID_COUNT_MB32B_L   (12U)
#define	CAN_WORD_COUNT_MB32B_L   (12U)
#define	CAN_WORD_COUNT_MB32B_L2   (8U)
#define	CAN_CS_COUNT_MB32B_H   (12U)
#define	CAN_ID_COUNT_MB32B_H   (12U)
#define	CAN_WORD_COUNT_MB32B_H   (12U)
#define	CAN_WORD_COUNT_MB32B_H2   (8U)
#define	CAN_CS_COUNT_MB64B_L   (7U)
#define	CAN_ID_COUNT_MB64B_L   (7U)
#define	CAN_WORD_COUNT_MB64B_L   (7U)
#define	CAN_WORD_COUNT_MB64B_L2   (16U)
#define	CAN_CS_COUNT_MB64B_H   (7U)
#define	CAN_ID_COUNT_MB64B_H   (7U)
#define	CAN_WORD_COUNT_MB64B_H   (7U)
#define	CAN_WORD_COUNT_MB64B_H2   (16U)
#define	CAN_CS_COUNT   (64U)
#define	CAN_ID_COUNT   (64U)
#define	CAN_WORD0_COUNT   (64U)
#define	CAN_WORD1_COUNT   (64U)
#define	CAN_RXIMR_COUNT   (64U)
#define	CAN1_BASE   (0x400C4000u)
#define	CAN1   ((CAN_Type *)CAN1_BASE)
#define	CAN2_BASE   (0x400C8000u)
#define	CAN2   ((CAN_Type *)CAN2_BASE)
#define	CAN3_BASE   (0x40C3C000u)
#define	CAN3   ((CAN_Type *)CAN3_BASE)
#define	CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
#define	CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
#define	CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Tx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Wake_Up_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Error_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Bus_Off_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_ORed_Message_buffer_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN1_WRAPPER_BASE   (0x400C4000u)
#define	CAN1_WRAPPER   ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE)
#define	CAN2_WRAPPER_BASE   (0x400C8000u)
#define	CAN2_WRAPPER   ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE)
#define	CAN3_WRAPPER_BASE   (0x40C3C000u)
#define	CAN3_WRAPPER   ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE)
#define	CAN_WRAPPER_BASE_ADDRS   { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE }
#define	CAN_WRAPPER_BASE_PTRS   { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER }
#define	CCM_CLOCK_ROOT_CONTROL_COUNT   (79U)
#define	CCM_CLOCK_ROOT_CONTROL_SET_COUNT   (79U)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_COUNT   (79U)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_COUNT   (79U)
#define	CCM_CLOCK_ROOT_STATUS0_COUNT   (79U)
#define	CCM_CLOCK_ROOT_STATUS1_COUNT   (79U)
#define	CCM_CLOCK_ROOT_CONFIG_COUNT   (79U)
#define	CCM_CLOCK_ROOT_AUTHEN_COUNT   (79U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_COUNT   (79U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT   (79U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT   (79U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT   (79U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2   (16U)
#define	CCM_CLOCK_GROUP_CONTROL_COUNT   (2U)
#define	CCM_CLOCK_GROUP_CONTROL_SET_COUNT   (2U)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_COUNT   (2U)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_COUNT   (2U)
#define	CCM_CLOCK_GROUP_STATUS0_COUNT   (2U)
#define	CCM_CLOCK_GROUP_STATUS1_COUNT   (2U)
#define	CCM_CLOCK_GROUP_CONFIG_COUNT   (2U)
#define	CCM_CLOCK_GROUP_AUTHEN_COUNT   (2U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_COUNT   (2U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT   (2U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT   (2U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT   (2U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2   (16U)
#define	CCM_GPR_SHARED_COUNT   (8U)
#define	CCM_GPR_SHARED_SET_COUNT   (8U)
#define	CCM_GPR_SHARED_CLR_COUNT   (8U)
#define	CCM_GPR_SHARED_TOG_COUNT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_COUNT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_SET_COUNT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_COUNT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_COUNT   (8U)
#define	CCM_OSCPLL_DIRECT_COUNT   (29U)
#define	CCM_OSCPLL_DOMAIN_COUNT   (29U)
#define	CCM_OSCPLL_SETPOINT_COUNT   (29U)
#define	CCM_OSCPLL_STATUS0_COUNT   (29U)
#define	CCM_OSCPLL_STATUS1_COUNT   (29U)
#define	CCM_OSCPLL_CONFIG_COUNT   (29U)
#define	CCM_OSCPLL_AUTHEN_COUNT   (29U)
#define	CCM_LPCG_DIRECT_COUNT   (138U)
#define	CCM_LPCG_DOMAIN_COUNT   (138U)
#define	CCM_LPCG_SETPOINT_COUNT   (138U)
#define	CCM_LPCG_STATUS0_COUNT   (138U)
#define	CCM_LPCG_STATUS1_COUNT   (138U)
#define	CCM_LPCG_CONFIG_COUNT   (138U)
#define	CCM_LPCG_AUTHEN_COUNT   (138U)
#define	CCM_BASE   (0x40CC0000u)
#define	CCM   ((CCM_Type *)CCM_BASE)
#define	CCM_BASE_ADDRS   { CCM_BASE }
#define	CCM_BASE_PTRS   { CCM }
#define	CCM_OBS_OBSERVE_CONTROL_COUNT   (6U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_COUNT   (6U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_COUNT   (6U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_COUNT   (6U)
#define	CCM_OBS_OBSERVE_STATUS0_COUNT   (6U)
#define	CCM_OBS_OBSERVE_AUTHEN_COUNT   (6U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_COUNT   (6U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT   (6U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT   (6U)
#define	CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT   (6U)
#define	CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT   (6U)
#define	CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT   (6U)
#define	CCM_OBS_BASE   (0x40150000u)
#define	CCM_OBS   ((CCM_OBS_Type *)CCM_OBS_BASE)
#define	CCM_OBS_BASE_ADDRS   { CCM_OBS_BASE }
#define	CCM_OBS_BASE_PTRS   { CCM_OBS }
#define	CDOG_BASE   (0x41900000u)
#define	CDOG   ((CDOG_Type *)CDOG_BASE)
#define	CDOG_BASE_ADDRS   { CDOG_BASE }
#define	CDOG_BASE_PTRS   { CDOG }
#define	CMP1_BASE   (0x401A4000u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x401A8000u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP3_BASE   (0x401AC000u)
#define	CMP3   ((CMP_Type *)CMP3_BASE)
#define	CMP4_BASE   (0x401B0000u)
#define	CMP4   ((CMP_Type *)CMP4_BASE)
#define	CMP_BASE_ADDRS   { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
#define	CMP_BASE_PTRS   { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
#define	CMP_IRQS   { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
#define	CSI_CR_COUNT   (256U)
#define	CSI_BASE   (0x40800000u)
#define	CSI   ((CSI_Type *)CSI_BASE)
#define	CSI_BASE_ADDRS   { CSI_BASE }
#define	CSI_BASE_PTRS   { CSI }
#define	CSI_IRQS   { CSI_IRQn }
#define	CSI_CSICR1_PIXEL_BIT_MASK   CSI_CR1_PIXEL_BIT_MASK
#define	CSI_CSICR1_PIXEL_BIT_SHIFT   CSI_CR1_PIXEL_BIT_SHIFT
#define	CSI_CSICR1_PIXEL_BIT(x)
#define	CSI_CSICR1_REDGE_MASK   CSI_CR1_REDGE_MASK
#define	CSI_CSICR1_REDGE_SHIFT   CSI_CR1_REDGE_SHIFT
#define	CSI_CSICR1_REDGE(x)
#define	CSI_CSICR1_INV_PCLK_MASK   CSI_CR1_INV_PCLK_MASK
#define	CSI_CSICR1_INV_PCLK_SHIFT   CSI_CR1_INV_PCLK_SHIFT
#define	CSI_CSICR1_INV_PCLK(x)
#define	CSI_CSICR1_INV_DATA_MASK   CSI_CR1_INV_DATA_MASK
#define	CSI_CSICR1_INV_DATA_SHIFT   CSI_CR1_INV_DATA_SHIFT
#define	CSI_CSICR1_INV_DATA(x)
#define	CSI_CSICR1_GCLK_MODE_MASK   CSI_CR1_GCLK_MODE_MASK
#define	CSI_CSICR1_GCLK_MODE_SHIFT   CSI_CR1_GCLK_MODE_SHIFT
#define	CSI_CSICR1_GCLK_MODE(x)
#define	CSI_CSICR1_CLR_RXFIFO_MASK   CSI_CR1_CLR_RXFIFO_MASK
#define	CSI_CSICR1_CLR_RXFIFO_SHIFT   CSI_CR1_CLR_RXFIFO_SHIFT
#define	CSI_CSICR1_CLR_RXFIFO(x)
#define	CSI_CSICR1_CLR_STATFIFO_MASK   CSI_CR1_CLR_STATFIFO_MASK
#define	CSI_CSICR1_CLR_STATFIFO_SHIFT   CSI_CR1_CLR_STATFIFO_SHIFT
#define	CSI_CSICR1_CLR_STATFIFO(x)
#define	CSI_CSICR1_PACK_DIR_MASK   CSI_CR1_PACK_DIR_MASK
#define	CSI_CSICR1_PACK_DIR_SHIFT   CSI_CR1_PACK_DIR_SHIFT
#define	CSI_CSICR1_PACK_DIR(x)
#define	CSI_CSICR1_FCC_MASK   CSI_CR1_FCC_MASK
#define	CSI_CSICR1_FCC_SHIFT   CSI_CR1_FCC_SHIFT
#define	CSI_CSICR1_FCC(x)
#define	CSI_CSICR1_CCIR_EN_MASK   CSI_CR1_CCIR_EN_MASK
#define	CSI_CSICR1_CCIR_EN_SHIFT   CSI_CR1_CCIR_EN_SHIFT
#define	CSI_CSICR1_CCIR_EN(x)
#define	CSI_CSICR1_HSYNC_POL_MASK   CSI_CR1_HSYNC_POL_MASK
#define	CSI_CSICR1_HSYNC_POL_SHIFT   CSI_CR1_HSYNC_POL_SHIFT
#define	CSI_CSICR1_HSYNC_POL(x)
#define	CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK   CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK
#define	CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT   CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT
#define	CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x)
#define	CSI_CSICR1_SOF_INTEN_MASK   CSI_CR1_SOF_INTEN_MASK
#define	CSI_CSICR1_SOF_INTEN_SHIFT   CSI_CR1_SOF_INTEN_SHIFT
#define	CSI_CSICR1_SOF_INTEN(x)
#define	CSI_CSICR1_SOF_POL_MASK   CSI_CR1_SOF_POL_MASK
#define	CSI_CSICR1_SOF_POL_SHIFT   CSI_CR1_SOF_POL_SHIFT
#define	CSI_CSICR1_SOF_POL(x)
#define	CSI_CSICR1_RXFF_INTEN_MASK   CSI_CR1_RXFF_INTEN_MASK
#define	CSI_CSICR1_RXFF_INTEN_SHIFT   CSI_CR1_RXFF_INTEN_SHIFT
#define	CSI_CSICR1_RXFF_INTEN(x)
#define	CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK   CSI_CR1_FB1_DMA_DONE_INTEN_MASK
#define	CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT   CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT
#define	CSI_CSICR1_FB1_DMA_DONE_INTEN(x)
#define	CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK   CSI_CR1_FB2_DMA_DONE_INTEN_MASK
#define	CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT   CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT
#define	CSI_CSICR1_FB2_DMA_DONE_INTEN(x)
#define	CSI_CSICR1_STATFF_INTEN_MASK   CSI_CR1_STATFF_INTEN_MASK
#define	CSI_CSICR1_STATFF_INTEN_SHIFT   CSI_CR1_STATFF_INTEN_SHIFT
#define	CSI_CSICR1_STATFF_INTEN(x)
#define	CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK   CSI_CR1_SFF_DMA_DONE_INTEN_MASK
#define	CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT   CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT
#define	CSI_CSICR1_SFF_DMA_DONE_INTEN(x)
#define	CSI_CSICR1_RF_OR_INTEN_MASK   CSI_CR1_RF_OR_INTEN_MASK
#define	CSI_CSICR1_RF_OR_INTEN_SHIFT   CSI_CR1_RF_OR_INTEN_SHIFT
#define	CSI_CSICR1_RF_OR_INTEN(x)
#define	CSI_CSICR1_SF_OR_INTEN_MASK   CSI_CR1_SF_OR_INTEN_MASK
#define	CSI_CSICR1_SF_OR_INTEN_SHIFT   CSI_CR1_SF_OR_INTEN_SHIFT
#define	CSI_CSICR1_SF_OR_INTEN(x)
#define	CSI_CSICR1_COF_INT_EN_MASK   CSI_CR1_COF_INT_EN_MASK
#define	CSI_CSICR1_COF_INT_EN_SHIFT   CSI_CR1_COF_INT_EN_SHIFT
#define	CSI_CSICR1_COF_INT_EN(x)
#define	CSI_CSICR1_VIDEO_MODE_MASK   CSI_CR1_VIDEO_MODE_MASK
#define	CSI_CSICR1_VIDEO_MODE_SHIFT   CSI_CR1_VIDEO_MODE_SHIFT
#define	CSI_CSICR1_VIDEO_MODE(x)
#define	CSI_CSICR1_EOF_INT_EN_MASK   CSI_CR1_EOF_INT_EN_MASK
#define	CSI_CSICR1_EOF_INT_EN_SHIFT   CSI_CR1_EOF_INT_EN_SHIFT
#define	CSI_CSICR1_EOF_INT_EN(x)
#define	CSI_CSICR1_EXT_VSYNC_MASK   CSI_CR1_EXT_VSYNC_MASK
#define	CSI_CSICR1_EXT_VSYNC_SHIFT   CSI_CR1_EXT_VSYNC_SHIFT
#define	CSI_CSICR1_EXT_VSYNC(x)
#define	CSI_CSICR1_SWAP16_EN_MASK   CSI_CR1_SWAP16_EN_MASK
#define	CSI_CSICR1_SWAP16_EN_SHIFT   CSI_CR1_SWAP16_EN_SHIFT
#define	CSI_CSICR1_SWAP16_EN(x)
#define	CSI_CSICR2_HSC_MASK   CSI_CR2_HSC_MASK
#define	CSI_CSICR2_HSC_SHIFT   CSI_CR2_HSC_SHIFT
#define	CSI_CSICR2_HSC(x)
#define	CSI_CSICR2_VSC_MASK   CSI_CR2_VSC_MASK
#define	CSI_CSICR2_VSC_SHIFT   CSI_CR2_VSC_SHIFT
#define	CSI_CSICR2_VSC(x)
#define	CSI_CSICR2_LVRM_MASK   CSI_CR2_LVRM_MASK
#define	CSI_CSICR2_LVRM_SHIFT   CSI_CR2_LVRM_SHIFT
#define	CSI_CSICR2_LVRM(x)
#define	CSI_CSICR2_BTS_MASK   CSI_CR2_BTS_MASK
#define	CSI_CSICR2_BTS_SHIFT   CSI_CR2_BTS_SHIFT
#define	CSI_CSICR2_BTS(x)
#define	CSI_CSICR2_SCE_MASK   CSI_CR2_SCE_MASK
#define	CSI_CSICR2_SCE_SHIFT   CSI_CR2_SCE_SHIFT
#define	CSI_CSICR2_SCE(x)
#define	CSI_CSICR2_AFS_MASK   CSI_CR2_AFS_MASK
#define	CSI_CSICR2_AFS_SHIFT   CSI_CR2_AFS_SHIFT
#define	CSI_CSICR2_AFS(x)
#define	CSI_CSICR2_DRM_MASK   CSI_CR2_DRM_MASK
#define	CSI_CSICR2_DRM_SHIFT   CSI_CR2_DRM_SHIFT
#define	CSI_CSICR2_DRM(x)
#define	CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK   CSI_CR2_DMA_BURST_TYPE_SFF_MASK
#define	CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT   CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT
#define	CSI_CSICR2_DMA_BURST_TYPE_SFF(x)
#define	CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK   CSI_CR2_DMA_BURST_TYPE_RFF_MASK
#define	CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT   CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT
#define	CSI_CSICR2_DMA_BURST_TYPE_RFF(x)
#define	CSI_CSICR3_ECC_AUTO_EN_MASK   CSI_CR3_ECC_AUTO_EN_MASK
#define	CSI_CSICR3_ECC_AUTO_EN_SHIFT   CSI_CR3_ECC_AUTO_EN_SHIFT
#define	CSI_CSICR3_ECC_AUTO_EN(x)
#define	CSI_CSICR3_ECC_INT_EN_MASK   CSI_CR3_ECC_INT_EN_MASK
#define	CSI_CSICR3_ECC_INT_EN_SHIFT   CSI_CR3_ECC_INT_EN_SHIFT
#define	CSI_CSICR3_ECC_INT_EN(x)
#define	CSI_CSICR3_ZERO_PACK_EN_MASK   CSI_CR3_ZERO_PACK_EN_MASK
#define	CSI_CSICR3_ZERO_PACK_EN_SHIFT   CSI_CR3_ZERO_PACK_EN_SHIFT
#define	CSI_CSICR3_ZERO_PACK_EN(x)
#define	CSI_CSICR3_SENSOR_16BITS_MASK   CSI_CR3_SENSOR_16BITS_MASK
#define	CSI_CSICR3_SENSOR_16BITS_SHIFT   CSI_CR3_SENSOR_16BITS_SHIFT
#define	CSI_CSICR3_SENSOR_16BITS(x)
#define	CSI_CSICR3_RxFF_LEVEL_MASK   CSI_CR3_RxFF_LEVEL_MASK
#define	CSI_CSICR3_RxFF_LEVEL_SHIFT   CSI_CR3_RxFF_LEVEL_SHIFT
#define	CSI_CSICR3_RxFF_LEVEL(x)
#define	CSI_CSICR3_HRESP_ERR_EN_MASK   CSI_CR3_HRESP_ERR_EN_MASK
#define	CSI_CSICR3_HRESP_ERR_EN_SHIFT   CSI_CR3_HRESP_ERR_EN_SHIFT
#define	CSI_CSICR3_HRESP_ERR_EN(x)
#define	CSI_CSICR3_STATFF_LEVEL_MASK   CSI_CR3_STATFF_LEVEL_MASK
#define	CSI_CSICR3_STATFF_LEVEL_SHIFT   CSI_CR3_STATFF_LEVEL_SHIFT
#define	CSI_CSICR3_STATFF_LEVEL(x)
#define	CSI_CSICR3_DMA_REQ_EN_SFF_MASK   CSI_CR3_DMA_REQ_EN_SFF_MASK
#define	CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT   CSI_CR3_DMA_REQ_EN_SFF_SHIFT
#define	CSI_CSICR3_DMA_REQ_EN_SFF(x)
#define	CSI_CSICR3_DMA_REQ_EN_RFF_MASK   CSI_CR3_DMA_REQ_EN_RFF_MASK
#define	CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT   CSI_CR3_DMA_REQ_EN_RFF_SHIFT
#define	CSI_CSICR3_DMA_REQ_EN_RFF(x)
#define	CSI_CSICR3_DMA_REFLASH_SFF_MASK   CSI_CR3_DMA_REFLASH_SFF_MASK
#define	CSI_CSICR3_DMA_REFLASH_SFF_SHIFT   CSI_CR3_DMA_REFLASH_SFF_SHIFT
#define	CSI_CSICR3_DMA_REFLASH_SFF(x)
#define	CSI_CSICR3_DMA_REFLASH_RFF_MASK   CSI_CR3_DMA_REFLASH_RFF_MASK
#define	CSI_CSICR3_DMA_REFLASH_RFF_SHIFT   CSI_CR3_DMA_REFLASH_RFF_SHIFT
#define	CSI_CSICR3_DMA_REFLASH_RFF(x)
#define	CSI_CSICR3_FRMCNT_RST_MASK   CSI_CR3_FRMCNT_RST_MASK
#define	CSI_CSICR3_FRMCNT_RST_SHIFT   CSI_CR3_FRMCNT_RST_SHIFT
#define	CSI_CSICR3_FRMCNT_RST(x)
#define	CSI_CSICR3_FRMCNT_MASK   CSI_CR3_FRMCNT_MASK
#define	CSI_CSICR3_FRMCNT_SHIFT   CSI_CR3_FRMCNT_SHIFT
#define	CSI_CSICR3_FRMCNT(x)
#define	CSI_CSISTATFIFO_STAT_MASK   CSI_STATFIFO_STAT_MASK
#define	CSI_CSISTATFIFO_STAT_SHIFT   CSI_STATFIFO_STAT_SHIFT
#define	CSI_CSISTATFIFO_STAT(x)
#define	CSI_CSIRFIFO_IMAGE_MASK   CSI_RFIFO_IMAGE_MASK
#define	CSI_CSIRFIFO_IMAGE_SHIFT   CSI_RFIFO_IMAGE_SHIFT
#define	CSI_CSIRFIFO_IMAGE(x)
#define	CSI_CSIRXCNT_RXCNT_MASK   CSI_RXCNT_RXCNT_MASK
#define	CSI_CSIRXCNT_RXCNT_SHIFT   CSI_RXCNT_RXCNT_SHIFT
#define	CSI_CSIRXCNT_RXCNT(x)
#define	CSI_CSISR_DRDY_MASK   CSI_SR_DRDY_MASK
#define	CSI_CSISR_DRDY_SHIFT   CSI_SR_DRDY_SHIFT
#define	CSI_CSISR_DRDY(x)
#define	CSI_CSISR_ECC_INT_MASK   CSI_SR_ECC_INT_MASK
#define	CSI_CSISR_ECC_INT_SHIFT   CSI_SR_ECC_INT_SHIFT
#define	CSI_CSISR_ECC_INT(x)
#define	CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK   CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK
#define	CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT   CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT
#define	CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x)
#define	CSI_CSISR_HRESP_ERR_INT_MASK   CSI_SR_HRESP_ERR_INT_MASK
#define	CSI_CSISR_HRESP_ERR_INT_SHIFT   CSI_SR_HRESP_ERR_INT_SHIFT
#define	CSI_CSISR_HRESP_ERR_INT(x)
#define	CSI_CSISR_COF_INT_MASK   CSI_SR_COF_INT_MASK
#define	CSI_CSISR_COF_INT_SHIFT   CSI_SR_COF_INT_SHIFT
#define	CSI_CSISR_COF_INT(x)
#define	CSI_CSISR_F1_INT_MASK   CSI_SR_F1_INT_MASK
#define	CSI_CSISR_F1_INT_SHIFT   CSI_SR_F1_INT_SHIFT
#define	CSI_CSISR_F1_INT(x)
#define	CSI_CSISR_F2_INT_MASK   CSI_SR_F2_INT_MASK
#define	CSI_CSISR_F2_INT_SHIFT   CSI_SR_F2_INT_SHIFT
#define	CSI_CSISR_F2_INT(x)
#define	CSI_CSISR_SOF_INT_MASK   CSI_SR_SOF_INT_MASK
#define	CSI_CSISR_SOF_INT_SHIFT   CSI_SR_SOF_INT_SHIFT
#define	CSI_CSISR_SOF_INT(x)
#define	CSI_CSISR_EOF_INT_MASK   CSI_SR_EOF_INT_MASK
#define	CSI_CSISR_EOF_INT_SHIFT   CSI_SR_EOF_INT_SHIFT
#define	CSI_CSISR_EOF_INT(x)
#define	CSI_CSISR_RxFF_INT_MASK   CSI_SR_RxFF_INT_MASK
#define	CSI_CSISR_RxFF_INT_SHIFT   CSI_SR_RxFF_INT_SHIFT
#define	CSI_CSISR_RxFF_INT(x)
#define	CSI_CSISR_DMA_TSF_DONE_FB1_MASK   CSI_SR_DMA_TSF_DONE_FB1_MASK
#define	CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT   CSI_SR_DMA_TSF_DONE_FB1_SHIFT
#define	CSI_CSISR_DMA_TSF_DONE_FB1(x)
#define	CSI_CSISR_DMA_TSF_DONE_FB2_MASK   CSI_SR_DMA_TSF_DONE_FB2_MASK
#define	CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT   CSI_SR_DMA_TSF_DONE_FB2_SHIFT
#define	CSI_CSISR_DMA_TSF_DONE_FB2(x)
#define	CSI_CSISR_STATFF_INT_MASK   CSI_SR_STATFF_INT_MASK
#define	CSI_CSISR_STATFF_INT_SHIFT   CSI_SR_STATFF_INT_SHIFT
#define	CSI_CSISR_STATFF_INT(x)
#define	CSI_CSISR_DMA_TSF_DONE_SFF_MASK   CSI_SR_DMA_TSF_DONE_SFF_MASK
#define	CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT   CSI_SR_DMA_TSF_DONE_SFF_SHIFT
#define	CSI_CSISR_DMA_TSF_DONE_SFF(x)
#define	CSI_CSISR_RF_OR_INT_MASK   CSI_SR_RF_OR_INT_MASK
#define	CSI_CSISR_RF_OR_INT_SHIFT   CSI_SR_RF_OR_INT_SHIFT
#define	CSI_CSISR_RF_OR_INT(x)
#define	CSI_CSISR_SF_OR_INT_MASK   CSI_SR_SF_OR_INT_MASK
#define	CSI_CSISR_SF_OR_INT_SHIFT   CSI_SR_SF_OR_INT_SHIFT
#define	CSI_CSISR_SF_OR_INT(x)
#define	CSI_CSISR_DMA_FIELD1_DONE_MASK   CSI_SR_DMA_FIELD1_DONE_MASK
#define	CSI_CSISR_DMA_FIELD1_DONE_SHIFT   CSI_SR_DMA_FIELD1_DONE_SHIFT
#define	CSI_CSISR_DMA_FIELD1_DONE(x)
#define	CSI_CSISR_DMA_FIELD0_DONE_MASK   CSI_SR_DMA_FIELD0_DONE_MASK
#define	CSI_CSISR_DMA_FIELD0_DONE_SHIFT   CSI_SR_DMA_FIELD0_DONE_SHIFT
#define	CSI_CSISR_DMA_FIELD0_DONE(x)
#define	CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK   CSI_SR_BASEADDR_CHHANGE_ERROR_MASK
#define	CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT   CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT
#define	CSI_CSISR_BASEADDR_CHHANGE_ERROR(x)
#define	CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK   CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK
#define	CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT   CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT
#define	CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x)
#define	CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK   CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK
#define	CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT   CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT
#define	CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
#define	CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK   CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK
#define	CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT   CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT
#define	CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)
#define	CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK   CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK
#define	CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT   CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT
#define	CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)
#define	CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK   CSI_FBUF_PARA_FBUF_STRIDE_MASK
#define	CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT   CSI_FBUF_PARA_FBUF_STRIDE_SHIFT
#define	CSI_CSIFBUF_PARA_FBUF_STRIDE(x)
#define	CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK   CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK
#define	CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT   CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT
#define	CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x)
#define	CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK   CSI_IMAG_PARA_IMAGE_HEIGHT_MASK
#define	CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT   CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT
#define	CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)
#define	CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK   CSI_IMAG_PARA_IMAGE_WIDTH_MASK
#define	CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT   CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT
#define	CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)
#define	CSI_CSICR18_NTSC_EN_MASK   CSI_CR18_NTSC_EN_MASK
#define	CSI_CSICR18_NTSC_EN_SHIFT   CSI_CR18_NTSC_EN_SHIFT
#define	CSI_CSICR18_NTSC_EN(x)
#define	CSI_CSICR18_TVDECODER_IN_EN_MASK   CSI_CR18_TVDECODER_IN_EN_MASK
#define	CSI_CSICR18_TVDECODER_IN_EN_SHIFT   CSI_CR18_TVDECODER_IN_EN_SHIFT
#define	CSI_CSICR18_TVDECODER_IN_EN(x)
#define	CSI_CSICR18_DEINTERLACE_EN_MASK   CSI_CR18_DEINTERLACE_EN_MASK
#define	CSI_CSICR18_DEINTERLACE_EN_SHIFT   CSI_CR18_DEINTERLACE_EN_SHIFT
#define	CSI_CSICR18_DEINTERLACE_EN(x)
#define	CSI_CSICR18_PARALLEL24_EN_MASK   CSI_CR18_PARALLEL24_EN_MASK
#define	CSI_CSICR18_PARALLEL24_EN_SHIFT   CSI_CR18_PARALLEL24_EN_SHIFT
#define	CSI_CSICR18_PARALLEL24_EN(x)
#define	CSI_CSICR18_BASEADDR_SWITCH_EN_MASK   CSI_CR18_BASEADDR_SWITCH_EN_MASK
#define	CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT   CSI_CR18_BASEADDR_SWITCH_EN_SHIFT
#define	CSI_CSICR18_BASEADDR_SWITCH_EN(x)
#define	CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK   CSI_CR18_BASEADDR_SWITCH_SEL_MASK
#define	CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT   CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT
#define	CSI_CSICR18_BASEADDR_SWITCH_SEL(x)
#define	CSI_CSICR18_FIELD0_DONE_IE_MASK   CSI_CR18_FIELD0_DONE_IE_MASK
#define	CSI_CSICR18_FIELD0_DONE_IE_SHIFT   CSI_CR18_FIELD0_DONE_IE_SHIFT
#define	CSI_CSICR18_FIELD0_DONE_IE(x)
#define	CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK   CSI_CR18_DMA_FIELD1_DONE_IE_MASK
#define	CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT   CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT
#define	CSI_CSICR18_DMA_FIELD1_DONE_IE(x)
#define	CSI_CSICR18_LAST_DMA_REQ_SEL_MASK   CSI_CR18_LAST_DMA_REQ_SEL_MASK
#define	CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT   CSI_CR18_LAST_DMA_REQ_SEL_SHIFT
#define	CSI_CSICR18_LAST_DMA_REQ_SEL(x)
#define	CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK   CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK
#define	CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT   CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT
#define	CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x)
#define	CSI_CSICR18_RGB888A_FORMAT_SEL_MASK   CSI_CR18_RGB888A_FORMAT_SEL_MASK
#define	CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT   CSI_CR18_RGB888A_FORMAT_SEL_SHIFT
#define	CSI_CSICR18_RGB888A_FORMAT_SEL(x)
#define	CSI_CSICR18_AHB_HPROT_MASK   CSI_CR18_AHB_HPROT_MASK
#define	CSI_CSICR18_AHB_HPROT_SHIFT   CSI_CR18_AHB_HPROT_SHIFT
#define	CSI_CSICR18_AHB_HPROT(x)
#define	CSI_CSICR18_MASK_OPTION_MASK   CSI_CR18_MASK_OPTION_MASK
#define	CSI_CSICR18_MASK_OPTION_SHIFT   CSI_CR18_MASK_OPTION_SHIFT
#define	CSI_CSICR18_MASK_OPTION(x)
#define	CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK   CSI_CR18_MIPI_DOUBLE_CMPNT_MASK
#define	CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT   CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT
#define	CSI_CSICR18_MIPI_DOUBLE_CMPNT(x)
#define	CSI_CSICR18_MIPI_YU_SWAP_MASK   CSI_CR18_MIPI_YU_SWAP_MASK
#define	CSI_CSICR18_MIPI_YU_SWAP_SHIFT   CSI_CR18_MIPI_YU_SWAP_SHIFT
#define	CSI_CSICR18_MIPI_YU_SWAP(x)
#define	CSI_CSICR18_DATA_FROM_MIPI_MASK   CSI_CR18_DATA_FROM_MIPI_MASK
#define	CSI_CSICR18_DATA_FROM_MIPI_SHIFT   CSI_CR18_DATA_FROM_MIPI_SHIFT
#define	CSI_CSICR18_DATA_FROM_MIPI(x)
#define	CSI_CSICR18_LINE_STRIDE_EN_MASK   CSI_CR18_LINE_STRIDE_EN_MASK
#define	CSI_CSICR18_LINE_STRIDE_EN_SHIFT   CSI_CR18_LINE_STRIDE_EN_SHIFT
#define	CSI_CSICR18_LINE_STRIDE_EN(x)
#define	CSI_CSICR18_MIPI_DATA_FORMAT_MASK   CSI_CR18_MIPI_DATA_FORMAT_MASK
#define	CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT   CSI_CR18_MIPI_DATA_FORMAT_SHIFT
#define	CSI_CSICR18_MIPI_DATA_FORMAT(x)
#define	CSI_CSICR18_CSI_ENABLE_MASK   CSI_CR18_CSI_ENABLE_MASK
#define	CSI_CSICR18_CSI_ENABLE_SHIFT   CSI_CR18_CSI_ENABLE_SHIFT
#define	CSI_CSICR18_CSI_ENABLE(x)
#define	CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK   CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK
#define	CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT   CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT
#define	CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
#define	CSI_CSICR20_THRESHOLD_MASK   CSI_CR20_THRESHOLD_MASK
#define	CSI_CSICR20_THRESHOLD_SHIFT   CSI_CR20_THRESHOLD_SHIFT
#define	CSI_CSICR20_THRESHOLD(x)
#define	CSI_CSICR20_BINARY_EN_MASK   CSI_CR20_BINARY_EN_MASK
#define	CSI_CSICR20_BINARY_EN_SHIFT   CSI_CR20_BINARY_EN_SHIFT
#define	CSI_CSICR20_BINARY_EN(x)
#define	CSI_CSICR20_QR_DATA_FORMAT_MASK   CSI_CR20_QR_DATA_FORMAT_MASK
#define	CSI_CSICR20_QR_DATA_FORMAT_SHIFT   CSI_CR20_QR_DATA_FORMAT_SHIFT
#define	CSI_CSICR20_QR_DATA_FORMAT(x)
#define	CSI_CSICR20_BIG_END_MASK   CSI_CR20_BIG_END_MASK
#define	CSI_CSICR20_BIG_END_SHIFT   CSI_CR20_BIG_END_SHIFT
#define	CSI_CSICR20_BIG_END(x)
#define	CSI_CSICR20_10BIT_NEW_EN_MASK   CSI_CR20_10BIT_NEW_EN_MASK
#define	CSI_CSICR20_10BIT_NEW_EN_SHIFT   CSI_CR20_10BIT_NEW_EN_SHIFT
#define	CSI_CSICR20_10BIT_NEW_EN(x)
#define	CSI_CSICR20_HISTOGRAM_EN_MASK   CSI_CR20_HISTOGRAM_EN_MASK
#define	CSI_CSICR20_HISTOGRAM_EN_SHIFT   CSI_CR20_HISTOGRAM_EN_SHIFT
#define	CSI_CSICR20_HISTOGRAM_EN(x)
#define	CSI_CSICR20_QRCODE_EN_MASK   CSI_CR20_QRCODE_EN_MASK
#define	CSI_CSICR20_QRCODE_EN_SHIFT   CSI_CR20_QRCODE_EN_SHIFT
#define	CSI_CSICR20_QRCODE_EN(x)
#define	CSI_CSICR21_PIXEL_COUNTERS_MASK   CSI_CR21_PIXEL_COUNTERS_MASK
#define	CSI_CSICR21_PIXEL_COUNTERS_SHIFT   CSI_CR21_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR21_PIXEL_COUNTERS(x)
#define	CSI_CSICR22_PIXEL_COUNTERS_MASK   CSI_CR22_PIXEL_COUNTERS_MASK
#define	CSI_CSICR22_PIXEL_COUNTERS_SHIFT   CSI_CR22_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR22_PIXEL_COUNTERS(x)
#define	CSI_CSICR23_PIXEL_COUNTERS_MASK   CSI_CR23_PIXEL_COUNTERS_MASK
#define	CSI_CSICR23_PIXEL_COUNTERS_SHIFT   CSI_CR23_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR23_PIXEL_COUNTERS(x)
#define	CSI_CSICR24_PIXEL_COUNTERS_MASK   CSI_CR24_PIXEL_COUNTERS_MASK
#define	CSI_CSICR24_PIXEL_COUNTERS_SHIFT   CSI_CR24_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR24_PIXEL_COUNTERS(x)
#define	CSI_CSICR25_PIXEL_COUNTERS_MASK   CSI_CR25_PIXEL_COUNTERS_MASK
#define	CSI_CSICR25_PIXEL_COUNTERS_SHIFT   CSI_CR25_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR25_PIXEL_COUNTERS(x)
#define	CSI_CSICR26_PIXEL_COUNTERS_MASK   CSI_CR26_PIXEL_COUNTERS_MASK
#define	CSI_CSICR26_PIXEL_COUNTERS_SHIFT   CSI_CR26_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR26_PIXEL_COUNTERS(x)
#define	CSI_CSICR27_PIXEL_COUNTERS_MASK   CSI_CR27_PIXEL_COUNTERS_MASK
#define	CSI_CSICR27_PIXEL_COUNTERS_SHIFT   CSI_CR27_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR27_PIXEL_COUNTERS(x)
#define	CSI_CSICR28_PIXEL_COUNTERS_MASK   CSI_CR28_PIXEL_COUNTERS_MASK
#define	CSI_CSICR28_PIXEL_COUNTERS_SHIFT   CSI_CR28_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR28_PIXEL_COUNTERS(x)
#define	CSI_CSICR29_PIXEL_COUNTERS_MASK   CSI_CR29_PIXEL_COUNTERS_MASK
#define	CSI_CSICR29_PIXEL_COUNTERS_SHIFT   CSI_CR29_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR29_PIXEL_COUNTERS(x)
#define	CSI_CSICR30_PIXEL_COUNTERS_MASK   CSI_CR30_PIXEL_COUNTERS_MASK
#define	CSI_CSICR30_PIXEL_COUNTERS_SHIFT   CSI_CR30_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR30_PIXEL_COUNTERS(x)
#define	CSI_CSICR31_PIXEL_COUNTERS_MASK   CSI_CR31_PIXEL_COUNTERS_MASK
#define	CSI_CSICR31_PIXEL_COUNTERS_SHIFT   CSI_CR31_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR31_PIXEL_COUNTERS(x)
#define	CSI_CSICR32_PIXEL_COUNTERS_MASK   CSI_CR32_PIXEL_COUNTERS_MASK
#define	CSI_CSICR32_PIXEL_COUNTERS_SHIFT   CSI_CR32_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR32_PIXEL_COUNTERS(x)
#define	CSI_CSICR33_PIXEL_COUNTERS_MASK   CSI_CR33_PIXEL_COUNTERS_MASK
#define	CSI_CSICR33_PIXEL_COUNTERS_SHIFT   CSI_CR33_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR33_PIXEL_COUNTERS(x)
#define	CSI_CSICR34_PIXEL_COUNTERS_MASK   CSI_CR34_PIXEL_COUNTERS_MASK
#define	CSI_CSICR34_PIXEL_COUNTERS_SHIFT   CSI_CR34_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR34_PIXEL_COUNTERS(x)
#define	CSI_CSICR35_PIXEL_COUNTERS_MASK   CSI_CR35_PIXEL_COUNTERS_MASK
#define	CSI_CSICR35_PIXEL_COUNTERS_SHIFT   CSI_CR35_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR35_PIXEL_COUNTERS(x)
#define	CSI_CSICR36_PIXEL_COUNTERS_MASK   CSI_CR36_PIXEL_COUNTERS_MASK
#define	CSI_CSICR36_PIXEL_COUNTERS_SHIFT   CSI_CR36_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR36_PIXEL_COUNTERS(x)
#define	CSI_CSICR37_PIXEL_COUNTERS_MASK   CSI_CR37_PIXEL_COUNTERS_MASK
#define	CSI_CSICR37_PIXEL_COUNTERS_SHIFT   CSI_CR37_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR37_PIXEL_COUNTERS(x)
#define	CSI_CSICR38_PIXEL_COUNTERS_MASK   CSI_CR38_PIXEL_COUNTERS_MASK
#define	CSI_CSICR38_PIXEL_COUNTERS_SHIFT   CSI_CR38_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR38_PIXEL_COUNTERS(x)
#define	CSI_CSICR39_PIXEL_COUNTERS_MASK   CSI_CR39_PIXEL_COUNTERS_MASK
#define	CSI_CSICR39_PIXEL_COUNTERS_SHIFT   CSI_CR39_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR39_PIXEL_COUNTERS(x)
#define	CSI_CSICR40_PIXEL_COUNTERS_MASK   CSI_CR40_PIXEL_COUNTERS_MASK
#define	CSI_CSICR40_PIXEL_COUNTERS_SHIFT   CSI_CR40_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR40_PIXEL_COUNTERS(x)
#define	CSI_CSICR41_PIXEL_COUNTERS_MASK   CSI_CR41_PIXEL_COUNTERS_MASK
#define	CSI_CSICR41_PIXEL_COUNTERS_SHIFT   CSI_CR41_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR41_PIXEL_COUNTERS(x)
#define	CSI_CSICR42_PIXEL_COUNTERS_MASK   CSI_CR42_PIXEL_COUNTERS_MASK
#define	CSI_CSICR42_PIXEL_COUNTERS_SHIFT   CSI_CR42_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR42_PIXEL_COUNTERS(x)
#define	CSI_CSICR43_PIXEL_COUNTERS_MASK   CSI_CR43_PIXEL_COUNTERS_MASK
#define	CSI_CSICR43_PIXEL_COUNTERS_SHIFT   CSI_CR43_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR43_PIXEL_COUNTERS(x)
#define	CSI_CSICR44_PIXEL_COUNTERS_MASK   CSI_CR44_PIXEL_COUNTERS_MASK
#define	CSI_CSICR44_PIXEL_COUNTERS_SHIFT   CSI_CR44_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR44_PIXEL_COUNTERS(x)
#define	CSI_CSICR45_PIXEL_COUNTERS_MASK   CSI_CR45_PIXEL_COUNTERS_MASK
#define	CSI_CSICR45_PIXEL_COUNTERS_SHIFT   CSI_CR45_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR45_PIXEL_COUNTERS(x)
#define	CSI_CSICR46_PIXEL_COUNTERS_MASK   CSI_CR46_PIXEL_COUNTERS_MASK
#define	CSI_CSICR46_PIXEL_COUNTERS_SHIFT   CSI_CR46_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR46_PIXEL_COUNTERS(x)
#define	CSI_CSICR47_PIXEL_COUNTERS_MASK   CSI_CR47_PIXEL_COUNTERS_MASK
#define	CSI_CSICR47_PIXEL_COUNTERS_SHIFT   CSI_CR47_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR47_PIXEL_COUNTERS(x)
#define	CSI_CSICR48_PIXEL_COUNTERS_MASK   CSI_CR48_PIXEL_COUNTERS_MASK
#define	CSI_CSICR48_PIXEL_COUNTERS_SHIFT   CSI_CR48_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR48_PIXEL_COUNTERS(x)
#define	CSI_CSICR49_PIXEL_COUNTERS_MASK   CSI_CR49_PIXEL_COUNTERS_MASK
#define	CSI_CSICR49_PIXEL_COUNTERS_SHIFT   CSI_CR49_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR49_PIXEL_COUNTERS(x)
#define	CSI_CSICR50_PIXEL_COUNTERS_MASK   CSI_CR50_PIXEL_COUNTERS_MASK
#define	CSI_CSICR50_PIXEL_COUNTERS_SHIFT   CSI_CR50_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR50_PIXEL_COUNTERS(x)
#define	CSI_CSICR51_PIXEL_COUNTERS_MASK   CSI_CR51_PIXEL_COUNTERS_MASK
#define	CSI_CSICR51_PIXEL_COUNTERS_SHIFT   CSI_CR51_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR51_PIXEL_COUNTERS(x)
#define	CSI_CSICR52_PIXEL_COUNTERS_MASK   CSI_CR52_PIXEL_COUNTERS_MASK
#define	CSI_CSICR52_PIXEL_COUNTERS_SHIFT   CSI_CR52_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR52_PIXEL_COUNTERS(x)
#define	CSI_CSICR53_PIXEL_COUNTERS_MASK   CSI_CR53_PIXEL_COUNTERS_MASK
#define	CSI_CSICR53_PIXEL_COUNTERS_SHIFT   CSI_CR53_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR53_PIXEL_COUNTERS(x)
#define	CSI_CSICR54_PIXEL_COUNTERS_MASK   CSI_CR54_PIXEL_COUNTERS_MASK
#define	CSI_CSICR54_PIXEL_COUNTERS_SHIFT   CSI_CR54_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR54_PIXEL_COUNTERS(x)
#define	CSI_CSICR55_PIXEL_COUNTERS_MASK   CSI_CR55_PIXEL_COUNTERS_MASK
#define	CSI_CSICR55_PIXEL_COUNTERS_SHIFT   CSI_CR55_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR55_PIXEL_COUNTERS(x)
#define	CSI_CSICR56_PIXEL_COUNTERS_MASK   CSI_CR56_PIXEL_COUNTERS_MASK
#define	CSI_CSICR56_PIXEL_COUNTERS_SHIFT   CSI_CR56_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR56_PIXEL_COUNTERS(x)
#define	CSI_CSICR57_PIXEL_COUNTERS_MASK   CSI_CR57_PIXEL_COUNTERS_MASK
#define	CSI_CSICR57_PIXEL_COUNTERS_SHIFT   CSI_CR57_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR57_PIXEL_COUNTERS(x)
#define	CSI_CSICR58_PIXEL_COUNTERS_MASK   CSI_CR58_PIXEL_COUNTERS_MASK
#define	CSI_CSICR58_PIXEL_COUNTERS_SHIFT   CSI_CR58_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR58_PIXEL_COUNTERS(x)
#define	CSI_CSICR59_PIXEL_COUNTERS_MASK   CSI_CR59_PIXEL_COUNTERS_MASK
#define	CSI_CSICR59_PIXEL_COUNTERS_SHIFT   CSI_CR59_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR59_PIXEL_COUNTERS(x)
#define	CSI_CSICR60_PIXEL_COUNTERS_MASK   CSI_CR60_PIXEL_COUNTERS_MASK
#define	CSI_CSICR60_PIXEL_COUNTERS_SHIFT   CSI_CR60_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR60_PIXEL_COUNTERS(x)
#define	CSI_CSICR61_PIXEL_COUNTERS_MASK   CSI_CR61_PIXEL_COUNTERS_MASK
#define	CSI_CSICR61_PIXEL_COUNTERS_SHIFT   CSI_CR61_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR61_PIXEL_COUNTERS(x)
#define	CSI_CSICR62_PIXEL_COUNTERS_MASK   CSI_CR62_PIXEL_COUNTERS_MASK
#define	CSI_CSICR62_PIXEL_COUNTERS_SHIFT   CSI_CR62_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR62_PIXEL_COUNTERS(x)
#define	CSI_CSICR63_PIXEL_COUNTERS_MASK   CSI_CR63_PIXEL_COUNTERS_MASK
#define	CSI_CSICR63_PIXEL_COUNTERS_SHIFT   CSI_CR63_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR63_PIXEL_COUNTERS(x)
#define	CSI_CSICR64_PIXEL_COUNTERS_MASK   CSI_CR64_PIXEL_COUNTERS_MASK
#define	CSI_CSICR64_PIXEL_COUNTERS_SHIFT   CSI_CR64_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR64_PIXEL_COUNTERS(x)
#define	CSI_CSICR65_PIXEL_COUNTERS_MASK   CSI_CR65_PIXEL_COUNTERS_MASK
#define	CSI_CSICR65_PIXEL_COUNTERS_SHIFT   CSI_CR65_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR65_PIXEL_COUNTERS(x)
#define	CSI_CSICR66_PIXEL_COUNTERS_MASK   CSI_CR66_PIXEL_COUNTERS_MASK
#define	CSI_CSICR66_PIXEL_COUNTERS_SHIFT   CSI_CR66_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR66_PIXEL_COUNTERS(x)
#define	CSI_CSICR67_PIXEL_COUNTERS_MASK   CSI_CR67_PIXEL_COUNTERS_MASK
#define	CSI_CSICR67_PIXEL_COUNTERS_SHIFT   CSI_CR67_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR67_PIXEL_COUNTERS(x)
#define	CSI_CSICR68_PIXEL_COUNTERS_MASK   CSI_CR68_PIXEL_COUNTERS_MASK
#define	CSI_CSICR68_PIXEL_COUNTERS_SHIFT   CSI_CR68_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR68_PIXEL_COUNTERS(x)
#define	CSI_CSICR69_PIXEL_COUNTERS_MASK   CSI_CR69_PIXEL_COUNTERS_MASK
#define	CSI_CSICR69_PIXEL_COUNTERS_SHIFT   CSI_CR69_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR69_PIXEL_COUNTERS(x)
#define	CSI_CSICR70_PIXEL_COUNTERS_MASK   CSI_CR70_PIXEL_COUNTERS_MASK
#define	CSI_CSICR70_PIXEL_COUNTERS_SHIFT   CSI_CR70_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR70_PIXEL_COUNTERS(x)
#define	CSI_CSICR71_PIXEL_COUNTERS_MASK   CSI_CR71_PIXEL_COUNTERS_MASK
#define	CSI_CSICR71_PIXEL_COUNTERS_SHIFT   CSI_CR71_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR71_PIXEL_COUNTERS(x)
#define	CSI_CSICR72_PIXEL_COUNTERS_MASK   CSI_CR72_PIXEL_COUNTERS_MASK
#define	CSI_CSICR72_PIXEL_COUNTERS_SHIFT   CSI_CR72_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR72_PIXEL_COUNTERS(x)
#define	CSI_CSICR73_PIXEL_COUNTERS_MASK   CSI_CR73_PIXEL_COUNTERS_MASK
#define	CSI_CSICR73_PIXEL_COUNTERS_SHIFT   CSI_CR73_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR73_PIXEL_COUNTERS(x)
#define	CSI_CSICR74_PIXEL_COUNTERS_MASK   CSI_CR74_PIXEL_COUNTERS_MASK
#define	CSI_CSICR74_PIXEL_COUNTERS_SHIFT   CSI_CR74_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR74_PIXEL_COUNTERS(x)
#define	CSI_CSICR75_PIXEL_COUNTERS_MASK   CSI_CR75_PIXEL_COUNTERS_MASK
#define	CSI_CSICR75_PIXEL_COUNTERS_SHIFT   CSI_CR75_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR75_PIXEL_COUNTERS(x)
#define	CSI_CSICR76_PIXEL_COUNTERS_MASK   CSI_CR76_PIXEL_COUNTERS_MASK
#define	CSI_CSICR76_PIXEL_COUNTERS_SHIFT   CSI_CR76_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR76_PIXEL_COUNTERS(x)
#define	CSI_CSICR77_PIXEL_COUNTERS_MASK   CSI_CR77_PIXEL_COUNTERS_MASK
#define	CSI_CSICR77_PIXEL_COUNTERS_SHIFT   CSI_CR77_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR77_PIXEL_COUNTERS(x)
#define	CSI_CSICR78_PIXEL_COUNTERS_MASK   CSI_CR78_PIXEL_COUNTERS_MASK
#define	CSI_CSICR78_PIXEL_COUNTERS_SHIFT   CSI_CR78_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR78_PIXEL_COUNTERS(x)
#define	CSI_CSICR79_PIXEL_COUNTERS_MASK   CSI_CR79_PIXEL_COUNTERS_MASK
#define	CSI_CSICR79_PIXEL_COUNTERS_SHIFT   CSI_CR79_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR79_PIXEL_COUNTERS(x)
#define	CSI_CSICR80_PIXEL_COUNTERS_MASK   CSI_CR80_PIXEL_COUNTERS_MASK
#define	CSI_CSICR80_PIXEL_COUNTERS_SHIFT   CSI_CR80_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR80_PIXEL_COUNTERS(x)
#define	CSI_CSICR81_PIXEL_COUNTERS_MASK   CSI_CR81_PIXEL_COUNTERS_MASK
#define	CSI_CSICR81_PIXEL_COUNTERS_SHIFT   CSI_CR81_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR81_PIXEL_COUNTERS(x)
#define	CSI_CSICR82_PIXEL_COUNTERS_MASK   CSI_CR82_PIXEL_COUNTERS_MASK
#define	CSI_CSICR82_PIXEL_COUNTERS_SHIFT   CSI_CR82_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR82_PIXEL_COUNTERS(x)
#define	CSI_CSICR83_PIXEL_COUNTERS_MASK   CSI_CR83_PIXEL_COUNTERS_MASK
#define	CSI_CSICR83_PIXEL_COUNTERS_SHIFT   CSI_CR83_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR83_PIXEL_COUNTERS(x)
#define	CSI_CSICR84_PIXEL_COUNTERS_MASK   CSI_CR84_PIXEL_COUNTERS_MASK
#define	CSI_CSICR84_PIXEL_COUNTERS_SHIFT   CSI_CR84_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR84_PIXEL_COUNTERS(x)
#define	CSI_CSICR85_PIXEL_COUNTERS_MASK   CSI_CR85_PIXEL_COUNTERS_MASK
#define	CSI_CSICR85_PIXEL_COUNTERS_SHIFT   CSI_CR85_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR85_PIXEL_COUNTERS(x)
#define	CSI_CSICR86_PIXEL_COUNTERS_MASK   CSI_CR86_PIXEL_COUNTERS_MASK
#define	CSI_CSICR86_PIXEL_COUNTERS_SHIFT   CSI_CR86_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR86_PIXEL_COUNTERS(x)
#define	CSI_CSICR87_PIXEL_COUNTERS_MASK   CSI_CR87_PIXEL_COUNTERS_MASK
#define	CSI_CSICR87_PIXEL_COUNTERS_SHIFT   CSI_CR87_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR87_PIXEL_COUNTERS(x)
#define	CSI_CSICR88_PIXEL_COUNTERS_MASK   CSI_CR88_PIXEL_COUNTERS_MASK
#define	CSI_CSICR88_PIXEL_COUNTERS_SHIFT   CSI_CR88_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR88_PIXEL_COUNTERS(x)
#define	CSI_CSICR89_PIXEL_COUNTERS_MASK   CSI_CR89_PIXEL_COUNTERS_MASK
#define	CSI_CSICR89_PIXEL_COUNTERS_SHIFT   CSI_CR89_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR89_PIXEL_COUNTERS(x)
#define	CSI_CSICR90_PIXEL_COUNTERS_MASK   CSI_CR90_PIXEL_COUNTERS_MASK
#define	CSI_CSICR90_PIXEL_COUNTERS_SHIFT   CSI_CR90_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR90_PIXEL_COUNTERS(x)
#define	CSI_CSICR91_PIXEL_COUNTERS_MASK   CSI_CR91_PIXEL_COUNTERS_MASK
#define	CSI_CSICR91_PIXEL_COUNTERS_SHIFT   CSI_CR91_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR91_PIXEL_COUNTERS(x)
#define	CSI_CSICR92_PIXEL_COUNTERS_MASK   CSI_CR92_PIXEL_COUNTERS_MASK
#define	CSI_CSICR92_PIXEL_COUNTERS_SHIFT   CSI_CR92_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR92_PIXEL_COUNTERS(x)
#define	CSI_CSICR93_PIXEL_COUNTERS_MASK   CSI_CR93_PIXEL_COUNTERS_MASK
#define	CSI_CSICR93_PIXEL_COUNTERS_SHIFT   CSI_CR93_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR93_PIXEL_COUNTERS(x)
#define	CSI_CSICR94_PIXEL_COUNTERS_MASK   CSI_CR94_PIXEL_COUNTERS_MASK
#define	CSI_CSICR94_PIXEL_COUNTERS_SHIFT   CSI_CR94_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR94_PIXEL_COUNTERS(x)
#define	CSI_CSICR95_PIXEL_COUNTERS_MASK   CSI_CR95_PIXEL_COUNTERS_MASK
#define	CSI_CSICR95_PIXEL_COUNTERS_SHIFT   CSI_CR95_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR95_PIXEL_COUNTERS(x)
#define	CSI_CSICR96_PIXEL_COUNTERS_MASK   CSI_CR96_PIXEL_COUNTERS_MASK
#define	CSI_CSICR96_PIXEL_COUNTERS_SHIFT   CSI_CR96_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR96_PIXEL_COUNTERS(x)
#define	CSI_CSICR97_PIXEL_COUNTERS_MASK   CSI_CR97_PIXEL_COUNTERS_MASK
#define	CSI_CSICR97_PIXEL_COUNTERS_SHIFT   CSI_CR97_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR97_PIXEL_COUNTERS(x)
#define	CSI_CSICR98_PIXEL_COUNTERS_MASK   CSI_CR98_PIXEL_COUNTERS_MASK
#define	CSI_CSICR98_PIXEL_COUNTERS_SHIFT   CSI_CR98_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR98_PIXEL_COUNTERS(x)
#define	CSI_CSICR99_PIXEL_COUNTERS_MASK   CSI_CR99_PIXEL_COUNTERS_MASK
#define	CSI_CSICR99_PIXEL_COUNTERS_SHIFT   CSI_CR99_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR99_PIXEL_COUNTERS(x)
#define	CSI_CSICR100_PIXEL_COUNTERS_MASK   CSI_CR100_PIXEL_COUNTERS_MASK
#define	CSI_CSICR100_PIXEL_COUNTERS_SHIFT   CSI_CR100_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR100_PIXEL_COUNTERS(x)
#define	CSI_CSICR101_PIXEL_COUNTERS_MASK   CSI_CR101_PIXEL_COUNTERS_MASK
#define	CSI_CSICR101_PIXEL_COUNTERS_SHIFT   CSI_CR101_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR101_PIXEL_COUNTERS(x)
#define	CSI_CSICR102_PIXEL_COUNTERS_MASK   CSI_CR102_PIXEL_COUNTERS_MASK
#define	CSI_CSICR102_PIXEL_COUNTERS_SHIFT   CSI_CR102_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR102_PIXEL_COUNTERS(x)
#define	CSI_CSICR103_PIXEL_COUNTERS_MASK   CSI_CR103_PIXEL_COUNTERS_MASK
#define	CSI_CSICR103_PIXEL_COUNTERS_SHIFT   CSI_CR103_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR103_PIXEL_COUNTERS(x)
#define	CSI_CSICR104_PIXEL_COUNTERS_MASK   CSI_CR104_PIXEL_COUNTERS_MASK
#define	CSI_CSICR104_PIXEL_COUNTERS_SHIFT   CSI_CR104_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR104_PIXEL_COUNTERS(x)
#define	CSI_CSICR105_PIXEL_COUNTERS_MASK   CSI_CR105_PIXEL_COUNTERS_MASK
#define	CSI_CSICR105_PIXEL_COUNTERS_SHIFT   CSI_CR105_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR105_PIXEL_COUNTERS(x)
#define	CSI_CSICR106_PIXEL_COUNTERS_MASK   CSI_CR106_PIXEL_COUNTERS_MASK
#define	CSI_CSICR106_PIXEL_COUNTERS_SHIFT   CSI_CR106_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR106_PIXEL_COUNTERS(x)
#define	CSI_CSICR107_PIXEL_COUNTERS_MASK   CSI_CR107_PIXEL_COUNTERS_MASK
#define	CSI_CSICR107_PIXEL_COUNTERS_SHIFT   CSI_CR107_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR107_PIXEL_COUNTERS(x)
#define	CSI_CSICR108_PIXEL_COUNTERS_MASK   CSI_CR108_PIXEL_COUNTERS_MASK
#define	CSI_CSICR108_PIXEL_COUNTERS_SHIFT   CSI_CR108_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR108_PIXEL_COUNTERS(x)
#define	CSI_CSICR109_PIXEL_COUNTERS_MASK   CSI_CR109_PIXEL_COUNTERS_MASK
#define	CSI_CSICR109_PIXEL_COUNTERS_SHIFT   CSI_CR109_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR109_PIXEL_COUNTERS(x)
#define	CSI_CSICR110_PIXEL_COUNTERS_MASK   CSI_CR110_PIXEL_COUNTERS_MASK
#define	CSI_CSICR110_PIXEL_COUNTERS_SHIFT   CSI_CR110_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR110_PIXEL_COUNTERS(x)
#define	CSI_CSICR111_PIXEL_COUNTERS_MASK   CSI_CR111_PIXEL_COUNTERS_MASK
#define	CSI_CSICR111_PIXEL_COUNTERS_SHIFT   CSI_CR111_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR111_PIXEL_COUNTERS(x)
#define	CSI_CSICR112_PIXEL_COUNTERS_MASK   CSI_CR112_PIXEL_COUNTERS_MASK
#define	CSI_CSICR112_PIXEL_COUNTERS_SHIFT   CSI_CR112_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR112_PIXEL_COUNTERS(x)
#define	CSI_CSICR113_PIXEL_COUNTERS_MASK   CSI_CR113_PIXEL_COUNTERS_MASK
#define	CSI_CSICR113_PIXEL_COUNTERS_SHIFT   CSI_CR113_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR113_PIXEL_COUNTERS(x)
#define	CSI_CSICR114_PIXEL_COUNTERS_MASK   CSI_CR114_PIXEL_COUNTERS_MASK
#define	CSI_CSICR114_PIXEL_COUNTERS_SHIFT   CSI_CR114_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR114_PIXEL_COUNTERS(x)
#define	CSI_CSICR115_PIXEL_COUNTERS_MASK   CSI_CR115_PIXEL_COUNTERS_MASK
#define	CSI_CSICR115_PIXEL_COUNTERS_SHIFT   CSI_CR115_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR115_PIXEL_COUNTERS(x)
#define	CSI_CSICR116_PIXEL_COUNTERS_MASK   CSI_CR116_PIXEL_COUNTERS_MASK
#define	CSI_CSICR116_PIXEL_COUNTERS_SHIFT   CSI_CR116_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR116_PIXEL_COUNTERS(x)
#define	CSI_CSICR117_PIXEL_COUNTERS_MASK   CSI_CR117_PIXEL_COUNTERS_MASK
#define	CSI_CSICR117_PIXEL_COUNTERS_SHIFT   CSI_CR117_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR117_PIXEL_COUNTERS(x)
#define	CSI_CSICR118_PIXEL_COUNTERS_MASK   CSI_CR118_PIXEL_COUNTERS_MASK
#define	CSI_CSICR118_PIXEL_COUNTERS_SHIFT   CSI_CR118_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR118_PIXEL_COUNTERS(x)
#define	CSI_CSICR119_PIXEL_COUNTERS_MASK   CSI_CR119_PIXEL_COUNTERS_MASK
#define	CSI_CSICR119_PIXEL_COUNTERS_SHIFT   CSI_CR119_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR119_PIXEL_COUNTERS(x)
#define	CSI_CSICR120_PIXEL_COUNTERS_MASK   CSI_CR120_PIXEL_COUNTERS_MASK
#define	CSI_CSICR120_PIXEL_COUNTERS_SHIFT   CSI_CR120_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR120_PIXEL_COUNTERS(x)
#define	CSI_CSICR121_PIXEL_COUNTERS_MASK   CSI_CR121_PIXEL_COUNTERS_MASK
#define	CSI_CSICR121_PIXEL_COUNTERS_SHIFT   CSI_CR121_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR121_PIXEL_COUNTERS(x)
#define	CSI_CSICR122_PIXEL_COUNTERS_MASK   CSI_CR122_PIXEL_COUNTERS_MASK
#define	CSI_CSICR122_PIXEL_COUNTERS_SHIFT   CSI_CR122_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR122_PIXEL_COUNTERS(x)
#define	CSI_CSICR123_PIXEL_COUNTERS_MASK   CSI_CR123_PIXEL_COUNTERS_MASK
#define	CSI_CSICR123_PIXEL_COUNTERS_SHIFT   CSI_CR123_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR123_PIXEL_COUNTERS(x)
#define	CSI_CSICR124_PIXEL_COUNTERS_MASK   CSI_CR124_PIXEL_COUNTERS_MASK
#define	CSI_CSICR124_PIXEL_COUNTERS_SHIFT   CSI_CR124_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR124_PIXEL_COUNTERS(x)
#define	CSI_CSICR125_PIXEL_COUNTERS_MASK   CSI_CR125_PIXEL_COUNTERS_MASK
#define	CSI_CSICR125_PIXEL_COUNTERS_SHIFT   CSI_CR125_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR125_PIXEL_COUNTERS(x)
#define	CSI_CSICR126_PIXEL_COUNTERS_MASK   CSI_CR126_PIXEL_COUNTERS_MASK
#define	CSI_CSICR126_PIXEL_COUNTERS_SHIFT   CSI_CR126_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR126_PIXEL_COUNTERS(x)
#define	CSI_CSICR127_PIXEL_COUNTERS_MASK   CSI_CR127_PIXEL_COUNTERS_MASK
#define	CSI_CSICR127_PIXEL_COUNTERS_SHIFT   CSI_CR127_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR127_PIXEL_COUNTERS(x)
#define	CSI_CSICR128_PIXEL_COUNTERS_MASK   CSI_CR128_PIXEL_COUNTERS_MASK
#define	CSI_CSICR128_PIXEL_COUNTERS_SHIFT   CSI_CR128_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR128_PIXEL_COUNTERS(x)
#define	CSI_CSICR129_PIXEL_COUNTERS_MASK   CSI_CR129_PIXEL_COUNTERS_MASK
#define	CSI_CSICR129_PIXEL_COUNTERS_SHIFT   CSI_CR129_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR129_PIXEL_COUNTERS(x)
#define	CSI_CSICR130_PIXEL_COUNTERS_MASK   CSI_CR130_PIXEL_COUNTERS_MASK
#define	CSI_CSICR130_PIXEL_COUNTERS_SHIFT   CSI_CR130_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR130_PIXEL_COUNTERS(x)
#define	CSI_CSICR131_PIXEL_COUNTERS_MASK   CSI_CR131_PIXEL_COUNTERS_MASK
#define	CSI_CSICR131_PIXEL_COUNTERS_SHIFT   CSI_CR131_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR131_PIXEL_COUNTERS(x)
#define	CSI_CSICR132_PIXEL_COUNTERS_MASK   CSI_CR132_PIXEL_COUNTERS_MASK
#define	CSI_CSICR132_PIXEL_COUNTERS_SHIFT   CSI_CR132_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR132_PIXEL_COUNTERS(x)
#define	CSI_CSICR133_PIXEL_COUNTERS_MASK   CSI_CR133_PIXEL_COUNTERS_MASK
#define	CSI_CSICR133_PIXEL_COUNTERS_SHIFT   CSI_CR133_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR133_PIXEL_COUNTERS(x)
#define	CSI_CSICR134_PIXEL_COUNTERS_MASK   CSI_CR134_PIXEL_COUNTERS_MASK
#define	CSI_CSICR134_PIXEL_COUNTERS_SHIFT   CSI_CR134_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR134_PIXEL_COUNTERS(x)
#define	CSI_CSICR135_PIXEL_COUNTERS_MASK   CSI_CR135_PIXEL_COUNTERS_MASK
#define	CSI_CSICR135_PIXEL_COUNTERS_SHIFT   CSI_CR135_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR135_PIXEL_COUNTERS(x)
#define	CSI_CSICR136_PIXEL_COUNTERS_MASK   CSI_CR136_PIXEL_COUNTERS_MASK
#define	CSI_CSICR136_PIXEL_COUNTERS_SHIFT   CSI_CR136_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR136_PIXEL_COUNTERS(x)
#define	CSI_CSICR137_PIXEL_COUNTERS_MASK   CSI_CR137_PIXEL_COUNTERS_MASK
#define	CSI_CSICR137_PIXEL_COUNTERS_SHIFT   CSI_CR137_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR137_PIXEL_COUNTERS(x)
#define	CSI_CSICR138_PIXEL_COUNTERS_MASK   CSI_CR138_PIXEL_COUNTERS_MASK
#define	CSI_CSICR138_PIXEL_COUNTERS_SHIFT   CSI_CR138_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR138_PIXEL_COUNTERS(x)
#define	CSI_CSICR139_PIXEL_COUNTERS_MASK   CSI_CR139_PIXEL_COUNTERS_MASK
#define	CSI_CSICR139_PIXEL_COUNTERS_SHIFT   CSI_CR139_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR139_PIXEL_COUNTERS(x)
#define	CSI_CSICR140_PIXEL_COUNTERS_MASK   CSI_CR140_PIXEL_COUNTERS_MASK
#define	CSI_CSICR140_PIXEL_COUNTERS_SHIFT   CSI_CR140_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR140_PIXEL_COUNTERS(x)
#define	CSI_CSICR141_PIXEL_COUNTERS_MASK   CSI_CR141_PIXEL_COUNTERS_MASK
#define	CSI_CSICR141_PIXEL_COUNTERS_SHIFT   CSI_CR141_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR141_PIXEL_COUNTERS(x)
#define	CSI_CSICR142_PIXEL_COUNTERS_MASK   CSI_CR142_PIXEL_COUNTERS_MASK
#define	CSI_CSICR142_PIXEL_COUNTERS_SHIFT   CSI_CR142_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR142_PIXEL_COUNTERS(x)
#define	CSI_CSICR143_PIXEL_COUNTERS_MASK   CSI_CR143_PIXEL_COUNTERS_MASK
#define	CSI_CSICR143_PIXEL_COUNTERS_SHIFT   CSI_CR143_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR143_PIXEL_COUNTERS(x)
#define	CSI_CSICR144_PIXEL_COUNTERS_MASK   CSI_CR144_PIXEL_COUNTERS_MASK
#define	CSI_CSICR144_PIXEL_COUNTERS_SHIFT   CSI_CR144_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR144_PIXEL_COUNTERS(x)
#define	CSI_CSICR145_PIXEL_COUNTERS_MASK   CSI_CR145_PIXEL_COUNTERS_MASK
#define	CSI_CSICR145_PIXEL_COUNTERS_SHIFT   CSI_CR145_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR145_PIXEL_COUNTERS(x)
#define	CSI_CSICR146_PIXEL_COUNTERS_MASK   CSI_CR146_PIXEL_COUNTERS_MASK
#define	CSI_CSICR146_PIXEL_COUNTERS_SHIFT   CSI_CR146_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR146_PIXEL_COUNTERS(x)
#define	CSI_CSICR147_PIXEL_COUNTERS_MASK   CSI_CR147_PIXEL_COUNTERS_MASK
#define	CSI_CSICR147_PIXEL_COUNTERS_SHIFT   CSI_CR147_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR147_PIXEL_COUNTERS(x)
#define	CSI_CSICR148_PIXEL_COUNTERS_MASK   CSI_CR148_PIXEL_COUNTERS_MASK
#define	CSI_CSICR148_PIXEL_COUNTERS_SHIFT   CSI_CR148_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR148_PIXEL_COUNTERS(x)
#define	CSI_CSICR149_PIXEL_COUNTERS_MASK   CSI_CR149_PIXEL_COUNTERS_MASK
#define	CSI_CSICR149_PIXEL_COUNTERS_SHIFT   CSI_CR149_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR149_PIXEL_COUNTERS(x)
#define	CSI_CSICR150_PIXEL_COUNTERS_MASK   CSI_CR150_PIXEL_COUNTERS_MASK
#define	CSI_CSICR150_PIXEL_COUNTERS_SHIFT   CSI_CR150_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR150_PIXEL_COUNTERS(x)
#define	CSI_CSICR151_PIXEL_COUNTERS_MASK   CSI_CR151_PIXEL_COUNTERS_MASK
#define	CSI_CSICR151_PIXEL_COUNTERS_SHIFT   CSI_CR151_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR151_PIXEL_COUNTERS(x)
#define	CSI_CSICR152_PIXEL_COUNTERS_MASK   CSI_CR152_PIXEL_COUNTERS_MASK
#define	CSI_CSICR152_PIXEL_COUNTERS_SHIFT   CSI_CR152_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR152_PIXEL_COUNTERS(x)
#define	CSI_CSICR153_PIXEL_COUNTERS_MASK   CSI_CR153_PIXEL_COUNTERS_MASK
#define	CSI_CSICR153_PIXEL_COUNTERS_SHIFT   CSI_CR153_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR153_PIXEL_COUNTERS(x)
#define	CSI_CSICR154_PIXEL_COUNTERS_MASK   CSI_CR154_PIXEL_COUNTERS_MASK
#define	CSI_CSICR154_PIXEL_COUNTERS_SHIFT   CSI_CR154_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR154_PIXEL_COUNTERS(x)
#define	CSI_CSICR155_PIXEL_COUNTERS_MASK   CSI_CR155_PIXEL_COUNTERS_MASK
#define	CSI_CSICR155_PIXEL_COUNTERS_SHIFT   CSI_CR155_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR155_PIXEL_COUNTERS(x)
#define	CSI_CSICR156_PIXEL_COUNTERS_MASK   CSI_CR156_PIXEL_COUNTERS_MASK
#define	CSI_CSICR156_PIXEL_COUNTERS_SHIFT   CSI_CR156_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR156_PIXEL_COUNTERS(x)
#define	CSI_CSICR157_PIXEL_COUNTERS_MASK   CSI_CR157_PIXEL_COUNTERS_MASK
#define	CSI_CSICR157_PIXEL_COUNTERS_SHIFT   CSI_CR157_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR157_PIXEL_COUNTERS(x)
#define	CSI_CSICR158_PIXEL_COUNTERS_MASK   CSI_CR158_PIXEL_COUNTERS_MASK
#define	CSI_CSICR158_PIXEL_COUNTERS_SHIFT   CSI_CR158_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR158_PIXEL_COUNTERS(x)
#define	CSI_CSICR159_PIXEL_COUNTERS_MASK   CSI_CR159_PIXEL_COUNTERS_MASK
#define	CSI_CSICR159_PIXEL_COUNTERS_SHIFT   CSI_CR159_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR159_PIXEL_COUNTERS(x)
#define	CSI_CSICR160_PIXEL_COUNTERS_MASK   CSI_CR160_PIXEL_COUNTERS_MASK
#define	CSI_CSICR160_PIXEL_COUNTERS_SHIFT   CSI_CR160_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR160_PIXEL_COUNTERS(x)
#define	CSI_CSICR161_PIXEL_COUNTERS_MASK   CSI_CR161_PIXEL_COUNTERS_MASK
#define	CSI_CSICR161_PIXEL_COUNTERS_SHIFT   CSI_CR161_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR161_PIXEL_COUNTERS(x)
#define	CSI_CSICR162_PIXEL_COUNTERS_MASK   CSI_CR162_PIXEL_COUNTERS_MASK
#define	CSI_CSICR162_PIXEL_COUNTERS_SHIFT   CSI_CR162_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR162_PIXEL_COUNTERS(x)
#define	CSI_CSICR163_PIXEL_COUNTERS_MASK   CSI_CR163_PIXEL_COUNTERS_MASK
#define	CSI_CSICR163_PIXEL_COUNTERS_SHIFT   CSI_CR163_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR163_PIXEL_COUNTERS(x)
#define	CSI_CSICR164_PIXEL_COUNTERS_MASK   CSI_CR164_PIXEL_COUNTERS_MASK
#define	CSI_CSICR164_PIXEL_COUNTERS_SHIFT   CSI_CR164_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR164_PIXEL_COUNTERS(x)
#define	CSI_CSICR165_PIXEL_COUNTERS_MASK   CSI_CR165_PIXEL_COUNTERS_MASK
#define	CSI_CSICR165_PIXEL_COUNTERS_SHIFT   CSI_CR165_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR165_PIXEL_COUNTERS(x)
#define	CSI_CSICR166_PIXEL_COUNTERS_MASK   CSI_CR166_PIXEL_COUNTERS_MASK
#define	CSI_CSICR166_PIXEL_COUNTERS_SHIFT   CSI_CR166_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR166_PIXEL_COUNTERS(x)
#define	CSI_CSICR167_PIXEL_COUNTERS_MASK   CSI_CR167_PIXEL_COUNTERS_MASK
#define	CSI_CSICR167_PIXEL_COUNTERS_SHIFT   CSI_CR167_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR167_PIXEL_COUNTERS(x)
#define	CSI_CSICR168_PIXEL_COUNTERS_MASK   CSI_CR168_PIXEL_COUNTERS_MASK
#define	CSI_CSICR168_PIXEL_COUNTERS_SHIFT   CSI_CR168_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR168_PIXEL_COUNTERS(x)
#define	CSI_CSICR169_PIXEL_COUNTERS_MASK   CSI_CR169_PIXEL_COUNTERS_MASK
#define	CSI_CSICR169_PIXEL_COUNTERS_SHIFT   CSI_CR169_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR169_PIXEL_COUNTERS(x)
#define	CSI_CSICR170_PIXEL_COUNTERS_MASK   CSI_CR170_PIXEL_COUNTERS_MASK
#define	CSI_CSICR170_PIXEL_COUNTERS_SHIFT   CSI_CR170_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR170_PIXEL_COUNTERS(x)
#define	CSI_CSICR171_PIXEL_COUNTERS_MASK   CSI_CR171_PIXEL_COUNTERS_MASK
#define	CSI_CSICR171_PIXEL_COUNTERS_SHIFT   CSI_CR171_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR171_PIXEL_COUNTERS(x)
#define	CSI_CSICR172_PIXEL_COUNTERS_MASK   CSI_CR172_PIXEL_COUNTERS_MASK
#define	CSI_CSICR172_PIXEL_COUNTERS_SHIFT   CSI_CR172_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR172_PIXEL_COUNTERS(x)
#define	CSI_CSICR173_PIXEL_COUNTERS_MASK   CSI_CR173_PIXEL_COUNTERS_MASK
#define	CSI_CSICR173_PIXEL_COUNTERS_SHIFT   CSI_CR173_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR173_PIXEL_COUNTERS(x)
#define	CSI_CSICR174_PIXEL_COUNTERS_MASK   CSI_CR174_PIXEL_COUNTERS_MASK
#define	CSI_CSICR174_PIXEL_COUNTERS_SHIFT   CSI_CR174_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR174_PIXEL_COUNTERS(x)
#define	CSI_CSICR175_PIXEL_COUNTERS_MASK   CSI_CR175_PIXEL_COUNTERS_MASK
#define	CSI_CSICR175_PIXEL_COUNTERS_SHIFT   CSI_CR175_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR175_PIXEL_COUNTERS(x)
#define	CSI_CSICR176_PIXEL_COUNTERS_MASK   CSI_CR176_PIXEL_COUNTERS_MASK
#define	CSI_CSICR176_PIXEL_COUNTERS_SHIFT   CSI_CR176_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR176_PIXEL_COUNTERS(x)
#define	CSI_CSICR177_PIXEL_COUNTERS_MASK   CSI_CR177_PIXEL_COUNTERS_MASK
#define	CSI_CSICR177_PIXEL_COUNTERS_SHIFT   CSI_CR177_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR177_PIXEL_COUNTERS(x)
#define	CSI_CSICR178_PIXEL_COUNTERS_MASK   CSI_CR178_PIXEL_COUNTERS_MASK
#define	CSI_CSICR178_PIXEL_COUNTERS_SHIFT   CSI_CR178_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR178_PIXEL_COUNTERS(x)
#define	CSI_CSICR179_PIXEL_COUNTERS_MASK   CSI_CR179_PIXEL_COUNTERS_MASK
#define	CSI_CSICR179_PIXEL_COUNTERS_SHIFT   CSI_CR179_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR179_PIXEL_COUNTERS(x)
#define	CSI_CSICR180_PIXEL_COUNTERS_MASK   CSI_CR180_PIXEL_COUNTERS_MASK
#define	CSI_CSICR180_PIXEL_COUNTERS_SHIFT   CSI_CR180_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR180_PIXEL_COUNTERS(x)
#define	CSI_CSICR181_PIXEL_COUNTERS_MASK   CSI_CR181_PIXEL_COUNTERS_MASK
#define	CSI_CSICR181_PIXEL_COUNTERS_SHIFT   CSI_CR181_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR181_PIXEL_COUNTERS(x)
#define	CSI_CSICR182_PIXEL_COUNTERS_MASK   CSI_CR182_PIXEL_COUNTERS_MASK
#define	CSI_CSICR182_PIXEL_COUNTERS_SHIFT   CSI_CR182_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR182_PIXEL_COUNTERS(x)
#define	CSI_CSICR183_PIXEL_COUNTERS_MASK   CSI_CR183_PIXEL_COUNTERS_MASK
#define	CSI_CSICR183_PIXEL_COUNTERS_SHIFT   CSI_CR183_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR183_PIXEL_COUNTERS(x)
#define	CSI_CSICR184_PIXEL_COUNTERS_MASK   CSI_CR184_PIXEL_COUNTERS_MASK
#define	CSI_CSICR184_PIXEL_COUNTERS_SHIFT   CSI_CR184_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR184_PIXEL_COUNTERS(x)
#define	CSI_CSICR185_PIXEL_COUNTERS_MASK   CSI_CR185_PIXEL_COUNTERS_MASK
#define	CSI_CSICR185_PIXEL_COUNTERS_SHIFT   CSI_CR185_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR185_PIXEL_COUNTERS(x)
#define	CSI_CSICR186_PIXEL_COUNTERS_MASK   CSI_CR186_PIXEL_COUNTERS_MASK
#define	CSI_CSICR186_PIXEL_COUNTERS_SHIFT   CSI_CR186_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR186_PIXEL_COUNTERS(x)
#define	CSI_CSICR187_PIXEL_COUNTERS_MASK   CSI_CR187_PIXEL_COUNTERS_MASK
#define	CSI_CSICR187_PIXEL_COUNTERS_SHIFT   CSI_CR187_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR187_PIXEL_COUNTERS(x)
#define	CSI_CSICR188_PIXEL_COUNTERS_MASK   CSI_CR188_PIXEL_COUNTERS_MASK
#define	CSI_CSICR188_PIXEL_COUNTERS_SHIFT   CSI_CR188_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR188_PIXEL_COUNTERS(x)
#define	CSI_CSICR189_PIXEL_COUNTERS_MASK   CSI_CR189_PIXEL_COUNTERS_MASK
#define	CSI_CSICR189_PIXEL_COUNTERS_SHIFT   CSI_CR189_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR189_PIXEL_COUNTERS(x)
#define	CSI_CSICR190_PIXEL_COUNTERS_MASK   CSI_CR190_PIXEL_COUNTERS_MASK
#define	CSI_CSICR190_PIXEL_COUNTERS_SHIFT   CSI_CR190_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR190_PIXEL_COUNTERS(x)
#define	CSI_CSICR191_PIXEL_COUNTERS_MASK   CSI_CR191_PIXEL_COUNTERS_MASK
#define	CSI_CSICR191_PIXEL_COUNTERS_SHIFT   CSI_CR191_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR191_PIXEL_COUNTERS(x)
#define	CSI_CSICR192_PIXEL_COUNTERS_MASK   CSI_CR192_PIXEL_COUNTERS_MASK
#define	CSI_CSICR192_PIXEL_COUNTERS_SHIFT   CSI_CR192_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR192_PIXEL_COUNTERS(x)
#define	CSI_CSICR193_PIXEL_COUNTERS_MASK   CSI_CR193_PIXEL_COUNTERS_MASK
#define	CSI_CSICR193_PIXEL_COUNTERS_SHIFT   CSI_CR193_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR193_PIXEL_COUNTERS(x)
#define	CSI_CSICR194_PIXEL_COUNTERS_MASK   CSI_CR194_PIXEL_COUNTERS_MASK
#define	CSI_CSICR194_PIXEL_COUNTERS_SHIFT   CSI_CR194_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR194_PIXEL_COUNTERS(x)
#define	CSI_CSICR195_PIXEL_COUNTERS_MASK   CSI_CR195_PIXEL_COUNTERS_MASK
#define	CSI_CSICR195_PIXEL_COUNTERS_SHIFT   CSI_CR195_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR195_PIXEL_COUNTERS(x)
#define	CSI_CSICR196_PIXEL_COUNTERS_MASK   CSI_CR196_PIXEL_COUNTERS_MASK
#define	CSI_CSICR196_PIXEL_COUNTERS_SHIFT   CSI_CR196_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR196_PIXEL_COUNTERS(x)
#define	CSI_CSICR197_PIXEL_COUNTERS_MASK   CSI_CR197_PIXEL_COUNTERS_MASK
#define	CSI_CSICR197_PIXEL_COUNTERS_SHIFT   CSI_CR197_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR197_PIXEL_COUNTERS(x)
#define	CSI_CSICR198_PIXEL_COUNTERS_MASK   CSI_CR198_PIXEL_COUNTERS_MASK
#define	CSI_CSICR198_PIXEL_COUNTERS_SHIFT   CSI_CR198_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR198_PIXEL_COUNTERS(x)
#define	CSI_CSICR199_PIXEL_COUNTERS_MASK   CSI_CR199_PIXEL_COUNTERS_MASK
#define	CSI_CSICR199_PIXEL_COUNTERS_SHIFT   CSI_CR199_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR199_PIXEL_COUNTERS(x)
#define	CSI_CSICR200_PIXEL_COUNTERS_MASK   CSI_CR200_PIXEL_COUNTERS_MASK
#define	CSI_CSICR200_PIXEL_COUNTERS_SHIFT   CSI_CR200_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR200_PIXEL_COUNTERS(x)
#define	CSI_CSICR201_PIXEL_COUNTERS_MASK   CSI_CR201_PIXEL_COUNTERS_MASK
#define	CSI_CSICR201_PIXEL_COUNTERS_SHIFT   CSI_CR201_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR201_PIXEL_COUNTERS(x)
#define	CSI_CSICR202_PIXEL_COUNTERS_MASK   CSI_CR202_PIXEL_COUNTERS_MASK
#define	CSI_CSICR202_PIXEL_COUNTERS_SHIFT   CSI_CR202_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR202_PIXEL_COUNTERS(x)
#define	CSI_CSICR203_PIXEL_COUNTERS_MASK   CSI_CR203_PIXEL_COUNTERS_MASK
#define	CSI_CSICR203_PIXEL_COUNTERS_SHIFT   CSI_CR203_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR203_PIXEL_COUNTERS(x)
#define	CSI_CSICR204_PIXEL_COUNTERS_MASK   CSI_CR204_PIXEL_COUNTERS_MASK
#define	CSI_CSICR204_PIXEL_COUNTERS_SHIFT   CSI_CR204_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR204_PIXEL_COUNTERS(x)
#define	CSI_CSICR205_PIXEL_COUNTERS_MASK   CSI_CR205_PIXEL_COUNTERS_MASK
#define	CSI_CSICR205_PIXEL_COUNTERS_SHIFT   CSI_CR205_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR205_PIXEL_COUNTERS(x)
#define	CSI_CSICR206_PIXEL_COUNTERS_MASK   CSI_CR206_PIXEL_COUNTERS_MASK
#define	CSI_CSICR206_PIXEL_COUNTERS_SHIFT   CSI_CR206_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR206_PIXEL_COUNTERS(x)
#define	CSI_CSICR207_PIXEL_COUNTERS_MASK   CSI_CR207_PIXEL_COUNTERS_MASK
#define	CSI_CSICR207_PIXEL_COUNTERS_SHIFT   CSI_CR207_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR207_PIXEL_COUNTERS(x)
#define	CSI_CSICR208_PIXEL_COUNTERS_MASK   CSI_CR208_PIXEL_COUNTERS_MASK
#define	CSI_CSICR208_PIXEL_COUNTERS_SHIFT   CSI_CR208_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR208_PIXEL_COUNTERS(x)
#define	CSI_CSICR209_PIXEL_COUNTERS_MASK   CSI_CR209_PIXEL_COUNTERS_MASK
#define	CSI_CSICR209_PIXEL_COUNTERS_SHIFT   CSI_CR209_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR209_PIXEL_COUNTERS(x)
#define	CSI_CSICR210_PIXEL_COUNTERS_MASK   CSI_CR210_PIXEL_COUNTERS_MASK
#define	CSI_CSICR210_PIXEL_COUNTERS_SHIFT   CSI_CR210_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR210_PIXEL_COUNTERS(x)
#define	CSI_CSICR211_PIXEL_COUNTERS_MASK   CSI_CR211_PIXEL_COUNTERS_MASK
#define	CSI_CSICR211_PIXEL_COUNTERS_SHIFT   CSI_CR211_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR211_PIXEL_COUNTERS(x)
#define	CSI_CSICR212_PIXEL_COUNTERS_MASK   CSI_CR212_PIXEL_COUNTERS_MASK
#define	CSI_CSICR212_PIXEL_COUNTERS_SHIFT   CSI_CR212_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR212_PIXEL_COUNTERS(x)
#define	CSI_CSICR213_PIXEL_COUNTERS_MASK   CSI_CR213_PIXEL_COUNTERS_MASK
#define	CSI_CSICR213_PIXEL_COUNTERS_SHIFT   CSI_CR213_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR213_PIXEL_COUNTERS(x)
#define	CSI_CSICR214_PIXEL_COUNTERS_MASK   CSI_CR214_PIXEL_COUNTERS_MASK
#define	CSI_CSICR214_PIXEL_COUNTERS_SHIFT   CSI_CR214_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR214_PIXEL_COUNTERS(x)
#define	CSI_CSICR215_PIXEL_COUNTERS_MASK   CSI_CR215_PIXEL_COUNTERS_MASK
#define	CSI_CSICR215_PIXEL_COUNTERS_SHIFT   CSI_CR215_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR215_PIXEL_COUNTERS(x)
#define	CSI_CSICR216_PIXEL_COUNTERS_MASK   CSI_CR216_PIXEL_COUNTERS_MASK
#define	CSI_CSICR216_PIXEL_COUNTERS_SHIFT   CSI_CR216_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR216_PIXEL_COUNTERS(x)
#define	CSI_CSICR217_PIXEL_COUNTERS_MASK   CSI_CR217_PIXEL_COUNTERS_MASK
#define	CSI_CSICR217_PIXEL_COUNTERS_SHIFT   CSI_CR217_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR217_PIXEL_COUNTERS(x)
#define	CSI_CSICR218_PIXEL_COUNTERS_MASK   CSI_CR218_PIXEL_COUNTERS_MASK
#define	CSI_CSICR218_PIXEL_COUNTERS_SHIFT   CSI_CR218_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR218_PIXEL_COUNTERS(x)
#define	CSI_CSICR219_PIXEL_COUNTERS_MASK   CSI_CR219_PIXEL_COUNTERS_MASK
#define	CSI_CSICR219_PIXEL_COUNTERS_SHIFT   CSI_CR219_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR219_PIXEL_COUNTERS(x)
#define	CSI_CSICR220_PIXEL_COUNTERS_MASK   CSI_CR220_PIXEL_COUNTERS_MASK
#define	CSI_CSICR220_PIXEL_COUNTERS_SHIFT   CSI_CR220_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR220_PIXEL_COUNTERS(x)
#define	CSI_CSICR221_PIXEL_COUNTERS_MASK   CSI_CR221_PIXEL_COUNTERS_MASK
#define	CSI_CSICR221_PIXEL_COUNTERS_SHIFT   CSI_CR221_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR221_PIXEL_COUNTERS(x)
#define	CSI_CSICR222_PIXEL_COUNTERS_MASK   CSI_CR222_PIXEL_COUNTERS_MASK
#define	CSI_CSICR222_PIXEL_COUNTERS_SHIFT   CSI_CR222_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR222_PIXEL_COUNTERS(x)
#define	CSI_CSICR223_PIXEL_COUNTERS_MASK   CSI_CR223_PIXEL_COUNTERS_MASK
#define	CSI_CSICR223_PIXEL_COUNTERS_SHIFT   CSI_CR223_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR223_PIXEL_COUNTERS(x)
#define	CSI_CSICR224_PIXEL_COUNTERS_MASK   CSI_CR224_PIXEL_COUNTERS_MASK
#define	CSI_CSICR224_PIXEL_COUNTERS_SHIFT   CSI_CR224_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR224_PIXEL_COUNTERS(x)
#define	CSI_CSICR225_PIXEL_COUNTERS_MASK   CSI_CR225_PIXEL_COUNTERS_MASK
#define	CSI_CSICR225_PIXEL_COUNTERS_SHIFT   CSI_CR225_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR225_PIXEL_COUNTERS(x)
#define	CSI_CSICR226_PIXEL_COUNTERS_MASK   CSI_CR226_PIXEL_COUNTERS_MASK
#define	CSI_CSICR226_PIXEL_COUNTERS_SHIFT   CSI_CR226_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR226_PIXEL_COUNTERS(x)
#define	CSI_CSICR227_PIXEL_COUNTERS_MASK   CSI_CR227_PIXEL_COUNTERS_MASK
#define	CSI_CSICR227_PIXEL_COUNTERS_SHIFT   CSI_CR227_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR227_PIXEL_COUNTERS(x)
#define	CSI_CSICR228_PIXEL_COUNTERS_MASK   CSI_CR228_PIXEL_COUNTERS_MASK
#define	CSI_CSICR228_PIXEL_COUNTERS_SHIFT   CSI_CR228_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR228_PIXEL_COUNTERS(x)
#define	CSI_CSICR229_PIXEL_COUNTERS_MASK   CSI_CR229_PIXEL_COUNTERS_MASK
#define	CSI_CSICR229_PIXEL_COUNTERS_SHIFT   CSI_CR229_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR229_PIXEL_COUNTERS(x)
#define	CSI_CSICR230_PIXEL_COUNTERS_MASK   CSI_CR230_PIXEL_COUNTERS_MASK
#define	CSI_CSICR230_PIXEL_COUNTERS_SHIFT   CSI_CR230_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR230_PIXEL_COUNTERS(x)
#define	CSI_CSICR231_PIXEL_COUNTERS_MASK   CSI_CR231_PIXEL_COUNTERS_MASK
#define	CSI_CSICR231_PIXEL_COUNTERS_SHIFT   CSI_CR231_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR231_PIXEL_COUNTERS(x)
#define	CSI_CSICR232_PIXEL_COUNTERS_MASK   CSI_CR232_PIXEL_COUNTERS_MASK
#define	CSI_CSICR232_PIXEL_COUNTERS_SHIFT   CSI_CR232_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR232_PIXEL_COUNTERS(x)
#define	CSI_CSICR233_PIXEL_COUNTERS_MASK   CSI_CR233_PIXEL_COUNTERS_MASK
#define	CSI_CSICR233_PIXEL_COUNTERS_SHIFT   CSI_CR233_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR233_PIXEL_COUNTERS(x)
#define	CSI_CSICR234_PIXEL_COUNTERS_MASK   CSI_CR234_PIXEL_COUNTERS_MASK
#define	CSI_CSICR234_PIXEL_COUNTERS_SHIFT   CSI_CR234_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR234_PIXEL_COUNTERS(x)
#define	CSI_CSICR235_PIXEL_COUNTERS_MASK   CSI_CR235_PIXEL_COUNTERS_MASK
#define	CSI_CSICR235_PIXEL_COUNTERS_SHIFT   CSI_CR235_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR235_PIXEL_COUNTERS(x)
#define	CSI_CSICR236_PIXEL_COUNTERS_MASK   CSI_CR236_PIXEL_COUNTERS_MASK
#define	CSI_CSICR236_PIXEL_COUNTERS_SHIFT   CSI_CR236_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR236_PIXEL_COUNTERS(x)
#define	CSI_CSICR237_PIXEL_COUNTERS_MASK   CSI_CR237_PIXEL_COUNTERS_MASK
#define	CSI_CSICR237_PIXEL_COUNTERS_SHIFT   CSI_CR237_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR237_PIXEL_COUNTERS(x)
#define	CSI_CSICR238_PIXEL_COUNTERS_MASK   CSI_CR238_PIXEL_COUNTERS_MASK
#define	CSI_CSICR238_PIXEL_COUNTERS_SHIFT   CSI_CR238_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR238_PIXEL_COUNTERS(x)
#define	CSI_CSICR239_PIXEL_COUNTERS_MASK   CSI_CR239_PIXEL_COUNTERS_MASK
#define	CSI_CSICR239_PIXEL_COUNTERS_SHIFT   CSI_CR239_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR239_PIXEL_COUNTERS(x)
#define	CSI_CSICR240_PIXEL_COUNTERS_MASK   CSI_CR240_PIXEL_COUNTERS_MASK
#define	CSI_CSICR240_PIXEL_COUNTERS_SHIFT   CSI_CR240_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR240_PIXEL_COUNTERS(x)
#define	CSI_CSICR241_PIXEL_COUNTERS_MASK   CSI_CR241_PIXEL_COUNTERS_MASK
#define	CSI_CSICR241_PIXEL_COUNTERS_SHIFT   CSI_CR241_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR241_PIXEL_COUNTERS(x)
#define	CSI_CSICR242_PIXEL_COUNTERS_MASK   CSI_CR242_PIXEL_COUNTERS_MASK
#define	CSI_CSICR242_PIXEL_COUNTERS_SHIFT   CSI_CR242_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR242_PIXEL_COUNTERS(x)
#define	CSI_CSICR243_PIXEL_COUNTERS_MASK   CSI_CR243_PIXEL_COUNTERS_MASK
#define	CSI_CSICR243_PIXEL_COUNTERS_SHIFT   CSI_CR243_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR243_PIXEL_COUNTERS(x)
#define	CSI_CSICR244_PIXEL_COUNTERS_MASK   CSI_CR244_PIXEL_COUNTERS_MASK
#define	CSI_CSICR244_PIXEL_COUNTERS_SHIFT   CSI_CR244_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR244_PIXEL_COUNTERS(x)
#define	CSI_CSICR245_PIXEL_COUNTERS_MASK   CSI_CR245_PIXEL_COUNTERS_MASK
#define	CSI_CSICR245_PIXEL_COUNTERS_SHIFT   CSI_CR245_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR245_PIXEL_COUNTERS(x)
#define	CSI_CSICR246_PIXEL_COUNTERS_MASK   CSI_CR246_PIXEL_COUNTERS_MASK
#define	CSI_CSICR246_PIXEL_COUNTERS_SHIFT   CSI_CR246_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR246_PIXEL_COUNTERS(x)
#define	CSI_CSICR247_PIXEL_COUNTERS_MASK   CSI_CR247_PIXEL_COUNTERS_MASK
#define	CSI_CSICR247_PIXEL_COUNTERS_SHIFT   CSI_CR247_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR247_PIXEL_COUNTERS(x)
#define	CSI_CSICR248_PIXEL_COUNTERS_MASK   CSI_CR248_PIXEL_COUNTERS_MASK
#define	CSI_CSICR248_PIXEL_COUNTERS_SHIFT   CSI_CR248_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR248_PIXEL_COUNTERS(x)
#define	CSI_CSICR249_PIXEL_COUNTERS_MASK   CSI_CR249_PIXEL_COUNTERS_MASK
#define	CSI_CSICR249_PIXEL_COUNTERS_SHIFT   CSI_CR249_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR249_PIXEL_COUNTERS(x)
#define	CSI_CSICR250_PIXEL_COUNTERS_MASK   CSI_CR250_PIXEL_COUNTERS_MASK
#define	CSI_CSICR250_PIXEL_COUNTERS_SHIFT   CSI_CR250_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR250_PIXEL_COUNTERS(x)
#define	CSI_CSICR251_PIXEL_COUNTERS_MASK   CSI_CR251_PIXEL_COUNTERS_MASK
#define	CSI_CSICR251_PIXEL_COUNTERS_SHIFT   CSI_CR251_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR251_PIXEL_COUNTERS(x)
#define	CSI_CSICR252_PIXEL_COUNTERS_MASK   CSI_CR252_PIXEL_COUNTERS_MASK
#define	CSI_CSICR252_PIXEL_COUNTERS_SHIFT   CSI_CR252_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR252_PIXEL_COUNTERS(x)
#define	CSI_CSICR253_PIXEL_COUNTERS_MASK   CSI_CR253_PIXEL_COUNTERS_MASK
#define	CSI_CSICR253_PIXEL_COUNTERS_SHIFT   CSI_CR253_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR253_PIXEL_COUNTERS(x)
#define	CSI_CSICR254_PIXEL_COUNTERS_MASK   CSI_CR254_PIXEL_COUNTERS_MASK
#define	CSI_CSICR254_PIXEL_COUNTERS_SHIFT   CSI_CR254_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR254_PIXEL_COUNTERS(x)
#define	CSI_CSICR255_PIXEL_COUNTERS_MASK   CSI_CR255_PIXEL_COUNTERS_MASK
#define	CSI_CSICR255_PIXEL_COUNTERS_SHIFT   CSI_CR255_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR255_PIXEL_COUNTERS(x)
#define	CSI_CSICR256_PIXEL_COUNTERS_MASK   CSI_CR256_PIXEL_COUNTERS_MASK
#define	CSI_CSICR256_PIXEL_COUNTERS_SHIFT   CSI_CR256_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR256_PIXEL_COUNTERS(x)
#define	CSI_CSICR257_PIXEL_COUNTERS_MASK   CSI_CR257_PIXEL_COUNTERS_MASK
#define	CSI_CSICR257_PIXEL_COUNTERS_SHIFT   CSI_CR257_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR257_PIXEL_COUNTERS(x)
#define	CSI_CSICR258_PIXEL_COUNTERS_MASK   CSI_CR258_PIXEL_COUNTERS_MASK
#define	CSI_CSICR258_PIXEL_COUNTERS_SHIFT   CSI_CR258_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR258_PIXEL_COUNTERS(x)
#define	CSI_CSICR259_PIXEL_COUNTERS_MASK   CSI_CR259_PIXEL_COUNTERS_MASK
#define	CSI_CSICR259_PIXEL_COUNTERS_SHIFT   CSI_CR259_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR259_PIXEL_COUNTERS(x)
#define	CSI_CSICR260_PIXEL_COUNTERS_MASK   CSI_CR260_PIXEL_COUNTERS_MASK
#define	CSI_CSICR260_PIXEL_COUNTERS_SHIFT   CSI_CR260_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR260_PIXEL_COUNTERS(x)
#define	CSI_CSICR261_PIXEL_COUNTERS_MASK   CSI_CR261_PIXEL_COUNTERS_MASK
#define	CSI_CSICR261_PIXEL_COUNTERS_SHIFT   CSI_CR261_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR261_PIXEL_COUNTERS(x)
#define	CSI_CSICR262_PIXEL_COUNTERS_MASK   CSI_CR262_PIXEL_COUNTERS_MASK
#define	CSI_CSICR262_PIXEL_COUNTERS_SHIFT   CSI_CR262_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR262_PIXEL_COUNTERS(x)
#define	CSI_CSICR263_PIXEL_COUNTERS_MASK   CSI_CR263_PIXEL_COUNTERS_MASK
#define	CSI_CSICR263_PIXEL_COUNTERS_SHIFT   CSI_CR263_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR263_PIXEL_COUNTERS(x)
#define	CSI_CSICR264_PIXEL_COUNTERS_MASK   CSI_CR264_PIXEL_COUNTERS_MASK
#define	CSI_CSICR264_PIXEL_COUNTERS_SHIFT   CSI_CR264_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR264_PIXEL_COUNTERS(x)
#define	CSI_CSICR265_PIXEL_COUNTERS_MASK   CSI_CR265_PIXEL_COUNTERS_MASK
#define	CSI_CSICR265_PIXEL_COUNTERS_SHIFT   CSI_CR265_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR265_PIXEL_COUNTERS(x)
#define	CSI_CSICR266_PIXEL_COUNTERS_MASK   CSI_CR266_PIXEL_COUNTERS_MASK
#define	CSI_CSICR266_PIXEL_COUNTERS_SHIFT   CSI_CR266_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR266_PIXEL_COUNTERS(x)
#define	CSI_CSICR267_PIXEL_COUNTERS_MASK   CSI_CR267_PIXEL_COUNTERS_MASK
#define	CSI_CSICR267_PIXEL_COUNTERS_SHIFT   CSI_CR267_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR267_PIXEL_COUNTERS(x)
#define	CSI_CSICR268_PIXEL_COUNTERS_MASK   CSI_CR268_PIXEL_COUNTERS_MASK
#define	CSI_CSICR268_PIXEL_COUNTERS_SHIFT   CSI_CR268_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR268_PIXEL_COUNTERS(x)
#define	CSI_CSICR269_PIXEL_COUNTERS_MASK   CSI_CR269_PIXEL_COUNTERS_MASK
#define	CSI_CSICR269_PIXEL_COUNTERS_SHIFT   CSI_CR269_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR269_PIXEL_COUNTERS(x)
#define	CSI_CSICR270_PIXEL_COUNTERS_MASK   CSI_CR270_PIXEL_COUNTERS_MASK
#define	CSI_CSICR270_PIXEL_COUNTERS_SHIFT   CSI_CR270_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR270_PIXEL_COUNTERS(x)
#define	CSI_CSICR271_PIXEL_COUNTERS_MASK   CSI_CR271_PIXEL_COUNTERS_MASK
#define	CSI_CSICR271_PIXEL_COUNTERS_SHIFT   CSI_CR271_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR271_PIXEL_COUNTERS(x)
#define	CSI_CSICR272_PIXEL_COUNTERS_MASK   CSI_CR272_PIXEL_COUNTERS_MASK
#define	CSI_CSICR272_PIXEL_COUNTERS_SHIFT   CSI_CR272_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR272_PIXEL_COUNTERS(x)
#define	CSI_CSICR273_PIXEL_COUNTERS_MASK   CSI_CR273_PIXEL_COUNTERS_MASK
#define	CSI_CSICR273_PIXEL_COUNTERS_SHIFT   CSI_CR273_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR273_PIXEL_COUNTERS(x)
#define	CSI_CSICR274_PIXEL_COUNTERS_MASK   CSI_CR274_PIXEL_COUNTERS_MASK
#define	CSI_CSICR274_PIXEL_COUNTERS_SHIFT   CSI_CR274_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR274_PIXEL_COUNTERS(x)
#define	CSI_CSICR275_PIXEL_COUNTERS_MASK   CSI_CR275_PIXEL_COUNTERS_MASK
#define	CSI_CSICR275_PIXEL_COUNTERS_SHIFT   CSI_CR275_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR275_PIXEL_COUNTERS(x)
#define	CSI_CSICR276_PIXEL_COUNTERS_MASK   CSI_CR276_PIXEL_COUNTERS_MASK
#define	CSI_CSICR276_PIXEL_COUNTERS_SHIFT   CSI_CR276_PIXEL_COUNTERS_SHIFT
#define	CSI_CSICR276_PIXEL_COUNTERS(x)
#define	DAC_BASE   (0x40064000u)
#define	DAC   ((DAC_Type *)DAC_BASE)
#define	DAC_BASE_ADDRS   { DAC_BASE }
#define	DAC_BASE_PTRS   { DAC }
#define	DAC_IRQS   { DAC_IRQn }
#define	DCDC_BASE   (0x40CA8000u)
#define	DCDC   ((DCDC_Type *)DCDC_BASE)
#define	DCDC_BASE_ADDRS   { DCDC_BASE }
#define	DCDC_BASE_PTRS   { DCDC }
#define	DCIC_DCICRC_COUNT   (16U)
#define	DCIC_DCICRS_COUNT   (16U)
#define	DCIC_DCICRRS_COUNT   (16U)
#define	DCIC_DCICRCS_COUNT   (16U)
#define	DCIC1_BASE   (0x40819000u)
#define	DCIC1   ((DCIC_Type *)DCIC1_BASE)
#define	DCIC2_BASE   (0x4081A000u)
#define	DCIC2   ((DCIC_Type *)DCIC2_BASE)
#define	DCIC_BASE_ADDRS   { 0u, DCIC1_BASE, DCIC2_BASE }
#define	DCIC_BASE_PTRS   { (DCIC_Type *)0u, DCIC1, DCIC2 }
#define	DMA_SADDR_COUNT   (32U)
#define	DMA_SOFF_COUNT   (32U)
#define	DMA_ATTR_COUNT   (32U)
#define	DMA_NBYTES_MLNO_COUNT   (32U)
#define	DMA_NBYTES_MLOFFNO_COUNT   (32U)
#define	DMA_NBYTES_MLOFFYES_COUNT   (32U)
#define	DMA_SLAST_COUNT   (32U)
#define	DMA_DADDR_COUNT   (32U)
#define	DMA_DOFF_COUNT   (32U)
#define	DMA_CITER_ELINKNO_COUNT   (32U)
#define	DMA_CITER_ELINKYES_COUNT   (32U)
#define	DMA_DLAST_SGA_COUNT   (32U)
#define	DMA_CSR_COUNT   (32U)
#define	DMA_BITER_ELINKNO_COUNT   (32U)
#define	DMA_BITER_ELINKYES_COUNT   (32U)
#define	DMA1_BASE   (0x40C14000u)
#define	DMA1   ((DMA_Type *)DMA1_BASE)
#define	DMA_BASE_ADDRS   { 0u, DMA1_BASE }
#define	DMA_BASE_PTRS   { (DMA_Type *)0u, DMA1 }
#define	DMA_CHN_IRQS
#define	DMA_ERROR_IRQS   { NotAvail_IRQn, DMA_ERROR_IRQn }
#define	DMAMUX_CHCFG_COUNT   (32U)
#define	DMAMUX1_BASE   (0x40C18000u)
#define	DMAMUX1   ((DMAMUX_Type *)DMAMUX1_BASE)
#define	DMAMUX_BASE_ADDRS   { 0u, DMAMUX1_BASE }
#define	DMAMUX_BASE_PTRS   { (DMAMUX_Type *)0u, DMAMUX1 }
#define	DSI_HOST_BASE   (0x4080C000u)
#define	DSI_HOST   ((DSI_HOST_Type *)DSI_HOST_BASE)
#define	DSI_HOST_BASE_ADDRS   { DSI_HOST_BASE }
#define	DSI_HOST_BASE_PTRS   { DSI_HOST }
#define	DSI_HOST_DSI_IRQS   { MIPI_DSI_IRQn }
#define	DSI_HOST_APB_PKT_IF_BASE   (0x4080C280u)
#define	DSI_HOST_APB_PKT_IF   ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE)
#define	DSI_HOST_APB_PKT_IF_BASE_ADDRS   { DSI_HOST_APB_PKT_IF_BASE }
#define	DSI_HOST_APB_PKT_IF_BASE_PTRS   { DSI_HOST_APB_PKT_IF }
#define	DSI_HOST_DPI_INTFC_BASE   (0x4080C200u)
#define	DSI_HOST_DPI_INTFC   ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE)
#define	DSI_HOST_DPI_INTFC_BASE_ADDRS   { DSI_HOST_DPI_INTFC_BASE }
#define	DSI_HOST_DPI_INTFC_BASE_PTRS   { DSI_HOST_DPI_INTFC }
#define	DSI_HOST_DPHY_INTFC_BASE   (0x4080C300u)
#define	DSI_HOST_DPHY_INTFC   ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS   { DSI_HOST_DPHY_INTFC_BASE }
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS   { DSI_HOST_DPHY_INTFC }
#define	EMVSIM1_BASE   (0x40154000u)
#define	EMVSIM1   ((EMVSIM_Type *)EMVSIM1_BASE)
#define	EMVSIM2_BASE   (0x40158000u)
#define	EMVSIM2   ((EMVSIM_Type *)EMVSIM2_BASE)
#define	EMVSIM_BASE_ADDRS   { 0u, EMVSIM1_BASE, EMVSIM2_BASE }
#define	EMVSIM_BASE_PTRS   { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 }
#define	EMVSIM_IRQS   { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn }
#define	ENC1_BASE   (0x40174000u)
#define	ENC1   ((ENC_Type *)ENC1_BASE)
#define	ENC2_BASE   (0x40178000u)
#define	ENC2   ((ENC_Type *)ENC2_BASE)
#define	ENC3_BASE   (0x4017C000u)
#define	ENC3   ((ENC_Type *)ENC3_BASE)
#define	ENC4_BASE   (0x40180000u)
#define	ENC4   ((ENC_Type *)ENC4_BASE)
#define	ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
#define	ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
#define	ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_HOME_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_WDOG_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INDEX_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INPUT_SWITCH_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENET_TXIC_COUNT   (3U)
#define	ENET_RXIC_COUNT   (3U)
#define	ENET_RCMR_COUNT   (2U)
#define	ENET_DMACFG_COUNT   (2U)
#define	ENET_TCSR_COUNT   (4U)
#define	ENET_TCCR_COUNT   (4U)
#define	ENET_BASE   (0x40424000u)
#define	ENET   ((ENET_Type *)ENET_BASE)
#define	ENET_1G_BASE   (0x40420000u)
#define	ENET_1G   ((ENET_Type *)ENET_1G_BASE)
#define	ENET_BASE_ADDRS   { ENET_BASE, ENET_1G_BASE }
#define	ENET_BASE_PTRS   { ENET, ENET_1G }
#define	ENET_Transmit_IRQS   { ENET_IRQn, ENET_1G_IRQn }
#define	ENET_Receive_IRQS   { ENET_IRQn, ENET_1G_IRQn }
#define	ENET_Error_IRQS   { ENET_IRQn, ENET_1G_IRQn }
#define	ENET_1588_Timer_IRQS   { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn }
#define	ENET_Ts_IRQS   { ENET_IRQn, ENET_1G_IRQn }
#define	ENET_BUFF_ALIGNMENT   (64U)
#define	ETHERNET_PLL_BASE   (0u)
#define	ETHERNET_PLL   ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE)
#define	ETHERNET_PLL_BASE_ADDRS   { ETHERNET_PLL_BASE }
#define	ETHERNET_PLL_BASE_PTRS   { ETHERNET_PLL }
#define	EWM_BASE   (0x4002C000u)
#define	EWM   ((EWM_Type *)EWM_BASE)
#define	EWM_BASE_ADDRS   { EWM_BASE }
#define	EWM_BASE_PTRS   { EWM }
#define	EWM_IRQS   { EWM_IRQn }
#define	FLEXIO_SHIFTCTL_COUNT   (8U)
#define	FLEXIO_SHIFTCFG_COUNT   (8U)
#define	FLEXIO_SHIFTBUF_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBIS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBYS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBBS_COUNT   (8U)
#define	FLEXIO_TIMCTL_COUNT   (8U)
#define	FLEXIO_TIMCFG_COUNT   (8U)
#define	FLEXIO_TIMCMP_COUNT   (8U)
#define	FLEXIO_SHIFTBUFNBS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFHWS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFNIS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFOES_COUNT   (8U)
#define	FLEXIO_SHIFTBUFEOS_COUNT   (8U)
#define	FLEXIO1_BASE   (0x400AC000u)
#define	FLEXIO1   ((FLEXIO_Type *)FLEXIO1_BASE)
#define	FLEXIO2_BASE   (0x400B0000u)
#define	FLEXIO2   ((FLEXIO_Type *)FLEXIO2_BASE)
#define	FLEXIO_BASE_ADDRS   { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
#define	FLEXIO_BASE_PTRS   { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
#define	FLEXIO_IRQS   { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
#define	FLEXRAM_BASE   (0x40028000u)
#define	FLEXRAM   ((FLEXRAM_Type *)FLEXRAM_BASE)
#define	FLEXRAM_BASE_ADDRS   { FLEXRAM_BASE }
#define	FLEXRAM_BASE_PTRS   { FLEXRAM }
#define	FLEXRAM_ECC_IRQS   { FLEXRAM_ECC_IRQn }
#define	FLEXSPI_AHBRXBUFCR0_COUNT   (8U)
#define	FLEXSPI_FLSHCR0_COUNT   (4U)
#define	FLEXSPI_FLSHCR1_COUNT   (4U)
#define	FLEXSPI_FLSHCR2_COUNT   (4U)
#define	FLEXSPI_DLLCR_COUNT   (2U)
#define	FLEXSPI_RFDR_COUNT   (32U)
#define	FLEXSPI_TFDR_COUNT   (32U)
#define	FLEXSPI_LUT_COUNT   (64U)
#define	FLEXSPI_HMSTRCR_COUNT   (8U)
#define	FLEXSPI1_BASE   (0x400CC000u)
#define	FLEXSPI1   ((FLEXSPI_Type *)FLEXSPI1_BASE)
#define	FLEXSPI2_BASE   (0x400D0000u)
#define	FLEXSPI2   ((FLEXSPI_Type *)FLEXSPI2_BASE)
#define	FLEXSPI_BASE_ADDRS   { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
#define	FLEXSPI_BASE_PTRS   { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
#define	FLEXSPI_IRQS   { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
#define	FlexSPI1_AMBA_BASE   (0x30000000U)
#define	FlexSPI1_ASFM_BASE   (0x30000000U)
#define	FlexSPI1_ARDF_BASE   (0x2FC00000U)
#define	FlexSPI1_ATDF_BASE   (0x2F800000U)
#define	FlexSPI1_ALIAS_BASE   (0x8000000U)
#define	FlexSPI2_AMBA_BASE   (0x60000000U)
#define	FlexSPI2_ASFM_BASE   (0x60000000U)
#define	FlexSPI2_ARDF_BASE   (0x7FC00000U)
#define	FlexSPI2_ATDF_BASE   (0x7F800000U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT   (8U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT   (8U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT   (16U)
#define	GPC_CPU_MODE_CTRL_0_BASE   (0x40C00000u)
#define	GPC_CPU_MODE_CTRL_0   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
#define	GPC_CPU_MODE_CTRL_1_BASE   (0x40C00800u)
#define	GPC_CPU_MODE_CTRL_1   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
#define	GPC_CPU_MODE_CTRL_BASE_ADDRS   { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
#define	GPC_CPU_MODE_CTRL_BASE_PTRS   { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
#define	GPC_SET_POINT_CTRL_BASE   (0x40C02000u)
#define	GPC_SET_POINT_CTRL   ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE)
#define	GPC_SET_POINT_CTRL_BASE_ADDRS   { GPC_SET_POINT_CTRL_BASE }
#define	GPC_SET_POINT_CTRL_BASE_PTRS   { GPC_SET_POINT_CTRL }
#define	GPC_STBY_CTRL_BASE   (0x40C02800u)
#define	GPC_STBY_CTRL   ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE)
#define	GPC_STBY_CTRL_BASE_ADDRS   { GPC_STBY_CTRL_BASE }
#define	GPC_STBY_CTRL_BASE_PTRS   { GPC_STBY_CTRL }
#define	GPIO1_BASE   (0x4012C000u)
#define	GPIO1   ((GPIO_Type *)GPIO1_BASE)
#define	GPIO2_BASE   (0x40130000u)
#define	GPIO2   ((GPIO_Type *)GPIO2_BASE)
#define	GPIO3_BASE   (0x40134000u)
#define	GPIO3   ((GPIO_Type *)GPIO3_BASE)
#define	GPIO4_BASE   (0x40138000u)
#define	GPIO4   ((GPIO_Type *)GPIO4_BASE)
#define	GPIO5_BASE   (0x4013C000u)
#define	GPIO5   ((GPIO_Type *)GPIO5_BASE)
#define	GPIO6_BASE   (0x40140000u)
#define	GPIO6   ((GPIO_Type *)GPIO6_BASE)
#define	GPIO7_BASE   (0x40C5C000u)
#define	GPIO7   ((GPIO_Type *)GPIO7_BASE)
#define	GPIO8_BASE   (0x40C60000u)
#define	GPIO8   ((GPIO_Type *)GPIO8_BASE)
#define	GPIO9_BASE   (0x40C64000u)
#define	GPIO9   ((GPIO_Type *)GPIO9_BASE)
#define	GPIO10_BASE   (0x40C68000u)
#define	GPIO10   ((GPIO_Type *)GPIO10_BASE)
#define	GPIO11_BASE   (0x40C6C000u)
#define	GPIO11   ((GPIO_Type *)GPIO11_BASE)
#define	GPIO12_BASE   (0x40C70000u)
#define	GPIO12   ((GPIO_Type *)GPIO12_BASE)
#define	GPIO13_BASE   (0x40CA0000u)
#define	GPIO13   ((GPIO_Type *)GPIO13_BASE)
#define	CM7_GPIO2_BASE   (0x42008000u)
#define	CM7_GPIO2   ((GPIO_Type *)CM7_GPIO2_BASE)
#define	CM7_GPIO3_BASE   (0x4200C000u)
#define	CM7_GPIO3   ((GPIO_Type *)CM7_GPIO3_BASE)
#define	GPIO_BASE_ADDRS   { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE }
#define	GPIO_BASE_PTRS   { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 }
#define	GPIO_COMBINED_LOW_IRQS   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, NotAvail_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO12_Combined_0_15_IRQn, GPIO13_Combined_0_31_IRQn, NotAvail_IRQn, NotAvail_IRQn }
#define	GPIO_COMBINED_HIGH_IRQS   { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, NotAvail_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO12_Combined_16_31_IRQn, GPIO13_Combined_0_31_IRQn, NotAvail_IRQn, NotAvail_IRQn }
#define	GPT_OCR_COUNT   (3U)
#define	GPT_ICR_COUNT   (2U)
#define	GPT1_BASE   (0x400EC000u)
#define	GPT1   ((GPT_Type *)GPT1_BASE)
#define	GPT2_BASE   (0x400F0000u)
#define	GPT2   ((GPT_Type *)GPT2_BASE)
#define	GPT3_BASE   (0x400F4000u)
#define	GPT3   ((GPT_Type *)GPT3_BASE)
#define	GPT4_BASE   (0x400F8000u)
#define	GPT4   ((GPT_Type *)GPT4_BASE)
#define	GPT5_BASE   (0x400FC000u)
#define	GPT5   ((GPT_Type *)GPT5_BASE)
#define	GPT6_BASE   (0x40100000u)
#define	GPT6   ((GPT_Type *)GPT6_BASE)
#define	GPT_BASE_ADDRS   { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
#define	GPT_BASE_PTRS   { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
#define	GPT_IRQS   { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
#define	I2S_TDR_COUNT   (4U)
#define	I2S_TFR_COUNT   (4U)
#define	I2S_RDR_COUNT   (4U)
#define	I2S_RFR_COUNT   (4U)
#define	SAI1_BASE   (0x40404000u)
#define	SAI1   ((I2S_Type *)SAI1_BASE)
#define	SAI2_BASE   (0x40408000u)
#define	SAI2   ((I2S_Type *)SAI2_BASE)
#define	SAI3_BASE   (0x4040C000u)
#define	SAI3   ((I2S_Type *)SAI3_BASE)
#define	SAI4_BASE   (0x40C40000u)
#define	SAI4   ((I2S_Type *)SAI4_BASE)
#define	I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
#define	I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
#define	I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
#define	I2S_TX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
#define	IEE_REGATTR_COUNT   (8U)
#define	IEE_REGPO_COUNT   (8U)
#define	IEE_REGKEY1_COUNT   (8U)
#define	IEE_REGKEY1_COUNT2   (8U)
#define	IEE_REGKEY2_COUNT   (8U)
#define	IEE_REGKEY2_COUNT2   (8U)
#define	IEE_AES_TST_DB_COUNT   (32U)
#define	IEE__IEE_RT1170_BASE   (0x4006C000u)
#define	IEE__IEE_RT1170   ((IEE_Type *)IEE__IEE_RT1170_BASE)
#define	IEE_BASE_ADDRS   { IEE__IEE_RT1170_BASE }
#define	IEE_BASE_PTRS   { IEE__IEE_RT1170 }
#define	IEE_APC_BASE   (0x40068000u)
#define	IEE_APC   ((IEE_APC_Type *)IEE_APC_BASE)
#define	IEE_APC_BASE_ADDRS   { IEE_APC_BASE }
#define	IEE_APC_BASE_PTRS   { IEE_APC }
#define	IOMUXC_SW_MUX_CTL_PAD_COUNT   (145U)
#define	IOMUXC_SW_PAD_CTL_PAD_COUNT   (145U)
#define	IOMUXC_SELECT_INPUT_COUNT   (160U)
#define	IOMUXC_BASE   (0x400E8000u)
#define	IOMUXC   ((IOMUXC_Type *)IOMUXC_BASE)
#define	IOMUXC_BASE_ADDRS   { IOMUXC_BASE }
#define	IOMUXC_BASE_PTRS   { IOMUXC }
#define	IOMUXC_GPR_BASE   (0x400E4000u)
#define	IOMUXC_GPR   ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
#define	IOMUXC_GPR_BASE_ADDRS   { IOMUXC_GPR_BASE }
#define	IOMUXC_GPR_BASE_PTRS   { IOMUXC_GPR }
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT   (16U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT   (16U)
#define	IOMUXC_LPSR_SELECT_INPUT_COUNT   (24U)
#define	IOMUXC_LPSR_BASE   (0x40C08000u)
#define	IOMUXC_LPSR   ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
#define	IOMUXC_LPSR_BASE_ADDRS   { IOMUXC_LPSR_BASE }
#define	IOMUXC_LPSR_BASE_PTRS   { IOMUXC_LPSR }
#define	IOMUXC_LPSR_GPR_BASE   (0x40C0C000u)
#define	IOMUXC_LPSR_GPR   ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
#define	IOMUXC_LPSR_GPR_BASE_ADDRS   { IOMUXC_LPSR_GPR_BASE }
#define	IOMUXC_LPSR_GPR_BASE_PTRS   { IOMUXC_LPSR_GPR }
#define	IOMUXC_SNVS_BASE   (0x40C94000u)
#define	IOMUXC_SNVS   ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
#define	IOMUXC_SNVS_BASE_ADDRS   { IOMUXC_SNVS_BASE }
#define	IOMUXC_SNVS_BASE_PTRS   { IOMUXC_SNVS }
#define	IOMUXC_SNVS_GPR_GPR_COUNT   (32U)
#define	IOMUXC_SNVS_GPR_BASE   (0x40C98000u)
#define	IOMUXC_SNVS_GPR   ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
#define	IOMUXC_SNVS_GPR_BASE_ADDRS   { IOMUXC_SNVS_GPR_BASE }
#define	IOMUXC_SNVS_GPR_BASE_PTRS   { IOMUXC_SNVS_GPR }
#define	IPS_DOMAIN_SLOT_CTRL_COUNT   (38U)
#define	IPS_DOMAIN_BASE   (0x40C87C00u)
#define	IPS_DOMAIN   ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE)
#define	IPS_DOMAIN_BASE_ADDRS   { IPS_DOMAIN_BASE }
#define	IPS_DOMAIN_BASE_PTRS   { IPS_DOMAIN }
#define	KEY_MANAGER_BASE   (0x40C80000u)
#define	KEY_MANAGER   ((KEY_MANAGER_Type *)KEY_MANAGER_BASE)
#define	KEY_MANAGER_BASE_ADDRS   { KEY_MANAGER_BASE }
#define	KEY_MANAGER_BASE_PTRS   { KEY_MANAGER }
#define	KPP_BASE   (0x400E0000u)
#define	KPP   ((KPP_Type *)KPP_BASE)
#define	KPP_BASE_ADDRS   { KPP_BASE }
#define	KPP_BASE_PTRS   { KPP }
#define	KPP_IRQS   { KPP_IRQn }
#define	LCDIF_PIGEON_0_COUNT   (12U)
#define	LCDIF_PIGEON_1_COUNT   (12U)
#define	LCDIF_PIGEON_2_COUNT   (12U)
#define	LCDIF_BASE   (0x40804000u)
#define	LCDIF   ((LCDIF_Type *)LCDIF_BASE)
#define	LCDIF_BASE_ADDRS   { LCDIF_BASE }
#define	LCDIF_BASE_PTRS   { LCDIF }
#define	LCDIF_IRQ0_IRQS   { eLCDIF_IRQn }
#define	LCDIFV2_INT_STATUS_COUNT   (2U)
#define	LCDIFV2_INT_ENABLE_COUNT   (2U)
#define	LCDIFV2_CTRLDESCL1_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL2_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL3_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL4_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL5_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL6_COUNT   (8U)
#define	LCDIFV2_CSC_COEF0_COUNT   (8U)
#define	LCDIFV2_CSC_COEF1_COUNT   (8U)
#define	LCDIFV2_CSC_COEF2_COUNT   (8U)
#define	LCDIFV2_BASE   (0x40808000u)
#define	LCDIFV2   ((LCDIFV2_Type *)LCDIFV2_BASE)
#define	LCDIFV2_BASE_ADDRS   { LCDIFV2_BASE }
#define	LCDIFV2_BASE_PTRS   { LCDIFV2 }
#define	LMEM_BASE   (0xE0082000u)
#define	LMEM   ((LMEM_Type *)LMEM_BASE)
#define	LMEM_BASE_ADDRS   { LMEM_BASE }
#define	LMEM_BASE_PTRS   { LMEM }
#define	LPI2C1_BASE   (0x40104000u)
#define	LPI2C1   ((LPI2C_Type *)LPI2C1_BASE)
#define	LPI2C2_BASE   (0x40108000u)
#define	LPI2C2   ((LPI2C_Type *)LPI2C2_BASE)
#define	LPI2C3_BASE   (0x4010C000u)
#define	LPI2C3   ((LPI2C_Type *)LPI2C3_BASE)
#define	LPI2C4_BASE   (0x40110000u)
#define	LPI2C4   ((LPI2C_Type *)LPI2C4_BASE)
#define	LPI2C5_BASE   (0x40C34000u)
#define	LPI2C5   ((LPI2C_Type *)LPI2C5_BASE)
#define	LPI2C6_BASE   (0x40C38000u)
#define	LPI2C6   ((LPI2C_Type *)LPI2C6_BASE)
#define	LPI2C_BASE_ADDRS   { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE }
#define	LPI2C_BASE_PTRS   { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 }
#define	LPI2C_IRQS   { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn }
#define	LPSPI1_BASE   (0x40114000u)
#define	LPSPI1   ((LPSPI_Type *)LPSPI1_BASE)
#define	LPSPI2_BASE   (0x40118000u)
#define	LPSPI2   ((LPSPI_Type *)LPSPI2_BASE)
#define	LPSPI3_BASE   (0x4011C000u)
#define	LPSPI3   ((LPSPI_Type *)LPSPI3_BASE)
#define	LPSPI4_BASE   (0x40120000u)
#define	LPSPI4   ((LPSPI_Type *)LPSPI4_BASE)
#define	LPSPI5_BASE   (0x40C2C000u)
#define	LPSPI5   ((LPSPI_Type *)LPSPI5_BASE)
#define	LPSPI6_BASE   (0x40C30000u)
#define	LPSPI6   ((LPSPI_Type *)LPSPI6_BASE)
#define	LPSPI_BASE_ADDRS   { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE }
#define	LPSPI_BASE_PTRS   { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 }
#define	LPSPI_IRQS   { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn }
#define	LPUART1_BASE   (0x4007C000u)
#define	LPUART1   ((LPUART_Type *)LPUART1_BASE)
#define	LPUART2_BASE   (0x40080000u)
#define	LPUART2   ((LPUART_Type *)LPUART2_BASE)
#define	LPUART3_BASE   (0x40084000u)
#define	LPUART3   ((LPUART_Type *)LPUART3_BASE)
#define	LPUART4_BASE   (0x40088000u)
#define	LPUART4   ((LPUART_Type *)LPUART4_BASE)
#define	LPUART5_BASE   (0x4008C000u)
#define	LPUART5   ((LPUART_Type *)LPUART5_BASE)
#define	LPUART6_BASE   (0x40090000u)
#define	LPUART6   ((LPUART_Type *)LPUART6_BASE)
#define	LPUART7_BASE   (0x40094000u)
#define	LPUART7   ((LPUART_Type *)LPUART7_BASE)
#define	LPUART8_BASE   (0x40098000u)
#define	LPUART8   ((LPUART_Type *)LPUART8_BASE)
#define	LPUART9_BASE   (0x4009C000u)
#define	LPUART9   ((LPUART_Type *)LPUART9_BASE)
#define	LPUART10_BASE   (0x400A0000u)
#define	LPUART10   ((LPUART_Type *)LPUART10_BASE)
#define	LPUART11_BASE   (0x40C24000u)
#define	LPUART11   ((LPUART_Type *)LPUART11_BASE)
#define	LPUART12_BASE   (0x40C28000u)
#define	LPUART12   ((LPUART_Type *)LPUART12_BASE)
#define	LPUART_BASE_ADDRS   { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE }
#define	LPUART_BASE_PTRS   { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 }
#define	LPUART_RX_TX_IRQS   { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn }
#define	MCM_LMDR_COUNT   (4U)
#define	MCM_BASE   (0xE0080000u)
#define	MCM   ((MCM_Type *)MCM_BASE)
#define	MCM_BASE_ADDRS   { MCM_BASE }
#define	MCM_BASE_PTRS   { MCM }
#define	MECC1_BASE   (0x40014000u)
#define	MECC1   ((MECC_Type *)MECC1_BASE)
#define	MECC2_BASE   (0x40018000u)
#define	MECC2   ((MECC_Type *)MECC2_BASE)
#define	MECC_BASE_ADDRS   { 0u, MECC1_BASE, MECC2_BASE }
#define	MECC_BASE_PTRS   { (MECC_Type *)0u, MECC1, MECC2 }
#define	MIPI_CSI2RX_BASE   (0x40810000u)
#define	MIPI_CSI2RX   ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
#define	MIPI_CSI2RX_BASE_ADDRS   { MIPI_CSI2RX_BASE }
#define	MIPI_CSI2RX_BASE_PTRS   { MIPI_CSI2RX }
#define	MMCAU_CA_COUNT   (9U)
#define	MMCAU_BASE   (0xE0081000u)
#define	MMCAU   ((MMCAU_Type *)MMCAU_BASE)
#define	MMCAU_BASE_ADDRS   { MMCAU_BASE }
#define	MMCAU_BASE_PTRS   { MMCAU }
#define	MU_TR_COUNT   (4U)
#define	MU_RR_COUNT   (4U)
#define	MUB_BASE   (0x40C4C000u)
#define	MUB   ((MU_Type *)MUB_BASE)
#define	MU_BASE_ADDRS   { MUB_BASE }
#define	MU_BASE_PTRS   { MUB }
#define	MU_IRQS   { MUB_IRQn }
#define	OCOTP_READ_FUSE_DATA_COUNT   (4U)
#define	OCOTP_FUSE_COUNT   (144U)
#define	OCOTP_BASE   (0x40CAC000u)
#define	OCOTP   ((OCOTP_Type *)OCOTP_BASE)
#define	OCOTP_BASE_ADDRS   { OCOTP_BASE }
#define	OCOTP_BASE_PTRS   { OCOTP }
#define	OSC_RC_400M_BASE   (0u)
#define	OSC_RC_400M   ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
#define	OSC_RC_400M_BASE_ADDRS   { OSC_RC_400M_BASE }
#define	OSC_RC_400M_BASE_PTRS   { OSC_RC_400M }
#define	OTFAD_KEY_COUNT   (4U)
#define	OTFAD_KEY_COUNT2   (4U)
#define	OTFAD_CTR_COUNT   (4U)
#define	OTFAD_CTR_COUNT2   (2U)
#define	OTFAD_RGD_W0_COUNT   (4U)
#define	OTFAD_RGD_W1_COUNT   (4U)
#define	OTFAD1_BASE   (0x400CC000u)
#define	OTFAD1   ((OTFAD_Type *)OTFAD1_BASE)
#define	OTFAD2_BASE   (0x400D0000u)
#define	OTFAD2   ((OTFAD_Type *)OTFAD2_BASE)
#define	OTFAD_BASE_ADDRS   { 0u, OTFAD1_BASE, OTFAD2_BASE }
#define	OTFAD_BASE_PTRS   { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
#define	PDM_DATACH_COUNT   (8U)
#define	PDM_BASE   (0x40C20000u)
#define	PDM   ((PDM_Type *)PDM_BASE)
#define	PDM_BASE_ADDRS   { PDM_BASE }
#define	PDM_BASE_PTRS   { PDM }
#define	PGMC_BPC0_BASE   (0x40C88000u)
#define	PGMC_BPC0   ((PGMC_BPC_Type *)PGMC_BPC0_BASE)
#define	PGMC_BPC1_BASE   (0x40C88200u)
#define	PGMC_BPC1   ((PGMC_BPC_Type *)PGMC_BPC1_BASE)
#define	PGMC_BPC2_BASE   (0x40C88400u)
#define	PGMC_BPC2   ((PGMC_BPC_Type *)PGMC_BPC2_BASE)
#define	PGMC_BPC3_BASE   (0x40C88600u)
#define	PGMC_BPC3   ((PGMC_BPC_Type *)PGMC_BPC3_BASE)
#define	PGMC_BPC4_BASE   (0x40C88800u)
#define	PGMC_BPC4   ((PGMC_BPC_Type *)PGMC_BPC4_BASE)
#define	PGMC_BPC5_BASE   (0x40C88A00u)
#define	PGMC_BPC5   ((PGMC_BPC_Type *)PGMC_BPC5_BASE)
#define	PGMC_BPC6_BASE   (0x40C88C00u)
#define	PGMC_BPC6   ((PGMC_BPC_Type *)PGMC_BPC6_BASE)
#define	PGMC_BPC7_BASE   (0x40C88E00u)
#define	PGMC_BPC7   ((PGMC_BPC_Type *)PGMC_BPC7_BASE)
#define	PGMC_BPC_BASE_ADDRS   { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE }
#define	PGMC_BPC_BASE_PTRS   { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 }
#define	PGMC_CPC0_BASE   (0x40C89000u)
#define	PGMC_CPC0   ((PGMC_CPC_Type *)PGMC_CPC0_BASE)
#define	PGMC_CPC1_BASE   (0x40C89400u)
#define	PGMC_CPC1   ((PGMC_CPC_Type *)PGMC_CPC1_BASE)
#define	PGMC_CPC_BASE_ADDRS   { PGMC_CPC0_BASE, PGMC_CPC1_BASE }
#define	PGMC_CPC_BASE_PTRS   { PGMC_CPC0, PGMC_CPC1 }
#define	PGMC_CPC0_MIF0_BASE   (0x40C89100u)
#define	PGMC_CPC0_MIF0   ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
#define	PGMC_CPC0_MIF1_BASE   (0x40C89200u)
#define	PGMC_CPC0_MIF1   ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
#define	PGMC_CPC1_MIF0_BASE   (0x40C89500u)
#define	PGMC_CPC1_MIF0   ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
#define	PGMC_CPC1_MIF1_BASE   (0x40C89600u)
#define	PGMC_CPC1_MIF1   ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
#define	PGMC_MIF_BASE_ADDRS   { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
#define	PGMC_MIF_BASE_PTRS   { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
#define	PGMC_PPC0_BASE   (0x40C8B000u)
#define	PGMC_PPC0   ((PGMC_PPC_Type *)PGMC_PPC0_BASE)
#define	PGMC_PPC_BASE_ADDRS   { PGMC_PPC0_BASE }
#define	PGMC_PPC_BASE_PTRS   { PGMC_PPC0 }
#define	PHY_LDO_BASE   (0u)
#define	PHY_LDO   ((PHY_LDO_Type *)PHY_LDO_BASE)
#define	PHY_LDO_BASE_ADDRS   { PHY_LDO_BASE }
#define	PHY_LDO_BASE_PTRS   { PHY_LDO }
#define	PIT_LDVAL_COUNT   (4U)
#define	PIT_CVAL_COUNT   (4U)
#define	PIT_TCTRL_COUNT   (4U)
#define	PIT_TFLG_COUNT   (4U)
#define	PIT1_BASE   (0x400D8000u)
#define	PIT1   ((PIT_Type *)PIT1_BASE)
#define	PIT2_BASE   (0x40CB0000u)
#define	PIT2   ((PIT_Type *)PIT2_BASE)
#define	PIT_BASE_ADDRS   { 0u, PIT1_BASE, PIT2_BASE }
#define	PIT_BASE_PTRS   { (PIT_Type *)0u, PIT1, PIT2 }
#define	PIT_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
#define	PUF_KEYMASK_COUNT   (2U)
#define	KEY_MANAGER__PUF_BASE   (0x40C82000u)
#define	KEY_MANAGER__PUF   ((PUF_Type *)KEY_MANAGER__PUF_BASE)
#define	PUF_BASE_ADDRS   { KEY_MANAGER__PUF_BASE }
#define	PUF_BASE_PTRS   { KEY_MANAGER__PUF }
#define	PWM_CNT_COUNT   (4U)
#define	PWM_INIT_COUNT   (4U)
#define	PWM_CTRL2_COUNT   (4U)
#define	PWM_CTRL_COUNT   (4U)
#define	PWM_VAL0_COUNT   (4U)
#define	PWM_FRACVAL1_COUNT   (4U)
#define	PWM_VAL1_COUNT   (4U)
#define	PWM_FRACVAL2_COUNT   (4U)
#define	PWM_VAL2_COUNT   (4U)
#define	PWM_FRACVAL3_COUNT   (4U)
#define	PWM_VAL3_COUNT   (4U)
#define	PWM_FRACVAL4_COUNT   (4U)
#define	PWM_VAL4_COUNT   (4U)
#define	PWM_FRACVAL5_COUNT   (4U)
#define	PWM_VAL5_COUNT   (4U)
#define	PWM_FRCTRL_COUNT   (4U)
#define	PWM_OCTRL_COUNT   (4U)
#define	PWM_STS_COUNT   (4U)
#define	PWM_INTEN_COUNT   (4U)
#define	PWM_DMAEN_COUNT   (4U)
#define	PWM_TCTRL_COUNT   (4U)
#define	PWM_DISMAP_COUNT   (4U)
#define	PWM_DISMAP_COUNT2   (1U)
#define	PWM_DTCNT0_COUNT   (4U)
#define	PWM_DTCNT1_COUNT   (4U)
#define	PWM_CAPTCTRLA_COUNT   (4U)
#define	PWM_CAPTCOMPA_COUNT   (4U)
#define	PWM_CAPTCTRLB_COUNT   (4U)
#define	PWM_CAPTCOMPB_COUNT   (4U)
#define	PWM_CAPTCTRLX_COUNT   (4U)
#define	PWM_CAPTCOMPX_COUNT   (4U)
#define	PWM_CVAL0_COUNT   (4U)
#define	PWM_CVAL0CYC_COUNT   (4U)
#define	PWM_CVAL1_COUNT   (4U)
#define	PWM_CVAL1CYC_COUNT   (4U)
#define	PWM_CVAL2_COUNT   (4U)
#define	PWM_CVAL2CYC_COUNT   (4U)
#define	PWM_CVAL3_COUNT   (4U)
#define	PWM_CVAL3CYC_COUNT   (4U)
#define	PWM_CVAL4_COUNT   (4U)
#define	PWM_CVAL4CYC_COUNT   (4U)
#define	PWM_CVAL5_COUNT   (4U)
#define	PWM_CVAL5CYC_COUNT   (4U)
#define	PWM1_BASE   (0x4018C000u)
#define	PWM1   ((PWM_Type *)PWM1_BASE)
#define	PWM2_BASE   (0x40190000u)
#define	PWM2   ((PWM_Type *)PWM2_BASE)
#define	PWM3_BASE   (0x40194000u)
#define	PWM3   ((PWM_Type *)PWM3_BASE)
#define	PWM4_BASE   (0x40198000u)
#define	PWM4   ((PWM_Type *)PWM4_BASE)
#define	PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
#define	PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
#define	PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_RELOAD_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_CAPTURE_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_FAULT_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PWM_RELOAD_ERROR_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PXP_BASE   (0x40814000u)
#define	PXP   ((PXP_Type *)PXP_BASE)
#define	PXP_BASE_ADDRS   { PXP_BASE }
#define	PXP_BASE_PTRS   { PXP }
#define	PXP_IRQ0_IRQS   { PXP_IRQn }
#define	RDC_MDA_COUNT   (12U)
#define	RDC_PDAP_COUNT   (128U)
#define	RDC_MRSA_COUNT   (59U)
#define	RDC_MREA_COUNT   (59U)
#define	RDC_MRC_COUNT   (59U)
#define	RDC_MRVS_COUNT   (59U)
#define	RDC_BASE   (0x40C78000u)
#define	RDC   ((RDC_Type *)RDC_BASE)
#define	RDC_BASE_ADDRS   { RDC_BASE }
#define	RDC_BASE_PTRS   { RDC }
#define	RDC_IRQS   { RDC_IRQn }
#define	RDC_SEMAPHORE_GATE_COUNT   (64U)
#define	RDC_SEMAPHORE1_BASE   (0x40C44000u)
#define	RDC_SEMAPHORE1   ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
#define	RDC_SEMAPHORE2_BASE   (0x40CCC000u)
#define	RDC_SEMAPHORE2   ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
#define	RDC_SEMAPHORE_BASE_ADDRS   { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
#define	RDC_SEMAPHORE_BASE_PTRS   { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
#define	RTWDOG3_BASE   (0x40038000u)
#define	RTWDOG3   ((RTWDOG_Type *)RTWDOG3_BASE)
#define	RTWDOG4_BASE   (0x40C10000u)
#define	RTWDOG4   ((RTWDOG_Type *)RTWDOG4_BASE)
#define	RTWDOG_BASE_ADDRS   { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE }
#define	RTWDOG_BASE_PTRS   { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 }
#define	RTWDOG_IRQS   { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn }
#define	RTWDOG_UPDATE_KEY   (0xD928C520U)
#define	RTWDOG_REFRESH_KEY   (0xB480A602U)
#define	SEMA4_GATE_COUNT   (16U)
#define	SEMA4_CPINE_COUNT   (2U)
#define	SEMA4_CPNTF_COUNT   (2U)
#define	SEMA4_BASE   (0x40CC8000u)
#define	SEMA4   ((SEMA4_Type *)SEMA4_BASE)
#define	SEMA4_BASE_ADDRS   { SEMA4_BASE }
#define	SEMA4_BASE_PTRS   { SEMA4 }
#define	SEMC_BR_COUNT   (9U)
#define	SEMC_BASE   (0x400D4000u)
#define	SEMC   ((SEMC_Type *)SEMC_BASE)
#define	SEMC_BASE_ADDRS   { SEMC_BASE }
#define	SEMC_BASE_PTRS   { SEMC }
#define	SEMC_IRQS   { SEMC_IRQn }
#define	SNVS_LPZMKR_COUNT   (8U)
#define	SNVS_LPGPR_ALIAS_COUNT   (4U)
#define	SNVS_LPATCR_COUNT   (5U)
#define	SNVS_LPGPR_COUNT   (4U)
#define	SNVS_BASE   (0x40C90000u)
#define	SNVS   ((SNVS_Type *)SNVS_BASE)
#define	SNVS_BASE_ADDRS   { SNVS_BASE }
#define	SNVS_BASE_PTRS   { SNVS }
#define	SNVS_IRQS   { SNVS_PULSE_EVENT_IRQn }
#define	SNVS_CONSOLIDATED_IRQS   { SNVS_HP_NON_TZ_IRQn }
#define	SNVS_SECURITY_IRQS   { SNVS_HP_TZ_IRQn }
#define	SPDIF_BASE   (0x40400000u)
#define	SPDIF   ((SPDIF_Type *)SPDIF_BASE)
#define	SPDIF_BASE_ADDRS   { SPDIF_BASE }
#define	SPDIF_BASE_PTRS   { SPDIF }
#define	SPDIF_IRQS   { SPDIF_IRQn }
#define	SRAM_BASE   (0x40C9C000u)
#define	SRAM   ((SRAM_Type *)SRAM_BASE)
#define	SRAM_BASE_ADDRS   { SRAM_BASE }
#define	SRAM_BASE_PTRS   { SRAM }
#define	SRC_GPR_COUNT   (20U)
#define	SRC_BASE   (0x40C04000u)
#define	SRC   ((SRC_Type *)SRC_BASE)
#define	SRC_BASE_ADDRS   { SRC_BASE }
#define	SRC_BASE_PTRS   { SRC }
#define	SSARC_HP_SRAM0_COUNT   (1024U)
#define	SSARC_HP_SRAM1_COUNT   (1024U)
#define	SSARC_HP_SRAM2_COUNT   (1024U)
#define	SSARC_HP_BASE   (0x40CB4000u)
#define	SSARC_HP   ((SSARC_HP_Type *)SSARC_HP_BASE)
#define	SSARC_HP_BASE_ADDRS   { SSARC_HP_BASE }
#define	SSARC_HP_BASE_PTRS   { SSARC_HP }
#define	SSARC_LP_DESC_CTRL0_COUNT   (16U)
#define	SSARC_LP_DESC_CTRL1_COUNT   (16U)
#define	SSARC_LP_DESC_ADDR_UP_COUNT   (16U)
#define	SSARC_LP_DESC_ADDR_DOWN_COUNT   (16U)
#define	SSARC_LP_BASE   (0x40CB8000u)
#define	SSARC_LP   ((SSARC_LP_Type *)SSARC_LP_BASE)
#define	SSARC_LP_BASE_ADDRS   { SSARC_LP_BASE }
#define	SSARC_LP_BASE_PTRS   { SSARC_LP }
#define	TMPSNS_BASE   (0u)
#define	TMPSNS   ((TMPSNS_Type *)TMPSNS_BASE)
#define	TMPSNS_BASE_ADDRS   { TMPSNS_BASE }
#define	TMPSNS_BASE_PTRS   { TMPSNS }
#define	TMR_COMP1_COUNT   (4U)
#define	TMR_COMP2_COUNT   (4U)
#define	TMR_CAPT_COUNT   (4U)
#define	TMR_LOAD_COUNT   (4U)
#define	TMR_HOLD_COUNT   (4U)
#define	TMR_CNTR_COUNT   (4U)
#define	TMR_CTRL_COUNT   (4U)
#define	TMR_SCTRL_COUNT   (4U)
#define	TMR_CMPLD1_COUNT   (4U)
#define	TMR_CMPLD2_COUNT   (4U)
#define	TMR_CSCTRL_COUNT   (4U)
#define	TMR_FILT_COUNT   (4U)
#define	TMR_DMA_COUNT   (4U)
#define	TMR_ENBL_COUNT   (4U)
#define	TMR1_BASE   (0x4015C000u)
#define	TMR1   ((TMR_Type *)TMR1_BASE)
#define	TMR2_BASE   (0x40160000u)
#define	TMR2   ((TMR_Type *)TMR2_BASE)
#define	TMR3_BASE   (0x40164000u)
#define	TMR3   ((TMR_Type *)TMR3_BASE)
#define	TMR4_BASE   (0x40168000u)
#define	TMR4   ((TMR_Type *)TMR4_BASE)
#define	TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
#define	TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
#define	TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
#define	USB_ENDPTCTRL_COUNT   (7U)
#define	USB_OTG1_BASE   (0x40430000u)
#define	USB_OTG1   ((USB_Type *)USB_OTG1_BASE)
#define	USB_OTG2_BASE   (0x4042C000u)
#define	USB_OTG2   ((USB_Type *)USB_OTG2_BASE)
#define	USB_BASE_ADDRS   { 0u, USB_OTG1_BASE, USB_OTG2_BASE }
#define	USB_BASE_PTRS   { (USB_Type *)0u, USB_OTG1, USB_OTG2 }
#define	USB_IRQS   { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
#define	GPTIMER0CTL   GPTIMER0CTRL
#define	GPTIMER1CTL   GPTIMER1CTRL
#define	USB_SBUSCFG   SBUSCFG
#define	EPLISTADDR   ENDPTLISTADDR
#define	EPSETUPSR   ENDPTSETUPSTAT
#define	EPPRIME   ENDPTPRIME
#define	EPFLUSH   ENDPTFLUSH
#define	EPSR   ENDPTSTAT
#define	EPCOMPLETE   ENDPTCOMPLETE
#define	EPCR   ENDPTCTRL
#define	EPCR0   ENDPTCTRL0
#define	USBHS_ID_ID_MASK   USB_ID_ID_MASK
#define	USBHS_ID_ID_SHIFT   USB_ID_ID_SHIFT
#define	USBHS_ID_ID(x)
#define	USBHS_ID_NID_MASK   USB_ID_NID_MASK
#define	USBHS_ID_NID_SHIFT   USB_ID_NID_SHIFT
#define	USBHS_ID_NID(x)
#define	USBHS_ID_REVISION_MASK   USB_ID_REVISION_MASK
#define	USBHS_ID_REVISION_SHIFT   USB_ID_REVISION_SHIFT
#define	USBHS_ID_REVISION(x)
#define	USBHS_HWGENERAL_PHYW_MASK   USB_HWGENERAL_PHYW_MASK
#define	USBHS_HWGENERAL_PHYW_SHIFT   USB_HWGENERAL_PHYW_SHIFT
#define	USBHS_HWGENERAL_PHYW(x)
#define	USBHS_HWGENERAL_PHYM_MASK   USB_HWGENERAL_PHYM_MASK
#define	USBHS_HWGENERAL_PHYM_SHIFT   USB_HWGENERAL_PHYM_SHIFT
#define	USBHS_HWGENERAL_PHYM(x)
#define	USBHS_HWGENERAL_SM_MASK   USB_HWGENERAL_SM_MASK
#define	USBHS_HWGENERAL_SM_SHIFT   USB_HWGENERAL_SM_SHIFT
#define	USBHS_HWGENERAL_SM(x)
#define	USBHS_HWHOST_HC_MASK   USB_HWHOST_HC_MASK
#define	USBHS_HWHOST_HC_SHIFT   USB_HWHOST_HC_SHIFT
#define	USBHS_HWHOST_HC(x)
#define	USBHS_HWHOST_NPORT_MASK   USB_HWHOST_NPORT_MASK
#define	USBHS_HWHOST_NPORT_SHIFT   USB_HWHOST_NPORT_SHIFT
#define	USBHS_HWHOST_NPORT(x)
#define	USBHS_HWDEVICE_DC_MASK   USB_HWDEVICE_DC_MASK
#define	USBHS_HWDEVICE_DC_SHIFT   USB_HWDEVICE_DC_SHIFT
#define	USBHS_HWDEVICE_DC(x)
#define	USBHS_HWDEVICE_DEVEP_MASK   USB_HWDEVICE_DEVEP_MASK
#define	USBHS_HWDEVICE_DEVEP_SHIFT   USB_HWDEVICE_DEVEP_SHIFT
#define	USBHS_HWDEVICE_DEVEP(x)
#define	USBHS_HWTXBUF_TXBURST_MASK   USB_HWTXBUF_TXBURST_MASK
#define	USBHS_HWTXBUF_TXBURST_SHIFT   USB_HWTXBUF_TXBURST_SHIFT
#define	USBHS_HWTXBUF_TXBURST(x)
#define	USBHS_HWTXBUF_TXCHANADD_MASK   USB_HWTXBUF_TXCHANADD_MASK
#define	USBHS_HWTXBUF_TXCHANADD_SHIFT   USB_HWTXBUF_TXCHANADD_SHIFT
#define	USBHS_HWTXBUF_TXCHANADD(x)
#define	USBHS_HWRXBUF_RXBURST_MASK   USB_HWRXBUF_RXBURST_MASK
#define	USBHS_HWRXBUF_RXBURST_SHIFT   USB_HWRXBUF_RXBURST_SHIFT
#define	USBHS_HWRXBUF_RXBURST(x)
#define	USBHS_HWRXBUF_RXADD_MASK   USB_HWRXBUF_RXADD_MASK
#define	USBHS_HWRXBUF_RXADD_SHIFT   USB_HWRXBUF_RXADD_SHIFT
#define	USBHS_HWRXBUF_RXADD(x)
#define	USBHS_GPTIMER0LD_GPTLD_MASK   USB_GPTIMER0LD_GPTLD_MASK
#define	USBHS_GPTIMER0LD_GPTLD_SHIFT   USB_GPTIMER0LD_GPTLD_SHIFT
#define	USBHS_GPTIMER0LD_GPTLD(x)
#define	USBHS_GPTIMER0CTL_GPTCNT_MASK   USB_GPTIMER0CTRL_GPTCNT_MASK
#define	USBHS_GPTIMER0CTL_GPTCNT_SHIFT   USB_GPTIMER0CTRL_GPTCNT_SHIFT
#define	USBHS_GPTIMER0CTL_GPTCNT(x)
#define	USBHS_GPTIMER0CTL_MODE_MASK   USB_GPTIMER0CTRL_GPTMODE_MASK
#define	USBHS_GPTIMER0CTL_MODE_SHIFT   USB_GPTIMER0CTRL_GPTMODE_SHIFT
#define	USBHS_GPTIMER0CTL_MODE(x)
#define	USBHS_GPTIMER0CTL_RST_MASK   USB_GPTIMER0CTRL_GPTRST_MASK
#define	USBHS_GPTIMER0CTL_RST_SHIFT   USB_GPTIMER0CTRL_GPTRST_SHIFT
#define	USBHS_GPTIMER0CTL_RST(x)
#define	USBHS_GPTIMER0CTL_RUN_MASK   USB_GPTIMER0CTRL_GPTRUN_MASK
#define	USBHS_GPTIMER0CTL_RUN_SHIFT   USB_GPTIMER0CTRL_GPTRUN_SHIFT
#define	USBHS_GPTIMER0CTL_RUN(x)
#define	USBHS_GPTIMER1LD_GPTLD_MASK   USB_GPTIMER1LD_GPTLD_MASK
#define	USBHS_GPTIMER1LD_GPTLD_SHIFT   USB_GPTIMER1LD_GPTLD_SHIFT
#define	USBHS_GPTIMER1LD_GPTLD(x)
#define	USBHS_GPTIMER1CTL_GPTCNT_MASK   USB_GPTIMER1CTRL_GPTCNT_MASK
#define	USBHS_GPTIMER1CTL_GPTCNT_SHIFT   USB_GPTIMER1CTRL_GPTCNT_SHIFT
#define	USBHS_GPTIMER1CTL_GPTCNT(x)
#define	USBHS_GPTIMER1CTL_MODE_MASK   USB_GPTIMER1CTRL_GPTMODE_MASK
#define	USBHS_GPTIMER1CTL_MODE_SHIFT   USB_GPTIMER1CTRL_GPTMODE_SHIFT
#define	USBHS_GPTIMER1CTL_MODE(x)
#define	USBHS_GPTIMER1CTL_RST_MASK   USB_GPTIMER1CTRL_GPTRST_MASK
#define	USBHS_GPTIMER1CTL_RST_SHIFT   USB_GPTIMER1CTRL_GPTRST_SHIFT
#define	USBHS_GPTIMER1CTL_RST(x)
#define	USBHS_GPTIMER1CTL_RUN_MASK   USB_GPTIMER1CTRL_GPTRUN_MASK
#define	USBHS_GPTIMER1CTL_RUN_SHIFT   USB_GPTIMER1CTRL_GPTRUN_SHIFT
#define	USBHS_GPTIMER1CTL_RUN(x)
#define	USBHS_USB_SBUSCFG_BURSTMODE_MASK   USB_SBUSCFG_AHBBRST_MASK
#define	USBHS_USB_SBUSCFG_BURSTMODE_SHIFT   USB_SBUSCFG_AHBBRST_SHIFT
#define	USBHS_USB_SBUSCFG_BURSTMODE(x)
#define	USBHS_HCIVERSION_CAPLENGTH(x)
#define	USBHS_HCIVERSION_HCIVERSION_MASK   USB_HCIVERSION_HCIVERSION_MASK
#define	USBHS_HCIVERSION_HCIVERSION_SHIFT   USB_HCIVERSION_HCIVERSION_SHIFT
#define	USBHS_HCIVERSION_HCIVERSION(x)
#define	USBHS_HCSPARAMS_N_PORTS_MASK   USB_HCSPARAMS_N_PORTS_MASK
#define	USBHS_HCSPARAMS_N_PORTS_SHIFT   USB_HCSPARAMS_N_PORTS_SHIFT
#define	USBHS_HCSPARAMS_N_PORTS(x)
#define	USBHS_HCSPARAMS_PPC_MASK   USB_HCSPARAMS_PPC_MASK
#define	USBHS_HCSPARAMS_PPC_SHIFT   USB_HCSPARAMS_PPC_SHIFT
#define	USBHS_HCSPARAMS_PPC(x)
#define	USBHS_HCSPARAMS_N_PCC_MASK   USB_HCSPARAMS_N_PCC_MASK
#define	USBHS_HCSPARAMS_N_PCC_SHIFT   USB_HCSPARAMS_N_PCC_SHIFT
#define	USBHS_HCSPARAMS_N_PCC(x)
#define	USBHS_HCSPARAMS_N_CC_MASK   USB_HCSPARAMS_N_CC_MASK
#define	USBHS_HCSPARAMS_N_CC_SHIFT   USB_HCSPARAMS_N_CC_SHIFT
#define	USBHS_HCSPARAMS_N_CC(x)
#define	USBHS_HCSPARAMS_PI_MASK   USB_HCSPARAMS_PI_MASK
#define	USBHS_HCSPARAMS_PI_SHIFT   USB_HCSPARAMS_PI_SHIFT
#define	USBHS_HCSPARAMS_PI(x)
#define	USBHS_HCSPARAMS_N_PTT_MASK   USB_HCSPARAMS_N_PTT_MASK
#define	USBHS_HCSPARAMS_N_PTT_SHIFT   USB_HCSPARAMS_N_PTT_SHIFT
#define	USBHS_HCSPARAMS_N_PTT(x)
#define	USBHS_HCSPARAMS_N_TT_MASK   USB_HCSPARAMS_N_TT_MASK
#define	USBHS_HCSPARAMS_N_TT_SHIFT   USB_HCSPARAMS_N_TT_SHIFT
#define	USBHS_HCSPARAMS_N_TT(x)
#define	USBHS_HCCPARAMS_ADC_MASK   USB_HCCPARAMS_ADC_MASK
#define	USBHS_HCCPARAMS_ADC_SHIFT   USB_HCCPARAMS_ADC_SHIFT
#define	USBHS_HCCPARAMS_ADC(x)
#define	USBHS_HCCPARAMS_PFL_MASK   USB_HCCPARAMS_PFL_MASK
#define	USBHS_HCCPARAMS_PFL_SHIFT   USB_HCCPARAMS_PFL_SHIFT
#define	USBHS_HCCPARAMS_PFL(x)
#define	USBHS_HCCPARAMS_ASP_MASK   USB_HCCPARAMS_ASP_MASK
#define	USBHS_HCCPARAMS_ASP_SHIFT   USB_HCCPARAMS_ASP_SHIFT
#define	USBHS_HCCPARAMS_ASP(x)
#define	USBHS_HCCPARAMS_IST_MASK   USB_HCCPARAMS_IST_MASK
#define	USBHS_HCCPARAMS_IST_SHIFT   USB_HCCPARAMS_IST_SHIFT
#define	USBHS_HCCPARAMS_IST(x)
#define	USBHS_HCCPARAMS_EECP_MASK   USB_HCCPARAMS_EECP_MASK
#define	USBHS_HCCPARAMS_EECP_SHIFT   USB_HCCPARAMS_EECP_SHIFT
#define	USBHS_HCCPARAMS_EECP(x)
#define	USBHS_DCIVERSION_DCIVERSION_MASK   USB_DCIVERSION_DCIVERSION_MASK
#define	USBHS_DCIVERSION_DCIVERSION_SHIFT   USB_DCIVERSION_DCIVERSION_SHIFT
#define	USBHS_DCIVERSION_DCIVERSION(x)
#define	USBHS_DCCPARAMS_DEN_MASK   USB_DCCPARAMS_DEN_MASK
#define	USBHS_DCCPARAMS_DEN_SHIFT   USB_DCCPARAMS_DEN_SHIFT
#define	USBHS_DCCPARAMS_DEN(x)
#define	USBHS_DCCPARAMS_DC_MASK   USB_DCCPARAMS_DC_MASK
#define	USBHS_DCCPARAMS_DC_SHIFT   USB_DCCPARAMS_DC_SHIFT
#define	USBHS_DCCPARAMS_DC(x)
#define	USBHS_DCCPARAMS_HC_MASK   USB_DCCPARAMS_HC_MASK
#define	USBHS_DCCPARAMS_HC_SHIFT   USB_DCCPARAMS_HC_SHIFT
#define	USBHS_DCCPARAMS_HC(x)
#define	USBHS_USBCMD_RS_MASK   USB_USBCMD_RS_MASK
#define	USBHS_USBCMD_RS_SHIFT   USB_USBCMD_RS_SHIFT
#define	USBHS_USBCMD_RS(x)
#define	USBHS_USBCMD_RST_MASK   USB_USBCMD_RST_MASK
#define	USBHS_USBCMD_RST_SHIFT   USB_USBCMD_RST_SHIFT
#define	USBHS_USBCMD_RST(x)
#define	USBHS_USBCMD_FS_MASK   USB_USBCMD_FS_1_MASK
#define	USBHS_USBCMD_FS_SHIFT   USB_USBCMD_FS_1_SHIFT
#define	USBHS_USBCMD_FS(x)
#define	USBHS_USBCMD_PSE_MASK   USB_USBCMD_PSE_MASK
#define	USBHS_USBCMD_PSE_SHIFT   USB_USBCMD_PSE_SHIFT
#define	USBHS_USBCMD_PSE(x)
#define	USBHS_USBCMD_ASE_MASK   USB_USBCMD_ASE_MASK
#define	USBHS_USBCMD_ASE_SHIFT   USB_USBCMD_ASE_SHIFT
#define	USBHS_USBCMD_ASE(x)
#define	USBHS_USBCMD_IAA_MASK   USB_USBCMD_IAA_MASK
#define	USBHS_USBCMD_IAA_SHIFT   USB_USBCMD_IAA_SHIFT
#define	USBHS_USBCMD_IAA(x)
#define	USBHS_USBCMD_ASP_MASK   USB_USBCMD_ASP_MASK
#define	USBHS_USBCMD_ASP_SHIFT   USB_USBCMD_ASP_SHIFT
#define	USBHS_USBCMD_ASP(x)
#define	USBHS_USBCMD_ASPE_MASK   USB_USBCMD_ASPE_MASK
#define	USBHS_USBCMD_ASPE_SHIFT   USB_USBCMD_ASPE_SHIFT
#define	USBHS_USBCMD_ASPE(x)
#define	USBHS_USBCMD_ATDTW_MASK   USB_USBCMD_ATDTW_MASK
#define	USBHS_USBCMD_ATDTW_SHIFT   USB_USBCMD_ATDTW_SHIFT
#define	USBHS_USBCMD_ATDTW(x)
#define	USBHS_USBCMD_SUTW_MASK   USB_USBCMD_SUTW_MASK
#define	USBHS_USBCMD_SUTW_SHIFT   USB_USBCMD_SUTW_SHIFT
#define	USBHS_USBCMD_SUTW(x)
#define	USBHS_USBCMD_FS2_MASK   USB_USBCMD_FS_2_MASK
#define	USBHS_USBCMD_FS2_SHIFT   USB_USBCMD_FS_2_SHIFT
#define	USBHS_USBCMD_FS2(x)
#define	USBHS_USBCMD_ITC_MASK   USB_USBCMD_ITC_MASK
#define	USBHS_USBCMD_ITC_SHIFT   USB_USBCMD_ITC_SHIFT
#define	USBHS_USBCMD_ITC(x)
#define	USBHS_USBSTS_UI_MASK   USB_USBSTS_UI_MASK
#define	USBHS_USBSTS_UI_SHIFT   USB_USBSTS_UI_SHIFT
#define	USBHS_USBSTS_UI(x)
#define	USBHS_USBSTS_UEI_MASK   USB_USBSTS_UEI_MASK
#define	USBHS_USBSTS_UEI_SHIFT   USB_USBSTS_UEI_SHIFT
#define	USBHS_USBSTS_UEI(x)
#define	USBHS_USBSTS_PCI_MASK   USB_USBSTS_PCI_MASK
#define	USBHS_USBSTS_PCI_SHIFT   USB_USBSTS_PCI_SHIFT
#define	USBHS_USBSTS_PCI(x)
#define	USBHS_USBSTS_FRI_MASK   USB_USBSTS_FRI_MASK
#define	USBHS_USBSTS_FRI_SHIFT   USB_USBSTS_FRI_SHIFT
#define	USBHS_USBSTS_FRI(x)
#define	USBHS_USBSTS_SEI_MASK   USB_USBSTS_SEI_MASK
#define	USBHS_USBSTS_SEI_SHIFT   USB_USBSTS_SEI_SHIFT
#define	USBHS_USBSTS_SEI(x)
#define	USBHS_USBSTS_AAI_MASK   USB_USBSTS_AAI_MASK
#define	USBHS_USBSTS_AAI_SHIFT   USB_USBSTS_AAI_SHIFT
#define	USBHS_USBSTS_AAI(x)
#define	USBHS_USBSTS_URI_MASK   USB_USBSTS_URI_MASK
#define	USBHS_USBSTS_URI_SHIFT   USB_USBSTS_URI_SHIFT
#define	USBHS_USBSTS_URI(x)
#define	USBHS_USBSTS_SRI_MASK   USB_USBSTS_SRI_MASK
#define	USBHS_USBSTS_SRI_SHIFT   USB_USBSTS_SRI_SHIFT
#define	USBHS_USBSTS_SRI(x)
#define	USBHS_USBSTS_SLI_MASK   USB_USBSTS_SLI_MASK
#define	USBHS_USBSTS_SLI_SHIFT   USB_USBSTS_SLI_SHIFT
#define	USBHS_USBSTS_SLI(x)
#define	USBHS_USBSTS_ULPII_MASK   USB_USBSTS_ULPII_MASK
#define	USBHS_USBSTS_ULPII_SHIFT   USB_USBSTS_ULPII_SHIFT
#define	USBHS_USBSTS_ULPII(x)
#define	USBHS_USBSTS_HCH_MASK   USB_USBSTS_HCH_MASK
#define	USBHS_USBSTS_HCH_SHIFT   USB_USBSTS_HCH_SHIFT
#define	USBHS_USBSTS_HCH(x)
#define	USBHS_USBSTS_RCL_MASK   USB_USBSTS_RCL_MASK
#define	USBHS_USBSTS_RCL_SHIFT   USB_USBSTS_RCL_SHIFT
#define	USBHS_USBSTS_RCL(x)
#define	USBHS_USBSTS_PS_MASK   USB_USBSTS_PS_MASK
#define	USBHS_USBSTS_PS_SHIFT   USB_USBSTS_PS_SHIFT
#define	USBHS_USBSTS_PS(x)
#define	USBHS_USBSTS_AS_MASK   USB_USBSTS_AS_MASK
#define	USBHS_USBSTS_AS_SHIFT   USB_USBSTS_AS_SHIFT
#define	USBHS_USBSTS_AS(x)
#define	USBHS_USBSTS_NAKI_MASK   USB_USBSTS_NAKI_MASK
#define	USBHS_USBSTS_NAKI_SHIFT   USB_USBSTS_NAKI_SHIFT
#define	USBHS_USBSTS_NAKI(x)
#define	USBHS_USBSTS_TI0_MASK   USB_USBSTS_TI0_MASK
#define	USBHS_USBSTS_TI0_SHIFT   USB_USBSTS_TI0_SHIFT
#define	USBHS_USBSTS_TI0(x)
#define	USBHS_USBSTS_TI1_MASK   USB_USBSTS_TI1_MASK
#define	USBHS_USBSTS_TI1_SHIFT   USB_USBSTS_TI1_SHIFT
#define	USBHS_USBSTS_TI1(x)
#define	USBHS_USBINTR_UE_MASK   USB_USBINTR_UE_MASK
#define	USBHS_USBINTR_UE_SHIFT   USB_USBINTR_UE_SHIFT
#define	USBHS_USBINTR_UE(x)
#define	USBHS_USBINTR_UEE_MASK   USB_USBINTR_UEE_MASK
#define	USBHS_USBINTR_UEE_SHIFT   USB_USBINTR_UEE_SHIFT
#define	USBHS_USBINTR_UEE(x)
#define	USBHS_USBINTR_PCE_MASK   USB_USBINTR_PCE_MASK
#define	USBHS_USBINTR_PCE_SHIFT   USB_USBINTR_PCE_SHIFT
#define	USBHS_USBINTR_PCE(x)
#define	USBHS_USBINTR_FRE_MASK   USB_USBINTR_FRE_MASK
#define	USBHS_USBINTR_FRE_SHIFT   USB_USBINTR_FRE_SHIFT
#define	USBHS_USBINTR_FRE(x)
#define	USBHS_USBINTR_SEE_MASK   USB_USBINTR_SEE_MASK
#define	USBHS_USBINTR_SEE_SHIFT   USB_USBINTR_SEE_SHIFT
#define	USBHS_USBINTR_SEE(x)
#define	USBHS_USBINTR_AAE_MASK   USB_USBINTR_AAE_MASK
#define	USBHS_USBINTR_AAE_SHIFT   USB_USBINTR_AAE_SHIFT
#define	USBHS_USBINTR_AAE(x)
#define	USBHS_USBINTR_URE_MASK   USB_USBINTR_URE_MASK
#define	USBHS_USBINTR_URE_SHIFT   USB_USBINTR_URE_SHIFT
#define	USBHS_USBINTR_URE(x)
#define	USBHS_USBINTR_SRE_MASK   USB_USBINTR_SRE_MASK
#define	USBHS_USBINTR_SRE_SHIFT   USB_USBINTR_SRE_SHIFT
#define	USBHS_USBINTR_SRE(x)
#define	USBHS_USBINTR_SLE_MASK   USB_USBINTR_SLE_MASK
#define	USBHS_USBINTR_SLE_SHIFT   USB_USBINTR_SLE_SHIFT
#define	USBHS_USBINTR_SLE(x)
#define	USBHS_USBINTR_ULPIE_MASK   USB_USBINTR_ULPIE_MASK
#define	USBHS_USBINTR_ULPIE_SHIFT   USB_USBINTR_ULPIE_SHIFT
#define	USBHS_USBINTR_ULPIE(x)
#define	USBHS_USBINTR_NAKE_MASK   USB_USBINTR_NAKE_MASK
#define	USBHS_USBINTR_NAKE_SHIFT   USB_USBINTR_NAKE_SHIFT
#define	USBHS_USBINTR_NAKE(x)
#define	USBHS_USBINTR_UAIE_MASK   USB_USBINTR_UAIE_MASK
#define	USBHS_USBINTR_UAIE_SHIFT   USB_USBINTR_UAIE_SHIFT
#define	USBHS_USBINTR_UAIE(x)
#define	USBHS_USBINTR_UPIE_MASK   USB_USBINTR_UPIE_MASK
#define	USBHS_USBINTR_UPIE_SHIFT   USB_USBINTR_UPIE_SHIFT
#define	USBHS_USBINTR_UPIE(x)
#define	USBHS_USBINTR_TIE0_MASK   USB_USBINTR_TIE0_MASK
#define	USBHS_USBINTR_TIE0_SHIFT   USB_USBINTR_TIE0_SHIFT
#define	USBHS_USBINTR_TIE0(x)
#define	USBHS_USBINTR_TIE1_MASK   USB_USBINTR_TIE1_MASK
#define	USBHS_USBINTR_TIE1_SHIFT   USB_USBINTR_TIE1_SHIFT
#define	USBHS_USBINTR_TIE1(x)
#define	USBHS_FRINDEX_FRINDEX_MASK   USB_FRINDEX_FRINDEX_MASK
#define	USBHS_FRINDEX_FRINDEX_SHIFT   USB_FRINDEX_FRINDEX_SHIFT
#define	USBHS_FRINDEX_FRINDEX(x)
#define	USBHS_DEVICEADDR_USBADRA_MASK   USB_DEVICEADDR_USBADRA_MASK
#define	USBHS_DEVICEADDR_USBADRA_SHIFT   USB_DEVICEADDR_USBADRA_SHIFT
#define	USBHS_DEVICEADDR_USBADRA(x)
#define	USBHS_DEVICEADDR_USBADR_MASK   USB_DEVICEADDR_USBADR_MASK
#define	USBHS_DEVICEADDR_USBADR_SHIFT   USB_DEVICEADDR_USBADR_SHIFT
#define	USBHS_DEVICEADDR_USBADR(x)
#define	USBHS_PERIODICLISTBASE_PERBASE_MASK   USB_PERIODICLISTBASE_BASEADR_MASK
#define	USBHS_PERIODICLISTBASE_PERBASE_SHIFT   USB_PERIODICLISTBASE_BASEADR_SHIFT
#define	USBHS_PERIODICLISTBASE_PERBASE(x)
#define	USBHS_ASYNCLISTADDR_ASYBASE_MASK   USB_ASYNCLISTADDR_ASYBASE_MASK
#define	USBHS_ASYNCLISTADDR_ASYBASE_SHIFT   USB_ASYNCLISTADDR_ASYBASE_SHIFT
#define	USBHS_ASYNCLISTADDR_ASYBASE(x)
#define	USBHS_EPLISTADDR_EPBASE_MASK   USB_ENDPTLISTADDR_EPBASE_MASK
#define	USBHS_EPLISTADDR_EPBASE_SHIFT   USB_ENDPTLISTADDR_EPBASE_SHIFT
#define	USBHS_EPLISTADDR_EPBASE(x)
#define	USBHS_BURSTSIZE_RXPBURST_MASK   USB_BURSTSIZE_RXPBURST_MASK
#define	USBHS_BURSTSIZE_RXPBURST_SHIFT   USB_BURSTSIZE_RXPBURST_SHIFT
#define	USBHS_BURSTSIZE_RXPBURST(x)
#define	USBHS_BURSTSIZE_TXPBURST_MASK   USB_BURSTSIZE_TXPBURST_MASK
#define	USBHS_BURSTSIZE_TXPBURST_SHIFT   USB_BURSTSIZE_TXPBURST_SHIFT
#define	USBHS_BURSTSIZE_TXPBURST(x)
#define	USBHS_TXFILLTUNING_TXSCHOH_MASK   USB_TXFILLTUNING_TXSCHOH_MASK
#define	USBHS_TXFILLTUNING_TXSCHOH_SHIFT   USB_TXFILLTUNING_TXSCHOH_SHIFT
#define	USBHS_TXFILLTUNING_TXSCHOH(x)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH_MASK   USB_TXFILLTUNING_TXSCHHEALTH_MASK
#define	USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT   USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
#define	USBHS_TXFILLTUNING_TXSCHHEALTH(x)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES_MASK   USB_TXFILLTUNING_TXFIFOTHRES_MASK
#define	USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT   USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
#define	USBHS_TXFILLTUNING_TXFIFOTHRES(x)
#define	USBHS_ENDPTNAK_EPRN_MASK   USB_ENDPTNAK_EPRN_MASK
#define	USBHS_ENDPTNAK_EPRN_SHIFT   USB_ENDPTNAK_EPRN_SHIFT
#define	USBHS_ENDPTNAK_EPRN(x)
#define	USBHS_ENDPTNAK_EPTN_MASK   USB_ENDPTNAK_EPTN_MASK
#define	USBHS_ENDPTNAK_EPTN_SHIFT   USB_ENDPTNAK_EPTN_SHIFT
#define	USBHS_ENDPTNAK_EPTN(x)
#define	USBHS_ENDPTNAKEN_EPRNE_MASK   USB_ENDPTNAKEN_EPRNE_MASK
#define	USBHS_ENDPTNAKEN_EPRNE_SHIFT   USB_ENDPTNAKEN_EPRNE_SHIFT
#define	USBHS_ENDPTNAKEN_EPRNE(x)
#define	USBHS_ENDPTNAKEN_EPTNE_MASK   USB_ENDPTNAKEN_EPTNE_MASK
#define	USBHS_ENDPTNAKEN_EPTNE_SHIFT   USB_ENDPTNAKEN_EPTNE_SHIFT
#define	USBHS_ENDPTNAKEN_EPTNE(x)
#define	USBHS_CONFIGFLAG_CF_MASK   USB_CONFIGFLAG_CF_MASK
#define	USBHS_CONFIGFLAG_CF_SHIFT   USB_CONFIGFLAG_CF_SHIFT
#define	USBHS_CONFIGFLAG_CF(x)
#define	USBHS_PORTSC1_CCS_MASK   USB_PORTSC1_CCS_MASK
#define	USBHS_PORTSC1_CCS_SHIFT   USB_PORTSC1_CCS_SHIFT
#define	USBHS_PORTSC1_CCS(x)
#define	USBHS_PORTSC1_CSC_MASK   USB_PORTSC1_CSC_MASK
#define	USBHS_PORTSC1_CSC_SHIFT   USB_PORTSC1_CSC_SHIFT
#define	USBHS_PORTSC1_CSC(x)
#define	USBHS_PORTSC1_PE_MASK   USB_PORTSC1_PE_MASK
#define	USBHS_PORTSC1_PE_SHIFT   USB_PORTSC1_PE_SHIFT
#define	USBHS_PORTSC1_PE(x)
#define	USBHS_PORTSC1_PEC_MASK   USB_PORTSC1_PEC_MASK
#define	USBHS_PORTSC1_PEC_SHIFT   USB_PORTSC1_PEC_SHIFT
#define	USBHS_PORTSC1_PEC(x)
#define	USBHS_PORTSC1_OCA_MASK   USB_PORTSC1_OCA_MASK
#define	USBHS_PORTSC1_OCA_SHIFT   USB_PORTSC1_OCA_SHIFT
#define	USBHS_PORTSC1_OCA(x)
#define	USBHS_PORTSC1_OCC_MASK   USB_PORTSC1_OCC_MASK
#define	USBHS_PORTSC1_OCC_SHIFT   USB_PORTSC1_OCC_SHIFT
#define	USBHS_PORTSC1_OCC(x)
#define	USBHS_PORTSC1_FPR_MASK   USB_PORTSC1_FPR_MASK
#define	USBHS_PORTSC1_FPR_SHIFT   USB_PORTSC1_FPR_SHIFT
#define	USBHS_PORTSC1_FPR(x)
#define	USBHS_PORTSC1_SUSP_MASK   USB_PORTSC1_SUSP_MASK
#define	USBHS_PORTSC1_SUSP_SHIFT   USB_PORTSC1_SUSP_SHIFT
#define	USBHS_PORTSC1_SUSP(x)
#define	USBHS_PORTSC1_PR_MASK   USB_PORTSC1_PR_MASK
#define	USBHS_PORTSC1_PR_SHIFT   USB_PORTSC1_PR_SHIFT
#define	USBHS_PORTSC1_PR(x)
#define	USBHS_PORTSC1_HSP_MASK   USB_PORTSC1_HSP_MASK
#define	USBHS_PORTSC1_HSP_SHIFT   USB_PORTSC1_HSP_SHIFT
#define	USBHS_PORTSC1_HSP(x)
#define	USBHS_PORTSC1_LS_MASK   USB_PORTSC1_LS_MASK
#define	USBHS_PORTSC1_LS_SHIFT   USB_PORTSC1_LS_SHIFT
#define	USBHS_PORTSC1_LS(x)
#define	USBHS_PORTSC1_PP_MASK   USB_PORTSC1_PP_MASK
#define	USBHS_PORTSC1_PP_SHIFT   USB_PORTSC1_PP_SHIFT
#define	USBHS_PORTSC1_PP(x)
#define	USBHS_PORTSC1_PO_MASK   USB_PORTSC1_PO_MASK
#define	USBHS_PORTSC1_PO_SHIFT   USB_PORTSC1_PO_SHIFT
#define	USBHS_PORTSC1_PO(x)
#define	USBHS_PORTSC1_PIC_MASK   USB_PORTSC1_PIC_MASK
#define	USBHS_PORTSC1_PIC_SHIFT   USB_PORTSC1_PIC_SHIFT
#define	USBHS_PORTSC1_PIC(x)
#define	USBHS_PORTSC1_PTC_MASK   USB_PORTSC1_PTC_MASK
#define	USBHS_PORTSC1_PTC_SHIFT   USB_PORTSC1_PTC_SHIFT
#define	USBHS_PORTSC1_PTC(x)
#define	USBHS_PORTSC1_WKCN_MASK   USB_PORTSC1_WKCN_MASK
#define	USBHS_PORTSC1_WKCN_SHIFT   USB_PORTSC1_WKCN_SHIFT
#define	USBHS_PORTSC1_WKCN(x)
#define	USBHS_PORTSC1_WKDS_MASK   USB_PORTSC1_WKDC_MASK
#define	USBHS_PORTSC1_WKDS_SHIFT   USB_PORTSC1_WKDC_SHIFT
#define	USBHS_PORTSC1_WKDS(x)
#define	USBHS_PORTSC1_WKOC_MASK   USB_PORTSC1_WKOC_MASK
#define	USBHS_PORTSC1_WKOC_SHIFT   USB_PORTSC1_WKOC_SHIFT
#define	USBHS_PORTSC1_WKOC(x)
#define	USBHS_PORTSC1_PHCD_MASK   USB_PORTSC1_PHCD_MASK
#define	USBHS_PORTSC1_PHCD_SHIFT   USB_PORTSC1_PHCD_SHIFT
#define	USBHS_PORTSC1_PHCD(x)
#define	USBHS_PORTSC1_PFSC_MASK   USB_PORTSC1_PFSC_MASK
#define	USBHS_PORTSC1_PFSC_SHIFT   USB_PORTSC1_PFSC_SHIFT
#define	USBHS_PORTSC1_PFSC(x)
#define	USBHS_PORTSC1_PTS2_MASK   USB_PORTSC1_PTS_2_MASK
#define	USBHS_PORTSC1_PTS2_SHIFT   USB_PORTSC1_PTS_2_SHIFT
#define	USBHS_PORTSC1_PTS2(x)
#define	USBHS_PORTSC1_PSPD_MASK   USB_PORTSC1_PSPD_MASK
#define	USBHS_PORTSC1_PSPD_SHIFT   USB_PORTSC1_PSPD_SHIFT
#define	USBHS_PORTSC1_PSPD(x)
#define	USBHS_PORTSC1_PTW_MASK   USB_PORTSC1_PTW_MASK
#define	USBHS_PORTSC1_PTW_SHIFT   USB_PORTSC1_PTW_SHIFT
#define	USBHS_PORTSC1_PTW(x)
#define	USBHS_PORTSC1_STS_MASK   USB_PORTSC1_STS_MASK
#define	USBHS_PORTSC1_STS_SHIFT   USB_PORTSC1_STS_SHIFT
#define	USBHS_PORTSC1_STS(x)
#define	USBHS_PORTSC1_PTS_MASK   USB_PORTSC1_PTS_1_MASK
#define	USBHS_PORTSC1_PTS_SHIFT   USB_PORTSC1_PTS_1_SHIFT
#define	USBHS_PORTSC1_PTS(x)
#define	USBHS_OTGSC_VD_MASK   USB_OTGSC_VD_MASK
#define	USBHS_OTGSC_VD_SHIFT   USB_OTGSC_VD_SHIFT
#define	USBHS_OTGSC_VD(x)
#define	USBHS_OTGSC_VC_MASK   USB_OTGSC_VC_MASK
#define	USBHS_OTGSC_VC_SHIFT   USB_OTGSC_VC_SHIFT
#define	USBHS_OTGSC_VC(x)
#define	USBHS_OTGSC_OT_MASK   USB_OTGSC_OT_MASK
#define	USBHS_OTGSC_OT_SHIFT   USB_OTGSC_OT_SHIFT
#define	USBHS_OTGSC_OT(x)
#define	USBHS_OTGSC_DP_MASK   USB_OTGSC_DP_MASK
#define	USBHS_OTGSC_DP_SHIFT   USB_OTGSC_DP_SHIFT
#define	USBHS_OTGSC_DP(x)
#define	USBHS_OTGSC_IDPU_MASK   USB_OTGSC_IDPU_MASK
#define	USBHS_OTGSC_IDPU_SHIFT   USB_OTGSC_IDPU_SHIFT
#define	USBHS_OTGSC_IDPU(x)
#define	USBHS_OTGSC_ID_MASK   USB_OTGSC_ID_MASK
#define	USBHS_OTGSC_ID_SHIFT   USB_OTGSC_ID_SHIFT
#define	USBHS_OTGSC_ID(x)
#define	USBHS_OTGSC_AVV_MASK   USB_OTGSC_AVV_MASK
#define	USBHS_OTGSC_AVV_SHIFT   USB_OTGSC_AVV_SHIFT
#define	USBHS_OTGSC_AVV(x)
#define	USBHS_OTGSC_ASV_MASK   USB_OTGSC_ASV_MASK
#define	USBHS_OTGSC_ASV_SHIFT   USB_OTGSC_ASV_SHIFT
#define	USBHS_OTGSC_ASV(x)
#define	USBHS_OTGSC_BSV_MASK   USB_OTGSC_BSV_MASK
#define	USBHS_OTGSC_BSV_SHIFT   USB_OTGSC_BSV_SHIFT
#define	USBHS_OTGSC_BSV(x)
#define	USBHS_OTGSC_BSE_MASK   USB_OTGSC_BSE_MASK
#define	USBHS_OTGSC_BSE_SHIFT   USB_OTGSC_BSE_SHIFT
#define	USBHS_OTGSC_BSE(x)
#define	USBHS_OTGSC_MST_MASK   USB_OTGSC_TOG_1MS_MASK
#define	USBHS_OTGSC_MST_SHIFT   USB_OTGSC_TOG_1MS_SHIFT
#define	USBHS_OTGSC_MST(x)
#define	USBHS_OTGSC_DPS_MASK   USB_OTGSC_DPS_MASK
#define	USBHS_OTGSC_DPS_SHIFT   USB_OTGSC_DPS_SHIFT
#define	USBHS_OTGSC_DPS(x)
#define	USBHS_OTGSC_IDIS_MASK   USB_OTGSC_IDIS_MASK
#define	USBHS_OTGSC_IDIS_SHIFT   USB_OTGSC_IDIS_SHIFT
#define	USBHS_OTGSC_IDIS(x)
#define	USBHS_OTGSC_AVVIS_MASK   USB_OTGSC_AVVIS_MASK
#define	USBHS_OTGSC_AVVIS_SHIFT   USB_OTGSC_AVVIS_SHIFT
#define	USBHS_OTGSC_AVVIS(x)
#define	USBHS_OTGSC_ASVIS_MASK   USB_OTGSC_ASVIS_MASK
#define	USBHS_OTGSC_ASVIS_SHIFT   USB_OTGSC_ASVIS_SHIFT
#define	USBHS_OTGSC_ASVIS(x)
#define	USBHS_OTGSC_BSVIS_MASK   USB_OTGSC_BSVIS_MASK
#define	USBHS_OTGSC_BSVIS_SHIFT   USB_OTGSC_BSVIS_SHIFT
#define	USBHS_OTGSC_BSVIS(x)
#define	USBHS_OTGSC_BSEIS_MASK   USB_OTGSC_BSEIS_MASK
#define	USBHS_OTGSC_BSEIS_SHIFT   USB_OTGSC_BSEIS_SHIFT
#define	USBHS_OTGSC_BSEIS(x)
#define	USBHS_OTGSC_MSS_MASK   USB_OTGSC_STATUS_1MS_MASK
#define	USBHS_OTGSC_MSS_SHIFT   USB_OTGSC_STATUS_1MS_SHIFT
#define	USBHS_OTGSC_MSS(x)
#define	USBHS_OTGSC_DPIS_MASK   USB_OTGSC_DPIS_MASK
#define	USBHS_OTGSC_DPIS_SHIFT   USB_OTGSC_DPIS_SHIFT
#define	USBHS_OTGSC_DPIS(x)
#define	USBHS_OTGSC_IDIE_MASK   USB_OTGSC_IDIE_MASK
#define	USBHS_OTGSC_IDIE_SHIFT   USB_OTGSC_IDIE_SHIFT
#define	USBHS_OTGSC_IDIE(x)
#define	USBHS_OTGSC_AVVIE_MASK   USB_OTGSC_AVVIE_MASK
#define	USBHS_OTGSC_AVVIE_SHIFT   USB_OTGSC_AVVIE_SHIFT
#define	USBHS_OTGSC_AVVIE(x)
#define	USBHS_OTGSC_ASVIE_MASK   USB_OTGSC_ASVIE_MASK
#define	USBHS_OTGSC_ASVIE_SHIFT   USB_OTGSC_ASVIE_SHIFT
#define	USBHS_OTGSC_ASVIE(x)
#define	USBHS_OTGSC_BSVIE_MASK   USB_OTGSC_BSVIE_MASK
#define	USBHS_OTGSC_BSVIE_SHIFT   USB_OTGSC_BSVIE_SHIFT
#define	USBHS_OTGSC_BSVIE(x)
#define	USBHS_OTGSC_BSEIE_MASK   USB_OTGSC_BSEIE_MASK
#define	USBHS_OTGSC_BSEIE_SHIFT   USB_OTGSC_BSEIE_SHIFT
#define	USBHS_OTGSC_BSEIE(x)
#define	USBHS_OTGSC_MSE_MASK   USB_OTGSC_EN_1MS_MASK
#define	USBHS_OTGSC_MSE_SHIFT   USB_OTGSC_EN_1MS_SHIFT
#define	USBHS_OTGSC_MSE(x)
#define	USBHS_OTGSC_DPIE_MASK   USB_OTGSC_DPIE_MASK
#define	USBHS_OTGSC_DPIE_SHIFT   USB_OTGSC_DPIE_SHIFT
#define	USBHS_OTGSC_DPIE(x)
#define	USBHS_USBMODE_CM_MASK   USB_USBMODE_CM_MASK
#define	USBHS_USBMODE_CM_SHIFT   USB_USBMODE_CM_SHIFT
#define	USBHS_USBMODE_CM(x)
#define	USBHS_USBMODE_ES_MASK   USB_USBMODE_ES_MASK
#define	USBHS_USBMODE_ES_SHIFT   USB_USBMODE_ES_SHIFT
#define	USBHS_USBMODE_ES(x)
#define	USBHS_USBMODE_SLOM_MASK   USB_USBMODE_SLOM_MASK
#define	USBHS_USBMODE_SLOM_SHIFT   USB_USBMODE_SLOM_SHIFT
#define	USBHS_USBMODE_SLOM(x)
#define	USBHS_USBMODE_SDIS_MASK   USB_USBMODE_SDIS_MASK
#define	USBHS_USBMODE_SDIS_SHIFT   USB_USBMODE_SDIS_SHIFT
#define	USBHS_USBMODE_SDIS(x)
#define	USBHS_EPSETUPSR_EPSETUPSTAT_MASK   USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
#define	USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT   USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
#define	USBHS_EPSETUPSR_EPSETUPSTAT(x)
#define	USBHS_EPPRIME_PERB_MASK   USB_ENDPTPRIME_PERB_MASK
#define	USBHS_EPPRIME_PERB_SHIFT   USB_ENDPTPRIME_PERB_SHIFT
#define	USBHS_EPPRIME_PERB(x)
#define	USBHS_EPPRIME_PETB_MASK   USB_ENDPTPRIME_PETB_MASK
#define	USBHS_EPPRIME_PETB_SHIFT   USB_ENDPTPRIME_PETB_SHIFT
#define	USBHS_EPPRIME_PETB(x)
#define	USBHS_EPFLUSH_FERB_MASK   USB_ENDPTFLUSH_FERB_MASK
#define	USBHS_EPFLUSH_FERB_SHIFT   USB_ENDPTFLUSH_FERB_SHIFT
#define	USBHS_EPFLUSH_FERB(x)
#define	USBHS_EPFLUSH_FETB_MASK   USB_ENDPTFLUSH_FETB_MASK
#define	USBHS_EPFLUSH_FETB_SHIFT   USB_ENDPTFLUSH_FETB_SHIFT
#define	USBHS_EPFLUSH_FETB(x)
#define	USBHS_EPSR_ERBR_MASK   USB_ENDPTSTAT_ERBR_MASK
#define	USBHS_EPSR_ERBR_SHIFT   USB_ENDPTSTAT_ERBR_SHIFT
#define	USBHS_EPSR_ERBR(x)
#define	USBHS_EPSR_ETBR_MASK   USB_ENDPTSTAT_ETBR_MASK
#define	USBHS_EPSR_ETBR_SHIFT   USB_ENDPTSTAT_ETBR_SHIFT
#define	USBHS_EPSR_ETBR(x)
#define	USBHS_EPCOMPLETE_ERCE_MASK   USB_ENDPTCOMPLETE_ERCE_MASK
#define	USBHS_EPCOMPLETE_ERCE_SHIFT   USB_ENDPTCOMPLETE_ERCE_SHIFT
#define	USBHS_EPCOMPLETE_ERCE(x)
#define	USBHS_EPCOMPLETE_ETCE_MASK   USB_ENDPTCOMPLETE_ETCE_MASK
#define	USBHS_EPCOMPLETE_ETCE_SHIFT   USB_ENDPTCOMPLETE_ETCE_SHIFT
#define	USBHS_EPCOMPLETE_ETCE(x)
#define	USBHS_EPCR0_RXS_MASK   USB_ENDPTCTRL0_RXS_MASK
#define	USBHS_EPCR0_RXS_SHIFT   USB_ENDPTCTRL0_RXS_SHIFT
#define	USBHS_EPCR0_RXS(x)
#define	USBHS_EPCR0_RXT_MASK   USB_ENDPTCTRL0_RXT_MASK
#define	USBHS_EPCR0_RXT_SHIFT   USB_ENDPTCTRL0_RXT_SHIFT
#define	USBHS_EPCR0_RXT(x)
#define	USBHS_EPCR0_RXE_MASK   USB_ENDPTCTRL0_RXE_MASK
#define	USBHS_EPCR0_RXE_SHIFT   USB_ENDPTCTRL0_RXE_SHIFT
#define	USBHS_EPCR0_RXE(x)
#define	USBHS_EPCR0_TXS_MASK   USB_ENDPTCTRL0_TXS_MASK
#define	USBHS_EPCR0_TXS_SHIFT   USB_ENDPTCTRL0_TXS_SHIFT
#define	USBHS_EPCR0_TXS(x)
#define	USBHS_EPCR0_TXT_MASK   USB_ENDPTCTRL0_TXT_MASK
#define	USBHS_EPCR0_TXT_SHIFT   USB_ENDPTCTRL0_TXT_SHIFT
#define	USBHS_EPCR0_TXT(x)
#define	USBHS_EPCR0_TXE_MASK   USB_ENDPTCTRL0_TXE_MASK
#define	USBHS_EPCR0_TXE_SHIFT   USB_ENDPTCTRL0_TXE_SHIFT
#define	USBHS_EPCR0_TXE(x)
#define	USBHS_EPCR_RXS_MASK   USB_ENDPTCTRL_RXS_MASK
#define	USBHS_EPCR_RXS_SHIFT   USB_ENDPTCTRL_RXS_SHIFT
#define	USBHS_EPCR_RXS(x)
#define	USBHS_EPCR_RXD_MASK   USB_ENDPTCTRL_RXD_MASK
#define	USBHS_EPCR_RXD_SHIFT   USB_ENDPTCTRL_RXD_SHIFT
#define	USBHS_EPCR_RXD(x)
#define	USBHS_EPCR_RXT_MASK   USB_ENDPTCTRL_RXT_MASK
#define	USBHS_EPCR_RXT_SHIFT   USB_ENDPTCTRL_RXT_SHIFT
#define	USBHS_EPCR_RXT(x)
#define	USBHS_EPCR_RXI_MASK   USB_ENDPTCTRL_RXI_MASK
#define	USBHS_EPCR_RXI_SHIFT   USB_ENDPTCTRL_RXI_SHIFT
#define	USBHS_EPCR_RXI(x)
#define	USBHS_EPCR_RXR_MASK   USB_ENDPTCTRL_RXR_MASK
#define	USBHS_EPCR_RXR_SHIFT   USB_ENDPTCTRL_RXR_SHIFT
#define	USBHS_EPCR_RXR(x)
#define	USBHS_EPCR_RXE_MASK   USB_ENDPTCTRL_RXE_MASK
#define	USBHS_EPCR_RXE_SHIFT   USB_ENDPTCTRL_RXE_SHIFT
#define	USBHS_EPCR_RXE(x)
#define	USBHS_EPCR_TXS_MASK   USB_ENDPTCTRL_TXS_MASK
#define	USBHS_EPCR_TXS_SHIFT   USB_ENDPTCTRL_TXS_SHIFT
#define	USBHS_EPCR_TXS(x)
#define	USBHS_EPCR_TXD_MASK   USB_ENDPTCTRL_TXD_MASK
#define	USBHS_EPCR_TXD_SHIFT   USB_ENDPTCTRL_TXD_SHIFT
#define	USBHS_EPCR_TXD(x)
#define	USBHS_EPCR_TXT_MASK   USB_ENDPTCTRL_TXT_MASK
#define	USBHS_EPCR_TXT_SHIFT   USB_ENDPTCTRL_TXT_SHIFT
#define	USBHS_EPCR_TXT(x)
#define	USBHS_EPCR_TXI_MASK   USB_ENDPTCTRL_TXI_MASK
#define	USBHS_EPCR_TXI_SHIFT   USB_ENDPTCTRL_TXI_SHIFT
#define	USBHS_EPCR_TXI(x)
#define	USBHS_EPCR_TXR_MASK   USB_ENDPTCTRL_TXR_MASK
#define	USBHS_EPCR_TXR_SHIFT   USB_ENDPTCTRL_TXR_SHIFT
#define	USBHS_EPCR_TXR(x)
#define	USBHS_EPCR_TXE_MASK   USB_ENDPTCTRL_TXE_MASK
#define	USBHS_EPCR_TXE_SHIFT   USB_ENDPTCTRL_TXE_SHIFT
#define	USBHS_EPCR_TXE(x)
#define	USBHS_EPCR_COUNT   USB_ENDPTCTRL_COUNT
#define	USBHS_Type   USB_Type
#define	USBHS_BASE_ADDRS   USB_BASE_ADDRS
#define	USBHS_IRQS   { USB_OTG1_IRQn, USB_OTG2_IRQn }
#define	USBHS_IRQHandler   USB_OTG1_IRQHandler
#define	USBHS_STACK_BASE_ADDRS   { USB_OTG1_BASE, USB_OTG2_BASE }
#define	USBHSDCD1_BASE   (0x40434800u)
#define	USBHSDCD1   ((USBHSDCD_Type *)USBHSDCD1_BASE)
#define	USBHSDCD2_BASE   (0x40438800u)
#define	USBHSDCD2   ((USBHSDCD_Type *)USBHSDCD2_BASE)
#define	USBHSDCD_BASE_ADDRS   { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
#define	USBHSDCD_BASE_PTRS   { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
#define	USBHSDCD_STACK_BASE_ADDRS   { USBHSDCD1_BASE, USBHSDCD2_BASE }
#define	USBNC_OTG1_BASE   (0x40430200u)
#define	USBNC_OTG1   ((USBNC_Type *)USBNC_OTG1_BASE)
#define	USBNC_OTG2_BASE   (0x4042C200u)
#define	USBNC_OTG2   ((USBNC_Type *)USBNC_OTG2_BASE)
#define	USBNC_BASE_ADDRS   { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE }
#define	USBNC_BASE_PTRS   { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 }
#define	USB_OTGn_CTRL   CTRL1
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK   USBNC_CTRL1_OVER_CUR_DIS_MASK
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT   USBNC_CTRL1_OVER_CUR_DIS_SHIFT
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK   USBNC_CTRL1_OVER_CUR_POL_MASK
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT   USBNC_CTRL1_OVER_CUR_POL_SHIFT
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)
#define	USBNC_USB_OTGn_CTRL_PWR_POL_MASK   USBNC_CTRL1_PWR_POL_MASK
#define	USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT   USBNC_CTRL1_PWR_POL_SHIFT
#define	USBNC_USB_OTGn_CTRL_PWR_POL(x)
#define	USBNC_USB_OTGn_CTRL_WIE_MASK   USBNC_CTRL1_WIE_MASK
#define	USBNC_USB_OTGn_CTRL_WIE_SHIFT   USBNC_CTRL1_WIE_SHIFT
#define	USBNC_USB_OTGn_CTRL_WIE(x)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK   USBNC_CTRL1_WKUP_SW_EN_MASK
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT   USBNC_CTRL1_WKUP_SW_EN_SHIFT
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_MASK   USBNC_CTRL1_WKUP_SW_MASK
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT   USBNC_CTRL1_WKUP_SW_SHIFT
#define	USBNC_USB_OTGn_CTRL_WKUP_SW(x)
#define	USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK   USBNC_CTRL1_WKUP_ID_EN_MASK
#define	USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT   USBNC_CTRL1_WKUP_ID_EN_SHIFT
#define	USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)
#define	USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK   USBNC_CTRL1_WKUP_VBUS_EN_MASK
#define	USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT   USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
#define	USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)
#define	USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK   USBNC_CTRL1_WKUP_DPDM_EN_MASK
#define	USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT   USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
#define	USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)
#define	USBNC_USB_OTGn_CTRL_WIR_MASK   USBNC_CTRL1_WIR_MASK
#define	USBNC_USB_OTGn_CTRL_WIR_SHIFT   USBNC_CTRL1_WIR_SHIFT
#define	USBNC_USB_OTGn_CTRL_WIR(x)
#define	USBNC_STACK_BASE_ADDRS   { USBNC_OTG1_BASE, USBNC_OTG2_BASE }
#define	USBPHY1_BASE   (0x40434000u)
#define	USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)
#define	USBPHY2_BASE   (0x40438000u)
#define	USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)
#define	USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }
#define	USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
#define	USBPHY_IRQS   { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
#define	USBPHY_CTRL_ENDEVPLUGINDET_MASK   USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define	USBPHY_CTRL_ENDEVPLUGINDET_SHIFT   USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define	USBPHY_CTRL_ENDEVPLUGINDET(x)
#define	USBPHY_TX_TXCAL45DM_MASK   USBPHY_TX_TXCAL45DN_MASK
#define	USBPHY_TX_TXCAL45DM_SHIFT   USBPHY_TX_TXCAL45DN_SHIFT
#define	USBPHY_TX_TXCAL45DM(x)
#define	USBPHY_STACK_BASE_ADDRS   { USBPHY1_BASE, USBPHY2_BASE }
#define	USDHC1_BASE   (0x40418000u)
#define	USDHC1   ((USDHC_Type *)USDHC1_BASE)
#define	USDHC2_BASE   (0x4041C000u)
#define	USDHC2   ((USDHC_Type *)USDHC2_BASE)
#define	USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }
#define	USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }
#define	USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
#define	VIDEO_MUX_BASE   (0x40818000u)
#define	VIDEO_MUX   ((VIDEO_MUX_Type *)VIDEO_MUX_BASE)
#define	VIDEO_MUX_BASE_ADDRS   { VIDEO_MUX_BASE }
#define	VIDEO_MUX_BASE_PTRS   { VIDEO_MUX }
#define	VIDEO_PLL_BASE   (0u)
#define	VIDEO_PLL   ((VIDEO_PLL_Type *)VIDEO_PLL_BASE)
#define	VIDEO_PLL_BASE_ADDRS   { VIDEO_PLL_BASE }
#define	VIDEO_PLL_BASE_PTRS   { VIDEO_PLL }
#define	VMBANDGAP_BASE   (0u)
#define	VMBANDGAP   ((VMBANDGAP_Type *)VMBANDGAP_BASE)
#define	VMBANDGAP_BASE_ADDRS   { VMBANDGAP_BASE }
#define	VMBANDGAP_BASE_PTRS   { VMBANDGAP }
#define	WDOG1_BASE   (0x40030000u)
#define	WDOG1   ((WDOG_Type *)WDOG1_BASE)
#define	WDOG2_BASE   (0x40034000u)
#define	WDOG2   ((WDOG_Type *)WDOG2_BASE)
#define	WDOG_BASE_ADDRS   { 0u, WDOG1_BASE, WDOG2_BASE }
#define	WDOG_BASE_PTRS   { (WDOG_Type *)0u, WDOG1, WDOG2 }
#define	WDOG_IRQS   { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
#define	XBARA1_BASE   (0x4003C000u)
#define	XBARA1   ((XBARA_Type *)XBARA1_BASE)
#define	XBARA_BASE_ADDRS   { 0u, XBARA1_BASE }
#define	XBARA_BASE_PTRS   { (XBARA_Type *)0u, XBARA1 }
#define	XBARB2_BASE   (0x40040000u)
#define	XBARB2   ((XBARB_Type *)XBARB2_BASE)
#define	XBARB3_BASE   (0x40044000u)
#define	XBARB3   ((XBARB_Type *)XBARB3_BASE)
#define	XBARB_BASE_ADDRS   { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
#define	XBARB_BASE_PTRS   { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
#define	XECC_FLEXSPI1_BASE   (0x4001C000u)
#define	XECC_FLEXSPI1   ((XECC_Type *)XECC_FLEXSPI1_BASE)
#define	XECC_FLEXSPI2_BASE   (0x40020000u)
#define	XECC_FLEXSPI2   ((XECC_Type *)XECC_FLEXSPI2_BASE)
#define	XECC_SEMC_BASE   (0x40024000u)
#define	XECC_SEMC   ((XECC_Type *)XECC_SEMC_BASE)
#define	XECC_BASE_ADDRS   { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE }
#define	XECC_BASE_PTRS   { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC }
#define	XRDC2_MSC_MSAC_W0_COUNT   (128U)
#define	XRDC2_MSC_MSAC_W1_COUNT   (128U)
#define	XRDC2_MDAC_MDA_W0_COUNT   (32U)
#define	XRDC2_MDAC_MDA_W0_COUNT2   (32U)
#define	XRDC2_MDAC_MDA_W1_COUNT   (32U)
#define	XRDC2_MDAC_MDA_W1_COUNT2   (32U)
#define	XRDC2_PAC_PDAC_W0_COUNT   (8U)
#define	XRDC2_PAC_PDAC_W0_COUNT2   (256U)
#define	XRDC2_PAC_PDAC_W1_COUNT   (8U)
#define	XRDC2_PAC_PDAC_W1_COUNT2   (256U)
#define	XRDC2_MRC_MRGD_W0_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W0_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W1_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W1_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W2_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W2_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W3_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W3_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W5_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W5_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W6_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W6_COUNT2   (32U)
#define	XRDC2_D0_BASE   (0x40CE0000u)
#define	XRDC2_D0   ((XRDC2_Type *)XRDC2_D0_BASE)
#define	XRDC2_D1_BASE   (0x40CD0000u)
#define	XRDC2_D1   ((XRDC2_Type *)XRDC2_D1_BASE)
#define	XRDC2_BASE_ADDRS   { XRDC2_D0_BASE, XRDC2_D1_BASE }
#define	XRDC2_BASE_PTRS   { XRDC2_D0, XRDC2_D1 }
#define	NXP_VAL2FLD(field, value)
	Mask and left-shift a bit field value for use in a register bit range.
#define	NXP_FLD2VAL(field, value)
	Mask and right-shift a register value to extract a bit field value.
VERID - Version ID Register
#define	ADC_VERID_RES_MASK   (0x1U)
#define	ADC_VERID_RES_SHIFT   (0U)
#define	ADC_VERID_RES(x)
#define	ADC_VERID_DIFFEN_MASK   (0x2U)
#define	ADC_VERID_DIFFEN_SHIFT   (1U)
#define	ADC_VERID_DIFFEN(x)
#define	ADC_VERID_MVI_MASK   (0x8U)
#define	ADC_VERID_MVI_SHIFT   (3U)
#define	ADC_VERID_MVI(x)
#define	ADC_VERID_CSW_MASK   (0x70U)
#define	ADC_VERID_CSW_SHIFT   (4U)
#define	ADC_VERID_CSW(x)
#define	ADC_VERID_VR1RNGI_MASK   (0x100U)
#define	ADC_VERID_VR1RNGI_SHIFT   (8U)
#define	ADC_VERID_VR1RNGI(x)
#define	ADC_VERID_IADCKI_MASK   (0x200U)
#define	ADC_VERID_IADCKI_SHIFT   (9U)
#define	ADC_VERID_IADCKI(x)
#define	ADC_VERID_CALOFSI_MASK   (0x400U)
#define	ADC_VERID_CALOFSI_SHIFT   (10U)
#define	ADC_VERID_CALOFSI(x)
#define	ADC_VERID_MINOR_MASK   (0xFF0000U)
#define	ADC_VERID_MINOR_SHIFT   (16U)
#define	ADC_VERID_MINOR(x)
#define	ADC_VERID_MAJOR_MASK   (0xFF000000U)
#define	ADC_VERID_MAJOR_SHIFT   (24U)
#define	ADC_VERID_MAJOR(x)
#define	CMP_VERID_FEATURE_MASK   (0xFFFFU)
#define	CMP_VERID_FEATURE_SHIFT   (0U)
#define	CMP_VERID_FEATURE(x)
#define	CMP_VERID_MINOR_MASK   (0xFF0000U)
#define	CMP_VERID_MINOR_SHIFT   (16U)
#define	CMP_VERID_MINOR(x)
#define	CMP_VERID_MAJOR_MASK   (0xFF000000U)
#define	CMP_VERID_MAJOR_SHIFT   (24U)
#define	CMP_VERID_MAJOR(x)
#define	FLEXIO_VERID_FEATURE_MASK   (0xFFFFU)
#define	FLEXIO_VERID_FEATURE_SHIFT   (0U)
#define	FLEXIO_VERID_FEATURE(x)
#define	FLEXIO_VERID_MINOR_MASK   (0xFF0000U)
#define	FLEXIO_VERID_MINOR_SHIFT   (16U)
#define	FLEXIO_VERID_MINOR(x)
#define	FLEXIO_VERID_MAJOR_MASK   (0xFF000000U)
#define	FLEXIO_VERID_MAJOR_SHIFT   (24U)
#define	FLEXIO_VERID_MAJOR(x)
#define	LPUART_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPUART_VERID_FEATURE_SHIFT   (0U)
#define	LPUART_VERID_FEATURE(x)
#define	LPUART_VERID_MINOR_MASK   (0xFF0000U)
#define	LPUART_VERID_MINOR_SHIFT   (16U)
#define	LPUART_VERID_MINOR(x)
#define	LPUART_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPUART_VERID_MAJOR_SHIFT   (24U)
#define	LPUART_VERID_MAJOR(x)
PARAM - Parameter Register
#define	ADC_PARAM_TRIG_NUM_MASK   (0xFFU)
#define	ADC_PARAM_TRIG_NUM_SHIFT   (0U)
#define	ADC_PARAM_TRIG_NUM(x)
#define	ADC_PARAM_FIFOSIZE_MASK   (0xFF00U)
#define	ADC_PARAM_FIFOSIZE_SHIFT   (8U)
#define	ADC_PARAM_FIFOSIZE(x)
#define	ADC_PARAM_CV_NUM_MASK   (0xFF0000U)
#define	ADC_PARAM_CV_NUM_SHIFT   (16U)
#define	ADC_PARAM_CV_NUM(x)
#define	ADC_PARAM_CMD_NUM_MASK   (0xFF000000U)
#define	ADC_PARAM_CMD_NUM_SHIFT   (24U)
#define	ADC_PARAM_CMD_NUM(x)
#define	CMP_PARAM_PARAM_MASK   (0xFFFFFFFFU)
#define	CMP_PARAM_PARAM_SHIFT   (0U)
#define	CMP_PARAM_PARAM(x)
#define	DAC_PARAM_FIFOSZ_MASK   (0x7U)
#define	DAC_PARAM_FIFOSZ_SHIFT   (0U)
#define	DAC_PARAM_FIFOSZ(x)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_MASK   (0xFFU)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT   (0U)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH(x)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_MASK   (0xFF00U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT   (8U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH(x)
#define	FLEXIO_PARAM_SHIFTER_MASK   (0xFFU)
#define	FLEXIO_PARAM_SHIFTER_SHIFT   (0U)
#define	FLEXIO_PARAM_SHIFTER(x)
#define	FLEXIO_PARAM_TIMER_MASK   (0xFF00U)
#define	FLEXIO_PARAM_TIMER_SHIFT   (8U)
#define	FLEXIO_PARAM_TIMER(x)
#define	FLEXIO_PARAM_PIN_MASK   (0xFF0000U)
#define	FLEXIO_PARAM_PIN_SHIFT   (16U)
#define	FLEXIO_PARAM_PIN(x)
#define	FLEXIO_PARAM_TRIGGER_MASK   (0xFF000000U)
#define	FLEXIO_PARAM_TRIGGER_SHIFT   (24U)
#define	FLEXIO_PARAM_TRIGGER(x)
#define	LPUART_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPUART_PARAM_TXFIFO_SHIFT   (0U)
#define	LPUART_PARAM_TXFIFO(x)
#define	LPUART_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPUART_PARAM_RXFIFO_SHIFT   (8U)
#define	LPUART_PARAM_RXFIFO(x)
CTRL - LPADC Control Register
#define	ADC_CTRL_ADCEN_MASK   (0x1U)
#define	ADC_CTRL_ADCEN_SHIFT   (0U)
#define	ADC_CTRL_ADCEN(x)
#define	ADC_CTRL_RST_MASK   (0x2U)
#define	ADC_CTRL_RST_SHIFT   (1U)
#define	ADC_CTRL_RST(x)
#define	ADC_CTRL_DOZEN_MASK   (0x4U)
#define	ADC_CTRL_DOZEN_SHIFT   (2U)
#define	ADC_CTRL_DOZEN(x)
#define	ADC_CTRL_TRIG_SRC_MASK   (0x18U)
#define	ADC_CTRL_TRIG_SRC_SHIFT   (3U)
#define	ADC_CTRL_TRIG_SRC(x)
#define	ADC_CTRL_RSTFIFO_MASK   (0x100U)
#define	ADC_CTRL_RSTFIFO_SHIFT   (8U)
#define	ADC_CTRL_RSTFIFO(x)
STAT - LPADC Status Register
#define	ADC_STAT_RDY_MASK   (0x1U)
#define	ADC_STAT_RDY_SHIFT   (0U)
#define	ADC_STAT_RDY(x)
#define	ADC_STAT_FOF_MASK   (0x2U)
#define	ADC_STAT_FOF_SHIFT   (1U)
#define	ADC_STAT_FOF(x)
#define	ADC_STAT_ADC_ACTIVE_MASK   (0x100U)
#define	ADC_STAT_ADC_ACTIVE_SHIFT   (8U)
#define	ADC_STAT_ADC_ACTIVE(x)
#define	ADC_STAT_TRGACT_MASK   (0x70000U)
#define	ADC_STAT_TRGACT_SHIFT   (16U)
#define	ADC_STAT_TRGACT(x)
#define	ADC_STAT_CMDACT_MASK   (0xF000000U)
#define	ADC_STAT_CMDACT_SHIFT   (24U)
#define	ADC_STAT_CMDACT(x)
IE - Interrupt Enable Register
#define	ADC_IE_FWMIE_MASK   (0x1U)
#define	ADC_IE_FWMIE_SHIFT   (0U)
#define	ADC_IE_FWMIE(x)
#define	ADC_IE_FOFIE_MASK   (0x2U)
#define	ADC_IE_FOFIE_SHIFT   (1U)
#define	ADC_IE_FOFIE(x)
DE - DMA Enable Register
#define	ADC_DE_FWMDE_MASK   (0x1U)
#define	ADC_DE_FWMDE_SHIFT   (0U)
#define	ADC_DE_FWMDE(x)
CFG - LPADC Configuration Register
#define	ADC_CFG_TPRICTRL_MASK   (0x1U)
#define	ADC_CFG_TPRICTRL_SHIFT   (0U)
#define	ADC_CFG_TPRICTRL(x)
#define	ADC_CFG_PWRSEL_MASK   (0x30U)
#define	ADC_CFG_PWRSEL_SHIFT   (4U)
#define	ADC_CFG_PWRSEL(x)
#define	ADC_CFG_REFSEL_MASK   (0xC0U)
#define	ADC_CFG_REFSEL_SHIFT   (6U)
#define	ADC_CFG_REFSEL(x)
#define	ADC_CFG_PUDLY_MASK   (0xFF0000U)
#define	ADC_CFG_PUDLY_SHIFT   (16U)
#define	ADC_CFG_PUDLY(x)
#define	ADC_CFG_PWREN_MASK   (0x10000000U)
#define	ADC_CFG_PWREN_SHIFT   (28U)
#define	ADC_CFG_PWREN(x)
PAUSE - LPADC Pause Register
#define	ADC_PAUSE_PAUSEDLY_MASK   (0x1FFU)
#define	ADC_PAUSE_PAUSEDLY_SHIFT   (0U)
#define	ADC_PAUSE_PAUSEDLY(x)
#define	ADC_PAUSE_PAUSEEN_MASK   (0x80000000U)
#define	ADC_PAUSE_PAUSEEN_SHIFT   (31U)
#define	ADC_PAUSE_PAUSEEN(x)
FCTRL - LPADC FIFO Control Register
#define	ADC_FCTRL_FCOUNT_MASK   (0x1FU)
#define	ADC_FCTRL_FCOUNT_SHIFT   (0U)
#define	ADC_FCTRL_FCOUNT(x)
#define	ADC_FCTRL_FWMARK_MASK   (0xF0000U)
#define	ADC_FCTRL_FWMARK_SHIFT   (16U)
#define	ADC_FCTRL_FWMARK(x)
SWTRIG - Software Trigger Register
#define	ADC_SWTRIG_SWT0_MASK   (0x1U)
#define	ADC_SWTRIG_SWT0_SHIFT   (0U)
#define	ADC_SWTRIG_SWT0(x)
#define	ADC_SWTRIG_SWT1_MASK   (0x2U)
#define	ADC_SWTRIG_SWT1_SHIFT   (1U)
#define	ADC_SWTRIG_SWT1(x)
#define	ADC_SWTRIG_SWT2_MASK   (0x4U)
#define	ADC_SWTRIG_SWT2_SHIFT   (2U)
#define	ADC_SWTRIG_SWT2(x)
#define	ADC_SWTRIG_SWT3_MASK   (0x8U)
#define	ADC_SWTRIG_SWT3_SHIFT   (3U)
#define	ADC_SWTRIG_SWT3(x)
#define	ADC_SWTRIG_SWT4_MASK   (0x10U)
#define	ADC_SWTRIG_SWT4_SHIFT   (4U)
#define	ADC_SWTRIG_SWT4(x)
#define	ADC_SWTRIG_SWT5_MASK   (0x20U)
#define	ADC_SWTRIG_SWT5_SHIFT   (5U)
#define	ADC_SWTRIG_SWT5(x)
#define	ADC_SWTRIG_SWT6_MASK   (0x40U)
#define	ADC_SWTRIG_SWT6_SHIFT   (6U)
#define	ADC_SWTRIG_SWT6(x)
#define	ADC_SWTRIG_SWT7_MASK   (0x80U)
#define	ADC_SWTRIG_SWT7_SHIFT   (7U)
#define	ADC_SWTRIG_SWT7(x)
TCTRL - Trigger Control Register
#define	ADC_TCTRL_HTEN_MASK   (0x1U)
#define	ADC_TCTRL_HTEN_SHIFT   (0U)
#define	ADC_TCTRL_HTEN(x)
#define	ADC_TCTRL_CMD_SEL_MASK   (0x2U)
#define	ADC_TCTRL_CMD_SEL_SHIFT   (1U)
#define	ADC_TCTRL_CMD_SEL(x)
#define	ADC_TCTRL_TPRI_MASK   (0x700U)
#define	ADC_TCTRL_TPRI_SHIFT   (8U)
#define	ADC_TCTRL_TPRI(x)
#define	ADC_TCTRL_TDLY_MASK   (0xF0000U)
#define	ADC_TCTRL_TDLY_SHIFT   (16U)
#define	ADC_TCTRL_TDLY(x)
#define	ADC_TCTRL_TCMD_MASK   (0xF000000U)
#define	ADC_TCTRL_TCMD_SHIFT   (24U)
#define	ADC_TCTRL_TCMD(x)
CMDL - LPADC Command Low Buffer Register
#define	ADC_CMDL_ADCH_MASK   (0x1FU)
#define	ADC_CMDL_ADCH_SHIFT   (0U)
#define	ADC_CMDL_ADCH(x)
#define	ADC_CMDL_ABSEL_MASK   (0x20U)
#define	ADC_CMDL_ABSEL_SHIFT   (5U)
#define	ADC_CMDL_ABSEL(x)
#define	ADC_CMDL_DIFF_MASK   (0x40U)
#define	ADC_CMDL_DIFF_SHIFT   (6U)
#define	ADC_CMDL_DIFF(x)
#define	ADC_CMDL_CSCALE_MASK   (0x2000U)
#define	ADC_CMDL_CSCALE_SHIFT   (13U)
#define	ADC_CMDL_CSCALE(x)
CMDH - LPADC Command High Buffer Register
#define	ADC_CMDH_CMPEN_MASK   (0x3U)
#define	ADC_CMDH_CMPEN_SHIFT   (0U)
#define	ADC_CMDH_CMPEN(x)
#define	ADC_CMDH_LWI_MASK   (0x80U)
#define	ADC_CMDH_LWI_SHIFT   (7U)
#define	ADC_CMDH_LWI(x)
#define	ADC_CMDH_STS_MASK   (0x700U)
#define	ADC_CMDH_STS_SHIFT   (8U)
#define	ADC_CMDH_STS(x)
#define	ADC_CMDH_AVGS_MASK   (0x7000U)
#define	ADC_CMDH_AVGS_SHIFT   (12U)
#define	ADC_CMDH_AVGS(x)
#define	ADC_CMDH_LOOP_MASK   (0xF0000U)
#define	ADC_CMDH_LOOP_SHIFT   (16U)
#define	ADC_CMDH_LOOP(x)
#define	ADC_CMDH_NEXT_MASK   (0xF000000U)
#define	ADC_CMDH_NEXT_SHIFT   (24U)
#define	ADC_CMDH_NEXT(x)
CV - Compare Value Register
#define	ADC_CV_CVL_MASK   (0xFFFFU)
#define	ADC_CV_CVL_SHIFT   (0U)
#define	ADC_CV_CVL(x)
#define	ADC_CV_CVH_MASK   (0xFFFF0000U)
#define	ADC_CV_CVH_SHIFT   (16U)
#define	ADC_CV_CVH(x)
RESFIFO - LPADC Data Result FIFO Register
#define	ADC_RESFIFO_D_MASK   (0xFFFFU)
#define	ADC_RESFIFO_D_SHIFT   (0U)
#define	ADC_RESFIFO_D(x)
#define	ADC_RESFIFO_TSRC_MASK   (0x70000U)
#define	ADC_RESFIFO_TSRC_SHIFT   (16U)
#define	ADC_RESFIFO_TSRC(x)
#define	ADC_RESFIFO_LOOPCNT_MASK   (0xF00000U)
#define	ADC_RESFIFO_LOOPCNT_SHIFT   (20U)
#define	ADC_RESFIFO_LOOPCNT(x)
#define	ADC_RESFIFO_CMDSRC_MASK   (0xF000000U)
#define	ADC_RESFIFO_CMDSRC_SHIFT   (24U)
#define	ADC_RESFIFO_CMDSRC(x)
#define	ADC_RESFIFO_VALID_MASK   (0x80000000U)
#define	ADC_RESFIFO_VALID_SHIFT   (31U)
#define	ADC_RESFIFO_VALID(x)
CTRL - ADC_ETC Global Control Register
#define	ADC_ETC_CTRL_TRIG_ENABLE_MASK   (0xFFU)
#define	ADC_ETC_CTRL_TRIG_ENABLE_SHIFT   (0U)
#define	ADC_ETC_CTRL_TRIG_ENABLE(x)
#define	ADC_ETC_CTRL_PRE_DIVIDER_MASK   (0xFF0000U)
#define	ADC_ETC_CTRL_PRE_DIVIDER_SHIFT   (16U)
#define	ADC_ETC_CTRL_PRE_DIVIDER(x)
#define	ADC_ETC_CTRL_DMA_MODE_SEL_MASK   (0x20000000U)
#define	ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT   (29U)
#define	ADC_ETC_CTRL_DMA_MODE_SEL(x)
#define	ADC_ETC_CTRL_SOFTRST_MASK   (0x80000000U)
#define	ADC_ETC_CTRL_SOFTRST_SHIFT   (31U)
#define	ADC_ETC_CTRL_SOFTRST(x)
DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK   (0x1U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT   (0U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK   (0x2U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT   (1U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK   (0x4U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT   (2U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK   (0x8U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT   (3U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK   (0x10U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT   (4U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK   (0x20U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT   (5U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK   (0x40U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT   (6U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK   (0x80U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT   (7U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK   (0x10000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT   (16U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK   (0x20000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT   (17U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK   (0x40000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT   (18U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK   (0x80000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT   (19U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK   (0x100000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT   (20U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK   (0x200000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT   (21U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK   (0x400000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT   (22U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x)
#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK   (0x800000U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT   (23U)
#define	ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x)
DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK   (0x1U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT   (0U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK   (0x2U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT   (1U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK   (0x4U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT   (2U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK   (0x8U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT   (3U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK   (0x10U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT   (4U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK   (0x20U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT   (5U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK   (0x40U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT   (6U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK   (0x80U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT   (7U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK   (0x100U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT   (8U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK   (0x200U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT   (9U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK   (0x400U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT   (10U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK   (0x800U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT   (11U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK   (0x1000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT   (12U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK   (0x2000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT   (13U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK   (0x4000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT   (14U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK   (0x8000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT   (15U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK   (0x10000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT   (16U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK   (0x20000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT   (17U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK   (0x40000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT   (18U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK   (0x80000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT   (19U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK   (0x100000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT   (20U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK   (0x200000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT   (21U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK   (0x400000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT   (22U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK   (0x800000U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT   (23U)
#define	ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x)
DMA_CTRL - ETC DMA control Register
#define	ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK   (0x1U)
#define	ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT   (0U)
#define	ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK   (0x2U)
#define	ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT   (1U)
#define	ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK   (0x4U)
#define	ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT   (2U)
#define	ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK   (0x8U)
#define	ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT   (3U)
#define	ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK   (0x10U)
#define	ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT   (4U)
#define	ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK   (0x20U)
#define	ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT   (5U)
#define	ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK   (0x40U)
#define	ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT   (6U)
#define	ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK   (0x80U)
#define	ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT   (7U)
#define	ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x)
#define	ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK   (0x10000U)
#define	ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT   (16U)
#define	ADC_ETC_DMA_CTRL_TRIG0_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK   (0x20000U)
#define	ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT   (17U)
#define	ADC_ETC_DMA_CTRL_TRIG1_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK   (0x40000U)
#define	ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT   (18U)
#define	ADC_ETC_DMA_CTRL_TRIG2_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK   (0x80000U)
#define	ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT   (19U)
#define	ADC_ETC_DMA_CTRL_TRIG3_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK   (0x100000U)
#define	ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT   (20U)
#define	ADC_ETC_DMA_CTRL_TRIG4_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK   (0x200000U)
#define	ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT   (21U)
#define	ADC_ETC_DMA_CTRL_TRIG5_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK   (0x400000U)
#define	ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT   (22U)
#define	ADC_ETC_DMA_CTRL_TRIG6_REQ(x)
#define	ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK   (0x800000U)
#define	ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT   (23U)
#define	ADC_ETC_DMA_CTRL_TRIG7_REQ(x)
TRIGn_CTRL - ETC_TRIG Control Register
#define	ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK   (0x1U)
#define	ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT   (0U)
#define	ADC_ETC_TRIGn_CTRL_SW_TRIG(x)
#define	ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK   (0x10U)
#define	ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT   (4U)
#define	ADC_ETC_TRIGn_CTRL_TRIG_MODE(x)
#define	ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK   (0x700U)
#define	ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT   (8U)
#define	ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x)
#define	ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK   (0x7000U)
#define	ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT   (12U)
#define	ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x)
#define	ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK   (0x10000U)
#define	ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT   (16U)
#define	ADC_ETC_TRIGn_CTRL_SYNC_MODE(x)
#define	ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK   (0xFF000000U)
#define	ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT   (24U)
#define	ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x)
TRIGn_COUNTER - ETC_TRIG Counter Register
#define	ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK   (0xFFFFU)
#define	ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT   (0U)
#define	ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x)
#define	ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK   (0xFFFF0000U)
#define	ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT   (16U)
#define	ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x)
TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK   (0xFU)
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT   (0U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK   (0xFF0U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT   (4U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK   (0x1000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT   (12U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK   (0x6000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT   (13U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK   (0x8000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT   (15U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK   (0xF0000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT   (16U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK   (0xFF00000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT   (20U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK   (0x10000000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT   (28U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK   (0x60000000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT   (29U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1(x)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK   (0x80000000U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT   (31U)
#define	ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x)
TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK   (0xFU)
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT   (0U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK   (0xFF0U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT   (4U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK   (0x1000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT   (12U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK   (0x6000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT   (13U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK   (0x8000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT   (15U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK   (0xF0000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT   (16U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK   (0xFF00000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT   (20U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK   (0x10000000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT   (28U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK   (0x60000000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT   (29U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3(x)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK   (0x80000000U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT   (31U)
#define	ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x)
TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK   (0xFU)
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT   (0U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK   (0xFF0U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT   (4U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK   (0x1000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT   (12U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK   (0x6000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT   (13U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK   (0x8000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT   (15U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK   (0xF0000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT   (16U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK   (0xFF00000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT   (20U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK   (0x10000000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT   (28U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK   (0x60000000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT   (29U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5(x)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK   (0x80000000U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT   (31U)
#define	ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x)
TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK   (0xFU)
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT   (0U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK   (0xFF0U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT   (4U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK   (0x1000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT   (12U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK   (0x6000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT   (13U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK   (0x8000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT   (15U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK   (0xF0000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT   (16U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK   (0xFF00000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT   (20U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK   (0x10000000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT   (28U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK   (0x60000000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT   (29U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7(x)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK   (0x80000000U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT   (31U)
#define	ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x)
TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK   (0xFFFU)
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT   (0U)
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA0(x)
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK   (0xFFF0000U)
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT   (16U)
#define	ADC_ETC_TRIGn_RESULT_1_0_DATA1(x)
TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK   (0xFFFU)
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT   (0U)
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA2(x)
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK   (0xFFF0000U)
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT   (16U)
#define	ADC_ETC_TRIGn_RESULT_3_2_DATA3(x)
TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK   (0xFFFU)
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT   (0U)
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA4(x)
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK   (0xFFF0000U)
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT   (16U)
#define	ADC_ETC_TRIGn_RESULT_5_4_DATA5(x)
TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK   (0xFFFU)
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT   (0U)
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA6(x)
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK   (0xFFF0000U)
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT   (16U)
#define	ADC_ETC_TRIGn_RESULT_7_6_DATA7(x)
PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK   (0x1U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT   (0U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK   (0x4U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT   (2U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK   (0x8U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT   (3U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK   (0x10U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT   (4U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK   (0x20U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT   (5U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK   (0x40U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT   (6U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK   (0x100U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT   (8U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK   (0x80000U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT   (19U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK   (0x100000U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT   (20U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x)
PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK   (0x3U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT   (0U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x)
PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK   (0x4U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT   (2U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK   (0x20U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT   (5U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK   (0x40U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT   (6U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK   (0x20000U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT   (17U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK   (0x40000U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT   (18U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK   (0x1F00000U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT   (20U)
#define	ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x)
PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK   (0x1U)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT   (0U)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK   (0x2U)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT   (1U)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK   (0x4U)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT   (2U)
#define	ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x)
MISC_DIFPROG - Chip Silicon Version Register
#define	ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT   (0U)
#define	ANADIG_MISC_MISC_DIFPROG_CHIPID(x)
VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK   (0xFFU)
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x)
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK   (0x10000U)
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT   (16U)
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x)
VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x)
VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x)
VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK   (0xFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK   (0x100U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT   (8U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK   (0x200U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT   (9U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK   (0x10000U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT   (16U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x)
VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x)
VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x)
VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK   (0xFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK   (0x100U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT   (8U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK   (0x200U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT   (9U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK   (0x10000U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT   (16U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x)
VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x)
VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x)
VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK   (0xFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK   (0x100U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT   (8U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK   (0x200U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT   (9U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK   (0x10000U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT   (16U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x)
VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x)
VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT   (0U)
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x)
VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK   (0xFFU)
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x)
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK   (0x10000U)
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT   (16U)
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x)
VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x)
VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x)
VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x)
VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK   (0xFFU)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK   (0x100U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT   (8U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK   (0x200U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT   (9U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK   (0x10000U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT   (16U)
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x)
VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x)
VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK   (0xFFFFFFFFU)
#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT   (0U)
#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x)
OSC_48M_CTRL - 48MHz RCOSC Control Register
#define	ANADIG_OSC_OSC_48M_CTRL_TEN_MASK   (0x2U)
#define	ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT   (1U)
#define	ANADIG_OSC_OSC_48M_CTRL_TEN(x)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK   (0x1000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT   (24U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK   (0x40000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT   (30U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x)
OSC_24M_CTRL - 24MHz OSC Control Register
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK   (0x1U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT   (0U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT   (1U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK   (0x4U)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT   (2U)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK   (0x8U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT   (3U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK   (0x10U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT   (4U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK   (0x80U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT   (7U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK   (0x40000000U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT   (30U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x)
OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT   (31U)
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x)
OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK   (0x1U)
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT   (0U)
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD(x)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK   (0x2U)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT   (1U)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x)
OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK   (0x1U)
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT   (0U)
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK   (0x400U)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT   (10U)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT   (24U)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x)
OSC_16M_CTRL - 16MHz RCOSC Control Register
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK   (0x2U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT   (1U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK   (0x8U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT   (3U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK   (0x100U)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT   (8U)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x)
ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK   (0xFFU)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT   (0U)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK   (0x1000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT   (12U)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK   (0x2000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT   (13U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK   (0x4000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT   (14U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK   (0x18000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT   (15U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK   (0x20000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT   (17U)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK   (0x20000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT   (29U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK   (0x40000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT   (30U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x)
SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK   (0x8U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT   (3U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK   (0x10U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT   (4U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK   (0x800U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT   (11U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK   (0x2000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT   (13U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK   (0x10000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT   (16U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK   (0x200000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT   (21U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK   (0x10000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT   (28U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK   (0x20000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT   (29U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK   (0x40000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT   (30U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x)
SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK   (0x2U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT   (1U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK   (0x4U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT   (2U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK   (0x8U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT   (3U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK   (0x10U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT   (4U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK   (0x20U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT   (5U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK   (0x40U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT   (6U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK   (0x80U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT   (7U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK   (0x100U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT   (8U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x)
SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK   (0x3FU)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK   (0x40U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT   (6U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK   (0x80U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT   (7U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK   (0x3F00U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT   (8U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK   (0x4000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT   (14U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK   (0x8000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT   (15U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK   (0x3F0000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT   (16U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK   (0x400000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT   (22U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK   (0x800000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT   (23U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK   (0x3F000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT   (24U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK   (0x40000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT   (30U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK   (0x80000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT   (31U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x)
SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK   (0x8U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT   (3U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK   (0x800U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT   (11U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK   (0x2000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT   (13U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK   (0x10000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT   (16U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK   (0x20000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT   (17U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK   (0x40000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT   (18U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK   (0x80000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT   (19U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK   (0x800000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT   (23U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK   (0x20000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT   (29U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK   (0x40000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT   (30U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x)
SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK   (0x2U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT   (1U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK   (0x4U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT   (2U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK   (0x8U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT   (3U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK   (0x10U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT   (4U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK   (0x20U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT   (5U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK   (0x40U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT   (6U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK   (0x80U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT   (7U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK   (0x100U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT   (8U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x)
SYS_PLL2_SS - SYS_PLL2_SS_REGISTER
#define	ANADIG_PLL_SYS_PLL2_SS_STEP_MASK   (0x7FFFU)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP(x)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK   (0x8000U)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT   (15U)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP_MASK   (0xFFFF0000U)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT   (16U)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP(x)
SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK   (0x3FU)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK   (0x40U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT   (6U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK   (0x80U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT   (7U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK   (0x3F00U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT   (8U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK   (0x4000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT   (14U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK   (0x8000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT   (15U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK   (0x3F0000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT   (16U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK   (0x400000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT   (22U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK   (0x800000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT   (23U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK   (0x3F000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT   (24U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK   (0x40000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT   (30U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK   (0x80000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT   (31U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x)
SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD(x)
SYS_PLL1_SS - SYS_PLL1_SS_REGISTER
#define	ANADIG_PLL_SYS_PLL1_SS_STEP_MASK   (0x7FFFU)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP(x)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK   (0x8000U)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT   (15U)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP_MASK   (0xFFFF0000U)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT   (16U)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP(x)
SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK   (0x2000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT   (13U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK   (0x4000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT   (14U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK   (0x2000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT   (25U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK   (0x4000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT   (26U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK   (0x8000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT   (27U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK   (0x10000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT   (28U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK   (0x20000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT   (29U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK   (0x40000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT   (30U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x)
SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x)
SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x)
SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK   (0x7FU)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT   (0U)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x)
PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK   (0x2000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT   (13U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK   (0x4000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT   (14U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK   (0x20000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT   (29U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK   (0x40000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT   (30U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x)
PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK   (0x7FFFU)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT   (0U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK   (0x8000U)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT   (15U)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK   (0xFFFF0000U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT   (16U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP(x)
PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT   (0U)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x)
PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT   (0U)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x)
PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK   (0x7FU)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT   (0U)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x)
PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK   (0x2000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT   (13U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK   (0x4000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT   (14U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK   (0x1000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT   (24U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK   (0x20000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT   (29U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK   (0x40000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT   (30U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x)
PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK   (0x7FFFU)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT   (0U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK   (0x8000U)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT   (15U)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK   (0xFFFF0000U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT   (16U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP(x)
PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT   (0U)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x)
PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT   (0U)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x)
PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK   (0x7FU)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT   (0U)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x)
PMU_LDO_PLL - PMU_LDO_PLL_REGISTER
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK   (0x1U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT   (0U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK   (0x2U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT   (1U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK   (0x10000U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT   (16U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK   (0x40000000U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT   (30U)
#define	ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x)
PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER
#define	ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK   (0x1FFFU)
#define	ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT   (0U)
#define	ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK   (0x4000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT   (14U)
#define	ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x)
PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK   (0x3FEU)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT   (1U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK   (0x1C00U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT   (10U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK   (0x1FE000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT   (13U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK   (0x400000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT   (22U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK   (0x800000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT   (23U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK   (0x1000000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT   (24U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK   (0x2000000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT   (25U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK   (0x4000000U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT   (26U)
#define	ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x)
PMU_REF_CTRL - PMU_REF_CTRL_REGISTER
#define	ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK   (0x1U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT   (0U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK   (0x2U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT   (1U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK   (0x4U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT   (2U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK   (0x8U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT   (3U)
#define	ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x)
#define	ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK   (0x10U)
#define	ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT   (4U)
#define	ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x)
PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER
#define	ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK   (0x100U)
#define	ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT   (8U)
#define	ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x)
LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x)
LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x)
LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x)
LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x)
LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x)
LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x)
LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x)
LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK   (0xFFU)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK   (0xFF00U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK   (0xFF0000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT   (16U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK   (0xFF000000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT   (24U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x)
LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK   (0xFFU)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK   (0xFF00U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK   (0xFF0000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT   (16U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK   (0xFF000000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT   (24U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x)
LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK   (0xFFU)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK   (0xFF00U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK   (0xFF0000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT   (16U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK   (0xFF000000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT   (24U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x)
LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK   (0xFFU)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK   (0xFF00U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK   (0xFF0000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT   (16U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK   (0xFF000000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT   (24U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x)
LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x)
LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x)
LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x)
LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x)
BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x)
RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x)
RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x)
BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x)
PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x)
RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x)
RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK   (0x1U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT   (0U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK   (0x2U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT   (1U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK   (0x4U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT   (2U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK   (0x8U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT   (3U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK   (0x10U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT   (4U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK   (0x20U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT   (5U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK   (0x40U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT   (6U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK   (0x80U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT   (7U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK   (0x100U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT   (8U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK   (0x200U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT   (9U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK   (0x400U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT   (10U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK   (0x800U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT   (11U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK   (0x1000U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT   (12U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK   (0x2000U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT   (13U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK   (0x4000U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT   (14U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK   (0x8000U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT   (15U)
#define	ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x)
RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK   (0xFU)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT   (0U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK   (0xF0U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT   (4U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK   (0x700U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT   (8U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK   (0x3800U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT   (11U)
#define	ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x)
RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK   (0xFU)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT   (0U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK   (0xF0U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT   (4U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK   (0x700U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT   (8U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK   (0x3800U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT   (11U)
#define	ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x)
REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK   (0x7U)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT   (0U)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK   (0x38U)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT   (3U)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK   (0x40U)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT   (6U)
#define	ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x)
LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER
#define	ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK   (0x3U)
#define	ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT   (0U)
#define	ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x)
#define	ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK   (0x4U)
#define	ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT   (2U)
#define	ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x)
TEMPSENSOR - Tempsensor Register
#define	ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK   (0x8000U)
#define	ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT   (15U)
#define	ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x)
#define	ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK   (0x10000U)
#define	ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT   (16U)
#define	ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x)
TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER
#define	ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK   (0x3FFC00U)
#define	ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT   (10U)
#define	ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x)
BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn
#define	AOI_BFCRT01_PT1_DC_MASK   (0x3U)
#define	AOI_BFCRT01_PT1_DC_SHIFT   (0U)
#define	AOI_BFCRT01_PT1_DC(x)
#define	AOI_BFCRT01_PT1_CC_MASK   (0xCU)
#define	AOI_BFCRT01_PT1_CC_SHIFT   (2U)
#define	AOI_BFCRT01_PT1_CC(x)
#define	AOI_BFCRT01_PT1_BC_MASK   (0x30U)
#define	AOI_BFCRT01_PT1_BC_SHIFT   (4U)
#define	AOI_BFCRT01_PT1_BC(x)
#define	AOI_BFCRT01_PT1_AC_MASK   (0xC0U)
#define	AOI_BFCRT01_PT1_AC_SHIFT   (6U)
#define	AOI_BFCRT01_PT1_AC(x)
#define	AOI_BFCRT01_PT0_DC_MASK   (0x300U)
#define	AOI_BFCRT01_PT0_DC_SHIFT   (8U)
#define	AOI_BFCRT01_PT0_DC(x)
#define	AOI_BFCRT01_PT0_CC_MASK   (0xC00U)
#define	AOI_BFCRT01_PT0_CC_SHIFT   (10U)
#define	AOI_BFCRT01_PT0_CC(x)
#define	AOI_BFCRT01_PT0_BC_MASK   (0x3000U)
#define	AOI_BFCRT01_PT0_BC_SHIFT   (12U)
#define	AOI_BFCRT01_PT0_BC(x)
#define	AOI_BFCRT01_PT0_AC_MASK   (0xC000U)
#define	AOI_BFCRT01_PT0_AC_SHIFT   (14U)
#define	AOI_BFCRT01_PT0_AC(x)
BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn
#define	AOI_BFCRT23_PT3_DC_MASK   (0x3U)
#define	AOI_BFCRT23_PT3_DC_SHIFT   (0U)
#define	AOI_BFCRT23_PT3_DC(x)
#define	AOI_BFCRT23_PT3_CC_MASK   (0xCU)
#define	AOI_BFCRT23_PT3_CC_SHIFT   (2U)
#define	AOI_BFCRT23_PT3_CC(x)
#define	AOI_BFCRT23_PT3_BC_MASK   (0x30U)
#define	AOI_BFCRT23_PT3_BC_SHIFT   (4U)
#define	AOI_BFCRT23_PT3_BC(x)
#define	AOI_BFCRT23_PT3_AC_MASK   (0xC0U)
#define	AOI_BFCRT23_PT3_AC_SHIFT   (6U)
#define	AOI_BFCRT23_PT3_AC(x)
#define	AOI_BFCRT23_PT2_DC_MASK   (0x300U)
#define	AOI_BFCRT23_PT2_DC_SHIFT   (8U)
#define	AOI_BFCRT23_PT2_DC(x)
#define	AOI_BFCRT23_PT2_CC_MASK   (0xC00U)
#define	AOI_BFCRT23_PT2_CC_SHIFT   (10U)
#define	AOI_BFCRT23_PT2_CC(x)
#define	AOI_BFCRT23_PT2_BC_MASK   (0x3000U)
#define	AOI_BFCRT23_PT2_BC_SHIFT   (12U)
#define	AOI_BFCRT23_PT2_BC(x)
#define	AOI_BFCRT23_PT2_AC_MASK   (0xC000U)
#define	AOI_BFCRT23_PT2_AC_SHIFT   (14U)
#define	AOI_BFCRT23_PT2_AC(x)
ASRCTR - ASRC Control Register
#define	ASRC_ASRCTR_ASRCEN_MASK   (0x1U)
#define	ASRC_ASRCTR_ASRCEN_SHIFT   (0U)
#define	ASRC_ASRCTR_ASRCEN(x)
#define	ASRC_ASRCTR_ASREA_MASK   (0x2U)
#define	ASRC_ASRCTR_ASREA_SHIFT   (1U)
#define	ASRC_ASRCTR_ASREA(x)
#define	ASRC_ASRCTR_ASREB_MASK   (0x4U)
#define	ASRC_ASRCTR_ASREB_SHIFT   (2U)
#define	ASRC_ASRCTR_ASREB(x)
#define	ASRC_ASRCTR_ASREC_MASK   (0x8U)
#define	ASRC_ASRCTR_ASREC_SHIFT   (3U)
#define	ASRC_ASRCTR_ASREC(x)
#define	ASRC_ASRCTR_SRST_MASK   (0x10U)
#define	ASRC_ASRCTR_SRST_SHIFT   (4U)
#define	ASRC_ASRCTR_SRST(x)
#define	ASRC_ASRCTR_IDRA_MASK   (0x2000U)
#define	ASRC_ASRCTR_IDRA_SHIFT   (13U)
#define	ASRC_ASRCTR_IDRA(x)
#define	ASRC_ASRCTR_USRA_MASK   (0x4000U)
#define	ASRC_ASRCTR_USRA_SHIFT   (14U)
#define	ASRC_ASRCTR_USRA(x)
#define	ASRC_ASRCTR_IDRB_MASK   (0x8000U)
#define	ASRC_ASRCTR_IDRB_SHIFT   (15U)
#define	ASRC_ASRCTR_IDRB(x)
#define	ASRC_ASRCTR_USRB_MASK   (0x10000U)
#define	ASRC_ASRCTR_USRB_SHIFT   (16U)
#define	ASRC_ASRCTR_USRB(x)
#define	ASRC_ASRCTR_IDRC_MASK   (0x20000U)
#define	ASRC_ASRCTR_IDRC_SHIFT   (17U)
#define	ASRC_ASRCTR_IDRC(x)
#define	ASRC_ASRCTR_USRC_MASK   (0x40000U)
#define	ASRC_ASRCTR_USRC_SHIFT   (18U)
#define	ASRC_ASRCTR_USRC(x)
#define	ASRC_ASRCTR_ATSA_MASK   (0x100000U)
#define	ASRC_ASRCTR_ATSA_SHIFT   (20U)
#define	ASRC_ASRCTR_ATSA(x)
#define	ASRC_ASRCTR_ATSB_MASK   (0x200000U)
#define	ASRC_ASRCTR_ATSB_SHIFT   (21U)
#define	ASRC_ASRCTR_ATSB(x)
#define	ASRC_ASRCTR_ATSC_MASK   (0x400000U)
#define	ASRC_ASRCTR_ATSC_SHIFT   (22U)
#define	ASRC_ASRCTR_ATSC(x)
ASRIER - ASRC Interrupt Enable Register
#define	ASRC_ASRIER_ADIEA_MASK   (0x1U)
#define	ASRC_ASRIER_ADIEA_SHIFT   (0U)
#define	ASRC_ASRIER_ADIEA(x)
#define	ASRC_ASRIER_ADIEB_MASK   (0x2U)
#define	ASRC_ASRIER_ADIEB_SHIFT   (1U)
#define	ASRC_ASRIER_ADIEB(x)
#define	ASRC_ASRIER_ADIEC_MASK   (0x4U)
#define	ASRC_ASRIER_ADIEC_SHIFT   (2U)
#define	ASRC_ASRIER_ADIEC(x)
#define	ASRC_ASRIER_ADOEA_MASK   (0x8U)
#define	ASRC_ASRIER_ADOEA_SHIFT   (3U)
#define	ASRC_ASRIER_ADOEA(x)
#define	ASRC_ASRIER_ADOEB_MASK   (0x10U)
#define	ASRC_ASRIER_ADOEB_SHIFT   (4U)
#define	ASRC_ASRIER_ADOEB(x)
#define	ASRC_ASRIER_ADOEC_MASK   (0x20U)
#define	ASRC_ASRIER_ADOEC_SHIFT   (5U)
#define	ASRC_ASRIER_ADOEC(x)
#define	ASRC_ASRIER_AOLIE_MASK   (0x40U)
#define	ASRC_ASRIER_AOLIE_SHIFT   (6U)
#define	ASRC_ASRIER_AOLIE(x)
#define	ASRC_ASRIER_AFPWE_MASK   (0x80U)
#define	ASRC_ASRIER_AFPWE_SHIFT   (7U)
#define	ASRC_ASRIER_AFPWE(x)
ASRCNCR - ASRC Channel Number Configuration Register
#define	ASRC_ASRCNCR_ANCA_MASK   (0xFU)
#define	ASRC_ASRCNCR_ANCA_SHIFT   (0U)
#define	ASRC_ASRCNCR_ANCA(x)
#define	ASRC_ASRCNCR_ANCB_MASK   (0xF0U)
#define	ASRC_ASRCNCR_ANCB_SHIFT   (4U)
#define	ASRC_ASRCNCR_ANCB(x)
#define	ASRC_ASRCNCR_ANCC_MASK   (0xF00U)
#define	ASRC_ASRCNCR_ANCC_SHIFT   (8U)
#define	ASRC_ASRCNCR_ANCC(x)
ASRCFG - ASRC Filter Configuration Status Register
#define	ASRC_ASRCFG_PREMODA_MASK   (0xC0U)
#define	ASRC_ASRCFG_PREMODA_SHIFT   (6U)
#define	ASRC_ASRCFG_PREMODA(x)
#define	ASRC_ASRCFG_POSTMODA_MASK   (0x300U)
#define	ASRC_ASRCFG_POSTMODA_SHIFT   (8U)
#define	ASRC_ASRCFG_POSTMODA(x)
#define	ASRC_ASRCFG_PREMODB_MASK   (0xC00U)
#define	ASRC_ASRCFG_PREMODB_SHIFT   (10U)
#define	ASRC_ASRCFG_PREMODB(x)
#define	ASRC_ASRCFG_POSTMODB_MASK   (0x3000U)
#define	ASRC_ASRCFG_POSTMODB_SHIFT   (12U)
#define	ASRC_ASRCFG_POSTMODB(x)
#define	ASRC_ASRCFG_PREMODC_MASK   (0xC000U)
#define	ASRC_ASRCFG_PREMODC_SHIFT   (14U)
#define	ASRC_ASRCFG_PREMODC(x)
#define	ASRC_ASRCFG_POSTMODC_MASK   (0x30000U)
#define	ASRC_ASRCFG_POSTMODC_SHIFT   (16U)
#define	ASRC_ASRCFG_POSTMODC(x)
#define	ASRC_ASRCFG_NDPRA_MASK   (0x40000U)
#define	ASRC_ASRCFG_NDPRA_SHIFT   (18U)
#define	ASRC_ASRCFG_NDPRA(x)
#define	ASRC_ASRCFG_NDPRB_MASK   (0x80000U)
#define	ASRC_ASRCFG_NDPRB_SHIFT   (19U)
#define	ASRC_ASRCFG_NDPRB(x)
#define	ASRC_ASRCFG_NDPRC_MASK   (0x100000U)
#define	ASRC_ASRCFG_NDPRC_SHIFT   (20U)
#define	ASRC_ASRCFG_NDPRC(x)
#define	ASRC_ASRCFG_INIRQA_MASK   (0x200000U)
#define	ASRC_ASRCFG_INIRQA_SHIFT   (21U)
#define	ASRC_ASRCFG_INIRQA(x)
#define	ASRC_ASRCFG_INIRQB_MASK   (0x400000U)
#define	ASRC_ASRCFG_INIRQB_SHIFT   (22U)
#define	ASRC_ASRCFG_INIRQB(x)
#define	ASRC_ASRCFG_INIRQC_MASK   (0x800000U)
#define	ASRC_ASRCFG_INIRQC_SHIFT   (23U)
#define	ASRC_ASRCFG_INIRQC(x)
ASRCSR - ASRC Clock Source Register
#define	ASRC_ASRCSR_AICSA_MASK   (0xFU)
#define	ASRC_ASRCSR_AICSA_SHIFT   (0U)
#define	ASRC_ASRCSR_AICSA(x)
#define	ASRC_ASRCSR_AICSB_MASK   (0xF0U)
#define	ASRC_ASRCSR_AICSB_SHIFT   (4U)
#define	ASRC_ASRCSR_AICSB(x)
#define	ASRC_ASRCSR_AICSC_MASK   (0xF00U)
#define	ASRC_ASRCSR_AICSC_SHIFT   (8U)
#define	ASRC_ASRCSR_AICSC(x)
#define	ASRC_ASRCSR_AOCSA_MASK   (0xF000U)
#define	ASRC_ASRCSR_AOCSA_SHIFT   (12U)
#define	ASRC_ASRCSR_AOCSA(x)
#define	ASRC_ASRCSR_AOCSB_MASK   (0xF0000U)
#define	ASRC_ASRCSR_AOCSB_SHIFT   (16U)
#define	ASRC_ASRCSR_AOCSB(x)
#define	ASRC_ASRCSR_AOCSC_MASK   (0xF00000U)
#define	ASRC_ASRCSR_AOCSC_SHIFT   (20U)
#define	ASRC_ASRCSR_AOCSC(x)
ASRCDR1 - ASRC Clock Divider Register 1
#define	ASRC_ASRCDR1_AICPA_MASK   (0x7U)
#define	ASRC_ASRCDR1_AICPA_SHIFT   (0U)
#define	ASRC_ASRCDR1_AICPA(x)
#define	ASRC_ASRCDR1_AICDA_MASK   (0x38U)
#define	ASRC_ASRCDR1_AICDA_SHIFT   (3U)
#define	ASRC_ASRCDR1_AICDA(x)
#define	ASRC_ASRCDR1_AICPB_MASK   (0x1C0U)
#define	ASRC_ASRCDR1_AICPB_SHIFT   (6U)
#define	ASRC_ASRCDR1_AICPB(x)
#define	ASRC_ASRCDR1_AICDB_MASK   (0xE00U)
#define	ASRC_ASRCDR1_AICDB_SHIFT   (9U)
#define	ASRC_ASRCDR1_AICDB(x)
#define	ASRC_ASRCDR1_AOCPA_MASK   (0x7000U)
#define	ASRC_ASRCDR1_AOCPA_SHIFT   (12U)
#define	ASRC_ASRCDR1_AOCPA(x)
#define	ASRC_ASRCDR1_AOCDA_MASK   (0x38000U)
#define	ASRC_ASRCDR1_AOCDA_SHIFT   (15U)
#define	ASRC_ASRCDR1_AOCDA(x)
#define	ASRC_ASRCDR1_AOCPB_MASK   (0x1C0000U)
#define	ASRC_ASRCDR1_AOCPB_SHIFT   (18U)
#define	ASRC_ASRCDR1_AOCPB(x)
#define	ASRC_ASRCDR1_AOCDB_MASK   (0xE00000U)
#define	ASRC_ASRCDR1_AOCDB_SHIFT   (21U)
#define	ASRC_ASRCDR1_AOCDB(x)
ASRCDR2 - ASRC Clock Divider Register 2
#define	ASRC_ASRCDR2_AICPC_MASK   (0x7U)
#define	ASRC_ASRCDR2_AICPC_SHIFT   (0U)
#define	ASRC_ASRCDR2_AICPC(x)
#define	ASRC_ASRCDR2_AICDC_MASK   (0x38U)
#define	ASRC_ASRCDR2_AICDC_SHIFT   (3U)
#define	ASRC_ASRCDR2_AICDC(x)
#define	ASRC_ASRCDR2_AOCPC_MASK   (0x1C0U)
#define	ASRC_ASRCDR2_AOCPC_SHIFT   (6U)
#define	ASRC_ASRCDR2_AOCPC(x)
#define	ASRC_ASRCDR2_AOCDC_MASK   (0xE00U)
#define	ASRC_ASRCDR2_AOCDC_SHIFT   (9U)
#define	ASRC_ASRCDR2_AOCDC(x)
ASRSTR - ASRC Status Register
#define	ASRC_ASRSTR_AIDEA_MASK   (0x1U)
#define	ASRC_ASRSTR_AIDEA_SHIFT   (0U)
#define	ASRC_ASRSTR_AIDEA(x)
#define	ASRC_ASRSTR_AIDEB_MASK   (0x2U)
#define	ASRC_ASRSTR_AIDEB_SHIFT   (1U)
#define	ASRC_ASRSTR_AIDEB(x)
#define	ASRC_ASRSTR_AIDEC_MASK   (0x4U)
#define	ASRC_ASRSTR_AIDEC_SHIFT   (2U)
#define	ASRC_ASRSTR_AIDEC(x)
#define	ASRC_ASRSTR_AODFA_MASK   (0x8U)
#define	ASRC_ASRSTR_AODFA_SHIFT   (3U)
#define	ASRC_ASRSTR_AODFA(x)
#define	ASRC_ASRSTR_AODFB_MASK   (0x10U)
#define	ASRC_ASRSTR_AODFB_SHIFT   (4U)
#define	ASRC_ASRSTR_AODFB(x)
#define	ASRC_ASRSTR_AODFC_MASK   (0x20U)
#define	ASRC_ASRSTR_AODFC_SHIFT   (5U)
#define	ASRC_ASRSTR_AODFC(x)
#define	ASRC_ASRSTR_AOLE_MASK   (0x40U)
#define	ASRC_ASRSTR_AOLE_SHIFT   (6U)
#define	ASRC_ASRSTR_AOLE(x)
#define	ASRC_ASRSTR_FPWT_MASK   (0x80U)
#define	ASRC_ASRSTR_FPWT_SHIFT   (7U)
#define	ASRC_ASRSTR_FPWT(x)
#define	ASRC_ASRSTR_AIDUA_MASK   (0x100U)
#define	ASRC_ASRSTR_AIDUA_SHIFT   (8U)
#define	ASRC_ASRSTR_AIDUA(x)
#define	ASRC_ASRSTR_AIDUB_MASK   (0x200U)
#define	ASRC_ASRSTR_AIDUB_SHIFT   (9U)
#define	ASRC_ASRSTR_AIDUB(x)
#define	ASRC_ASRSTR_AIDUC_MASK   (0x400U)
#define	ASRC_ASRSTR_AIDUC_SHIFT   (10U)
#define	ASRC_ASRSTR_AIDUC(x)
#define	ASRC_ASRSTR_AODOA_MASK   (0x800U)
#define	ASRC_ASRSTR_AODOA_SHIFT   (11U)
#define	ASRC_ASRSTR_AODOA(x)
#define	ASRC_ASRSTR_AODOB_MASK   (0x1000U)
#define	ASRC_ASRSTR_AODOB_SHIFT   (12U)
#define	ASRC_ASRSTR_AODOB(x)
#define	ASRC_ASRSTR_AODOC_MASK   (0x2000U)
#define	ASRC_ASRSTR_AODOC_SHIFT   (13U)
#define	ASRC_ASRSTR_AODOC(x)
#define	ASRC_ASRSTR_AIOLA_MASK   (0x4000U)
#define	ASRC_ASRSTR_AIOLA_SHIFT   (14U)
#define	ASRC_ASRSTR_AIOLA(x)
#define	ASRC_ASRSTR_AIOLB_MASK   (0x8000U)
#define	ASRC_ASRSTR_AIOLB_SHIFT   (15U)
#define	ASRC_ASRSTR_AIOLB(x)
#define	ASRC_ASRSTR_AIOLC_MASK   (0x10000U)
#define	ASRC_ASRSTR_AIOLC_SHIFT   (16U)
#define	ASRC_ASRSTR_AIOLC(x)
#define	ASRC_ASRSTR_AOOLA_MASK   (0x20000U)
#define	ASRC_ASRSTR_AOOLA_SHIFT   (17U)
#define	ASRC_ASRSTR_AOOLA(x)
#define	ASRC_ASRSTR_AOOLB_MASK   (0x40000U)
#define	ASRC_ASRSTR_AOOLB_SHIFT   (18U)
#define	ASRC_ASRSTR_AOOLB(x)
#define	ASRC_ASRSTR_AOOLC_MASK   (0x80000U)
#define	ASRC_ASRSTR_AOOLC_SHIFT   (19U)
#define	ASRC_ASRSTR_AOOLC(x)
#define	ASRC_ASRSTR_ATQOL_MASK   (0x100000U)
#define	ASRC_ASRSTR_ATQOL_SHIFT   (20U)
#define	ASRC_ASRSTR_ATQOL(x)
#define	ASRC_ASRSTR_DSLCNT_MASK   (0x200000U)
#define	ASRC_ASRSTR_DSLCNT_SHIFT   (21U)
#define	ASRC_ASRSTR_DSLCNT(x)
ASRPM - ASRC Parameter Register n
#define	ASRC_ASRPM_PARAMETER_VALUE_MASK   (0xFFFFFFU)
#define	ASRC_ASRPM_PARAMETER_VALUE_SHIFT   (0U)
#define	ASRC_ASRPM_PARAMETER_VALUE(x)
ASRTFR1 - ASRC Task Queue FIFO Register 1
#define	ASRC_ASRTFR1_TF_BASE_MASK   (0x1FC0U)
#define	ASRC_ASRTFR1_TF_BASE_SHIFT   (6U)
#define	ASRC_ASRTFR1_TF_BASE(x)
#define	ASRC_ASRTFR1_TF_FILL_MASK   (0xFE000U)
#define	ASRC_ASRTFR1_TF_FILL_SHIFT   (13U)
#define	ASRC_ASRTFR1_TF_FILL(x)
ASRCCR - ASRC Channel Counter Register
#define	ASRC_ASRCCR_ACIA_MASK   (0xFU)
#define	ASRC_ASRCCR_ACIA_SHIFT   (0U)
#define	ASRC_ASRCCR_ACIA(x)
#define	ASRC_ASRCCR_ACIB_MASK   (0xF0U)
#define	ASRC_ASRCCR_ACIB_SHIFT   (4U)
#define	ASRC_ASRCCR_ACIB(x)
#define	ASRC_ASRCCR_ACIC_MASK   (0xF00U)
#define	ASRC_ASRCCR_ACIC_SHIFT   (8U)
#define	ASRC_ASRCCR_ACIC(x)
#define	ASRC_ASRCCR_ACOA_MASK   (0xF000U)
#define	ASRC_ASRCCR_ACOA_SHIFT   (12U)
#define	ASRC_ASRCCR_ACOA(x)
#define	ASRC_ASRCCR_ACOB_MASK   (0xF0000U)
#define	ASRC_ASRCCR_ACOB_SHIFT   (16U)
#define	ASRC_ASRCCR_ACOB(x)
#define	ASRC_ASRCCR_ACOC_MASK   (0xF00000U)
#define	ASRC_ASRCCR_ACOC_SHIFT   (20U)
#define	ASRC_ASRCCR_ACOC(x)
ASRDIA - ASRC Data Input Register for Pair x
#define	ASRC_ASRDIA_DATA_MASK   (0xFFFFFFU)
#define	ASRC_ASRDIA_DATA_SHIFT   (0U)
#define	ASRC_ASRDIA_DATA(x)
ASRDOA - ASRC Data Output Register for Pair x
#define	ASRC_ASRDOA_DATA_MASK   (0xFFFFFFU)
#define	ASRC_ASRDOA_DATA_SHIFT   (0U)
#define	ASRC_ASRDOA_DATA(x)
ASRDIB - ASRC Data Input Register for Pair x
#define	ASRC_ASRDIB_DATA_MASK   (0xFFFFFFU)
#define	ASRC_ASRDIB_DATA_SHIFT   (0U)
#define	ASRC_ASRDIB_DATA(x)
ASRDOB - ASRC Data Output Register for Pair x
#define	ASRC_ASRDOB_DATA_MASK   (0xFFFFFFU)
#define	ASRC_ASRDOB_DATA_SHIFT   (0U)
#define	ASRC_ASRDOB_DATA(x)
ASRDIC - ASRC Data Input Register for Pair x
#define	ASRC_ASRDIC_DATA_MASK   (0xFFFFFFU)
#define	ASRC_ASRDIC_DATA_SHIFT   (0U)
#define	ASRC_ASRDIC_DATA(x)
ASRDOC - ASRC Data Output Register for Pair x
#define	ASRC_ASRDOC_DATA_MASK   (0xFFFFFFU)
#define	ASRC_ASRDOC_DATA_SHIFT   (0U)
#define	ASRC_ASRDOC_DATA(x)
ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part
#define	ASRC_ASRIDRHA_IDRATIOA_H_MASK   (0xFFU)
#define	ASRC_ASRIDRHA_IDRATIOA_H_SHIFT   (0U)
#define	ASRC_ASRIDRHA_IDRATIOA_H(x)
ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part
#define	ASRC_ASRIDRLA_IDRATIOA_L_MASK   (0xFFFFFFU)
#define	ASRC_ASRIDRLA_IDRATIOA_L_SHIFT   (0U)
#define	ASRC_ASRIDRLA_IDRATIOA_L(x)
ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part
#define	ASRC_ASRIDRHB_IDRATIOB_H_MASK   (0xFFU)
#define	ASRC_ASRIDRHB_IDRATIOB_H_SHIFT   (0U)
#define	ASRC_ASRIDRHB_IDRATIOB_H(x)
ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part
#define	ASRC_ASRIDRLB_IDRATIOB_L_MASK   (0xFFFFFFU)
#define	ASRC_ASRIDRLB_IDRATIOB_L_SHIFT   (0U)
#define	ASRC_ASRIDRLB_IDRATIOB_L(x)
ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part
#define	ASRC_ASRIDRHC_IDRATIOC_H_MASK   (0xFFU)
#define	ASRC_ASRIDRHC_IDRATIOC_H_SHIFT   (0U)
#define	ASRC_ASRIDRHC_IDRATIOC_H(x)
ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part
#define	ASRC_ASRIDRLC_IDRATIOC_L_MASK   (0xFFFFFFU)
#define	ASRC_ASRIDRLC_IDRATIOC_L_SHIFT   (0U)
#define	ASRC_ASRIDRLC_IDRATIOC_L(x)
ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock
#define	ASRC_ASR76K_ASR76K_MASK   (0x1FFFFU)
#define	ASRC_ASR76K_ASR76K_SHIFT   (0U)
#define	ASRC_ASR76K_ASR76K(x)
ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock
#define	ASRC_ASR56K_ASR56K_MASK   (0x1FFFFU)
#define	ASRC_ASR56K_ASR56K_SHIFT   (0U)
#define	ASRC_ASR56K_ASR56K(x)
ASRMCRA - ASRC Misc Control Register for Pair A
#define	ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK   (0x3FU)
#define	ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT   (0U)
#define	ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)
#define	ASRC_ASRMCRA_RSYNOFA_MASK   (0x400U)
#define	ASRC_ASRMCRA_RSYNOFA_SHIFT   (10U)
#define	ASRC_ASRMCRA_RSYNOFA(x)
#define	ASRC_ASRMCRA_RSYNIFA_MASK   (0x800U)
#define	ASRC_ASRMCRA_RSYNIFA_SHIFT   (11U)
#define	ASRC_ASRMCRA_RSYNIFA(x)
#define	ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK   (0x3F000U)
#define	ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT   (12U)
#define	ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)
#define	ASRC_ASRMCRA_BYPASSPOLYA_MASK   (0x100000U)
#define	ASRC_ASRMCRA_BYPASSPOLYA_SHIFT   (20U)
#define	ASRC_ASRMCRA_BYPASSPOLYA(x)
#define	ASRC_ASRMCRA_BUFSTALLA_MASK   (0x200000U)
#define	ASRC_ASRMCRA_BUFSTALLA_SHIFT   (21U)
#define	ASRC_ASRMCRA_BUFSTALLA(x)
#define	ASRC_ASRMCRA_EXTTHRSHA_MASK   (0x400000U)
#define	ASRC_ASRMCRA_EXTTHRSHA_SHIFT   (22U)
#define	ASRC_ASRMCRA_EXTTHRSHA(x)
#define	ASRC_ASRMCRA_ZEROBUFA_MASK   (0x800000U)
#define	ASRC_ASRMCRA_ZEROBUFA_SHIFT   (23U)
#define	ASRC_ASRMCRA_ZEROBUFA(x)
ASRFSTA - ASRC FIFO Status Register for Pair A
#define	ASRC_ASRFSTA_INFIFO_FILLA_MASK   (0x7FU)
#define	ASRC_ASRFSTA_INFIFO_FILLA_SHIFT   (0U)
#define	ASRC_ASRFSTA_INFIFO_FILLA(x)
#define	ASRC_ASRFSTA_IAEA_MASK   (0x800U)
#define	ASRC_ASRFSTA_IAEA_SHIFT   (11U)
#define	ASRC_ASRFSTA_IAEA(x)
#define	ASRC_ASRFSTA_OUTFIFO_FILLA_MASK   (0x7F000U)
#define	ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT   (12U)
#define	ASRC_ASRFSTA_OUTFIFO_FILLA(x)
#define	ASRC_ASRFSTA_OAFA_MASK   (0x800000U)
#define	ASRC_ASRFSTA_OAFA_SHIFT   (23U)
#define	ASRC_ASRFSTA_OAFA(x)
ASRMCRB - ASRC Misc Control Register for Pair B
#define	ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK   (0x3FU)
#define	ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT   (0U)
#define	ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)
#define	ASRC_ASRMCRB_RSYNOFB_MASK   (0x400U)
#define	ASRC_ASRMCRB_RSYNOFB_SHIFT   (10U)
#define	ASRC_ASRMCRB_RSYNOFB(x)
#define	ASRC_ASRMCRB_RSYNIFB_MASK   (0x800U)
#define	ASRC_ASRMCRB_RSYNIFB_SHIFT   (11U)
#define	ASRC_ASRMCRB_RSYNIFB(x)
#define	ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK   (0x3F000U)
#define	ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT   (12U)
#define	ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)
#define	ASRC_ASRMCRB_BYPASSPOLYB_MASK   (0x100000U)
#define	ASRC_ASRMCRB_BYPASSPOLYB_SHIFT   (20U)
#define	ASRC_ASRMCRB_BYPASSPOLYB(x)
#define	ASRC_ASRMCRB_BUFSTALLB_MASK   (0x200000U)
#define	ASRC_ASRMCRB_BUFSTALLB_SHIFT   (21U)
#define	ASRC_ASRMCRB_BUFSTALLB(x)
#define	ASRC_ASRMCRB_EXTTHRSHB_MASK   (0x400000U)
#define	ASRC_ASRMCRB_EXTTHRSHB_SHIFT   (22U)
#define	ASRC_ASRMCRB_EXTTHRSHB(x)
#define	ASRC_ASRMCRB_ZEROBUFB_MASK   (0x800000U)
#define	ASRC_ASRMCRB_ZEROBUFB_SHIFT   (23U)
#define	ASRC_ASRMCRB_ZEROBUFB(x)
ASRFSTB - ASRC FIFO Status Register for Pair B
#define	ASRC_ASRFSTB_INFIFO_FILLB_MASK   (0x7FU)
#define	ASRC_ASRFSTB_INFIFO_FILLB_SHIFT   (0U)
#define	ASRC_ASRFSTB_INFIFO_FILLB(x)
#define	ASRC_ASRFSTB_IAEB_MASK   (0x800U)
#define	ASRC_ASRFSTB_IAEB_SHIFT   (11U)
#define	ASRC_ASRFSTB_IAEB(x)
#define	ASRC_ASRFSTB_OUTFIFO_FILLB_MASK   (0x7F000U)
#define	ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT   (12U)
#define	ASRC_ASRFSTB_OUTFIFO_FILLB(x)
#define	ASRC_ASRFSTB_OAFB_MASK   (0x800000U)
#define	ASRC_ASRFSTB_OAFB_SHIFT   (23U)
#define	ASRC_ASRFSTB_OAFB(x)
ASRMCRC - ASRC Misc Control Register for Pair C
#define	ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK   (0x3FU)
#define	ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT   (0U)
#define	ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)
#define	ASRC_ASRMCRC_RSYNOFC_MASK   (0x400U)
#define	ASRC_ASRMCRC_RSYNOFC_SHIFT   (10U)
#define	ASRC_ASRMCRC_RSYNOFC(x)
#define	ASRC_ASRMCRC_RSYNIFC_MASK   (0x800U)
#define	ASRC_ASRMCRC_RSYNIFC_SHIFT   (11U)
#define	ASRC_ASRMCRC_RSYNIFC(x)
#define	ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK   (0x3F000U)
#define	ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT   (12U)
#define	ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)
#define	ASRC_ASRMCRC_BYPASSPOLYC_MASK   (0x100000U)
#define	ASRC_ASRMCRC_BYPASSPOLYC_SHIFT   (20U)
#define	ASRC_ASRMCRC_BYPASSPOLYC(x)
#define	ASRC_ASRMCRC_BUFSTALLC_MASK   (0x200000U)
#define	ASRC_ASRMCRC_BUFSTALLC_SHIFT   (21U)
#define	ASRC_ASRMCRC_BUFSTALLC(x)
#define	ASRC_ASRMCRC_EXTTHRSHC_MASK   (0x400000U)
#define	ASRC_ASRMCRC_EXTTHRSHC_SHIFT   (22U)
#define	ASRC_ASRMCRC_EXTTHRSHC(x)
#define	ASRC_ASRMCRC_ZEROBUFC_MASK   (0x800000U)
#define	ASRC_ASRMCRC_ZEROBUFC_SHIFT   (23U)
#define	ASRC_ASRMCRC_ZEROBUFC(x)
ASRFSTC - ASRC FIFO Status Register for Pair C
#define	ASRC_ASRFSTC_INFIFO_FILLC_MASK   (0x7FU)
#define	ASRC_ASRFSTC_INFIFO_FILLC_SHIFT   (0U)
#define	ASRC_ASRFSTC_INFIFO_FILLC(x)
#define	ASRC_ASRFSTC_IAEC_MASK   (0x800U)
#define	ASRC_ASRFSTC_IAEC_SHIFT   (11U)
#define	ASRC_ASRFSTC_IAEC(x)
#define	ASRC_ASRFSTC_OUTFIFO_FILLC_MASK   (0x7F000U)
#define	ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT   (12U)
#define	ASRC_ASRFSTC_OUTFIFO_FILLC(x)
#define	ASRC_ASRFSTC_OAFC_MASK   (0x800000U)
#define	ASRC_ASRFSTC_OAFC_SHIFT   (23U)
#define	ASRC_ASRFSTC_OAFC(x)
ASRMCR1 - ASRC Misc Control Register 1 for Pair X
#define	ASRC_ASRMCR1_OW16_MASK   (0x1U)
#define	ASRC_ASRMCR1_OW16_SHIFT   (0U)
#define	ASRC_ASRMCR1_OW16(x)
#define	ASRC_ASRMCR1_OSGN_MASK   (0x2U)
#define	ASRC_ASRMCR1_OSGN_SHIFT   (1U)
#define	ASRC_ASRMCR1_OSGN(x)
#define	ASRC_ASRMCR1_OMSB_MASK   (0x4U)
#define	ASRC_ASRMCR1_OMSB_SHIFT   (2U)
#define	ASRC_ASRMCR1_OMSB(x)
#define	ASRC_ASRMCR1_IMSB_MASK   (0x100U)
#define	ASRC_ASRMCR1_IMSB_SHIFT   (8U)
#define	ASRC_ASRMCR1_IMSB(x)
#define	ASRC_ASRMCR1_IWD_MASK   (0x600U)
#define	ASRC_ASRMCR1_IWD_SHIFT   (9U)
#define	ASRC_ASRMCR1_IWD(x)
CTRL0 - Fractional PLL Control Register
#define	AUDIO_PLL_CTRL0_DIV_SELECT_MASK   (0x7FU)
#define	AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT   (0U)
#define	AUDIO_PLL_CTRL0_DIV_SELECT(x)
#define	AUDIO_PLL_CTRL0_ENABLE_ALT_MASK   (0x100U)
#define	AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT   (8U)
#define	AUDIO_PLL_CTRL0_ENABLE_ALT(x)
#define	AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK   (0x2000U)
#define	AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT   (13U)
#define	AUDIO_PLL_CTRL0_HOLD_RING_OFF(x)
#define	AUDIO_PLL_CTRL0_POWERUP_MASK   (0x4000U)
#define	AUDIO_PLL_CTRL0_POWERUP_SHIFT   (14U)
#define	AUDIO_PLL_CTRL0_POWERUP(x)
#define	AUDIO_PLL_CTRL0_ENABLE_MASK   (0x8000U)
#define	AUDIO_PLL_CTRL0_ENABLE_SHIFT   (15U)
#define	AUDIO_PLL_CTRL0_ENABLE(x)
#define	AUDIO_PLL_CTRL0_BYPASS_MASK   (0x10000U)
#define	AUDIO_PLL_CTRL0_BYPASS_SHIFT   (16U)
#define	AUDIO_PLL_CTRL0_BYPASS(x)
#define	AUDIO_PLL_CTRL0_DITHER_EN_MASK   (0x20000U)
#define	AUDIO_PLL_CTRL0_DITHER_EN_SHIFT   (17U)
#define	AUDIO_PLL_CTRL0_DITHER_EN(x)
#define	AUDIO_PLL_CTRL0_BIAS_TRIM_MASK   (0x380000U)
#define	AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT   (19U)
#define	AUDIO_PLL_CTRL0_BIAS_TRIM(x)
#define	AUDIO_PLL_CTRL0_PLL_REG_EN_MASK   (0x400000U)
#define	AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT   (22U)
#define	AUDIO_PLL_CTRL0_PLL_REG_EN(x)
#define	AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK   (0xE000000U)
#define	AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT   (25U)
#define	AUDIO_PLL_CTRL0_POST_DIV_SEL(x)
#define	AUDIO_PLL_CTRL0_BIAS_SELECT_MASK   (0x20000000U)
#define	AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT   (29U)
#define	AUDIO_PLL_CTRL0_BIAS_SELECT(x)
#define	ETHERNET_PLL_CTRL0_DIV_SELECT_MASK   (0x7FU)
#define	ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT   (0U)
#define	ETHERNET_PLL_CTRL0_DIV_SELECT(x)
#define	ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK   (0x100U)
#define	ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT   (8U)
#define	ETHERNET_PLL_CTRL0_ENABLE_ALT(x)
#define	ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK   (0x2000U)
#define	ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT   (13U)
#define	ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x)
#define	ETHERNET_PLL_CTRL0_POWERUP_MASK   (0x4000U)
#define	ETHERNET_PLL_CTRL0_POWERUP_SHIFT   (14U)
#define	ETHERNET_PLL_CTRL0_POWERUP(x)
#define	ETHERNET_PLL_CTRL0_ENABLE_MASK   (0x8000U)
#define	ETHERNET_PLL_CTRL0_ENABLE_SHIFT   (15U)
#define	ETHERNET_PLL_CTRL0_ENABLE(x)
#define	ETHERNET_PLL_CTRL0_BYPASS_MASK   (0x10000U)
#define	ETHERNET_PLL_CTRL0_BYPASS_SHIFT   (16U)
#define	ETHERNET_PLL_CTRL0_BYPASS(x)
#define	ETHERNET_PLL_CTRL0_DITHER_EN_MASK   (0x20000U)
#define	ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT   (17U)
#define	ETHERNET_PLL_CTRL0_DITHER_EN(x)
#define	ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK   (0x380000U)
#define	ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT   (19U)
#define	ETHERNET_PLL_CTRL0_BIAS_TRIM(x)
#define	ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK   (0x400000U)
#define	ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT   (22U)
#define	ETHERNET_PLL_CTRL0_PLL_REG_EN(x)
#define	ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK   (0xE000000U)
#define	ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT   (25U)
#define	ETHERNET_PLL_CTRL0_POST_DIV_SEL(x)
#define	ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK   (0x20000000U)
#define	ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT   (29U)
#define	ETHERNET_PLL_CTRL0_BIAS_SELECT(x)
#define	VIDEO_PLL_CTRL0_DIV_SELECT_MASK   (0x7FU)
#define	VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT   (0U)
#define	VIDEO_PLL_CTRL0_DIV_SELECT(x)
#define	VIDEO_PLL_CTRL0_ENABLE_ALT_MASK   (0x100U)
#define	VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT   (8U)
#define	VIDEO_PLL_CTRL0_ENABLE_ALT(x)
#define	VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK   (0x2000U)
#define	VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT   (13U)
#define	VIDEO_PLL_CTRL0_HOLD_RING_OFF(x)
#define	VIDEO_PLL_CTRL0_POWERUP_MASK   (0x4000U)
#define	VIDEO_PLL_CTRL0_POWERUP_SHIFT   (14U)
#define	VIDEO_PLL_CTRL0_POWERUP(x)
#define	VIDEO_PLL_CTRL0_ENABLE_MASK   (0x8000U)
#define	VIDEO_PLL_CTRL0_ENABLE_SHIFT   (15U)
#define	VIDEO_PLL_CTRL0_ENABLE(x)
#define	VIDEO_PLL_CTRL0_BYPASS_MASK   (0x10000U)
#define	VIDEO_PLL_CTRL0_BYPASS_SHIFT   (16U)
#define	VIDEO_PLL_CTRL0_BYPASS(x)
#define	VIDEO_PLL_CTRL0_DITHER_EN_MASK   (0x20000U)
#define	VIDEO_PLL_CTRL0_DITHER_EN_SHIFT   (17U)
#define	VIDEO_PLL_CTRL0_DITHER_EN(x)
#define	VIDEO_PLL_CTRL0_BIAS_TRIM_MASK   (0x380000U)
#define	VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT   (19U)
#define	VIDEO_PLL_CTRL0_BIAS_TRIM(x)
#define	VIDEO_PLL_CTRL0_PLL_REG_EN_MASK   (0x400000U)
#define	VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT   (22U)
#define	VIDEO_PLL_CTRL0_PLL_REG_EN(x)
#define	VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK   (0xE000000U)
#define	VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT   (25U)
#define	VIDEO_PLL_CTRL0_POST_DIV_SEL(x)
#define	VIDEO_PLL_CTRL0_BIAS_SELECT_MASK   (0x20000000U)
#define	VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT   (29U)
#define	VIDEO_PLL_CTRL0_BIAS_SELECT(x)
SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register
#define	AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK   (0x7FFFU)
#define	AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT   (0U)
#define	AUDIO_PLL_SPREAD_SPECTRUM_STEP(x)
#define	AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK   (0x8000U)
#define	AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
#define	AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x)
#define	AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK   (0xFFFF0000U)
#define	AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT   (16U)
#define	AUDIO_PLL_SPREAD_SPECTRUM_STOP(x)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK   (0x7FFFU)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT   (0U)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK   (0x8000U)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK   (0xFFFF0000U)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT   (16U)
#define	ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x)
#define	VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK   (0x7FFFU)
#define	VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT   (0U)
#define	VIDEO_PLL_SPREAD_SPECTRUM_STEP(x)
#define	VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK   (0x8000U)
#define	VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
#define	VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x)
#define	VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK   (0xFFFF0000U)
#define	VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT   (16U)
#define	VIDEO_PLL_SPREAD_SPECTRUM_STOP(x)
NUMERATOR - Fractional PLL Numerator Control Register
#define	AUDIO_PLL_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
#define	AUDIO_PLL_NUMERATOR_NUM_SHIFT   (0U)
#define	AUDIO_PLL_NUMERATOR_NUM(x)
#define	ETHERNET_PLL_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
#define	ETHERNET_PLL_NUMERATOR_NUM_SHIFT   (0U)
#define	ETHERNET_PLL_NUMERATOR_NUM(x)
#define	VIDEO_PLL_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
#define	VIDEO_PLL_NUMERATOR_NUM_SHIFT   (0U)
#define	VIDEO_PLL_NUMERATOR_NUM(x)
DENOMINATOR - Fractional PLL Denominator Control Register
#define	AUDIO_PLL_DENOMINATOR_DENOM_MASK   (0x3FFFFFFFU)
#define	AUDIO_PLL_DENOMINATOR_DENOM_SHIFT   (0U)
#define	AUDIO_PLL_DENOMINATOR_DENOM(x)
#define	ETHERNET_PLL_DENOMINATOR_DENOM_MASK   (0x3FFFFFFFU)
#define	ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT   (0U)
#define	ETHERNET_PLL_DENOMINATOR_DENOM(x)
#define	VIDEO_PLL_DENOMINATOR_DENOM_MASK   (0x3FFFFFFFU)
#define	VIDEO_PLL_DENOMINATOR_DENOM_SHIFT   (0U)
#define	VIDEO_PLL_DENOMINATOR_DENOM(x)
MCFGR - Master Configuration Register
#define	CAAM_MCFGR_NORMAL_BURST_MASK   (0x1U)
#define	CAAM_MCFGR_NORMAL_BURST_SHIFT   (0U)
#define	CAAM_MCFGR_NORMAL_BURST(x)
#define	CAAM_MCFGR_LARGE_BURST_MASK   (0x4U)
#define	CAAM_MCFGR_LARGE_BURST_SHIFT   (2U)
#define	CAAM_MCFGR_LARGE_BURST(x)
#define	CAAM_MCFGR_AXIPIPE_MASK   (0xF0U)
#define	CAAM_MCFGR_AXIPIPE_SHIFT   (4U)
#define	CAAM_MCFGR_AXIPIPE(x)
#define	CAAM_MCFGR_AWCACHE_MASK   (0xF00U)
#define	CAAM_MCFGR_AWCACHE_SHIFT   (8U)
#define	CAAM_MCFGR_AWCACHE(x)
#define	CAAM_MCFGR_ARCACHE_MASK   (0xF000U)
#define	CAAM_MCFGR_ARCACHE_SHIFT   (12U)
#define	CAAM_MCFGR_ARCACHE(x)
#define	CAAM_MCFGR_PS_MASK   (0x10000U)
#define	CAAM_MCFGR_PS_SHIFT   (16U)
#define	CAAM_MCFGR_PS(x)
#define	CAAM_MCFGR_DWT_MASK   (0x80000U)
#define	CAAM_MCFGR_DWT_SHIFT   (19U)
#define	CAAM_MCFGR_DWT(x)
#define	CAAM_MCFGR_WRHD_MASK   (0x8000000U)
#define	CAAM_MCFGR_WRHD_SHIFT   (27U)
#define	CAAM_MCFGR_WRHD(x)
#define	CAAM_MCFGR_DMA_RST_MASK   (0x10000000U)
#define	CAAM_MCFGR_DMA_RST_SHIFT   (28U)
#define	CAAM_MCFGR_DMA_RST(x)
#define	CAAM_MCFGR_WDF_MASK   (0x20000000U)
#define	CAAM_MCFGR_WDF_SHIFT   (29U)
#define	CAAM_MCFGR_WDF(x)
#define	CAAM_MCFGR_WDE_MASK   (0x40000000U)
#define	CAAM_MCFGR_WDE_SHIFT   (30U)
#define	CAAM_MCFGR_WDE(x)
#define	CAAM_MCFGR_SWRST_MASK   (0x80000000U)
#define	CAAM_MCFGR_SWRST_SHIFT   (31U)
#define	CAAM_MCFGR_SWRST(x)
PAGE0_SDID - Page 0 SDID Register
#define	CAAM_PAGE0_SDID_SDID_MASK   (0x7FFFU)
#define	CAAM_PAGE0_SDID_SDID_SHIFT   (0U)
#define	CAAM_PAGE0_SDID_SDID(x)
SCFGR - Security Configuration Register
#define	CAAM_SCFGR_PRIBLOB_MASK   (0x3U)
#define	CAAM_SCFGR_PRIBLOB_SHIFT   (0U)
#define	CAAM_SCFGR_PRIBLOB(x)
#define	CAAM_SCFGR_RNGSH0_MASK   (0x200U)
#define	CAAM_SCFGR_RNGSH0_SHIFT   (9U)
#define	CAAM_SCFGR_RNGSH0(x)
#define	CAAM_SCFGR_LCK_TRNG_MASK   (0x800U)
#define	CAAM_SCFGR_LCK_TRNG_SHIFT   (11U)
#define	CAAM_SCFGR_LCK_TRNG(x)
#define	CAAM_SCFGR_VIRT_EN_MASK   (0x8000U)
#define	CAAM_SCFGR_VIRT_EN_SHIFT   (15U)
#define	CAAM_SCFGR_VIRT_EN(x)
#define	CAAM_SCFGR_MPMRL_MASK   (0x4000000U)
#define	CAAM_SCFGR_MPMRL_SHIFT   (26U)
#define	CAAM_SCFGR_MPMRL(x)
#define	CAAM_SCFGR_MPPKRC_MASK   (0x8000000U)
#define	CAAM_SCFGR_MPPKRC_SHIFT   (27U)
#define	CAAM_SCFGR_MPPKRC(x)
#define	CAAM_SCFGR_MPCURVE_MASK   (0xF0000000U)
#define	CAAM_SCFGR_MPCURVE_SHIFT   (28U)
#define	CAAM_SCFGR_MPCURVE(x)
JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half
#define	CAAM_JRDID_MS_PRIM_DID_MASK   (0xFU)
#define	CAAM_JRDID_MS_PRIM_DID_SHIFT   (0U)
#define	CAAM_JRDID_MS_PRIM_DID(x)
#define	CAAM_JRDID_MS_PRIM_TZ_MASK   (0x10U)
#define	CAAM_JRDID_MS_PRIM_TZ_SHIFT   (4U)
#define	CAAM_JRDID_MS_PRIM_TZ(x)
#define	CAAM_JRDID_MS_SDID_MS_MASK   (0x7FE0U)
#define	CAAM_JRDID_MS_SDID_MS_SHIFT   (5U)
#define	CAAM_JRDID_MS_SDID_MS(x)
#define	CAAM_JRDID_MS_TZ_OWN_MASK   (0x8000U)
#define	CAAM_JRDID_MS_TZ_OWN_SHIFT   (15U)
#define	CAAM_JRDID_MS_TZ_OWN(x)
#define	CAAM_JRDID_MS_AMTD_MASK   (0x10000U)
#define	CAAM_JRDID_MS_AMTD_SHIFT   (16U)
#define	CAAM_JRDID_MS_AMTD(x)
#define	CAAM_JRDID_MS_LAMTD_MASK   (0x20000U)
#define	CAAM_JRDID_MS_LAMTD_SHIFT   (17U)
#define	CAAM_JRDID_MS_LAMTD(x)
#define	CAAM_JRDID_MS_PRIM_ICID_MASK   (0x3FF80000U)
#define	CAAM_JRDID_MS_PRIM_ICID_SHIFT   (19U)
#define	CAAM_JRDID_MS_PRIM_ICID(x)
#define	CAAM_JRDID_MS_USE_OUT_MASK   (0x40000000U)
#define	CAAM_JRDID_MS_USE_OUT_SHIFT   (30U)
#define	CAAM_JRDID_MS_USE_OUT(x)
#define	CAAM_JRDID_MS_LDID_MASK   (0x80000000U)
#define	CAAM_JRDID_MS_LDID_SHIFT   (31U)
#define	CAAM_JRDID_MS_LDID(x)
JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half
#define	CAAM_JRDID_LS_OUT_DID_MASK   (0xFU)
#define	CAAM_JRDID_LS_OUT_DID_SHIFT   (0U)
#define	CAAM_JRDID_LS_OUT_DID(x)
#define	CAAM_JRDID_LS_OUT_ICID_MASK   (0x3FF80000U)
#define	CAAM_JRDID_LS_OUT_ICID_SHIFT   (19U)
#define	CAAM_JRDID_LS_OUT_ICID(x)
DEBUGCTL - Debug Control Register
#define	CAAM_DEBUGCTL_STOP_MASK   (0x10000U)
#define	CAAM_DEBUGCTL_STOP_SHIFT   (16U)
#define	CAAM_DEBUGCTL_STOP(x)
#define	CAAM_DEBUGCTL_STOP_ACK_MASK   (0x20000U)
#define	CAAM_DEBUGCTL_STOP_ACK_SHIFT   (17U)
#define	CAAM_DEBUGCTL_STOP_ACK(x)
JRSTARTR - Job Ring Start Register
#define	CAAM_JRSTARTR_Start_JR0_MASK   (0x1U)
#define	CAAM_JRSTARTR_Start_JR0_SHIFT   (0U)
#define	CAAM_JRSTARTR_Start_JR0(x)
#define	CAAM_JRSTARTR_Start_JR1_MASK   (0x2U)
#define	CAAM_JRSTARTR_Start_JR1_SHIFT   (1U)
#define	CAAM_JRSTARTR_Start_JR1(x)
#define	CAAM_JRSTARTR_Start_JR2_MASK   (0x4U)
#define	CAAM_JRSTARTR_Start_JR2_SHIFT   (2U)
#define	CAAM_JRSTARTR_Start_JR2(x)
#define	CAAM_JRSTARTR_Start_JR3_MASK   (0x8U)
#define	CAAM_JRSTARTR_Start_JR3_SHIFT   (3U)
#define	CAAM_JRSTARTR_Start_JR3(x)
RTIC_OWN - RTIC OWN Register
#define	CAAM_RTIC_OWN_ROWN_DID_MASK   (0xFU)
#define	CAAM_RTIC_OWN_ROWN_DID_SHIFT   (0U)
#define	CAAM_RTIC_OWN_ROWN_DID(x)
#define	CAAM_RTIC_OWN_ROWN_TZ_MASK   (0x10U)
#define	CAAM_RTIC_OWN_ROWN_TZ_SHIFT   (4U)
#define	CAAM_RTIC_OWN_ROWN_TZ(x)
#define	CAAM_RTIC_OWN_LCK_MASK   (0x80000000U)
#define	CAAM_RTIC_OWN_LCK_SHIFT   (31U)
#define	CAAM_RTIC_OWN_LCK(x)
RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D
#define	CAAM_RTIC_DID_RTIC_DID_MASK   (0xFU)
#define	CAAM_RTIC_DID_RTIC_DID_SHIFT   (0U)
#define	CAAM_RTIC_DID_RTIC_DID(x)
#define	CAAM_RTIC_DID_RTIC_TZ_MASK   (0x10U)
#define	CAAM_RTIC_DID_RTIC_TZ_SHIFT   (4U)
#define	CAAM_RTIC_DID_RTIC_TZ(x)
#define	CAAM_RTIC_DID_RTIC_ICID_MASK   (0x3FF80000U)
#define	CAAM_RTIC_DID_RTIC_ICID_SHIFT   (19U)
#define	CAAM_RTIC_DID_RTIC_ICID(x)
DECORSR - DECO Request Source Register
#define	CAAM_DECORSR_JR_MASK   (0x3U)
#define	CAAM_DECORSR_JR_SHIFT   (0U)
#define	CAAM_DECORSR_JR(x)
#define	CAAM_DECORSR_VALID_MASK   (0x80000000U)
#define	CAAM_DECORSR_VALID_SHIFT   (31U)
#define	CAAM_DECORSR_VALID(x)
DECORR - DECO Request Register
#define	CAAM_DECORR_RQD0_MASK   (0x1U)
#define	CAAM_DECORR_RQD0_SHIFT   (0U)
#define	CAAM_DECORR_RQD0(x)
#define	CAAM_DECORR_DEN0_MASK   (0x10000U)
#define	CAAM_DECORR_DEN0_SHIFT   (16U)
#define	CAAM_DECORR_DEN0(x)
DECODID_MS - DECO0 DID Register - most significant half
#define	CAAM_DECODID_MS_DPRIM_DID_MASK   (0xFU)
#define	CAAM_DECODID_MS_DPRIM_DID_SHIFT   (0U)
#define	CAAM_DECODID_MS_DPRIM_DID(x)
#define	CAAM_DECODID_MS_D_NS_MASK   (0x10U)
#define	CAAM_DECODID_MS_D_NS_SHIFT   (4U)
#define	CAAM_DECODID_MS_D_NS(x)
#define	CAAM_DECODID_MS_LCK_MASK   (0x80000000U)
#define	CAAM_DECODID_MS_LCK_SHIFT   (31U)
#define	CAAM_DECODID_MS_LCK(x)
DECODID_LS - DECO0 DID Register - least significant half
#define	CAAM_DECODID_LS_DSEQ_DID_MASK   (0xFU)
#define	CAAM_DECODID_LS_DSEQ_DID_SHIFT   (0U)
#define	CAAM_DECODID_LS_DSEQ_DID(x)
#define	CAAM_DECODID_LS_DSEQ_NS_MASK   (0x10U)
#define	CAAM_DECODID_LS_DSEQ_NS_SHIFT   (4U)
#define	CAAM_DECODID_LS_DSEQ_NS(x)
#define	CAAM_DECODID_LS_DNSEQ_DID_MASK   (0xF0000U)
#define	CAAM_DECODID_LS_DNSEQ_DID_SHIFT   (16U)
#define	CAAM_DECODID_LS_DNSEQ_DID(x)
#define	CAAM_DECODID_LS_DNONSEQ_NS_MASK   (0x100000U)
#define	CAAM_DECODID_LS_DNONSEQ_NS_SHIFT   (20U)
#define	CAAM_DECODID_LS_DNONSEQ_NS(x)
DAR - DECO Availability Register
#define	CAAM_DAR_NYA0_MASK   (0x1U)
#define	CAAM_DAR_NYA0_SHIFT   (0U)
#define	CAAM_DAR_NYA0(x)
DRR - DECO Reset Register
#define	CAAM_DRR_RST0_MASK   (0x1U)
#define	CAAM_DRR_RST0_SHIFT   (0U)
#define	CAAM_DRR_RST0(x)
JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register
#define	CAAM_JRSMVBAR_SMVBA_MASK   (0xFFFFFFFFU)
#define	CAAM_JRSMVBAR_SMVBA_SHIFT   (0U)
#define	CAAM_JRSMVBAR_SMVBA(x)
PBSL - Peak Bandwidth Smoothing Limit Register
#define	CAAM_PBSL_PBSL_MASK   (0x7FU)
#define	CAAM_PBSL_PBSL_SHIFT   (0U)
#define	CAAM_PBSL_PBSL(x)
DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS
#define	CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK   (0xFFU)
#define	CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT   (0U)
#define	CAAM_DMA_AIDL_MAP_MS_AID4_BID(x)
#define	CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK   (0xFF00U)
#define	CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT   (8U)
#define	CAAM_DMA_AIDL_MAP_MS_AID5_BID(x)
#define	CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT   (16U)
#define	CAAM_DMA_AIDL_MAP_MS_AID6_BID(x)
#define	CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT   (24U)
#define	CAAM_DMA_AIDL_MAP_MS_AID7_BID(x)
DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS
#define	CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK   (0xFFU)
#define	CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT   (0U)
#define	CAAM_DMA_AIDL_MAP_LS_AID0_BID(x)
#define	CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK   (0xFF00U)
#define	CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT   (8U)
#define	CAAM_DMA_AIDL_MAP_LS_AID1_BID(x)
#define	CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT   (16U)
#define	CAAM_DMA_AIDL_MAP_LS_AID2_BID(x)
#define	CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT   (24U)
#define	CAAM_DMA_AIDL_MAP_LS_AID3_BID(x)
DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS
#define	CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK   (0xFFU)
#define	CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT   (0U)
#define	CAAM_DMA_AIDM_MAP_MS_AID12_BID(x)
#define	CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK   (0xFF00U)
#define	CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT   (8U)
#define	CAAM_DMA_AIDM_MAP_MS_AID13_BID(x)
#define	CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT   (16U)
#define	CAAM_DMA_AIDM_MAP_MS_AID14_BID(x)
#define	CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT   (24U)
#define	CAAM_DMA_AIDM_MAP_MS_AID15_BID(x)
DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS
#define	CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK   (0xFFU)
#define	CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT   (0U)
#define	CAAM_DMA_AIDM_MAP_LS_AID8_BID(x)
#define	CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK   (0xFF00U)
#define	CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT   (8U)
#define	CAAM_DMA_AIDM_MAP_LS_AID9_BID(x)
#define	CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT   (16U)
#define	CAAM_DMA_AIDM_MAP_LS_AID10_BID(x)
#define	CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT   (24U)
#define	CAAM_DMA_AIDM_MAP_LS_AID11_BID(x)
DMA0_AID_ENB - DMA0 AXI ID Enable Register
#define	CAAM_DMA0_AID_ENB_AID0E_MASK   (0x1U)
#define	CAAM_DMA0_AID_ENB_AID0E_SHIFT   (0U)
#define	CAAM_DMA0_AID_ENB_AID0E(x)
#define	CAAM_DMA0_AID_ENB_AID1E_MASK   (0x2U)
#define	CAAM_DMA0_AID_ENB_AID1E_SHIFT   (1U)
#define	CAAM_DMA0_AID_ENB_AID1E(x)
#define	CAAM_DMA0_AID_ENB_AID2E_MASK   (0x4U)
#define	CAAM_DMA0_AID_ENB_AID2E_SHIFT   (2U)
#define	CAAM_DMA0_AID_ENB_AID2E(x)
#define	CAAM_DMA0_AID_ENB_AID3E_MASK   (0x8U)
#define	CAAM_DMA0_AID_ENB_AID3E_SHIFT   (3U)
#define	CAAM_DMA0_AID_ENB_AID3E(x)
#define	CAAM_DMA0_AID_ENB_AID4E_MASK   (0x10U)
#define	CAAM_DMA0_AID_ENB_AID4E_SHIFT   (4U)
#define	CAAM_DMA0_AID_ENB_AID4E(x)
#define	CAAM_DMA0_AID_ENB_AID5E_MASK   (0x20U)
#define	CAAM_DMA0_AID_ENB_AID5E_SHIFT   (5U)
#define	CAAM_DMA0_AID_ENB_AID5E(x)
#define	CAAM_DMA0_AID_ENB_AID6E_MASK   (0x40U)
#define	CAAM_DMA0_AID_ENB_AID6E_SHIFT   (6U)
#define	CAAM_DMA0_AID_ENB_AID6E(x)
#define	CAAM_DMA0_AID_ENB_AID7E_MASK   (0x80U)
#define	CAAM_DMA0_AID_ENB_AID7E_SHIFT   (7U)
#define	CAAM_DMA0_AID_ENB_AID7E(x)
#define	CAAM_DMA0_AID_ENB_AID8E_MASK   (0x100U)
#define	CAAM_DMA0_AID_ENB_AID8E_SHIFT   (8U)
#define	CAAM_DMA0_AID_ENB_AID8E(x)
#define	CAAM_DMA0_AID_ENB_AID9E_MASK   (0x200U)
#define	CAAM_DMA0_AID_ENB_AID9E_SHIFT   (9U)
#define	CAAM_DMA0_AID_ENB_AID9E(x)
#define	CAAM_DMA0_AID_ENB_AID10E_MASK   (0x400U)
#define	CAAM_DMA0_AID_ENB_AID10E_SHIFT   (10U)
#define	CAAM_DMA0_AID_ENB_AID10E(x)
#define	CAAM_DMA0_AID_ENB_AID11E_MASK   (0x800U)
#define	CAAM_DMA0_AID_ENB_AID11E_SHIFT   (11U)
#define	CAAM_DMA0_AID_ENB_AID11E(x)
#define	CAAM_DMA0_AID_ENB_AID12E_MASK   (0x1000U)
#define	CAAM_DMA0_AID_ENB_AID12E_SHIFT   (12U)
#define	CAAM_DMA0_AID_ENB_AID12E(x)
#define	CAAM_DMA0_AID_ENB_AID13E_MASK   (0x2000U)
#define	CAAM_DMA0_AID_ENB_AID13E_SHIFT   (13U)
#define	CAAM_DMA0_AID_ENB_AID13E(x)
#define	CAAM_DMA0_AID_ENB_AID14E_MASK   (0x4000U)
#define	CAAM_DMA0_AID_ENB_AID14E_SHIFT   (14U)
#define	CAAM_DMA0_AID_ENB_AID14E(x)
#define	CAAM_DMA0_AID_ENB_AID15E_MASK   (0x8000U)
#define	CAAM_DMA0_AID_ENB_AID15E_SHIFT   (15U)
#define	CAAM_DMA0_AID_ENB_AID15E(x)
DMA0_ARD_TC - DMA0 AXI Read Timing Check Register
#define	CAAM_DMA0_ARD_TC_ARSC_MASK   (0xFFFFFU)
#define	CAAM_DMA0_ARD_TC_ARSC_SHIFT   (0U)
#define	CAAM_DMA0_ARD_TC_ARSC(x)
#define	CAAM_DMA0_ARD_TC_ARLC_MASK   (0xFFFFF000000U)
#define	CAAM_DMA0_ARD_TC_ARLC_SHIFT   (24U)
#define	CAAM_DMA0_ARD_TC_ARLC(x)
#define	CAAM_DMA0_ARD_TC_ARL_MASK   (0xFFF000000000000U)
#define	CAAM_DMA0_ARD_TC_ARL_SHIFT   (48U)
#define	CAAM_DMA0_ARD_TC_ARL(x)
#define	CAAM_DMA0_ARD_TC_ARTL_MASK   (0x1000000000000000U)
#define	CAAM_DMA0_ARD_TC_ARTL_SHIFT   (60U)
#define	CAAM_DMA0_ARD_TC_ARTL(x)
#define	CAAM_DMA0_ARD_TC_ARTT_MASK   (0x2000000000000000U)
#define	CAAM_DMA0_ARD_TC_ARTT_SHIFT   (61U)
#define	CAAM_DMA0_ARD_TC_ARTT(x)
#define	CAAM_DMA0_ARD_TC_ARCT_MASK   (0x4000000000000000U)
#define	CAAM_DMA0_ARD_TC_ARCT_SHIFT   (62U)
#define	CAAM_DMA0_ARD_TC_ARCT(x)
#define	CAAM_DMA0_ARD_TC_ARTCE_MASK   (0x8000000000000000U)
#define	CAAM_DMA0_ARD_TC_ARTCE_SHIFT   (63U)
#define	CAAM_DMA0_ARD_TC_ARTCE(x)
DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register
#define	CAAM_DMA0_ARD_LAT_SARL_MASK   (0xFFFFFFFFU)
#define	CAAM_DMA0_ARD_LAT_SARL_SHIFT   (0U)
#define	CAAM_DMA0_ARD_LAT_SARL(x)
DMA0_AWR_TC - DMA0 AXI Write Timing Check Register
#define	CAAM_DMA0_AWR_TC_AWSC_MASK   (0xFFFFFU)
#define	CAAM_DMA0_AWR_TC_AWSC_SHIFT   (0U)
#define	CAAM_DMA0_AWR_TC_AWSC(x)
#define	CAAM_DMA0_AWR_TC_AWLC_MASK   (0xFFFFF000000U)
#define	CAAM_DMA0_AWR_TC_AWLC_SHIFT   (24U)
#define	CAAM_DMA0_AWR_TC_AWLC(x)
#define	CAAM_DMA0_AWR_TC_AWL_MASK   (0xFFF000000000000U)
#define	CAAM_DMA0_AWR_TC_AWL_SHIFT   (48U)
#define	CAAM_DMA0_AWR_TC_AWL(x)
#define	CAAM_DMA0_AWR_TC_AWTT_MASK   (0x2000000000000000U)
#define	CAAM_DMA0_AWR_TC_AWTT_SHIFT   (61U)
#define	CAAM_DMA0_AWR_TC_AWTT(x)
#define	CAAM_DMA0_AWR_TC_AWCT_MASK   (0x4000000000000000U)
#define	CAAM_DMA0_AWR_TC_AWCT_SHIFT   (62U)
#define	CAAM_DMA0_AWR_TC_AWCT(x)
#define	CAAM_DMA0_AWR_TC_AWTCE_MASK   (0x8000000000000000U)
#define	CAAM_DMA0_AWR_TC_AWTCE_SHIFT   (63U)
#define	CAAM_DMA0_AWR_TC_AWTCE(x)
DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register
#define	CAAM_DMA0_AWR_LAT_SAWL_MASK   (0xFFFFFFFFU)
#define	CAAM_DMA0_AWR_LAT_SAWL_SHIFT   (0U)
#define	CAAM_DMA0_AWR_LAT_SAWL(x)
MPPKR - Manufacturing Protection Private Key Register
#define	CAAM_MPPKR_MPPrivK_MASK   (0xFFU)
#define	CAAM_MPPKR_MPPrivK_SHIFT   (0U)
#define	CAAM_MPPKR_MPPrivK(x)
MPMR - Manufacturing Protection Message Register
#define	CAAM_MPMR_MPMSG_MASK   (0xFFU)
#define	CAAM_MPMR_MPMSG_SHIFT   (0U)
#define	CAAM_MPMR_MPMSG(x)
MPTESTR - Manufacturing Protection Test Register
#define	CAAM_MPTESTR_TEST_VALUE_MASK   (0xFFU)
#define	CAAM_MPTESTR_TEST_VALUE_SHIFT   (0U)
#define	CAAM_MPTESTR_TEST_VALUE(x)
MPECC - Manufacturing Protection ECC Register
#define	CAAM_MPECC_MP_SYNDROME_MASK   (0x1FF0000U)
#define	CAAM_MPECC_MP_SYNDROME_SHIFT   (16U)
#define	CAAM_MPECC_MP_SYNDROME(x)
#define	CAAM_MPECC_MP_ZERO_MASK   (0x8000000U)
#define	CAAM_MPECC_MP_ZERO_SHIFT   (27U)
#define	CAAM_MPECC_MP_ZERO(x)
JDKEKR - Job Descriptor Key Encryption Key Register
#define	CAAM_JDKEKR_JDKEK_MASK   (0xFFFFFFFFU)
#define	CAAM_JDKEKR_JDKEK_SHIFT   (0U)
#define	CAAM_JDKEKR_JDKEK(x)
TDKEKR - Trusted Descriptor Key Encryption Key Register
#define	CAAM_TDKEKR_TDKEK_MASK   (0xFFFFFFFFU)
#define	CAAM_TDKEKR_TDKEK_SHIFT   (0U)
#define	CAAM_TDKEKR_TDKEK(x)
TDSKR - Trusted Descriptor Signing Key Register
#define	CAAM_TDSKR_TDSK_MASK   (0xFFFFFFFFU)
#define	CAAM_TDSKR_TDSK_SHIFT   (0U)
#define	CAAM_TDSKR_TDSK(x)
SKNR - Secure Key Nonce Register
#define	CAAM_SKNR_SK_NONCE_LS_MASK   (0xFFFFFFFFU)
#define	CAAM_SKNR_SK_NONCE_LS_SHIFT   (0U)
#define	CAAM_SKNR_SK_NONCE_LS(x)
#define	CAAM_SKNR_SK_NONCE_MS_MASK   (0x7FFF00000000U)
#define	CAAM_SKNR_SK_NONCE_MS_SHIFT   (32U)
#define	CAAM_SKNR_SK_NONCE_MS(x)
DMA_STA - DMA Status Register
#define	CAAM_DMA_STA_DMA0_ETIF_MASK   (0x1FU)
#define	CAAM_DMA_STA_DMA0_ETIF_SHIFT   (0U)
#define	CAAM_DMA_STA_DMA0_ETIF(x)
#define	CAAM_DMA_STA_DMA0_ITIF_MASK   (0x20U)
#define	CAAM_DMA_STA_DMA0_ITIF_SHIFT   (5U)
#define	CAAM_DMA_STA_DMA0_ITIF(x)
#define	CAAM_DMA_STA_DMA0_IDLE_MASK   (0x80U)
#define	CAAM_DMA_STA_DMA0_IDLE_SHIFT   (7U)
#define	CAAM_DMA_STA_DMA0_IDLE(x)
DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP
#define	CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK   (0xFFU)
#define	CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT   (0U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x)
#define	CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK   (0xFF00U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT   (8U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x)
#define	CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT   (16U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x)
#define	CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT   (24U)
#define	CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x)
DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP
#define	CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK   (0xFFU)
#define	CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT   (0U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x)
#define	CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK   (0xFF00U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT   (8U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x)
#define	CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT   (16U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x)
#define	CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT   (24U)
#define	CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x)
DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP
#define	CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK   (0xFFU)
#define	CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT   (0U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x)
#define	CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK   (0xFF00U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT   (8U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x)
#define	CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT   (16U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x)
#define	CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT   (24U)
#define	CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x)
DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP
#define	CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK   (0xFFU)
#define	CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT   (0U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x)
#define	CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK   (0xFF00U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT   (8U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x)
#define	CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK   (0xFF0000U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT   (16U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x)
#define	CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK   (0xFF000000U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT   (24U)
#define	CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x)
DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register
#define	CAAM_DMA_X_AID_15_0_EN_AID0E_MASK   (0x1U)
#define	CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT   (0U)
#define	CAAM_DMA_X_AID_15_0_EN_AID0E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID1E_MASK   (0x2U)
#define	CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT   (1U)
#define	CAAM_DMA_X_AID_15_0_EN_AID1E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID2E_MASK   (0x4U)
#define	CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT   (2U)
#define	CAAM_DMA_X_AID_15_0_EN_AID2E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID3E_MASK   (0x8U)
#define	CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT   (3U)
#define	CAAM_DMA_X_AID_15_0_EN_AID3E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID4E_MASK   (0x10U)
#define	CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT   (4U)
#define	CAAM_DMA_X_AID_15_0_EN_AID4E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID5E_MASK   (0x20U)
#define	CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT   (5U)
#define	CAAM_DMA_X_AID_15_0_EN_AID5E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID6E_MASK   (0x40U)
#define	CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT   (6U)
#define	CAAM_DMA_X_AID_15_0_EN_AID6E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID7E_MASK   (0x80U)
#define	CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT   (7U)
#define	CAAM_DMA_X_AID_15_0_EN_AID7E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID8E_MASK   (0x100U)
#define	CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT   (8U)
#define	CAAM_DMA_X_AID_15_0_EN_AID8E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID9E_MASK   (0x200U)
#define	CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT   (9U)
#define	CAAM_DMA_X_AID_15_0_EN_AID9E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID10E_MASK   (0x400U)
#define	CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT   (10U)
#define	CAAM_DMA_X_AID_15_0_EN_AID10E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID11E_MASK   (0x800U)
#define	CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT   (11U)
#define	CAAM_DMA_X_AID_15_0_EN_AID11E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID12E_MASK   (0x1000U)
#define	CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT   (12U)
#define	CAAM_DMA_X_AID_15_0_EN_AID12E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID13E_MASK   (0x2000U)
#define	CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT   (13U)
#define	CAAM_DMA_X_AID_15_0_EN_AID13E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID14E_MASK   (0x4000U)
#define	CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT   (14U)
#define	CAAM_DMA_X_AID_15_0_EN_AID14E(x)
#define	CAAM_DMA_X_AID_15_0_EN_AID15E_MASK   (0x8000U)
#define	CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT   (15U)
#define	CAAM_DMA_X_AID_15_0_EN_AID15E(x)
DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register
#define	CAAM_DMA_X_ARTC_CTL_ART_MASK   (0xFFFU)
#define	CAAM_DMA_X_ARTC_CTL_ART_SHIFT   (0U)
#define	CAAM_DMA_X_ARTC_CTL_ART(x)
#define	CAAM_DMA_X_ARTC_CTL_ARL_MASK   (0xFFF0000U)
#define	CAAM_DMA_X_ARTC_CTL_ARL_SHIFT   (16U)
#define	CAAM_DMA_X_ARTC_CTL_ARL(x)
#define	CAAM_DMA_X_ARTC_CTL_ARTL_MASK   (0x10000000U)
#define	CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT   (28U)
#define	CAAM_DMA_X_ARTC_CTL_ARTL(x)
#define	CAAM_DMA_X_ARTC_CTL_ARTT_MASK   (0x20000000U)
#define	CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT   (29U)
#define	CAAM_DMA_X_ARTC_CTL_ARTT(x)
#define	CAAM_DMA_X_ARTC_CTL_ARCT_MASK   (0x40000000U)
#define	CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT   (30U)
#define	CAAM_DMA_X_ARTC_CTL_ARCT(x)
#define	CAAM_DMA_X_ARTC_CTL_ARTCE_MASK   (0x80000000U)
#define	CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT   (31U)
#define	CAAM_DMA_X_ARTC_CTL_ARTCE(x)
DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register
#define	CAAM_DMA_X_ARTC_LC_ARLC_MASK   (0xFFFFFU)
#define	CAAM_DMA_X_ARTC_LC_ARLC_SHIFT   (0U)
#define	CAAM_DMA_X_ARTC_LC_ARLC(x)
DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register
#define	CAAM_DMA_X_ARTC_SC_ARSC_MASK   (0xFFFFFU)
#define	CAAM_DMA_X_ARTC_SC_ARSC_SHIFT   (0U)
#define	CAAM_DMA_X_ARTC_SC_ARSC(x)
DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register
#define	CAAM_DMA_X_ARTC_LAT_SARL_MASK   (0xFFFFFFFFU)
#define	CAAM_DMA_X_ARTC_LAT_SARL_SHIFT   (0U)
#define	CAAM_DMA_X_ARTC_LAT_SARL(x)
DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register
#define	CAAM_DMA_X_AWTC_CTL_AWT_MASK   (0xFFFU)
#define	CAAM_DMA_X_AWTC_CTL_AWT_SHIFT   (0U)
#define	CAAM_DMA_X_AWTC_CTL_AWT(x)
#define	CAAM_DMA_X_AWTC_CTL_AWL_MASK   (0xFFF0000U)
#define	CAAM_DMA_X_AWTC_CTL_AWL_SHIFT   (16U)
#define	CAAM_DMA_X_AWTC_CTL_AWL(x)
#define	CAAM_DMA_X_AWTC_CTL_AWTT_MASK   (0x20000000U)
#define	CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT   (29U)
#define	CAAM_DMA_X_AWTC_CTL_AWTT(x)
#define	CAAM_DMA_X_AWTC_CTL_AWCT_MASK   (0x40000000U)
#define	CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT   (30U)
#define	CAAM_DMA_X_AWTC_CTL_AWCT(x)
#define	CAAM_DMA_X_AWTC_CTL_AWTCE_MASK   (0x80000000U)
#define	CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT   (31U)
#define	CAAM_DMA_X_AWTC_CTL_AWTCE(x)
DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register
#define	CAAM_DMA_X_AWTC_LC_AWLC_MASK   (0xFFFFFU)
#define	CAAM_DMA_X_AWTC_LC_AWLC_SHIFT   (0U)
#define	CAAM_DMA_X_AWTC_LC_AWLC(x)
DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register
#define	CAAM_DMA_X_AWTC_SC_AWSC_MASK   (0xFFFFFU)
#define	CAAM_DMA_X_AWTC_SC_AWSC_SHIFT   (0U)
#define	CAAM_DMA_X_AWTC_SC_AWSC(x)
DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register
#define	CAAM_DMA_X_AWTC_LAT_SAWL_MASK   (0xFFFFFFFFU)
#define	CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT   (0U)
#define	CAAM_DMA_X_AWTC_LAT_SAWL(x)
RTMCTL - RNG TRNG Miscellaneous Control Register
#define	CAAM_RTMCTL_SAMP_MODE_MASK   (0x3U)
#define	CAAM_RTMCTL_SAMP_MODE_SHIFT   (0U)
#define	CAAM_RTMCTL_SAMP_MODE(x)
#define	CAAM_RTMCTL_OSC_DIV_MASK   (0xCU)
#define	CAAM_RTMCTL_OSC_DIV_SHIFT   (2U)
#define	CAAM_RTMCTL_OSC_DIV(x)
#define	CAAM_RTMCTL_CLK_OUT_EN_MASK   (0x10U)
#define	CAAM_RTMCTL_CLK_OUT_EN_SHIFT   (4U)
#define	CAAM_RTMCTL_CLK_OUT_EN(x)
#define	CAAM_RTMCTL_TRNG_ACC_MASK   (0x20U)
#define	CAAM_RTMCTL_TRNG_ACC_SHIFT   (5U)
#define	CAAM_RTMCTL_TRNG_ACC(x)
#define	CAAM_RTMCTL_RST_DEF_MASK   (0x40U)
#define	CAAM_RTMCTL_RST_DEF_SHIFT   (6U)
#define	CAAM_RTMCTL_RST_DEF(x)
#define	CAAM_RTMCTL_FORCE_SYSCLK_MASK   (0x80U)
#define	CAAM_RTMCTL_FORCE_SYSCLK_SHIFT   (7U)
#define	CAAM_RTMCTL_FORCE_SYSCLK(x)
#define	CAAM_RTMCTL_FCT_FAIL_MASK   (0x100U)
#define	CAAM_RTMCTL_FCT_FAIL_SHIFT   (8U)
#define	CAAM_RTMCTL_FCT_FAIL(x)
#define	CAAM_RTMCTL_FCT_VAL_MASK   (0x200U)
#define	CAAM_RTMCTL_FCT_VAL_SHIFT   (9U)
#define	CAAM_RTMCTL_FCT_VAL(x)
#define	CAAM_RTMCTL_ENT_VAL_MASK   (0x400U)
#define	CAAM_RTMCTL_ENT_VAL_SHIFT   (10U)
#define	CAAM_RTMCTL_ENT_VAL(x)
#define	CAAM_RTMCTL_TST_OUT_MASK   (0x800U)
#define	CAAM_RTMCTL_TST_OUT_SHIFT   (11U)
#define	CAAM_RTMCTL_TST_OUT(x)
#define	CAAM_RTMCTL_ERR_MASK   (0x1000U)
#define	CAAM_RTMCTL_ERR_SHIFT   (12U)
#define	CAAM_RTMCTL_ERR(x)
#define	CAAM_RTMCTL_TSTOP_OK_MASK   (0x2000U)
#define	CAAM_RTMCTL_TSTOP_OK_SHIFT   (13U)
#define	CAAM_RTMCTL_TSTOP_OK(x)
#define	CAAM_RTMCTL_PRGM_MASK   (0x10000U)
#define	CAAM_RTMCTL_PRGM_SHIFT   (16U)
#define	CAAM_RTMCTL_PRGM(x)
RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register
#define	CAAM_RTSCMISC_LRUN_MAX_MASK   (0xFFU)
#define	CAAM_RTSCMISC_LRUN_MAX_SHIFT   (0U)
#define	CAAM_RTSCMISC_LRUN_MAX(x)
#define	CAAM_RTSCMISC_RTY_CNT_MASK   (0xF0000U)
#define	CAAM_RTSCMISC_RTY_CNT_SHIFT   (16U)
#define	CAAM_RTSCMISC_RTY_CNT(x)
RTPKRRNG - RNG TRNG Poker Range Register
#define	CAAM_RTPKRRNG_PKR_RNG_MASK   (0xFFFFU)
#define	CAAM_RTPKRRNG_PKR_RNG_SHIFT   (0U)
#define	CAAM_RTPKRRNG_PKR_RNG(x)
RTPKRMAX - RNG TRNG Poker Maximum Limit Register
#define	CAAM_RTPKRMAX_PKR_MAX_MASK   (0xFFFFFFU)
#define	CAAM_RTPKRMAX_PKR_MAX_SHIFT   (0U)
#define	CAAM_RTPKRMAX_PKR_MAX(x)
RTPKRSQ - RNG TRNG Poker Square Calculation Result Register
#define	CAAM_RTPKRSQ_PKR_SQ_MASK   (0xFFFFFFU)
#define	CAAM_RTPKRSQ_PKR_SQ_SHIFT   (0U)
#define	CAAM_RTPKRSQ_PKR_SQ(x)
RTSDCTL - RNG TRNG Seed Control Register
#define	CAAM_RTSDCTL_SAMP_SIZE_MASK   (0xFFFFU)
#define	CAAM_RTSDCTL_SAMP_SIZE_SHIFT   (0U)
#define	CAAM_RTSDCTL_SAMP_SIZE(x)
#define	CAAM_RTSDCTL_ENT_DLY_MASK   (0xFFFF0000U)
#define	CAAM_RTSDCTL_ENT_DLY_SHIFT   (16U)
#define	CAAM_RTSDCTL_ENT_DLY(x)
RTSBLIM - RNG TRNG Sparse Bit Limit Register
#define	CAAM_RTSBLIM_SB_LIM_MASK   (0x3FFU)
#define	CAAM_RTSBLIM_SB_LIM_SHIFT   (0U)
#define	CAAM_RTSBLIM_SB_LIM(x)
RTTOTSAM - RNG TRNG Total Samples Register
#define	CAAM_RTTOTSAM_TOT_SAM_MASK   (0xFFFFFU)
#define	CAAM_RTTOTSAM_TOT_SAM_SHIFT   (0U)
#define	CAAM_RTTOTSAM_TOT_SAM(x)
RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register
#define	CAAM_RTFRQMIN_FRQ_MIN_MASK   (0x3FFFFFU)
#define	CAAM_RTFRQMIN_FRQ_MIN_SHIFT   (0U)
#define	CAAM_RTFRQMIN_FRQ_MIN(x)
RTFRQCNT - RNG TRNG Frequency Count Register
#define	CAAM_RTFRQCNT_FRQ_CNT_MASK   (0x3FFFFFU)
#define	CAAM_RTFRQCNT_FRQ_CNT_SHIFT   (0U)
#define	CAAM_RTFRQCNT_FRQ_CNT(x)
RTSCMC - RNG TRNG Statistical Check Monobit Count Register
#define	CAAM_RTSCMC_MONO_CNT_MASK   (0xFFFFU)
#define	CAAM_RTSCMC_MONO_CNT_SHIFT   (0U)
#define	CAAM_RTSCMC_MONO_CNT(x)
RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register
#define	CAAM_RTSCR1C_R1_0_COUNT_MASK   (0x7FFFU)
#define	CAAM_RTSCR1C_R1_0_COUNT_SHIFT   (0U)
#define	CAAM_RTSCR1C_R1_0_COUNT(x)
#define	CAAM_RTSCR1C_R1_1_COUNT_MASK   (0x7FFF0000U)
#define	CAAM_RTSCR1C_R1_1_COUNT_SHIFT   (16U)
#define	CAAM_RTSCR1C_R1_1_COUNT(x)
RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register
#define	CAAM_RTSCR2C_R2_0_COUNT_MASK   (0x3FFFU)
#define	CAAM_RTSCR2C_R2_0_COUNT_SHIFT   (0U)
#define	CAAM_RTSCR2C_R2_0_COUNT(x)
#define	CAAM_RTSCR2C_R2_1_COUNT_MASK   (0x3FFF0000U)
#define	CAAM_RTSCR2C_R2_1_COUNT_SHIFT   (16U)
#define	CAAM_RTSCR2C_R2_1_COUNT(x)
RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register
#define	CAAM_RTSCR3C_R3_0_COUNT_MASK   (0x1FFFU)
#define	CAAM_RTSCR3C_R3_0_COUNT_SHIFT   (0U)
#define	CAAM_RTSCR3C_R3_0_COUNT(x)
#define	CAAM_RTSCR3C_R3_1_COUNT_MASK   (0x1FFF0000U)
#define	CAAM_RTSCR3C_R3_1_COUNT_SHIFT   (16U)
#define	CAAM_RTSCR3C_R3_1_COUNT(x)
RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register
#define	CAAM_RTSCR4C_R4_0_COUNT_MASK   (0xFFFU)
#define	CAAM_RTSCR4C_R4_0_COUNT_SHIFT   (0U)
#define	CAAM_RTSCR4C_R4_0_COUNT(x)
#define	CAAM_RTSCR4C_R4_1_COUNT_MASK   (0xFFF0000U)
#define	CAAM_RTSCR4C_R4_1_COUNT_SHIFT   (16U)
#define	CAAM_RTSCR4C_R4_1_COUNT(x)
RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register
#define	CAAM_RTSCR5C_R5_0_COUNT_MASK   (0x7FFU)
#define	CAAM_RTSCR5C_R5_0_COUNT_SHIFT   (0U)
#define	CAAM_RTSCR5C_R5_0_COUNT(x)
#define	CAAM_RTSCR5C_R5_1_COUNT_MASK   (0x7FF0000U)
#define	CAAM_RTSCR5C_R5_1_COUNT_SHIFT   (16U)
#define	CAAM_RTSCR5C_R5_1_COUNT(x)
RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register
#define	CAAM_RTSCR6PC_R6P_0_COUNT_MASK   (0x7FFU)
#define	CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT   (0U)
#define	CAAM_RTSCR6PC_R6P_0_COUNT(x)
#define	CAAM_RTSCR6PC_R6P_1_COUNT_MASK   (0x7FF0000U)
#define	CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT   (16U)
#define	CAAM_RTSCR6PC_R6P_1_COUNT(x)
RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register
#define	CAAM_RTFRQMAX_FRQ_MAX_MASK   (0x3FFFFFU)
#define	CAAM_RTFRQMAX_FRQ_MAX_SHIFT   (0U)
#define	CAAM_RTFRQMAX_FRQ_MAX(x)
RTSCML - RNG TRNG Statistical Check Monobit Limit Register
#define	CAAM_RTSCML_MONO_MAX_MASK   (0xFFFFU)
#define	CAAM_RTSCML_MONO_MAX_SHIFT   (0U)
#define	CAAM_RTSCML_MONO_MAX(x)
#define	CAAM_RTSCML_MONO_RNG_MASK   (0xFFFF0000U)
#define	CAAM_RTSCML_MONO_RNG_SHIFT   (16U)
#define	CAAM_RTSCML_MONO_RNG(x)
RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register
#define	CAAM_RTSCR1L_RUN1_MAX_MASK   (0x7FFFU)
#define	CAAM_RTSCR1L_RUN1_MAX_SHIFT   (0U)
#define	CAAM_RTSCR1L_RUN1_MAX(x)
#define	CAAM_RTSCR1L_RUN1_RNG_MASK   (0x7FFF0000U)
#define	CAAM_RTSCR1L_RUN1_RNG_SHIFT   (16U)
#define	CAAM_RTSCR1L_RUN1_RNG(x)
RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register
#define	CAAM_RTSCR2L_RUN2_MAX_MASK   (0x3FFFU)
#define	CAAM_RTSCR2L_RUN2_MAX_SHIFT   (0U)
#define	CAAM_RTSCR2L_RUN2_MAX(x)
#define	CAAM_RTSCR2L_RUN2_RNG_MASK   (0x3FFF0000U)
#define	CAAM_RTSCR2L_RUN2_RNG_SHIFT   (16U)
#define	CAAM_RTSCR2L_RUN2_RNG(x)
RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register
#define	CAAM_RTSCR3L_RUN3_MAX_MASK   (0x1FFFU)
#define	CAAM_RTSCR3L_RUN3_MAX_SHIFT   (0U)
#define	CAAM_RTSCR3L_RUN3_MAX(x)
#define	CAAM_RTSCR3L_RUN3_RNG_MASK   (0x1FFF0000U)
#define	CAAM_RTSCR3L_RUN3_RNG_SHIFT   (16U)
#define	CAAM_RTSCR3L_RUN3_RNG(x)
RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register
#define	CAAM_RTSCR4L_RUN4_MAX_MASK   (0xFFFU)
#define	CAAM_RTSCR4L_RUN4_MAX_SHIFT   (0U)
#define	CAAM_RTSCR4L_RUN4_MAX(x)
#define	CAAM_RTSCR4L_RUN4_RNG_MASK   (0xFFF0000U)
#define	CAAM_RTSCR4L_RUN4_RNG_SHIFT   (16U)
#define	CAAM_RTSCR4L_RUN4_RNG(x)
RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register
#define	CAAM_RTSCR5L_RUN5_MAX_MASK   (0x7FFU)
#define	CAAM_RTSCR5L_RUN5_MAX_SHIFT   (0U)
#define	CAAM_RTSCR5L_RUN5_MAX(x)
#define	CAAM_RTSCR5L_RUN5_RNG_MASK   (0x7FF0000U)
#define	CAAM_RTSCR5L_RUN5_RNG_SHIFT   (16U)
#define	CAAM_RTSCR5L_RUN5_RNG(x)
RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register
#define	CAAM_RTSCR6PL_RUN6P_MAX_MASK   (0x7FFU)
#define	CAAM_RTSCR6PL_RUN6P_MAX_SHIFT   (0U)
#define	CAAM_RTSCR6PL_RUN6P_MAX(x)
#define	CAAM_RTSCR6PL_RUN6P_RNG_MASK   (0x7FF0000U)
#define	CAAM_RTSCR6PL_RUN6P_RNG_SHIFT   (16U)
#define	CAAM_RTSCR6PL_RUN6P_RNG(x)
RTSTATUS - RNG TRNG Status Register
#define	CAAM_RTSTATUS_F1BR0TF_MASK   (0x1U)
#define	CAAM_RTSTATUS_F1BR0TF_SHIFT   (0U)
#define	CAAM_RTSTATUS_F1BR0TF(x)
#define	CAAM_RTSTATUS_F1BR1TF_MASK   (0x2U)
#define	CAAM_RTSTATUS_F1BR1TF_SHIFT   (1U)
#define	CAAM_RTSTATUS_F1BR1TF(x)
#define	CAAM_RTSTATUS_F2BR0TF_MASK   (0x4U)
#define	CAAM_RTSTATUS_F2BR0TF_SHIFT   (2U)
#define	CAAM_RTSTATUS_F2BR0TF(x)
#define	CAAM_RTSTATUS_F2BR1TF_MASK   (0x8U)
#define	CAAM_RTSTATUS_F2BR1TF_SHIFT   (3U)
#define	CAAM_RTSTATUS_F2BR1TF(x)
#define	CAAM_RTSTATUS_F3BR01TF_MASK   (0x10U)
#define	CAAM_RTSTATUS_F3BR01TF_SHIFT   (4U)
#define	CAAM_RTSTATUS_F3BR01TF(x)
#define	CAAM_RTSTATUS_F3BR1TF_MASK   (0x20U)
#define	CAAM_RTSTATUS_F3BR1TF_SHIFT   (5U)
#define	CAAM_RTSTATUS_F3BR1TF(x)
#define	CAAM_RTSTATUS_F4BR0TF_MASK   (0x40U)
#define	CAAM_RTSTATUS_F4BR0TF_SHIFT   (6U)
#define	CAAM_RTSTATUS_F4BR0TF(x)
#define	CAAM_RTSTATUS_F4BR1TF_MASK   (0x80U)
#define	CAAM_RTSTATUS_F4BR1TF_SHIFT   (7U)
#define	CAAM_RTSTATUS_F4BR1TF(x)
#define	CAAM_RTSTATUS_F5BR0TF_MASK   (0x100U)
#define	CAAM_RTSTATUS_F5BR0TF_SHIFT   (8U)
#define	CAAM_RTSTATUS_F5BR0TF(x)
#define	CAAM_RTSTATUS_F5BR1TF_MASK   (0x200U)
#define	CAAM_RTSTATUS_F5BR1TF_SHIFT   (9U)
#define	CAAM_RTSTATUS_F5BR1TF(x)
#define	CAAM_RTSTATUS_F6PBR0TF_MASK   (0x400U)
#define	CAAM_RTSTATUS_F6PBR0TF_SHIFT   (10U)
#define	CAAM_RTSTATUS_F6PBR0TF(x)
#define	CAAM_RTSTATUS_F6PBR1TF_MASK   (0x800U)
#define	CAAM_RTSTATUS_F6PBR1TF_SHIFT   (11U)
#define	CAAM_RTSTATUS_F6PBR1TF(x)
#define	CAAM_RTSTATUS_FSBTF_MASK   (0x1000U)
#define	CAAM_RTSTATUS_FSBTF_SHIFT   (12U)
#define	CAAM_RTSTATUS_FSBTF(x)
#define	CAAM_RTSTATUS_FLRTF_MASK   (0x2000U)
#define	CAAM_RTSTATUS_FLRTF_SHIFT   (13U)
#define	CAAM_RTSTATUS_FLRTF(x)
#define	CAAM_RTSTATUS_FPTF_MASK   (0x4000U)
#define	CAAM_RTSTATUS_FPTF_SHIFT   (14U)
#define	CAAM_RTSTATUS_FPTF(x)
#define	CAAM_RTSTATUS_FMBTF_MASK   (0x8000U)
#define	CAAM_RTSTATUS_FMBTF_SHIFT   (15U)
#define	CAAM_RTSTATUS_FMBTF(x)
#define	CAAM_RTSTATUS_RETRY_COUNT_MASK   (0xF0000U)
#define	CAAM_RTSTATUS_RETRY_COUNT_SHIFT   (16U)
#define	CAAM_RTSTATUS_RETRY_COUNT(x)
RTENT - RNG TRNG Entropy Read Register
#define	CAAM_RTENT_ENT_MASK   (0xFFFFFFFFU)
#define	CAAM_RTENT_ENT_SHIFT   (0U)
#define	CAAM_RTENT_ENT(x)
RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register
#define	CAAM_RTPKRCNT10_PKR_0_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNT10_PKR_0_CNT(x)
#define	CAAM_RTPKRCNT10_PKR_1_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNT10_PKR_1_CNT(x)
RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register
#define	CAAM_RTPKRCNT32_PKR_2_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNT32_PKR_2_CNT(x)
#define	CAAM_RTPKRCNT32_PKR_3_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNT32_PKR_3_CNT(x)
RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register
#define	CAAM_RTPKRCNT54_PKR_4_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNT54_PKR_4_CNT(x)
#define	CAAM_RTPKRCNT54_PKR_5_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNT54_PKR_5_CNT(x)
RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register
#define	CAAM_RTPKRCNT76_PKR_6_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNT76_PKR_6_CNT(x)
#define	CAAM_RTPKRCNT76_PKR_7_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNT76_PKR_7_CNT(x)
RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register
#define	CAAM_RTPKRCNT98_PKR_8_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNT98_PKR_8_CNT(x)
#define	CAAM_RTPKRCNT98_PKR_9_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNT98_PKR_9_CNT(x)
RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register
#define	CAAM_RTPKRCNTBA_PKR_A_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNTBA_PKR_A_CNT(x)
#define	CAAM_RTPKRCNTBA_PKR_B_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNTBA_PKR_B_CNT(x)
RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register
#define	CAAM_RTPKRCNTDC_PKR_C_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNTDC_PKR_C_CNT(x)
#define	CAAM_RTPKRCNTDC_PKR_D_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNTDC_PKR_D_CNT(x)
RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register
#define	CAAM_RTPKRCNTFE_PKR_E_CNT_MASK   (0xFFFFU)
#define	CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT   (0U)
#define	CAAM_RTPKRCNTFE_PKR_E_CNT(x)
#define	CAAM_RTPKRCNTFE_PKR_F_CNT_MASK   (0xFFFF0000U)
#define	CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT   (16U)
#define	CAAM_RTPKRCNTFE_PKR_F_CNT(x)
RDSTA - RNG DRNG Status Register
#define	CAAM_RDSTA_IF0_MASK   (0x1U)
#define	CAAM_RDSTA_IF0_SHIFT   (0U)
#define	CAAM_RDSTA_IF0(x)
#define	CAAM_RDSTA_IF1_MASK   (0x2U)
#define	CAAM_RDSTA_IF1_SHIFT   (1U)
#define	CAAM_RDSTA_IF1(x)
#define	CAAM_RDSTA_PR0_MASK   (0x10U)
#define	CAAM_RDSTA_PR0_SHIFT   (4U)
#define	CAAM_RDSTA_PR0(x)
#define	CAAM_RDSTA_PR1_MASK   (0x20U)
#define	CAAM_RDSTA_PR1_SHIFT   (5U)
#define	CAAM_RDSTA_PR1(x)
#define	CAAM_RDSTA_TF0_MASK   (0x100U)
#define	CAAM_RDSTA_TF0_SHIFT   (8U)
#define	CAAM_RDSTA_TF0(x)
#define	CAAM_RDSTA_TF1_MASK   (0x200U)
#define	CAAM_RDSTA_TF1_SHIFT   (9U)
#define	CAAM_RDSTA_TF1(x)
#define	CAAM_RDSTA_ERRCODE_MASK   (0xF0000U)
#define	CAAM_RDSTA_ERRCODE_SHIFT   (16U)
#define	CAAM_RDSTA_ERRCODE(x)
#define	CAAM_RDSTA_CE_MASK   (0x100000U)
#define	CAAM_RDSTA_CE_SHIFT   (20U)
#define	CAAM_RDSTA_CE(x)
#define	CAAM_RDSTA_SKVN_MASK   (0x40000000U)
#define	CAAM_RDSTA_SKVN_SHIFT   (30U)
#define	CAAM_RDSTA_SKVN(x)
#define	CAAM_RDSTA_SKVT_MASK   (0x80000000U)
#define	CAAM_RDSTA_SKVT_SHIFT   (31U)
#define	CAAM_RDSTA_SKVT(x)
RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register
#define	CAAM_RDINT0_RESINT0_MASK   (0xFFFFFFFFU)
#define	CAAM_RDINT0_RESINT0_SHIFT   (0U)
#define	CAAM_RDINT0_RESINT0(x)
RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register
#define	CAAM_RDINT1_RESINT1_MASK   (0xFFFFFFFFU)
#define	CAAM_RDINT1_RESINT1_SHIFT   (0U)
#define	CAAM_RDINT1_RESINT1(x)
RDHCNTL - RNG DRNG Hash Control Register
#define	CAAM_RDHCNTL_HD_MASK   (0x1U)
#define	CAAM_RDHCNTL_HD_SHIFT   (0U)
#define	CAAM_RDHCNTL_HD(x)
#define	CAAM_RDHCNTL_HB_MASK   (0x2U)
#define	CAAM_RDHCNTL_HB_SHIFT   (1U)
#define	CAAM_RDHCNTL_HB(x)
#define	CAAM_RDHCNTL_HI_MASK   (0x4U)
#define	CAAM_RDHCNTL_HI_SHIFT   (2U)
#define	CAAM_RDHCNTL_HI(x)
#define	CAAM_RDHCNTL_HTM_MASK   (0x8U)
#define	CAAM_RDHCNTL_HTM_SHIFT   (3U)
#define	CAAM_RDHCNTL_HTM(x)
#define	CAAM_RDHCNTL_HTC_MASK   (0x10U)
#define	CAAM_RDHCNTL_HTC_SHIFT   (4U)
#define	CAAM_RDHCNTL_HTC(x)
RDHDIG - RNG DRNG Hash Digest Register
#define	CAAM_RDHDIG_HASHMD_MASK   (0xFFFFFFFFU)
#define	CAAM_RDHDIG_HASHMD_SHIFT   (0U)
#define	CAAM_RDHDIG_HASHMD(x)
RDHBUF - RNG DRNG Hash Buffer Register
#define	CAAM_RDHBUF_HASHBUF_MASK   (0xFFFFFFFFU)
#define	CAAM_RDHBUF_HASHBUF_SHIFT   (0U)
#define	CAAM_RDHBUF_HASHBUF(x)
PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register
#define	CAAM_PX_SDID_PG0_SDID_MASK   (0xFFFFU)
#define	CAAM_PX_SDID_PG0_SDID_SHIFT   (0U)
#define	CAAM_PX_SDID_PG0_SDID(x)
PX_SMAPR_PG0 - Secure Memory Access Permissions register
#define	CAAM_PX_SMAPR_PG0_G1_READ_MASK   (0x1U)
#define	CAAM_PX_SMAPR_PG0_G1_READ_SHIFT   (0U)
#define	CAAM_PX_SMAPR_PG0_G1_READ(x)
#define	CAAM_PX_SMAPR_PG0_G1_WRITE_MASK   (0x2U)
#define	CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT   (1U)
#define	CAAM_PX_SMAPR_PG0_G1_WRITE(x)
#define	CAAM_PX_SMAPR_PG0_G1_TDO_MASK   (0x4U)
#define	CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT   (2U)
#define	CAAM_PX_SMAPR_PG0_G1_TDO(x)
#define	CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK   (0x8U)
#define	CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT   (3U)
#define	CAAM_PX_SMAPR_PG0_G1_SMBLOB(x)
#define	CAAM_PX_SMAPR_PG0_G2_READ_MASK   (0x10U)
#define	CAAM_PX_SMAPR_PG0_G2_READ_SHIFT   (4U)
#define	CAAM_PX_SMAPR_PG0_G2_READ(x)
#define	CAAM_PX_SMAPR_PG0_G2_WRITE_MASK   (0x20U)
#define	CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT   (5U)
#define	CAAM_PX_SMAPR_PG0_G2_WRITE(x)
#define	CAAM_PX_SMAPR_PG0_G2_TDO_MASK   (0x40U)
#define	CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT   (6U)
#define	CAAM_PX_SMAPR_PG0_G2_TDO(x)
#define	CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK   (0x80U)
#define	CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT   (7U)
#define	CAAM_PX_SMAPR_PG0_G2_SMBLOB(x)
#define	CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK   (0x1000U)
#define	CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT   (12U)
#define	CAAM_PX_SMAPR_PG0_SMAG_LCK(x)
#define	CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK   (0x2000U)
#define	CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT   (13U)
#define	CAAM_PX_SMAPR_PG0_SMAP_LCK(x)
#define	CAAM_PX_SMAPR_PG0_PSP_MASK   (0x4000U)
#define	CAAM_PX_SMAPR_PG0_PSP_SHIFT   (14U)
#define	CAAM_PX_SMAPR_PG0_PSP(x)
#define	CAAM_PX_SMAPR_PG0_CSP_MASK   (0x8000U)
#define	CAAM_PX_SMAPR_PG0_CSP_SHIFT   (15U)
#define	CAAM_PX_SMAPR_PG0_CSP(x)
#define	CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK   (0xFFFF0000U)
#define	CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT   (16U)
#define	CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x)
PX_SMAG2_PG0 - Secure Memory Access Group Registers
#define	CAAM_PX_SMAG2_PG0_Gx_ID00_MASK   (0x1U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT   (0U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID00(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID01_MASK   (0x2U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT   (1U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID01(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID02_MASK   (0x4U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT   (2U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID02(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID03_MASK   (0x8U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT   (3U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID03(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID04_MASK   (0x10U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT   (4U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID04(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID05_MASK   (0x20U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT   (5U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID05(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID06_MASK   (0x40U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT   (6U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID06(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID07_MASK   (0x80U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT   (7U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID07(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID08_MASK   (0x100U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT   (8U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID08(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID09_MASK   (0x200U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT   (9U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID09(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID10_MASK   (0x400U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT   (10U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID10(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID11_MASK   (0x800U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT   (11U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID11(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID12_MASK   (0x1000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT   (12U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID12(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID13_MASK   (0x2000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT   (13U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID13(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID14_MASK   (0x4000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT   (14U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID14(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID15_MASK   (0x8000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT   (15U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID15(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID16_MASK   (0x10000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT   (16U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID16(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID17_MASK   (0x20000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT   (17U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID17(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID18_MASK   (0x40000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT   (18U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID18(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID19_MASK   (0x80000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT   (19U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID19(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID20_MASK   (0x100000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT   (20U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID20(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID21_MASK   (0x200000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT   (21U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID21(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID22_MASK   (0x400000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT   (22U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID22(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID23_MASK   (0x800000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT   (23U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID23(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID24_MASK   (0x1000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT   (24U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID24(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID25_MASK   (0x2000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT   (25U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID25(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID26_MASK   (0x4000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT   (26U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID26(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID27_MASK   (0x8000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT   (27U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID27(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID28_MASK   (0x10000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT   (28U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID28(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID29_MASK   (0x20000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT   (29U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID29(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID30_MASK   (0x40000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT   (30U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID30(x)
#define	CAAM_PX_SMAG2_PG0_Gx_ID31_MASK   (0x80000000U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT   (31U)
#define	CAAM_PX_SMAG2_PG0_Gx_ID31(x)
PX_SMAG1_PG0 - Secure Memory Access Group Registers
#define	CAAM_PX_SMAG1_PG0_Gx_ID00_MASK   (0x1U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT   (0U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID00(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID01_MASK   (0x2U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT   (1U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID01(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID02_MASK   (0x4U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT   (2U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID02(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID03_MASK   (0x8U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT   (3U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID03(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID04_MASK   (0x10U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT   (4U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID04(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID05_MASK   (0x20U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT   (5U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID05(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID06_MASK   (0x40U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT   (6U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID06(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID07_MASK   (0x80U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT   (7U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID07(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID08_MASK   (0x100U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT   (8U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID08(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID09_MASK   (0x200U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT   (9U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID09(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID10_MASK   (0x400U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT   (10U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID10(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID11_MASK   (0x800U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT   (11U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID11(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID12_MASK   (0x1000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT   (12U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID12(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID13_MASK   (0x2000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT   (13U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID13(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID14_MASK   (0x4000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT   (14U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID14(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID15_MASK   (0x8000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT   (15U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID15(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID16_MASK   (0x10000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT   (16U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID16(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID17_MASK   (0x20000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT   (17U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID17(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID18_MASK   (0x40000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT   (18U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID18(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID19_MASK   (0x80000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT   (19U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID19(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID20_MASK   (0x100000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT   (20U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID20(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID21_MASK   (0x200000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT   (21U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID21(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID22_MASK   (0x400000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT   (22U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID22(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID23_MASK   (0x800000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT   (23U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID23(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID24_MASK   (0x1000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT   (24U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID24(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID25_MASK   (0x2000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT   (25U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID25(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID26_MASK   (0x4000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT   (26U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID26(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID27_MASK   (0x8000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT   (27U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID27(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID28_MASK   (0x10000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT   (28U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID28(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID29_MASK   (0x20000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT   (29U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID29(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID30_MASK   (0x40000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT   (30U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID30(x)
#define	CAAM_PX_SMAG1_PG0_Gx_ID31_MASK   (0x80000000U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT   (31U)
#define	CAAM_PX_SMAG1_PG0_Gx_ID31(x)
REIS - Recoverable Error Interrupt Status
#define	CAAM_REIS_CWDE_MASK   (0x1U)
#define	CAAM_REIS_CWDE_SHIFT   (0U)
#define	CAAM_REIS_CWDE(x)
#define	CAAM_REIS_RBAE_MASK   (0x10000U)
#define	CAAM_REIS_RBAE_SHIFT   (16U)
#define	CAAM_REIS_RBAE(x)
#define	CAAM_REIS_JBAE0_MASK   (0x1000000U)
#define	CAAM_REIS_JBAE0_SHIFT   (24U)
#define	CAAM_REIS_JBAE0(x)
#define	CAAM_REIS_JBAE1_MASK   (0x2000000U)
#define	CAAM_REIS_JBAE1_SHIFT   (25U)
#define	CAAM_REIS_JBAE1(x)
#define	CAAM_REIS_JBAE2_MASK   (0x4000000U)
#define	CAAM_REIS_JBAE2_SHIFT   (26U)
#define	CAAM_REIS_JBAE2(x)
#define	CAAM_REIS_JBAE3_MASK   (0x8000000U)
#define	CAAM_REIS_JBAE3_SHIFT   (27U)
#define	CAAM_REIS_JBAE3(x)
REIE - Recoverable Error Interrupt Enable
#define	CAAM_REIE_CWDE_MASK   (0x1U)
#define	CAAM_REIE_CWDE_SHIFT   (0U)
#define	CAAM_REIE_CWDE(x)
#define	CAAM_REIE_RBAE_MASK   (0x10000U)
#define	CAAM_REIE_RBAE_SHIFT   (16U)
#define	CAAM_REIE_RBAE(x)
#define	CAAM_REIE_JBAE0_MASK   (0x1000000U)
#define	CAAM_REIE_JBAE0_SHIFT   (24U)
#define	CAAM_REIE_JBAE0(x)
#define	CAAM_REIE_JBAE1_MASK   (0x2000000U)
#define	CAAM_REIE_JBAE1_SHIFT   (25U)
#define	CAAM_REIE_JBAE1(x)
#define	CAAM_REIE_JBAE2_MASK   (0x4000000U)
#define	CAAM_REIE_JBAE2_SHIFT   (26U)
#define	CAAM_REIE_JBAE2(x)
#define	CAAM_REIE_JBAE3_MASK   (0x8000000U)
#define	CAAM_REIE_JBAE3_SHIFT   (27U)
#define	CAAM_REIE_JBAE3(x)
REIF - Recoverable Error Interrupt Force
#define	CAAM_REIF_CWDE_MASK   (0x1U)
#define	CAAM_REIF_CWDE_SHIFT   (0U)
#define	CAAM_REIF_CWDE(x)
#define	CAAM_REIF_RBAE_MASK   (0x10000U)
#define	CAAM_REIF_RBAE_SHIFT   (16U)
#define	CAAM_REIF_RBAE(x)
#define	CAAM_REIF_JBAE0_MASK   (0x1000000U)
#define	CAAM_REIF_JBAE0_SHIFT   (24U)
#define	CAAM_REIF_JBAE0(x)
#define	CAAM_REIF_JBAE1_MASK   (0x2000000U)
#define	CAAM_REIF_JBAE1_SHIFT   (25U)
#define	CAAM_REIF_JBAE1(x)
#define	CAAM_REIF_JBAE2_MASK   (0x4000000U)
#define	CAAM_REIF_JBAE2_SHIFT   (26U)
#define	CAAM_REIF_JBAE2(x)
#define	CAAM_REIF_JBAE3_MASK   (0x8000000U)
#define	CAAM_REIF_JBAE3_SHIFT   (27U)
#define	CAAM_REIF_JBAE3(x)
REIH - Recoverable Error Interrupt Halt
#define	CAAM_REIH_CWDE_MASK   (0x1U)
#define	CAAM_REIH_CWDE_SHIFT   (0U)
#define	CAAM_REIH_CWDE(x)
#define	CAAM_REIH_RBAE_MASK   (0x10000U)
#define	CAAM_REIH_RBAE_SHIFT   (16U)
#define	CAAM_REIH_RBAE(x)
#define	CAAM_REIH_JBAE0_MASK   (0x1000000U)
#define	CAAM_REIH_JBAE0_SHIFT   (24U)
#define	CAAM_REIH_JBAE0(x)
#define	CAAM_REIH_JBAE1_MASK   (0x2000000U)
#define	CAAM_REIH_JBAE1_SHIFT   (25U)
#define	CAAM_REIH_JBAE1(x)
#define	CAAM_REIH_JBAE2_MASK   (0x4000000U)
#define	CAAM_REIH_JBAE2_SHIFT   (26U)
#define	CAAM_REIH_JBAE2(x)
#define	CAAM_REIH_JBAE3_MASK   (0x8000000U)
#define	CAAM_REIH_JBAE3_SHIFT   (27U)
#define	CAAM_REIH_JBAE3(x)
SMWPJRR - Secure Memory Write Protect Job Ring Register
#define	CAAM_SMWPJRR_SMR_WP_JRa_MASK   (0x1U)
#define	CAAM_SMWPJRR_SMR_WP_JRa_SHIFT   (0U)
#define	CAAM_SMWPJRR_SMR_WP_JRa(x)
SMCR_PG0 - Secure Memory Command Register
#define	CAAM_SMCR_PG0_CMD_MASK   (0xFU)
#define	CAAM_SMCR_PG0_CMD_SHIFT   (0U)
#define	CAAM_SMCR_PG0_CMD(x)
#define	CAAM_SMCR_PG0_PRTN_MASK   (0xF00U)
#define	CAAM_SMCR_PG0_PRTN_SHIFT   (8U)
#define	CAAM_SMCR_PG0_PRTN(x)
#define	CAAM_SMCR_PG0_PAGE_MASK   (0xFFFF0000U)
#define	CAAM_SMCR_PG0_PAGE_SHIFT   (16U)
#define	CAAM_SMCR_PG0_PAGE(x)
SMCSR_PG0 - Secure Memory Command Status Register
#define	CAAM_SMCSR_PG0_PRTN_MASK   (0xFU)
#define	CAAM_SMCSR_PG0_PRTN_SHIFT   (0U)
#define	CAAM_SMCSR_PG0_PRTN(x)
#define	CAAM_SMCSR_PG0_PO_MASK   (0xC0U)
#define	CAAM_SMCSR_PG0_PO_SHIFT   (6U)
#define	CAAM_SMCSR_PG0_PO(x)
#define	CAAM_SMCSR_PG0_AERR_MASK   (0x3000U)
#define	CAAM_SMCSR_PG0_AERR_SHIFT   (12U)
#define	CAAM_SMCSR_PG0_AERR(x)
#define	CAAM_SMCSR_PG0_CERR_MASK   (0xC000U)
#define	CAAM_SMCSR_PG0_CERR_SHIFT   (14U)
#define	CAAM_SMCSR_PG0_CERR(x)
#define	CAAM_SMCSR_PG0_PAGE_MASK   (0xFFF0000U)
#define	CAAM_SMCSR_PG0_PAGE_SHIFT   (16U)
#define	CAAM_SMCSR_PG0_PAGE(x)
CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half
#define	CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK   (0xFFU)
#define	CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT   (0U)
#define	CAAM_CAAMVID_MS_TRAD_MIN_REV(x)
#define	CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK   (0xFF00U)
#define	CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT   (8U)
#define	CAAM_CAAMVID_MS_TRAD_MAJ_REV(x)
#define	CAAM_CAAMVID_MS_TRAD_IP_ID_MASK   (0xFFFF0000U)
#define	CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT   (16U)
#define	CAAM_CAAMVID_MS_TRAD_IP_ID(x)
CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half
#define	CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK   (0xFFU)
#define	CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT   (0U)
#define	CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x)
#define	CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK   (0xFF00U)
#define	CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT   (8U)
#define	CAAM_CAAMVID_LS_TRAD_ECO_REV(x)
#define	CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK   (0xFF0000U)
#define	CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT   (16U)
#define	CAAM_CAAMVID_LS_TRAD_INTG_OPT(x)
#define	CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK   (0xFF000000U)
#define	CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT   (24U)
#define	CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x)
HT_JD_ADDR - Holding Tank 0 Job Descriptor Address
#define	CAAM_HT_JD_ADDR_JD_ADDR_MASK   (0xFFFFFFFFFU)
#define	CAAM_HT_JD_ADDR_JD_ADDR_SHIFT   (0U)
#define	CAAM_HT_JD_ADDR_JD_ADDR(x)
HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address
#define	CAAM_HT_SD_ADDR_SD_ADDR_MASK   (0xFFFFFFFFFU)
#define	CAAM_HT_SD_ADDR_SD_ADDR_SHIFT   (0U)
#define	CAAM_HT_SD_ADDR_SD_ADDR(x)
HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half
#define	CAAM_HT_JQ_CTRL_MS_ID_MASK   (0x7U)
#define	CAAM_HT_JQ_CTRL_MS_ID_SHIFT   (0U)
#define	CAAM_HT_JQ_CTRL_MS_ID(x)
#define	CAAM_HT_JQ_CTRL_MS_SRC_MASK   (0x700U)
#define	CAAM_HT_JQ_CTRL_MS_SRC_SHIFT   (8U)
#define	CAAM_HT_JQ_CTRL_MS_SRC(x)
#define	CAAM_HT_JQ_CTRL_MS_JDDS_MASK   (0x4000U)
#define	CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT   (14U)
#define	CAAM_HT_JQ_CTRL_MS_JDDS(x)
#define	CAAM_HT_JQ_CTRL_MS_AMTD_MASK   (0x8000U)
#define	CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT   (15U)
#define	CAAM_HT_JQ_CTRL_MS_AMTD(x)
#define	CAAM_HT_JQ_CTRL_MS_SOB_MASK   (0x10000U)
#define	CAAM_HT_JQ_CTRL_MS_SOB_SHIFT   (16U)
#define	CAAM_HT_JQ_CTRL_MS_SOB(x)
#define	CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK   (0x60000U)
#define	CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT   (17U)
#define	CAAM_HT_JQ_CTRL_MS_HT_ERROR(x)
#define	CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK   (0x80000U)
#define	CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT   (19U)
#define	CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x)
#define	CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK   (0x7C00000U)
#define	CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT   (22U)
#define	CAAM_HT_JQ_CTRL_MS_SHR_FROM(x)
#define	CAAM_HT_JQ_CTRL_MS_ILE_MASK   (0x8000000U)
#define	CAAM_HT_JQ_CTRL_MS_ILE_SHIFT   (27U)
#define	CAAM_HT_JQ_CTRL_MS_ILE(x)
#define	CAAM_HT_JQ_CTRL_MS_FOUR_MASK   (0x10000000U)
#define	CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT   (28U)
#define	CAAM_HT_JQ_CTRL_MS_FOUR(x)
#define	CAAM_HT_JQ_CTRL_MS_WHL_MASK   (0x20000000U)
#define	CAAM_HT_JQ_CTRL_MS_WHL_SHIFT   (29U)
#define	CAAM_HT_JQ_CTRL_MS_WHL(x)
HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half
#define	CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK   (0xFU)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT   (0U)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_DID(x)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK   (0x10U)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT   (4U)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK   (0xFFE0U)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT   (5U)
#define	CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x)
#define	CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK   (0xF0000U)
#define	CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT   (16U)
#define	CAAM_HT_JQ_CTRL_LS_OUT_DID(x)
#define	CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK   (0xFFE00000U)
#define	CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT   (21U)
#define	CAAM_HT_JQ_CTRL_LS_OUT_ICID(x)
HT_STATUS - Holding Tank Status
#define	CAAM_HT_STATUS_PEND_0_MASK   (0x1U)
#define	CAAM_HT_STATUS_PEND_0_SHIFT   (0U)
#define	CAAM_HT_STATUS_PEND_0(x)
#define	CAAM_HT_STATUS_IN_USE_MASK   (0x40000000U)
#define	CAAM_HT_STATUS_IN_USE_SHIFT   (30U)
#define	CAAM_HT_STATUS_IN_USE(x)
#define	CAAM_HT_STATUS_BC_MASK   (0x80000000U)
#define	CAAM_HT_STATUS_BC_SHIFT   (31U)
#define	CAAM_HT_STATUS_BC(x)
JQ_DEBUG_SEL - Job Queue Debug Select Register
#define	CAAM_JQ_DEBUG_SEL_HT_SEL_MASK   (0x1U)
#define	CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT   (0U)
#define	CAAM_JQ_DEBUG_SEL_HT_SEL(x)
#define	CAAM_JQ_DEBUG_SEL_JOB_ID_MASK   (0x70000U)
#define	CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT   (16U)
#define	CAAM_JQ_DEBUG_SEL_JOB_ID(x)
JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half
#define	CAAM_JRJIDU_LS_JID00_MASK   (0x1U)
#define	CAAM_JRJIDU_LS_JID00_SHIFT   (0U)
#define	CAAM_JRJIDU_LS_JID00(x)
#define	CAAM_JRJIDU_LS_JID01_MASK   (0x2U)
#define	CAAM_JRJIDU_LS_JID01_SHIFT   (1U)
#define	CAAM_JRJIDU_LS_JID01(x)
#define	CAAM_JRJIDU_LS_JID02_MASK   (0x4U)
#define	CAAM_JRJIDU_LS_JID02_SHIFT   (2U)
#define	CAAM_JRJIDU_LS_JID02(x)
#define	CAAM_JRJIDU_LS_JID03_MASK   (0x8U)
#define	CAAM_JRJIDU_LS_JID03_SHIFT   (3U)
#define	CAAM_JRJIDU_LS_JID03(x)
JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC
#define	CAAM_JRJDJIFBC_BC_MASK   (0x80000000U)
#define	CAAM_JRJDJIFBC_BC_SHIFT   (31U)
#define	CAAM_JRJDJIFBC_BC(x)
JRJDJIF - Job Ring Job-Done Job ID FIFO
#define	CAAM_JRJDJIF_JOB_ID_ENTRY_MASK   (0x7U)
#define	CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT   (0U)
#define	CAAM_JRJDJIF_JOB_ID_ENTRY(x)
JRJDS1 - Job Ring Job-Done Source 1
#define	CAAM_JRJDS1_SRC_MASK   (0x3U)
#define	CAAM_JRJDS1_SRC_SHIFT   (0U)
#define	CAAM_JRJDS1_SRC(x)
#define	CAAM_JRJDS1_VALID_MASK   (0x80000000U)
#define	CAAM_JRJDS1_VALID_SHIFT   (31U)
#define	CAAM_JRJDS1_VALID(x)
JRJDDA - Job Ring Job-Done Descriptor Address 0 Register
#define	CAAM_JRJDDA_JD_ADDR_MASK   (0xFFFFFFFFFU)
#define	CAAM_JRJDDA_JD_ADDR_SHIFT   (0U)
#define	CAAM_JRJDDA_JD_ADDR(x)
CRNR_MS - CHA Revision Number Register, most-significant half
#define	CAAM_CRNR_MS_CRCRN_MASK   (0xFU)
#define	CAAM_CRNR_MS_CRCRN_SHIFT   (0U)
#define	CAAM_CRNR_MS_CRCRN(x)
#define	CAAM_CRNR_MS_SNW9RN_MASK   (0xF0U)
#define	CAAM_CRNR_MS_SNW9RN_SHIFT   (4U)
#define	CAAM_CRNR_MS_SNW9RN(x)
#define	CAAM_CRNR_MS_ZERN_MASK   (0xF00U)
#define	CAAM_CRNR_MS_ZERN_SHIFT   (8U)
#define	CAAM_CRNR_MS_ZERN(x)
#define	CAAM_CRNR_MS_ZARN_MASK   (0xF000U)
#define	CAAM_CRNR_MS_ZARN_SHIFT   (12U)
#define	CAAM_CRNR_MS_ZARN(x)
#define	CAAM_CRNR_MS_DECORN_MASK   (0xF000000U)
#define	CAAM_CRNR_MS_DECORN_SHIFT   (24U)
#define	CAAM_CRNR_MS_DECORN(x)
#define	CAAM_CRNR_MS_JRRN_MASK   (0xF0000000U)
#define	CAAM_CRNR_MS_JRRN_SHIFT   (28U)
#define	CAAM_CRNR_MS_JRRN(x)
CRNR_LS - CHA Revision Number Register, least-significant half
#define	CAAM_CRNR_LS_AESRN_MASK   (0xFU)
#define	CAAM_CRNR_LS_AESRN_SHIFT   (0U)
#define	CAAM_CRNR_LS_AESRN(x)
#define	CAAM_CRNR_LS_DESRN_MASK   (0xF0U)
#define	CAAM_CRNR_LS_DESRN_SHIFT   (4U)
#define	CAAM_CRNR_LS_DESRN(x)
#define	CAAM_CRNR_LS_MDRN_MASK   (0xF000U)
#define	CAAM_CRNR_LS_MDRN_SHIFT   (12U)
#define	CAAM_CRNR_LS_MDRN(x)
#define	CAAM_CRNR_LS_RNGRN_MASK   (0xF0000U)
#define	CAAM_CRNR_LS_RNGRN_SHIFT   (16U)
#define	CAAM_CRNR_LS_RNGRN(x)
#define	CAAM_CRNR_LS_SNW8RN_MASK   (0xF00000U)
#define	CAAM_CRNR_LS_SNW8RN_SHIFT   (20U)
#define	CAAM_CRNR_LS_SNW8RN(x)
#define	CAAM_CRNR_LS_KASRN_MASK   (0xF000000U)
#define	CAAM_CRNR_LS_KASRN_SHIFT   (24U)
#define	CAAM_CRNR_LS_KASRN(x)
#define	CAAM_CRNR_LS_PKRN_MASK   (0xF0000000U)
#define	CAAM_CRNR_LS_PKRN_SHIFT   (28U)
#define	CAAM_CRNR_LS_PKRN(x)
CTPR_MS - Compile Time Parameters Register, most-significant half
#define	CAAM_CTPR_MS_VIRT_EN_INCL_MASK   (0x1U)
#define	CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT   (0U)
#define	CAAM_CTPR_MS_VIRT_EN_INCL(x)
#define	CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK   (0x2U)
#define	CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT   (1U)
#define	CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x)
#define	CAAM_CTPR_MS_REG_PG_SIZE_MASK   (0x10U)
#define	CAAM_CTPR_MS_REG_PG_SIZE_SHIFT   (4U)
#define	CAAM_CTPR_MS_REG_PG_SIZE(x)
#define	CAAM_CTPR_MS_RNG_I_MASK   (0x700U)
#define	CAAM_CTPR_MS_RNG_I_SHIFT   (8U)
#define	CAAM_CTPR_MS_RNG_I(x)
#define	CAAM_CTPR_MS_AI_INCL_MASK   (0x800U)
#define	CAAM_CTPR_MS_AI_INCL_SHIFT   (11U)
#define	CAAM_CTPR_MS_AI_INCL(x)
#define	CAAM_CTPR_MS_DPAA2_MASK   (0x2000U)
#define	CAAM_CTPR_MS_DPAA2_SHIFT   (13U)
#define	CAAM_CTPR_MS_DPAA2(x)
#define	CAAM_CTPR_MS_IP_CLK_MASK   (0x4000U)
#define	CAAM_CTPR_MS_IP_CLK_SHIFT   (14U)
#define	CAAM_CTPR_MS_IP_CLK(x)
#define	CAAM_CTPR_MS_MCFG_BURST_MASK   (0x10000U)
#define	CAAM_CTPR_MS_MCFG_BURST_SHIFT   (16U)
#define	CAAM_CTPR_MS_MCFG_BURST(x)
#define	CAAM_CTPR_MS_MCFG_PS_MASK   (0x20000U)
#define	CAAM_CTPR_MS_MCFG_PS_SHIFT   (17U)
#define	CAAM_CTPR_MS_MCFG_PS(x)
#define	CAAM_CTPR_MS_SG8_MASK   (0x40000U)
#define	CAAM_CTPR_MS_SG8_SHIFT   (18U)
#define	CAAM_CTPR_MS_SG8(x)
#define	CAAM_CTPR_MS_PM_EVT_BUS_MASK   (0x80000U)
#define	CAAM_CTPR_MS_PM_EVT_BUS_SHIFT   (19U)
#define	CAAM_CTPR_MS_PM_EVT_BUS(x)
#define	CAAM_CTPR_MS_DECO_WD_MASK   (0x100000U)
#define	CAAM_CTPR_MS_DECO_WD_SHIFT   (20U)
#define	CAAM_CTPR_MS_DECO_WD(x)
#define	CAAM_CTPR_MS_PC_MASK   (0x200000U)
#define	CAAM_CTPR_MS_PC_SHIFT   (21U)
#define	CAAM_CTPR_MS_PC(x)
#define	CAAM_CTPR_MS_C1C2_MASK   (0x800000U)
#define	CAAM_CTPR_MS_C1C2_SHIFT   (23U)
#define	CAAM_CTPR_MS_C1C2(x)
#define	CAAM_CTPR_MS_ACC_CTL_MASK   (0x1000000U)
#define	CAAM_CTPR_MS_ACC_CTL_SHIFT   (24U)
#define	CAAM_CTPR_MS_ACC_CTL(x)
#define	CAAM_CTPR_MS_QI_MASK   (0x2000000U)
#define	CAAM_CTPR_MS_QI_SHIFT   (25U)
#define	CAAM_CTPR_MS_QI(x)
#define	CAAM_CTPR_MS_AXI_PRI_MASK   (0x4000000U)
#define	CAAM_CTPR_MS_AXI_PRI_SHIFT   (26U)
#define	CAAM_CTPR_MS_AXI_PRI(x)
#define	CAAM_CTPR_MS_AXI_LIODN_MASK   (0x8000000U)
#define	CAAM_CTPR_MS_AXI_LIODN_SHIFT   (27U)
#define	CAAM_CTPR_MS_AXI_LIODN(x)
#define	CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK   (0xF0000000U)
#define	CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT   (28U)
#define	CAAM_CTPR_MS_AXI_PIPE_DEPTH(x)
CTPR_LS - Compile Time Parameters Register, least-significant half
#define	CAAM_CTPR_LS_KG_DS_MASK   (0x1U)
#define	CAAM_CTPR_LS_KG_DS_SHIFT   (0U)
#define	CAAM_CTPR_LS_KG_DS(x)
#define	CAAM_CTPR_LS_BLOB_MASK   (0x2U)
#define	CAAM_CTPR_LS_BLOB_SHIFT   (1U)
#define	CAAM_CTPR_LS_BLOB(x)
#define	CAAM_CTPR_LS_WIFI_MASK   (0x4U)
#define	CAAM_CTPR_LS_WIFI_SHIFT   (2U)
#define	CAAM_CTPR_LS_WIFI(x)
#define	CAAM_CTPR_LS_WIMAX_MASK   (0x8U)
#define	CAAM_CTPR_LS_WIMAX_SHIFT   (3U)
#define	CAAM_CTPR_LS_WIMAX(x)
#define	CAAM_CTPR_LS_SRTP_MASK   (0x10U)
#define	CAAM_CTPR_LS_SRTP_SHIFT   (4U)
#define	CAAM_CTPR_LS_SRTP(x)
#define	CAAM_CTPR_LS_IPSEC_MASK   (0x20U)
#define	CAAM_CTPR_LS_IPSEC_SHIFT   (5U)
#define	CAAM_CTPR_LS_IPSEC(x)
#define	CAAM_CTPR_LS_IKE_MASK   (0x40U)
#define	CAAM_CTPR_LS_IKE_SHIFT   (6U)
#define	CAAM_CTPR_LS_IKE(x)
#define	CAAM_CTPR_LS_SSL_TLS_MASK   (0x80U)
#define	CAAM_CTPR_LS_SSL_TLS_SHIFT   (7U)
#define	CAAM_CTPR_LS_SSL_TLS(x)
#define	CAAM_CTPR_LS_TLS_PRF_MASK   (0x100U)
#define	CAAM_CTPR_LS_TLS_PRF_SHIFT   (8U)
#define	CAAM_CTPR_LS_TLS_PRF(x)
#define	CAAM_CTPR_LS_MACSEC_MASK   (0x200U)
#define	CAAM_CTPR_LS_MACSEC_SHIFT   (9U)
#define	CAAM_CTPR_LS_MACSEC(x)
#define	CAAM_CTPR_LS_RSA_MASK   (0x400U)
#define	CAAM_CTPR_LS_RSA_SHIFT   (10U)
#define	CAAM_CTPR_LS_RSA(x)
#define	CAAM_CTPR_LS_P3G_LTE_MASK   (0x800U)
#define	CAAM_CTPR_LS_P3G_LTE_SHIFT   (11U)
#define	CAAM_CTPR_LS_P3G_LTE(x)
#define	CAAM_CTPR_LS_DBL_CRC_MASK   (0x1000U)
#define	CAAM_CTPR_LS_DBL_CRC_SHIFT   (12U)
#define	CAAM_CTPR_LS_DBL_CRC(x)
#define	CAAM_CTPR_LS_MAN_PROT_MASK   (0x2000U)
#define	CAAM_CTPR_LS_MAN_PROT_SHIFT   (13U)
#define	CAAM_CTPR_LS_MAN_PROT(x)
#define	CAAM_CTPR_LS_DKP_MASK   (0x4000U)
#define	CAAM_CTPR_LS_DKP_SHIFT   (14U)
#define	CAAM_CTPR_LS_DKP(x)
SMSTA - Secure Memory Status Register
#define	CAAM_SMSTA_STATE_MASK   (0xFU)
#define	CAAM_SMSTA_STATE_SHIFT   (0U)
#define	CAAM_SMSTA_STATE(x)
#define	CAAM_SMSTA_ACCERR_MASK   (0xF0U)
#define	CAAM_SMSTA_ACCERR_SHIFT   (4U)
#define	CAAM_SMSTA_ACCERR(x)
#define	CAAM_SMSTA_DID_MASK   (0xF00U)
#define	CAAM_SMSTA_DID_SHIFT   (8U)
#define	CAAM_SMSTA_DID(x)
#define	CAAM_SMSTA_NS_MASK   (0x1000U)
#define	CAAM_SMSTA_NS_SHIFT   (12U)
#define	CAAM_SMSTA_NS(x)
#define	CAAM_SMSTA_SMR_WP_MASK   (0x8000U)
#define	CAAM_SMSTA_SMR_WP_SHIFT   (15U)
#define	CAAM_SMSTA_SMR_WP(x)
#define	CAAM_SMSTA_PAGE_MASK   (0x7FF0000U)
#define	CAAM_SMSTA_PAGE_SHIFT   (16U)
#define	CAAM_SMSTA_PAGE(x)
#define	CAAM_SMSTA_PART_MASK   (0xF0000000U)
#define	CAAM_SMSTA_PART_SHIFT   (28U)
#define	CAAM_SMSTA_PART(x)
SMPO - Secure Memory Partition Owners Register
#define	CAAM_SMPO_PO0_MASK   (0x3U)
#define	CAAM_SMPO_PO0_SHIFT   (0U)
#define	CAAM_SMPO_PO0(x)
#define	CAAM_SMPO_PO1_MASK   (0xCU)
#define	CAAM_SMPO_PO1_SHIFT   (2U)
#define	CAAM_SMPO_PO1(x)
#define	CAAM_SMPO_PO2_MASK   (0x30U)
#define	CAAM_SMPO_PO2_SHIFT   (4U)
#define	CAAM_SMPO_PO2(x)
#define	CAAM_SMPO_PO3_MASK   (0xC0U)
#define	CAAM_SMPO_PO3_SHIFT   (6U)
#define	CAAM_SMPO_PO3(x)
#define	CAAM_SMPO_PO4_MASK   (0x300U)
#define	CAAM_SMPO_PO4_SHIFT   (8U)
#define	CAAM_SMPO_PO4(x)
#define	CAAM_SMPO_PO5_MASK   (0xC00U)
#define	CAAM_SMPO_PO5_SHIFT   (10U)
#define	CAAM_SMPO_PO5(x)
#define	CAAM_SMPO_PO6_MASK   (0x3000U)
#define	CAAM_SMPO_PO6_SHIFT   (12U)
#define	CAAM_SMPO_PO6(x)
#define	CAAM_SMPO_PO7_MASK   (0xC000U)
#define	CAAM_SMPO_PO7_SHIFT   (14U)
#define	CAAM_SMPO_PO7(x)
#define	CAAM_SMPO_PO8_MASK   (0x30000U)
#define	CAAM_SMPO_PO8_SHIFT   (16U)
#define	CAAM_SMPO_PO8(x)
#define	CAAM_SMPO_PO9_MASK   (0xC0000U)
#define	CAAM_SMPO_PO9_SHIFT   (18U)
#define	CAAM_SMPO_PO9(x)
#define	CAAM_SMPO_PO10_MASK   (0x300000U)
#define	CAAM_SMPO_PO10_SHIFT   (20U)
#define	CAAM_SMPO_PO10(x)
#define	CAAM_SMPO_PO11_MASK   (0xC00000U)
#define	CAAM_SMPO_PO11_SHIFT   (22U)
#define	CAAM_SMPO_PO11(x)
#define	CAAM_SMPO_PO12_MASK   (0x3000000U)
#define	CAAM_SMPO_PO12_SHIFT   (24U)
#define	CAAM_SMPO_PO12(x)
#define	CAAM_SMPO_PO13_MASK   (0xC000000U)
#define	CAAM_SMPO_PO13_SHIFT   (26U)
#define	CAAM_SMPO_PO13(x)
#define	CAAM_SMPO_PO14_MASK   (0x30000000U)
#define	CAAM_SMPO_PO14_SHIFT   (28U)
#define	CAAM_SMPO_PO14(x)
#define	CAAM_SMPO_PO15_MASK   (0xC0000000U)
#define	CAAM_SMPO_PO15_SHIFT   (30U)
#define	CAAM_SMPO_PO15(x)
FAR - Fault Address Register
#define	CAAM_FAR_FAR_MASK   (0xFFFFFFFFFU)
#define	CAAM_FAR_FAR_SHIFT   (0U)
#define	CAAM_FAR_FAR(x)
FADID - Fault Address DID Register
#define	CAAM_FADID_FDID_MASK   (0xFU)
#define	CAAM_FADID_FDID_SHIFT   (0U)
#define	CAAM_FADID_FDID(x)
#define	CAAM_FADID_FNS_MASK   (0x10U)
#define	CAAM_FADID_FNS_SHIFT   (4U)
#define	CAAM_FADID_FNS(x)
#define	CAAM_FADID_FICID_MASK   (0xFFE0U)
#define	CAAM_FADID_FICID_SHIFT   (5U)
#define	CAAM_FADID_FICID(x)
FADR - Fault Address Detail Register
#define	CAAM_FADR_FSZ_MASK   (0x7FU)
#define	CAAM_FADR_FSZ_SHIFT   (0U)
#define	CAAM_FADR_FSZ(x)
#define	CAAM_FADR_TYP_MASK   (0x80U)
#define	CAAM_FADR_TYP_SHIFT   (7U)
#define	CAAM_FADR_TYP(x)
#define	CAAM_FADR_BLKID_MASK   (0xF00U)
#define	CAAM_FADR_BLKID_SHIFT   (8U)
#define	CAAM_FADR_BLKID(x)
#define	CAAM_FADR_JSRC_MASK   (0x7000U)
#define	CAAM_FADR_JSRC_SHIFT   (12U)
#define	CAAM_FADR_JSRC(x)
#define	CAAM_FADR_DTYP_MASK   (0x8000U)
#define	CAAM_FADR_DTYP_SHIFT   (15U)
#define	CAAM_FADR_DTYP(x)
#define	CAAM_FADR_FSZ_EXT_MASK   (0x70000U)
#define	CAAM_FADR_FSZ_EXT_SHIFT   (16U)
#define	CAAM_FADR_FSZ_EXT(x)
#define	CAAM_FADR_FKMOD_MASK   (0x1000000U)
#define	CAAM_FADR_FKMOD_SHIFT   (24U)
#define	CAAM_FADR_FKMOD(x)
#define	CAAM_FADR_FKEY_MASK   (0x2000000U)
#define	CAAM_FADR_FKEY_SHIFT   (25U)
#define	CAAM_FADR_FKEY(x)
#define	CAAM_FADR_FTDSC_MASK   (0x4000000U)
#define	CAAM_FADR_FTDSC_SHIFT   (26U)
#define	CAAM_FADR_FTDSC(x)
#define	CAAM_FADR_FBNDG_MASK   (0x8000000U)
#define	CAAM_FADR_FBNDG_SHIFT   (27U)
#define	CAAM_FADR_FBNDG(x)
#define	CAAM_FADR_FNS_MASK   (0x10000000U)
#define	CAAM_FADR_FNS_SHIFT   (28U)
#define	CAAM_FADR_FNS(x)
#define	CAAM_FADR_FERR_MASK   (0xC0000000U)
#define	CAAM_FADR_FERR_SHIFT   (30U)
#define	CAAM_FADR_FERR(x)
CSTA - CAAM Status Register
#define	CAAM_CSTA_BSY_MASK   (0x1U)
#define	CAAM_CSTA_BSY_SHIFT   (0U)
#define	CAAM_CSTA_BSY(x)
#define	CAAM_CSTA_IDLE_MASK   (0x2U)
#define	CAAM_CSTA_IDLE_SHIFT   (1U)
#define	CAAM_CSTA_IDLE(x)
#define	CAAM_CSTA_TRNG_IDLE_MASK   (0x4U)
#define	CAAM_CSTA_TRNG_IDLE_SHIFT   (2U)
#define	CAAM_CSTA_TRNG_IDLE(x)
#define	CAAM_CSTA_MOO_MASK   (0x300U)
#define	CAAM_CSTA_MOO_SHIFT   (8U)
#define	CAAM_CSTA_MOO(x)
#define	CAAM_CSTA_PLEND_MASK   (0x400U)
#define	CAAM_CSTA_PLEND_SHIFT   (10U)
#define	CAAM_CSTA_PLEND(x)
SMVID_MS - Secure Memory Version ID Register, most-significant half
#define	CAAM_SMVID_MS_NPAG_MASK   (0x3FFU)
#define	CAAM_SMVID_MS_NPAG_SHIFT   (0U)
#define	CAAM_SMVID_MS_NPAG(x)
#define	CAAM_SMVID_MS_NPRT_MASK   (0xF000U)
#define	CAAM_SMVID_MS_NPRT_SHIFT   (12U)
#define	CAAM_SMVID_MS_NPRT(x)
#define	CAAM_SMVID_MS_MAX_NPAG_MASK   (0x3FF0000U)
#define	CAAM_SMVID_MS_MAX_NPAG_SHIFT   (16U)
#define	CAAM_SMVID_MS_MAX_NPAG(x)
SMVID_LS - Secure Memory Version ID Register, least-significant half
#define	CAAM_SMVID_LS_SMNV_MASK   (0xFFU)
#define	CAAM_SMVID_LS_SMNV_SHIFT   (0U)
#define	CAAM_SMVID_LS_SMNV(x)
#define	CAAM_SMVID_LS_SMJV_MASK   (0xFF00U)
#define	CAAM_SMVID_LS_SMJV_SHIFT   (8U)
#define	CAAM_SMVID_LS_SMJV(x)
#define	CAAM_SMVID_LS_PSIZ_MASK   (0x70000U)
#define	CAAM_SMVID_LS_PSIZ_SHIFT   (16U)
#define	CAAM_SMVID_LS_PSIZ(x)
RVID - RTIC Version ID Register
#define	CAAM_RVID_RMNV_MASK   (0xFFU)
#define	CAAM_RVID_RMNV_SHIFT   (0U)
#define	CAAM_RVID_RMNV(x)
#define	CAAM_RVID_RMJV_MASK   (0xFF00U)
#define	CAAM_RVID_RMJV_SHIFT   (8U)
#define	CAAM_RVID_RMJV(x)
#define	CAAM_RVID_SHA_256_MASK   (0x20000U)
#define	CAAM_RVID_SHA_256_SHIFT   (17U)
#define	CAAM_RVID_SHA_256(x)
#define	CAAM_RVID_SHA_512_MASK   (0x80000U)
#define	CAAM_RVID_SHA_512_SHIFT   (19U)
#define	CAAM_RVID_SHA_512(x)
#define	CAAM_RVID_MA_MASK   (0x1000000U)
#define	CAAM_RVID_MA_SHIFT   (24U)
#define	CAAM_RVID_MA(x)
#define	CAAM_RVID_MB_MASK   (0x2000000U)
#define	CAAM_RVID_MB_SHIFT   (25U)
#define	CAAM_RVID_MB(x)
#define	CAAM_RVID_MC_MASK   (0x4000000U)
#define	CAAM_RVID_MC_SHIFT   (26U)
#define	CAAM_RVID_MC(x)
#define	CAAM_RVID_MD_MASK   (0x8000000U)
#define	CAAM_RVID_MD_SHIFT   (27U)
#define	CAAM_RVID_MD(x)
CCBVID - CHA Cluster Block Version ID Register
#define	CAAM_CCBVID_AMNV_MASK   (0xFFU)
#define	CAAM_CCBVID_AMNV_SHIFT   (0U)
#define	CAAM_CCBVID_AMNV(x)
#define	CAAM_CCBVID_AMJV_MASK   (0xFF00U)
#define	CAAM_CCBVID_AMJV_SHIFT   (8U)
#define	CAAM_CCBVID_AMJV(x)
#define	CAAM_CCBVID_CAAM_ERA_MASK   (0xFF000000U)
#define	CAAM_CCBVID_CAAM_ERA_SHIFT   (24U)
#define	CAAM_CCBVID_CAAM_ERA(x)
CHAVID_MS - CHA Version ID Register, most-significant half
#define	CAAM_CHAVID_MS_CRCVID_MASK   (0xFU)
#define	CAAM_CHAVID_MS_CRCVID_SHIFT   (0U)
#define	CAAM_CHAVID_MS_CRCVID(x)
#define	CAAM_CHAVID_MS_SNW9VID_MASK   (0xF0U)
#define	CAAM_CHAVID_MS_SNW9VID_SHIFT   (4U)
#define	CAAM_CHAVID_MS_SNW9VID(x)
#define	CAAM_CHAVID_MS_ZEVID_MASK   (0xF00U)
#define	CAAM_CHAVID_MS_ZEVID_SHIFT   (8U)
#define	CAAM_CHAVID_MS_ZEVID(x)
#define	CAAM_CHAVID_MS_ZAVID_MASK   (0xF000U)
#define	CAAM_CHAVID_MS_ZAVID_SHIFT   (12U)
#define	CAAM_CHAVID_MS_ZAVID(x)
#define	CAAM_CHAVID_MS_DECOVID_MASK   (0xF000000U)
#define	CAAM_CHAVID_MS_DECOVID_SHIFT   (24U)
#define	CAAM_CHAVID_MS_DECOVID(x)
#define	CAAM_CHAVID_MS_JRVID_MASK   (0xF0000000U)
#define	CAAM_CHAVID_MS_JRVID_SHIFT   (28U)
#define	CAAM_CHAVID_MS_JRVID(x)
CHAVID_LS - CHA Version ID Register, least-significant half
#define	CAAM_CHAVID_LS_AESVID_MASK   (0xFU)
#define	CAAM_CHAVID_LS_AESVID_SHIFT   (0U)
#define	CAAM_CHAVID_LS_AESVID(x)
#define	CAAM_CHAVID_LS_DESVID_MASK   (0xF0U)
#define	CAAM_CHAVID_LS_DESVID_SHIFT   (4U)
#define	CAAM_CHAVID_LS_DESVID(x)
#define	CAAM_CHAVID_LS_MDVID_MASK   (0xF000U)
#define	CAAM_CHAVID_LS_MDVID_SHIFT   (12U)
#define	CAAM_CHAVID_LS_MDVID(x)
#define	CAAM_CHAVID_LS_RNGVID_MASK   (0xF0000U)
#define	CAAM_CHAVID_LS_RNGVID_SHIFT   (16U)
#define	CAAM_CHAVID_LS_RNGVID(x)
#define	CAAM_CHAVID_LS_SNW8VID_MASK   (0xF00000U)
#define	CAAM_CHAVID_LS_SNW8VID_SHIFT   (20U)
#define	CAAM_CHAVID_LS_SNW8VID(x)
#define	CAAM_CHAVID_LS_KASVID_MASK   (0xF000000U)
#define	CAAM_CHAVID_LS_KASVID_SHIFT   (24U)
#define	CAAM_CHAVID_LS_KASVID(x)
#define	CAAM_CHAVID_LS_PKVID_MASK   (0xF0000000U)
#define	CAAM_CHAVID_LS_PKVID_SHIFT   (28U)
#define	CAAM_CHAVID_LS_PKVID(x)
CHANUM_MS - CHA Number Register, most-significant half
#define	CAAM_CHANUM_MS_CRCNUM_MASK   (0xFU)
#define	CAAM_CHANUM_MS_CRCNUM_SHIFT   (0U)
#define	CAAM_CHANUM_MS_CRCNUM(x)
#define	CAAM_CHANUM_MS_SNW9NUM_MASK   (0xF0U)
#define	CAAM_CHANUM_MS_SNW9NUM_SHIFT   (4U)
#define	CAAM_CHANUM_MS_SNW9NUM(x)
#define	CAAM_CHANUM_MS_ZENUM_MASK   (0xF00U)
#define	CAAM_CHANUM_MS_ZENUM_SHIFT   (8U)
#define	CAAM_CHANUM_MS_ZENUM(x)
#define	CAAM_CHANUM_MS_ZANUM_MASK   (0xF000U)
#define	CAAM_CHANUM_MS_ZANUM_SHIFT   (12U)
#define	CAAM_CHANUM_MS_ZANUM(x)
#define	CAAM_CHANUM_MS_DECONUM_MASK   (0xF000000U)
#define	CAAM_CHANUM_MS_DECONUM_SHIFT   (24U)
#define	CAAM_CHANUM_MS_DECONUM(x)
#define	CAAM_CHANUM_MS_JRNUM_MASK   (0xF0000000U)
#define	CAAM_CHANUM_MS_JRNUM_SHIFT   (28U)
#define	CAAM_CHANUM_MS_JRNUM(x)
CHANUM_LS - CHA Number Register, least-significant half
#define	CAAM_CHANUM_LS_AESNUM_MASK   (0xFU)
#define	CAAM_CHANUM_LS_AESNUM_SHIFT   (0U)
#define	CAAM_CHANUM_LS_AESNUM(x)
#define	CAAM_CHANUM_LS_DESNUM_MASK   (0xF0U)
#define	CAAM_CHANUM_LS_DESNUM_SHIFT   (4U)
#define	CAAM_CHANUM_LS_DESNUM(x)
#define	CAAM_CHANUM_LS_ARC4NUM_MASK   (0xF00U)
#define	CAAM_CHANUM_LS_ARC4NUM_SHIFT   (8U)
#define	CAAM_CHANUM_LS_ARC4NUM(x)
#define	CAAM_CHANUM_LS_MDNUM_MASK   (0xF000U)
#define	CAAM_CHANUM_LS_MDNUM_SHIFT   (12U)
#define	CAAM_CHANUM_LS_MDNUM(x)
#define	CAAM_CHANUM_LS_RNGNUM_MASK   (0xF0000U)
#define	CAAM_CHANUM_LS_RNGNUM_SHIFT   (16U)
#define	CAAM_CHANUM_LS_RNGNUM(x)
#define	CAAM_CHANUM_LS_SNW8NUM_MASK   (0xF00000U)
#define	CAAM_CHANUM_LS_SNW8NUM_SHIFT   (20U)
#define	CAAM_CHANUM_LS_SNW8NUM(x)
#define	CAAM_CHANUM_LS_KASNUM_MASK   (0xF000000U)
#define	CAAM_CHANUM_LS_KASNUM_SHIFT   (24U)
#define	CAAM_CHANUM_LS_KASNUM(x)
#define	CAAM_CHANUM_LS_PKNUM_MASK   (0xF0000000U)
#define	CAAM_CHANUM_LS_PKNUM_SHIFT   (28U)
#define	CAAM_CHANUM_LS_PKNUM(x)
IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3
#define	CAAM_IRBAR_JR_IRBA_MASK   (0xFFFFFFFFFU)
#define	CAAM_IRBAR_JR_IRBA_SHIFT   (0U)
#define	CAAM_IRBAR_JR_IRBA(x)
IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3
#define	CAAM_IRSR_JR_IRS_MASK   (0x3FFU)
#define	CAAM_IRSR_JR_IRS_SHIFT   (0U)
#define	CAAM_IRSR_JR_IRS(x)
IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3
#define	CAAM_IRSAR_JR_IRSA_MASK   (0x3FFU)
#define	CAAM_IRSAR_JR_IRSA_SHIFT   (0U)
#define	CAAM_IRSAR_JR_IRSA(x)
IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3
#define	CAAM_IRJAR_JR_IRJA_MASK   (0x3FFU)
#define	CAAM_IRJAR_JR_IRJA_SHIFT   (0U)
#define	CAAM_IRJAR_JR_IRJA(x)
ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3
#define	CAAM_ORBAR_JR_ORBA_MASK   (0xFFFFFFFFFU)
#define	CAAM_ORBAR_JR_ORBA_SHIFT   (0U)
#define	CAAM_ORBAR_JR_ORBA(x)
ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3
#define	CAAM_ORSR_JR_ORS_MASK   (0x3FFU)
#define	CAAM_ORSR_JR_ORS_SHIFT   (0U)
#define	CAAM_ORSR_JR_ORS(x)
ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3
#define	CAAM_ORJRR_JR_ORJR_MASK   (0x3FFU)
#define	CAAM_ORJRR_JR_ORJR_SHIFT   (0U)
#define	CAAM_ORJRR_JR_ORJR(x)
ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3
#define	CAAM_ORSFR_JR_ORSF_MASK   (0x3FFU)
#define	CAAM_ORSFR_JR_ORSF_SHIFT   (0U)
#define	CAAM_ORSFR_JR_ORSF(x)
JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3
#define	CAAM_JRSTAR_JR_SSED_MASK   (0xFFFFFFFU)
#define	CAAM_JRSTAR_JR_SSED_SHIFT   (0U)
#define	CAAM_JRSTAR_JR_SSED(x)
#define	CAAM_JRSTAR_JR_SSRC_MASK   (0xF0000000U)
#define	CAAM_JRSTAR_JR_SSRC_SHIFT   (28U)
#define	CAAM_JRSTAR_JR_SSRC(x)
JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3
#define	CAAM_JRINTR_JR_JRI_MASK   (0x1U)
#define	CAAM_JRINTR_JR_JRI_SHIFT   (0U)
#define	CAAM_JRINTR_JR_JRI(x)
#define	CAAM_JRINTR_JR_JRE_MASK   (0x2U)
#define	CAAM_JRINTR_JR_JRE_SHIFT   (1U)
#define	CAAM_JRINTR_JR_JRE(x)
#define	CAAM_JRINTR_JR_HALT_MASK   (0xCU)
#define	CAAM_JRINTR_JR_HALT_SHIFT   (2U)
#define	CAAM_JRINTR_JR_HALT(x)
#define	CAAM_JRINTR_JR_ENTER_FAIL_MASK   (0x10U)
#define	CAAM_JRINTR_JR_ENTER_FAIL_SHIFT   (4U)
#define	CAAM_JRINTR_JR_ENTER_FAIL(x)
#define	CAAM_JRINTR_JR_EXIT_FAIL_MASK   (0x20U)
#define	CAAM_JRINTR_JR_EXIT_FAIL_SHIFT   (5U)
#define	CAAM_JRINTR_JR_EXIT_FAIL(x)
#define	CAAM_JRINTR_JR_ERR_TYPE_MASK   (0x1F00U)
#define	CAAM_JRINTR_JR_ERR_TYPE_SHIFT   (8U)
#define	CAAM_JRINTR_JR_ERR_TYPE(x)
#define	CAAM_JRINTR_JR_ERR_ORWI_MASK   (0x3FFF0000U)
#define	CAAM_JRINTR_JR_ERR_ORWI_SHIFT   (16U)
#define	CAAM_JRINTR_JR_ERR_ORWI(x)
JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half
#define	CAAM_JRCFGR_JR_MS_MBSI_MASK   (0x1U)
#define	CAAM_JRCFGR_JR_MS_MBSI_SHIFT   (0U)
#define	CAAM_JRCFGR_JR_MS_MBSI(x)
#define	CAAM_JRCFGR_JR_MS_MHWSI_MASK   (0x2U)
#define	CAAM_JRCFGR_JR_MS_MHWSI_SHIFT   (1U)
#define	CAAM_JRCFGR_JR_MS_MHWSI(x)
#define	CAAM_JRCFGR_JR_MS_MWSI_MASK   (0x4U)
#define	CAAM_JRCFGR_JR_MS_MWSI_SHIFT   (2U)
#define	CAAM_JRCFGR_JR_MS_MWSI(x)
#define	CAAM_JRCFGR_JR_MS_CBSI_MASK   (0x10U)
#define	CAAM_JRCFGR_JR_MS_CBSI_SHIFT   (4U)
#define	CAAM_JRCFGR_JR_MS_CBSI(x)
#define	CAAM_JRCFGR_JR_MS_CHWSI_MASK   (0x20U)
#define	CAAM_JRCFGR_JR_MS_CHWSI_SHIFT   (5U)
#define	CAAM_JRCFGR_JR_MS_CHWSI(x)
#define	CAAM_JRCFGR_JR_MS_CWSI_MASK   (0x40U)
#define	CAAM_JRCFGR_JR_MS_CWSI_SHIFT   (6U)
#define	CAAM_JRCFGR_JR_MS_CWSI(x)
#define	CAAM_JRCFGR_JR_MS_MBSO_MASK   (0x100U)
#define	CAAM_JRCFGR_JR_MS_MBSO_SHIFT   (8U)
#define	CAAM_JRCFGR_JR_MS_MBSO(x)
#define	CAAM_JRCFGR_JR_MS_MHWSO_MASK   (0x200U)
#define	CAAM_JRCFGR_JR_MS_MHWSO_SHIFT   (9U)
#define	CAAM_JRCFGR_JR_MS_MHWSO(x)
#define	CAAM_JRCFGR_JR_MS_MWSO_MASK   (0x400U)
#define	CAAM_JRCFGR_JR_MS_MWSO_SHIFT   (10U)
#define	CAAM_JRCFGR_JR_MS_MWSO(x)
#define	CAAM_JRCFGR_JR_MS_CBSO_MASK   (0x1000U)
#define	CAAM_JRCFGR_JR_MS_CBSO_SHIFT   (12U)
#define	CAAM_JRCFGR_JR_MS_CBSO(x)
#define	CAAM_JRCFGR_JR_MS_CHWSO_MASK   (0x2000U)
#define	CAAM_JRCFGR_JR_MS_CHWSO_SHIFT   (13U)
#define	CAAM_JRCFGR_JR_MS_CHWSO(x)
#define	CAAM_JRCFGR_JR_MS_CWSO_MASK   (0x4000U)
#define	CAAM_JRCFGR_JR_MS_CWSO_SHIFT   (14U)
#define	CAAM_JRCFGR_JR_MS_CWSO(x)
#define	CAAM_JRCFGR_JR_MS_DMBS_MASK   (0x10000U)
#define	CAAM_JRCFGR_JR_MS_DMBS_SHIFT   (16U)
#define	CAAM_JRCFGR_JR_MS_DMBS(x)
#define	CAAM_JRCFGR_JR_MS_PEO_MASK   (0x20000U)
#define	CAAM_JRCFGR_JR_MS_PEO_SHIFT   (17U)
#define	CAAM_JRCFGR_JR_MS_PEO(x)
#define	CAAM_JRCFGR_JR_MS_DWSO_MASK   (0x40000U)
#define	CAAM_JRCFGR_JR_MS_DWSO_SHIFT   (18U)
#define	CAAM_JRCFGR_JR_MS_DWSO(x)
#define	CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK   (0x20000000U)
#define	CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT   (29U)
#define	CAAM_JRCFGR_JR_MS_FAIL_MODE(x)
#define	CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK   (0x40000000U)
#define	CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT   (30U)
#define	CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x)
JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half
#define	CAAM_JRCFGR_JR_LS_IMSK_MASK   (0x1U)
#define	CAAM_JRCFGR_JR_LS_IMSK_SHIFT   (0U)
#define	CAAM_JRCFGR_JR_LS_IMSK(x)
#define	CAAM_JRCFGR_JR_LS_ICEN_MASK   (0x2U)
#define	CAAM_JRCFGR_JR_LS_ICEN_SHIFT   (1U)
#define	CAAM_JRCFGR_JR_LS_ICEN(x)
#define	CAAM_JRCFGR_JR_LS_ICDCT_MASK   (0xFF00U)
#define	CAAM_JRCFGR_JR_LS_ICDCT_SHIFT   (8U)
#define	CAAM_JRCFGR_JR_LS_ICDCT(x)
#define	CAAM_JRCFGR_JR_LS_ICTT_MASK   (0xFFFF0000U)
#define	CAAM_JRCFGR_JR_LS_ICTT_SHIFT   (16U)
#define	CAAM_JRCFGR_JR_LS_ICTT(x)
IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3
#define	CAAM_IRRIR_JR_IRRI_MASK   (0x1FFFU)
#define	CAAM_IRRIR_JR_IRRI_SHIFT   (0U)
#define	CAAM_IRRIR_JR_IRRI(x)
ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3
#define	CAAM_ORWIR_JR_ORWI_MASK   (0x3FFFU)
#define	CAAM_ORWIR_JR_ORWI_SHIFT   (0U)
#define	CAAM_ORWIR_JR_ORWI(x)
JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3
#define	CAAM_JRCR_JR_RESET_MASK   (0x1U)
#define	CAAM_JRCR_JR_RESET_SHIFT   (0U)
#define	CAAM_JRCR_JR_RESET(x)
#define	CAAM_JRCR_JR_PARK_MASK   (0x2U)
#define	CAAM_JRCR_JR_PARK_SHIFT   (1U)
#define	CAAM_JRCR_JR_PARK(x)
JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register
#define	CAAM_JRAAV_V0_MASK   (0x1U)
#define	CAAM_JRAAV_V0_SHIFT   (0U)
#define	CAAM_JRAAV_V0(x)
#define	CAAM_JRAAV_V1_MASK   (0x2U)
#define	CAAM_JRAAV_V1_SHIFT   (1U)
#define	CAAM_JRAAV_V1(x)
#define	CAAM_JRAAV_V2_MASK   (0x4U)
#define	CAAM_JRAAV_V2_SHIFT   (2U)
#define	CAAM_JRAAV_V2(x)
#define	CAAM_JRAAV_V3_MASK   (0x8U)
#define	CAAM_JRAAV_V3_SHIFT   (3U)
#define	CAAM_JRAAV_V3(x)
#define	CAAM_JRAAV_BC_MASK   (0x80000000U)
#define	CAAM_JRAAV_BC_SHIFT   (31U)
#define	CAAM_JRAAV_BC(x)
JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register
#define	CAAM_JRAAA_JD_ADDR_MASK   (0xFFFFFFFFFU)
#define	CAAM_JRAAA_JD_ADDR_SHIFT   (0U)
#define	CAAM_JRAAA_JD_ADDR(x)
PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register
#define	CAAM_PX_SDID_JR_SDID_MASK   (0xFFFFU)
#define	CAAM_PX_SDID_JR_SDID_SHIFT   (0U)
#define	CAAM_PX_SDID_JR_SDID(x)
PX_SMAPR_JR - Secure Memory Access Permissions register
#define	CAAM_PX_SMAPR_JR_G1_READ_MASK   (0x1U)
#define	CAAM_PX_SMAPR_JR_G1_READ_SHIFT   (0U)
#define	CAAM_PX_SMAPR_JR_G1_READ(x)
#define	CAAM_PX_SMAPR_JR_G1_WRITE_MASK   (0x2U)
#define	CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT   (1U)
#define	CAAM_PX_SMAPR_JR_G1_WRITE(x)
#define	CAAM_PX_SMAPR_JR_G1_TDO_MASK   (0x4U)
#define	CAAM_PX_SMAPR_JR_G1_TDO_SHIFT   (2U)
#define	CAAM_PX_SMAPR_JR_G1_TDO(x)
#define	CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK   (0x8U)
#define	CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT   (3U)
#define	CAAM_PX_SMAPR_JR_G1_SMBLOB(x)
#define	CAAM_PX_SMAPR_JR_G2_READ_MASK   (0x10U)
#define	CAAM_PX_SMAPR_JR_G2_READ_SHIFT   (4U)
#define	CAAM_PX_SMAPR_JR_G2_READ(x)
#define	CAAM_PX_SMAPR_JR_G2_WRITE_MASK   (0x20U)
#define	CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT   (5U)
#define	CAAM_PX_SMAPR_JR_G2_WRITE(x)
#define	CAAM_PX_SMAPR_JR_G2_TDO_MASK   (0x40U)
#define	CAAM_PX_SMAPR_JR_G2_TDO_SHIFT   (6U)
#define	CAAM_PX_SMAPR_JR_G2_TDO(x)
#define	CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK   (0x80U)
#define	CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT   (7U)
#define	CAAM_PX_SMAPR_JR_G2_SMBLOB(x)
#define	CAAM_PX_SMAPR_JR_SMAG_LCK_MASK   (0x1000U)
#define	CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT   (12U)
#define	CAAM_PX_SMAPR_JR_SMAG_LCK(x)
#define	CAAM_PX_SMAPR_JR_SMAP_LCK_MASK   (0x2000U)
#define	CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT   (13U)
#define	CAAM_PX_SMAPR_JR_SMAP_LCK(x)
#define	CAAM_PX_SMAPR_JR_PSP_MASK   (0x4000U)
#define	CAAM_PX_SMAPR_JR_PSP_SHIFT   (14U)
#define	CAAM_PX_SMAPR_JR_PSP(x)
#define	CAAM_PX_SMAPR_JR_CSP_MASK   (0x8000U)
#define	CAAM_PX_SMAPR_JR_CSP_SHIFT   (15U)
#define	CAAM_PX_SMAPR_JR_CSP(x)
#define	CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK   (0xFFFF0000U)
#define	CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT   (16U)
#define	CAAM_PX_SMAPR_JR_PARTITION_KMOD(x)
PX_SMAG2_JR - Secure Memory Access Group Registers
#define	CAAM_PX_SMAG2_JR_Gx_ID00_MASK   (0x1U)
#define	CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT   (0U)
#define	CAAM_PX_SMAG2_JR_Gx_ID00(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID01_MASK   (0x2U)
#define	CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT   (1U)
#define	CAAM_PX_SMAG2_JR_Gx_ID01(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID02_MASK   (0x4U)
#define	CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT   (2U)
#define	CAAM_PX_SMAG2_JR_Gx_ID02(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID03_MASK   (0x8U)
#define	CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT   (3U)
#define	CAAM_PX_SMAG2_JR_Gx_ID03(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID04_MASK   (0x10U)
#define	CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT   (4U)
#define	CAAM_PX_SMAG2_JR_Gx_ID04(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID05_MASK   (0x20U)
#define	CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT   (5U)
#define	CAAM_PX_SMAG2_JR_Gx_ID05(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID06_MASK   (0x40U)
#define	CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT   (6U)
#define	CAAM_PX_SMAG2_JR_Gx_ID06(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID07_MASK   (0x80U)
#define	CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT   (7U)
#define	CAAM_PX_SMAG2_JR_Gx_ID07(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID08_MASK   (0x100U)
#define	CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT   (8U)
#define	CAAM_PX_SMAG2_JR_Gx_ID08(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID09_MASK   (0x200U)
#define	CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT   (9U)
#define	CAAM_PX_SMAG2_JR_Gx_ID09(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID10_MASK   (0x400U)
#define	CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT   (10U)
#define	CAAM_PX_SMAG2_JR_Gx_ID10(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID11_MASK   (0x800U)
#define	CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT   (11U)
#define	CAAM_PX_SMAG2_JR_Gx_ID11(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID12_MASK   (0x1000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT   (12U)
#define	CAAM_PX_SMAG2_JR_Gx_ID12(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID13_MASK   (0x2000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT   (13U)
#define	CAAM_PX_SMAG2_JR_Gx_ID13(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID14_MASK   (0x4000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT   (14U)
#define	CAAM_PX_SMAG2_JR_Gx_ID14(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID15_MASK   (0x8000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT   (15U)
#define	CAAM_PX_SMAG2_JR_Gx_ID15(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID16_MASK   (0x10000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT   (16U)
#define	CAAM_PX_SMAG2_JR_Gx_ID16(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID17_MASK   (0x20000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT   (17U)
#define	CAAM_PX_SMAG2_JR_Gx_ID17(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID18_MASK   (0x40000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT   (18U)
#define	CAAM_PX_SMAG2_JR_Gx_ID18(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID19_MASK   (0x80000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT   (19U)
#define	CAAM_PX_SMAG2_JR_Gx_ID19(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID20_MASK   (0x100000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT   (20U)
#define	CAAM_PX_SMAG2_JR_Gx_ID20(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID21_MASK   (0x200000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT   (21U)
#define	CAAM_PX_SMAG2_JR_Gx_ID21(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID22_MASK   (0x400000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT   (22U)
#define	CAAM_PX_SMAG2_JR_Gx_ID22(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID23_MASK   (0x800000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT   (23U)
#define	CAAM_PX_SMAG2_JR_Gx_ID23(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID24_MASK   (0x1000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT   (24U)
#define	CAAM_PX_SMAG2_JR_Gx_ID24(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID25_MASK   (0x2000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT   (25U)
#define	CAAM_PX_SMAG2_JR_Gx_ID25(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID26_MASK   (0x4000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT   (26U)
#define	CAAM_PX_SMAG2_JR_Gx_ID26(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID27_MASK   (0x8000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT   (27U)
#define	CAAM_PX_SMAG2_JR_Gx_ID27(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID28_MASK   (0x10000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT   (28U)
#define	CAAM_PX_SMAG2_JR_Gx_ID28(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID29_MASK   (0x20000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT   (29U)
#define	CAAM_PX_SMAG2_JR_Gx_ID29(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID30_MASK   (0x40000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT   (30U)
#define	CAAM_PX_SMAG2_JR_Gx_ID30(x)
#define	CAAM_PX_SMAG2_JR_Gx_ID31_MASK   (0x80000000U)
#define	CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT   (31U)
#define	CAAM_PX_SMAG2_JR_Gx_ID31(x)
PX_SMAG1_JR - Secure Memory Access Group Registers
#define	CAAM_PX_SMAG1_JR_Gx_ID00_MASK   (0x1U)
#define	CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT   (0U)
#define	CAAM_PX_SMAG1_JR_Gx_ID00(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID01_MASK   (0x2U)
#define	CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT   (1U)
#define	CAAM_PX_SMAG1_JR_Gx_ID01(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID02_MASK   (0x4U)
#define	CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT   (2U)
#define	CAAM_PX_SMAG1_JR_Gx_ID02(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID03_MASK   (0x8U)
#define	CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT   (3U)
#define	CAAM_PX_SMAG1_JR_Gx_ID03(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID04_MASK   (0x10U)
#define	CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT   (4U)
#define	CAAM_PX_SMAG1_JR_Gx_ID04(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID05_MASK   (0x20U)
#define	CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT   (5U)
#define	CAAM_PX_SMAG1_JR_Gx_ID05(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID06_MASK   (0x40U)
#define	CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT   (6U)
#define	CAAM_PX_SMAG1_JR_Gx_ID06(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID07_MASK   (0x80U)
#define	CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT   (7U)
#define	CAAM_PX_SMAG1_JR_Gx_ID07(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID08_MASK   (0x100U)
#define	CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT   (8U)
#define	CAAM_PX_SMAG1_JR_Gx_ID08(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID09_MASK   (0x200U)
#define	CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT   (9U)
#define	CAAM_PX_SMAG1_JR_Gx_ID09(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID10_MASK   (0x400U)
#define	CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT   (10U)
#define	CAAM_PX_SMAG1_JR_Gx_ID10(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID11_MASK   (0x800U)
#define	CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT   (11U)
#define	CAAM_PX_SMAG1_JR_Gx_ID11(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID12_MASK   (0x1000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT   (12U)
#define	CAAM_PX_SMAG1_JR_Gx_ID12(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID13_MASK   (0x2000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT   (13U)
#define	CAAM_PX_SMAG1_JR_Gx_ID13(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID14_MASK   (0x4000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT   (14U)
#define	CAAM_PX_SMAG1_JR_Gx_ID14(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID15_MASK   (0x8000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT   (15U)
#define	CAAM_PX_SMAG1_JR_Gx_ID15(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID16_MASK   (0x10000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT   (16U)
#define	CAAM_PX_SMAG1_JR_Gx_ID16(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID17_MASK   (0x20000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT   (17U)
#define	CAAM_PX_SMAG1_JR_Gx_ID17(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID18_MASK   (0x40000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT   (18U)
#define	CAAM_PX_SMAG1_JR_Gx_ID18(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID19_MASK   (0x80000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT   (19U)
#define	CAAM_PX_SMAG1_JR_Gx_ID19(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID20_MASK   (0x100000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT   (20U)
#define	CAAM_PX_SMAG1_JR_Gx_ID20(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID21_MASK   (0x200000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT   (21U)
#define	CAAM_PX_SMAG1_JR_Gx_ID21(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID22_MASK   (0x400000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT   (22U)
#define	CAAM_PX_SMAG1_JR_Gx_ID22(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID23_MASK   (0x800000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT   (23U)
#define	CAAM_PX_SMAG1_JR_Gx_ID23(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID24_MASK   (0x1000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT   (24U)
#define	CAAM_PX_SMAG1_JR_Gx_ID24(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID25_MASK   (0x2000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT   (25U)
#define	CAAM_PX_SMAG1_JR_Gx_ID25(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID26_MASK   (0x4000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT   (26U)
#define	CAAM_PX_SMAG1_JR_Gx_ID26(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID27_MASK   (0x8000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT   (27U)
#define	CAAM_PX_SMAG1_JR_Gx_ID27(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID28_MASK   (0x10000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT   (28U)
#define	CAAM_PX_SMAG1_JR_Gx_ID28(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID29_MASK   (0x20000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT   (29U)
#define	CAAM_PX_SMAG1_JR_Gx_ID29(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID30_MASK   (0x40000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT   (30U)
#define	CAAM_PX_SMAG1_JR_Gx_ID30(x)
#define	CAAM_PX_SMAG1_JR_Gx_ID31_MASK   (0x80000000U)
#define	CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT   (31U)
#define	CAAM_PX_SMAG1_JR_Gx_ID31(x)
SMCR_JR - Secure Memory Command Register
#define	CAAM_SMCR_JR_CMD_MASK   (0xFU)
#define	CAAM_SMCR_JR_CMD_SHIFT   (0U)
#define	CAAM_SMCR_JR_CMD(x)
#define	CAAM_SMCR_JR_PRTN_MASK   (0xF00U)
#define	CAAM_SMCR_JR_PRTN_SHIFT   (8U)
#define	CAAM_SMCR_JR_PRTN(x)
#define	CAAM_SMCR_JR_PAGE_MASK   (0xFFFF0000U)
#define	CAAM_SMCR_JR_PAGE_SHIFT   (16U)
#define	CAAM_SMCR_JR_PAGE(x)
SMCSR_JR - Secure Memory Command Status Register
#define	CAAM_SMCSR_JR_PRTN_MASK   (0xFU)
#define	CAAM_SMCSR_JR_PRTN_SHIFT   (0U)
#define	CAAM_SMCSR_JR_PRTN(x)
#define	CAAM_SMCSR_JR_PO_MASK   (0xC0U)
#define	CAAM_SMCSR_JR_PO_SHIFT   (6U)
#define	CAAM_SMCSR_JR_PO(x)
#define	CAAM_SMCSR_JR_AERR_MASK   (0x3000U)
#define	CAAM_SMCSR_JR_AERR_SHIFT   (12U)
#define	CAAM_SMCSR_JR_AERR(x)
#define	CAAM_SMCSR_JR_CERR_MASK   (0xC000U)
#define	CAAM_SMCSR_JR_CERR_SHIFT   (14U)
#define	CAAM_SMCSR_JR_CERR(x)
#define	CAAM_SMCSR_JR_PAGE_MASK   (0xFFF0000U)
#define	CAAM_SMCSR_JR_PAGE_SHIFT   (16U)
#define	CAAM_SMCSR_JR_PAGE(x)
REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3
#define	CAAM_REIR0JR_TYPE_MASK   (0x3000000U)
#define	CAAM_REIR0JR_TYPE_SHIFT   (24U)
#define	CAAM_REIR0JR_TYPE(x)
#define	CAAM_REIR0JR_MISS_MASK   (0x80000000U)
#define	CAAM_REIR0JR_MISS_SHIFT   (31U)
#define	CAAM_REIR0JR_MISS(x)
REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3
#define	CAAM_REIR2JR_ADDR_MASK   (0xFFFFFFFFFU)
#define	CAAM_REIR2JR_ADDR_SHIFT   (0U)
#define	CAAM_REIR2JR_ADDR(x)
REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3
#define	CAAM_REIR4JR_ICID_MASK   (0x7FFU)
#define	CAAM_REIR4JR_ICID_SHIFT   (0U)
#define	CAAM_REIR4JR_ICID(x)
#define	CAAM_REIR4JR_DID_MASK   (0x7800U)
#define	CAAM_REIR4JR_DID_SHIFT   (11U)
#define	CAAM_REIR4JR_DID(x)
#define	CAAM_REIR4JR_AXCACHE_MASK   (0xF0000U)
#define	CAAM_REIR4JR_AXCACHE_SHIFT   (16U)
#define	CAAM_REIR4JR_AXCACHE(x)
#define	CAAM_REIR4JR_AXPROT_MASK   (0x700000U)
#define	CAAM_REIR4JR_AXPROT_SHIFT   (20U)
#define	CAAM_REIR4JR_AXPROT(x)
#define	CAAM_REIR4JR_RWB_MASK   (0x800000U)
#define	CAAM_REIR4JR_RWB_SHIFT   (23U)
#define	CAAM_REIR4JR_RWB(x)
#define	CAAM_REIR4JR_ERR_MASK   (0x30000000U)
#define	CAAM_REIR4JR_ERR_SHIFT   (28U)
#define	CAAM_REIR4JR_ERR(x)
#define	CAAM_REIR4JR_MIX_MASK   (0xC0000000U)
#define	CAAM_REIR4JR_MIX_SHIFT   (30U)
#define	CAAM_REIR4JR_MIX(x)
REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3
#define	CAAM_REIR5JR_BID_MASK   (0xF0000U)
#define	CAAM_REIR5JR_BID_SHIFT   (16U)
#define	CAAM_REIR5JR_BID(x)
#define	CAAM_REIR5JR_BNDG_MASK   (0x2000000U)
#define	CAAM_REIR5JR_BNDG_SHIFT   (25U)
#define	CAAM_REIR5JR_BNDG(x)
#define	CAAM_REIR5JR_TDSC_MASK   (0x4000000U)
#define	CAAM_REIR5JR_TDSC_SHIFT   (26U)
#define	CAAM_REIR5JR_TDSC(x)
#define	CAAM_REIR5JR_KMOD_MASK   (0x8000000U)
#define	CAAM_REIR5JR_KMOD_SHIFT   (27U)
#define	CAAM_REIR5JR_KMOD(x)
#define	CAAM_REIR5JR_KEY_MASK   (0x10000000U)
#define	CAAM_REIR5JR_KEY_SHIFT   (28U)
#define	CAAM_REIR5JR_KEY(x)
#define	CAAM_REIR5JR_SMA_MASK   (0x20000000U)
#define	CAAM_REIR5JR_SMA_SHIFT   (29U)
#define	CAAM_REIR5JR_SMA(x)
RSTA - RTIC Status Register
#define	CAAM_RSTA_BSY_MASK   (0x1U)
#define	CAAM_RSTA_BSY_SHIFT   (0U)
#define	CAAM_RSTA_BSY(x)
#define	CAAM_RSTA_HD_MASK   (0x2U)
#define	CAAM_RSTA_HD_SHIFT   (1U)
#define	CAAM_RSTA_HD(x)
#define	CAAM_RSTA_SV_MASK   (0x4U)
#define	CAAM_RSTA_SV_SHIFT   (2U)
#define	CAAM_RSTA_SV(x)
#define	CAAM_RSTA_HE_MASK   (0x8U)
#define	CAAM_RSTA_HE_SHIFT   (3U)
#define	CAAM_RSTA_HE(x)
#define	CAAM_RSTA_MIS_MASK   (0xF0U)
#define	CAAM_RSTA_MIS_SHIFT   (4U)
#define	CAAM_RSTA_MIS(x)
#define	CAAM_RSTA_AE_MASK   (0xF00U)
#define	CAAM_RSTA_AE_SHIFT   (8U)
#define	CAAM_RSTA_AE(x)
#define	CAAM_RSTA_WE_MASK   (0x10000U)
#define	CAAM_RSTA_WE_SHIFT   (16U)
#define	CAAM_RSTA_WE(x)
#define	CAAM_RSTA_ABH_MASK   (0x20000U)
#define	CAAM_RSTA_ABH_SHIFT   (17U)
#define	CAAM_RSTA_ABH(x)
#define	CAAM_RSTA_HOD_MASK   (0x40000U)
#define	CAAM_RSTA_HOD_SHIFT   (18U)
#define	CAAM_RSTA_HOD(x)
#define	CAAM_RSTA_RTD_MASK   (0x80000U)
#define	CAAM_RSTA_RTD_SHIFT   (19U)
#define	CAAM_RSTA_RTD(x)
#define	CAAM_RSTA_CS_MASK   (0x6000000U)
#define	CAAM_RSTA_CS_SHIFT   (25U)
#define	CAAM_RSTA_CS(x)
RCMD - RTIC Command Register
#define	CAAM_RCMD_CINT_MASK   (0x1U)
#define	CAAM_RCMD_CINT_SHIFT   (0U)
#define	CAAM_RCMD_CINT(x)
#define	CAAM_RCMD_HO_MASK   (0x2U)
#define	CAAM_RCMD_HO_SHIFT   (1U)
#define	CAAM_RCMD_HO(x)
#define	CAAM_RCMD_RTC_MASK   (0x4U)
#define	CAAM_RCMD_RTC_SHIFT   (2U)
#define	CAAM_RCMD_RTC(x)
#define	CAAM_RCMD_RTD_MASK   (0x8U)
#define	CAAM_RCMD_RTD_SHIFT   (3U)
#define	CAAM_RCMD_RTD(x)
RCTL - RTIC Control Register
#define	CAAM_RCTL_IE_MASK   (0x1U)
#define	CAAM_RCTL_IE_SHIFT   (0U)
#define	CAAM_RCTL_IE(x)
#define	CAAM_RCTL_RREQS_MASK   (0xEU)
#define	CAAM_RCTL_RREQS_SHIFT   (1U)
#define	CAAM_RCTL_RREQS(x)
#define	CAAM_RCTL_HOME_MASK   (0xF0U)
#define	CAAM_RCTL_HOME_SHIFT   (4U)
#define	CAAM_RCTL_HOME(x)
#define	CAAM_RCTL_RTME_MASK   (0xF00U)
#define	CAAM_RCTL_RTME_SHIFT   (8U)
#define	CAAM_RCTL_RTME(x)
#define	CAAM_RCTL_RTMU_MASK   (0xF000U)
#define	CAAM_RCTL_RTMU_SHIFT   (12U)
#define	CAAM_RCTL_RTMU(x)
#define	CAAM_RCTL_RALG_MASK   (0xF0000U)
#define	CAAM_RCTL_RALG_SHIFT   (16U)
#define	CAAM_RCTL_RALG(x)
#define	CAAM_RCTL_RIDLE_MASK   (0x100000U)
#define	CAAM_RCTL_RIDLE_SHIFT   (20U)
#define	CAAM_RCTL_RIDLE(x)
RTHR - RTIC Throttle Register
#define	CAAM_RTHR_RTHR_MASK   (0xFFFFU)
#define	CAAM_RTHR_RTHR_SHIFT   (0U)
#define	CAAM_RTHR_RTHR(x)
RWDOG - RTIC Watchdog Timer
#define	CAAM_RWDOG_RWDOG_MASK   (0xFFFFFFFFU)
#define	CAAM_RWDOG_RWDOG_SHIFT   (0U)
#define	CAAM_RWDOG_RWDOG(x)
REND - RTIC Endian Register
#define	CAAM_REND_REPO_MASK   (0xFU)
#define	CAAM_REND_REPO_SHIFT   (0U)
#define	CAAM_REND_REPO(x)
#define	CAAM_REND_RBS_MASK   (0xF0U)
#define	CAAM_REND_RBS_SHIFT   (4U)
#define	CAAM_REND_RBS(x)
#define	CAAM_REND_RHWS_MASK   (0xF00U)
#define	CAAM_REND_RHWS_SHIFT   (8U)
#define	CAAM_REND_RHWS(x)
#define	CAAM_REND_RWS_MASK   (0xF000U)
#define	CAAM_REND_RWS_SHIFT   (12U)
#define	CAAM_REND_RWS(x)
RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register
#define	CAAM_RMA_MEMBLKADDR_MASK   (0xFFFFFFFFFU)
#define	CAAM_RMA_MEMBLKADDR_SHIFT   (0U)
#define	CAAM_RMA_MEMBLKADDR(x)
RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register
#define	CAAM_RML_MEMBLKLEN_MASK   (0xFFFFFFFFU)
#define	CAAM_RML_MEMBLKLEN_SHIFT   (0U)
#define	CAAM_RML_MEMBLKLEN(x)
RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31
#define	CAAM_RMD_RTIC_Hash_Result_MASK   (0xFFFFFFFFU)
#define	CAAM_RMD_RTIC_Hash_Result_SHIFT   (0U)
#define	CAAM_RMD_RTIC_Hash_Result(x)
REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC
#define	CAAM_REIR0RTIC_TYPE_MASK   (0x3000000U)
#define	CAAM_REIR0RTIC_TYPE_SHIFT   (24U)
#define	CAAM_REIR0RTIC_TYPE(x)
#define	CAAM_REIR0RTIC_MISS_MASK   (0x80000000U)
#define	CAAM_REIR0RTIC_MISS_SHIFT   (31U)
#define	CAAM_REIR0RTIC_MISS(x)
REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC
#define	CAAM_REIR2RTIC_ADDR_MASK   (0xFFFFFFFFFFFFFFFFU)
#define	CAAM_REIR2RTIC_ADDR_SHIFT   (0U)
#define	CAAM_REIR2RTIC_ADDR(x)
REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC
#define	CAAM_REIR4RTIC_ICID_MASK   (0x7FFU)
#define	CAAM_REIR4RTIC_ICID_SHIFT   (0U)
#define	CAAM_REIR4RTIC_ICID(x)
#define	CAAM_REIR4RTIC_DID_MASK   (0x7800U)
#define	CAAM_REIR4RTIC_DID_SHIFT   (11U)
#define	CAAM_REIR4RTIC_DID(x)
#define	CAAM_REIR4RTIC_AXCACHE_MASK   (0xF0000U)
#define	CAAM_REIR4RTIC_AXCACHE_SHIFT   (16U)
#define	CAAM_REIR4RTIC_AXCACHE(x)
#define	CAAM_REIR4RTIC_AXPROT_MASK   (0x700000U)
#define	CAAM_REIR4RTIC_AXPROT_SHIFT   (20U)
#define	CAAM_REIR4RTIC_AXPROT(x)
#define	CAAM_REIR4RTIC_RWB_MASK   (0x800000U)
#define	CAAM_REIR4RTIC_RWB_SHIFT   (23U)
#define	CAAM_REIR4RTIC_RWB(x)
#define	CAAM_REIR4RTIC_ERR_MASK   (0x30000000U)
#define	CAAM_REIR4RTIC_ERR_SHIFT   (28U)
#define	CAAM_REIR4RTIC_ERR(x)
#define	CAAM_REIR4RTIC_MIX_MASK   (0xC0000000U)
#define	CAAM_REIR4RTIC_MIX_SHIFT   (30U)
#define	CAAM_REIR4RTIC_MIX(x)
REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC
#define	CAAM_REIR5RTIC_BID_MASK   (0xF0000U)
#define	CAAM_REIR5RTIC_BID_SHIFT   (16U)
#define	CAAM_REIR5RTIC_BID(x)
#define	CAAM_REIR5RTIC_SAFE_MASK   (0x1000000U)
#define	CAAM_REIR5RTIC_SAFE_SHIFT   (24U)
#define	CAAM_REIR5RTIC_SAFE(x)
#define	CAAM_REIR5RTIC_SMA_MASK   (0x2000000U)
#define	CAAM_REIR5RTIC_SMA_SHIFT   (25U)
#define	CAAM_REIR5RTIC_SMA(x)
CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms
#define	CAAM_CC1MR_ENC_MASK   (0x1U)
#define	CAAM_CC1MR_ENC_SHIFT   (0U)
#define	CAAM_CC1MR_ENC(x)
#define	CAAM_CC1MR_ICV_TEST_MASK   (0x2U)
#define	CAAM_CC1MR_ICV_TEST_SHIFT   (1U)
#define	CAAM_CC1MR_ICV_TEST(x)
#define	CAAM_CC1MR_AS_MASK   (0xCU)
#define	CAAM_CC1MR_AS_SHIFT   (2U)
#define	CAAM_CC1MR_AS(x)
#define	CAAM_CC1MR_AAI_MASK   (0x1FF0U)
#define	CAAM_CC1MR_AAI_SHIFT   (4U)
#define	CAAM_CC1MR_AAI(x)
#define	CAAM_CC1MR_ALG_MASK   (0xFF0000U)
#define	CAAM_CC1MR_ALG_SHIFT   (16U)
#define	CAAM_CC1MR_ALG(x)
CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms
#define	CAAM_CC1MR_PK_PKHA_MODE_LS_MASK   (0xFFFU)
#define	CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT   (0U)
#define	CAAM_CC1MR_PK_PKHA_MODE_LS(x)
#define	CAAM_CC1MR_PK_PKHA_MODE_MS_MASK   (0xF0000U)
#define	CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT   (16U)
#define	CAAM_CC1MR_PK_PKHA_MODE_MS(x)
CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4
#define	CAAM_CC1MR_RNG_TST_MASK   (0x1U)
#define	CAAM_CC1MR_RNG_TST_SHIFT   (0U)
#define	CAAM_CC1MR_RNG_TST(x)
#define	CAAM_CC1MR_RNG_PR_MASK   (0x2U)
#define	CAAM_CC1MR_RNG_PR_SHIFT   (1U)
#define	CAAM_CC1MR_RNG_PR(x)
#define	CAAM_CC1MR_RNG_AS_MASK   (0xCU)
#define	CAAM_CC1MR_RNG_AS_SHIFT   (2U)
#define	CAAM_CC1MR_RNG_AS(x)
#define	CAAM_CC1MR_RNG_SH_MASK   (0x30U)
#define	CAAM_CC1MR_RNG_SH_SHIFT   (4U)
#define	CAAM_CC1MR_RNG_SH(x)
#define	CAAM_CC1MR_RNG_NZB_MASK   (0x100U)
#define	CAAM_CC1MR_RNG_NZB_SHIFT   (8U)
#define	CAAM_CC1MR_RNG_NZB(x)
#define	CAAM_CC1MR_RNG_OBP_MASK   (0x200U)
#define	CAAM_CC1MR_RNG_OBP_SHIFT   (9U)
#define	CAAM_CC1MR_RNG_OBP(x)
#define	CAAM_CC1MR_RNG_PS_MASK   (0x400U)
#define	CAAM_CC1MR_RNG_PS_SHIFT   (10U)
#define	CAAM_CC1MR_RNG_PS(x)
#define	CAAM_CC1MR_RNG_AI_MASK   (0x800U)
#define	CAAM_CC1MR_RNG_AI_SHIFT   (11U)
#define	CAAM_CC1MR_RNG_AI(x)
#define	CAAM_CC1MR_RNG_SK_MASK   (0x1000U)
#define	CAAM_CC1MR_RNG_SK_SHIFT   (12U)
#define	CAAM_CC1MR_RNG_SK(x)
#define	CAAM_CC1MR_RNG_ALG_MASK   (0xFF0000U)
#define	CAAM_CC1MR_RNG_ALG_SHIFT   (16U)
#define	CAAM_CC1MR_RNG_ALG(x)
CC1KSR - CCB 0 Class 1 Key Size Register
#define	CAAM_CC1KSR_C1KS_MASK   (0x7FU)
#define	CAAM_CC1KSR_C1KS_SHIFT   (0U)
#define	CAAM_CC1KSR_C1KS(x)
CC1DSR - CCB 0 Class 1 Data Size Register
#define	CAAM_CC1DSR_C1DS_MASK   (0xFFFFFFFFU)
#define	CAAM_CC1DSR_C1DS_SHIFT   (0U)
#define	CAAM_CC1DSR_C1DS(x)
#define	CAAM_CC1DSR_C1CY_MASK   (0x100000000U)
#define	CAAM_CC1DSR_C1CY_SHIFT   (32U)
#define	CAAM_CC1DSR_C1CY(x)
#define	CAAM_CC1DSR_NUMBITS_MASK   (0xE000000000000000U)
#define	CAAM_CC1DSR_NUMBITS_SHIFT   (61U)
#define	CAAM_CC1DSR_NUMBITS(x)
CC1ICVSR - CCB 0 Class 1 ICV Size Register
#define	CAAM_CC1ICVSR_C1ICVS_MASK   (0x1FU)
#define	CAAM_CC1ICVSR_C1ICVS_SHIFT   (0U)
#define	CAAM_CC1ICVSR_C1ICVS(x)
CCCTRL - CCB 0 CHA Control Register
#define	CAAM_CCCTRL_CCB_MASK   (0x1U)
#define	CAAM_CCCTRL_CCB_SHIFT   (0U)
#define	CAAM_CCCTRL_CCB(x)
#define	CAAM_CCCTRL_AES_MASK   (0x2U)
#define	CAAM_CCCTRL_AES_SHIFT   (1U)
#define	CAAM_CCCTRL_AES(x)
#define	CAAM_CCCTRL_DES_MASK   (0x4U)
#define	CAAM_CCCTRL_DES_SHIFT   (2U)
#define	CAAM_CCCTRL_DES(x)
#define	CAAM_CCCTRL_PK_MASK   (0x40U)
#define	CAAM_CCCTRL_PK_SHIFT   (6U)
#define	CAAM_CCCTRL_PK(x)
#define	CAAM_CCCTRL_MD_MASK   (0x80U)
#define	CAAM_CCCTRL_MD_SHIFT   (7U)
#define	CAAM_CCCTRL_MD(x)
#define	CAAM_CCCTRL_CRC_MASK   (0x100U)
#define	CAAM_CCCTRL_CRC_SHIFT   (8U)
#define	CAAM_CCCTRL_CRC(x)
#define	CAAM_CCCTRL_RNG_MASK   (0x200U)
#define	CAAM_CCCTRL_RNG_SHIFT   (9U)
#define	CAAM_CCCTRL_RNG(x)
#define	CAAM_CCCTRL_UA0_MASK   (0x10000U)
#define	CAAM_CCCTRL_UA0_SHIFT   (16U)
#define	CAAM_CCCTRL_UA0(x)
#define	CAAM_CCCTRL_UA1_MASK   (0x20000U)
#define	CAAM_CCCTRL_UA1_SHIFT   (17U)
#define	CAAM_CCCTRL_UA1(x)
#define	CAAM_CCCTRL_UA2_MASK   (0x40000U)
#define	CAAM_CCCTRL_UA2_SHIFT   (18U)
#define	CAAM_CCCTRL_UA2(x)
#define	CAAM_CCCTRL_UA3_MASK   (0x80000U)
#define	CAAM_CCCTRL_UA3_SHIFT   (19U)
#define	CAAM_CCCTRL_UA3(x)
#define	CAAM_CCCTRL_UB0_MASK   (0x100000U)
#define	CAAM_CCCTRL_UB0_SHIFT   (20U)
#define	CAAM_CCCTRL_UB0(x)
#define	CAAM_CCCTRL_UB1_MASK   (0x200000U)
#define	CAAM_CCCTRL_UB1_SHIFT   (21U)
#define	CAAM_CCCTRL_UB1(x)
#define	CAAM_CCCTRL_UB2_MASK   (0x400000U)
#define	CAAM_CCCTRL_UB2_SHIFT   (22U)
#define	CAAM_CCCTRL_UB2(x)
#define	CAAM_CCCTRL_UB3_MASK   (0x800000U)
#define	CAAM_CCCTRL_UB3_SHIFT   (23U)
#define	CAAM_CCCTRL_UB3(x)
#define	CAAM_CCCTRL_UN_MASK   (0x1000000U)
#define	CAAM_CCCTRL_UN_SHIFT   (24U)
#define	CAAM_CCCTRL_UN(x)
#define	CAAM_CCCTRL_UA_MASK   (0x4000000U)
#define	CAAM_CCCTRL_UA_SHIFT   (26U)
#define	CAAM_CCCTRL_UA(x)
#define	CAAM_CCCTRL_UB_MASK   (0x8000000U)
#define	CAAM_CCCTRL_UB_SHIFT   (27U)
#define	CAAM_CCCTRL_UB(x)
CICTL - CCB 0 Interrupt Control Register
#define	CAAM_CICTL_ADI_MASK   (0x2U)
#define	CAAM_CICTL_ADI_SHIFT   (1U)
#define	CAAM_CICTL_ADI(x)
#define	CAAM_CICTL_DDI_MASK   (0x4U)
#define	CAAM_CICTL_DDI_SHIFT   (2U)
#define	CAAM_CICTL_DDI(x)
#define	CAAM_CICTL_PDI_MASK   (0x40U)
#define	CAAM_CICTL_PDI_SHIFT   (6U)
#define	CAAM_CICTL_PDI(x)
#define	CAAM_CICTL_MDI_MASK   (0x80U)
#define	CAAM_CICTL_MDI_SHIFT   (7U)
#define	CAAM_CICTL_MDI(x)
#define	CAAM_CICTL_CDI_MASK   (0x100U)
#define	CAAM_CICTL_CDI_SHIFT   (8U)
#define	CAAM_CICTL_CDI(x)
#define	CAAM_CICTL_RNDI_MASK   (0x200U)
#define	CAAM_CICTL_RNDI_SHIFT   (9U)
#define	CAAM_CICTL_RNDI(x)
#define	CAAM_CICTL_AEI_MASK   (0x20000U)
#define	CAAM_CICTL_AEI_SHIFT   (17U)
#define	CAAM_CICTL_AEI(x)
#define	CAAM_CICTL_DEI_MASK   (0x40000U)
#define	CAAM_CICTL_DEI_SHIFT   (18U)
#define	CAAM_CICTL_DEI(x)
#define	CAAM_CICTL_PEI_MASK   (0x400000U)
#define	CAAM_CICTL_PEI_SHIFT   (22U)
#define	CAAM_CICTL_PEI(x)
#define	CAAM_CICTL_MEI_MASK   (0x800000U)
#define	CAAM_CICTL_MEI_SHIFT   (23U)
#define	CAAM_CICTL_MEI(x)
#define	CAAM_CICTL_CEI_MASK   (0x1000000U)
#define	CAAM_CICTL_CEI_SHIFT   (24U)
#define	CAAM_CICTL_CEI(x)
#define	CAAM_CICTL_RNEI_MASK   (0x2000000U)
#define	CAAM_CICTL_RNEI_SHIFT   (25U)
#define	CAAM_CICTL_RNEI(x)
CCWR - CCB 0 Clear Written Register
#define	CAAM_CCWR_C1M_MASK   (0x1U)
#define	CAAM_CCWR_C1M_SHIFT   (0U)
#define	CAAM_CCWR_C1M(x)
#define	CAAM_CCWR_C1DS_MASK   (0x4U)
#define	CAAM_CCWR_C1DS_SHIFT   (2U)
#define	CAAM_CCWR_C1DS(x)
#define	CAAM_CCWR_C1ICV_MASK   (0x8U)
#define	CAAM_CCWR_C1ICV_SHIFT   (3U)
#define	CAAM_CCWR_C1ICV(x)
#define	CAAM_CCWR_C1C_MASK   (0x20U)
#define	CAAM_CCWR_C1C_SHIFT   (5U)
#define	CAAM_CCWR_C1C(x)
#define	CAAM_CCWR_C1K_MASK   (0x40U)
#define	CAAM_CCWR_C1K_SHIFT   (6U)
#define	CAAM_CCWR_C1K(x)
#define	CAAM_CCWR_CPKA_MASK   (0x1000U)
#define	CAAM_CCWR_CPKA_SHIFT   (12U)
#define	CAAM_CCWR_CPKA(x)
#define	CAAM_CCWR_CPKB_MASK   (0x2000U)
#define	CAAM_CCWR_CPKB_SHIFT   (13U)
#define	CAAM_CCWR_CPKB(x)
#define	CAAM_CCWR_CPKN_MASK   (0x4000U)
#define	CAAM_CCWR_CPKN_SHIFT   (14U)
#define	CAAM_CCWR_CPKN(x)
#define	CAAM_CCWR_CPKE_MASK   (0x8000U)
#define	CAAM_CCWR_CPKE_SHIFT   (15U)
#define	CAAM_CCWR_CPKE(x)
#define	CAAM_CCWR_C2M_MASK   (0x10000U)
#define	CAAM_CCWR_C2M_SHIFT   (16U)
#define	CAAM_CCWR_C2M(x)
#define	CAAM_CCWR_C2DS_MASK   (0x40000U)
#define	CAAM_CCWR_C2DS_SHIFT   (18U)
#define	CAAM_CCWR_C2DS(x)
#define	CAAM_CCWR_C2C_MASK   (0x200000U)
#define	CAAM_CCWR_C2C_SHIFT   (21U)
#define	CAAM_CCWR_C2C(x)
#define	CAAM_CCWR_C2K_MASK   (0x400000U)
#define	CAAM_CCWR_C2K_SHIFT   (22U)
#define	CAAM_CCWR_C2K(x)
#define	CAAM_CCWR_CDS_MASK   (0x2000000U)
#define	CAAM_CCWR_CDS_SHIFT   (25U)
#define	CAAM_CCWR_CDS(x)
#define	CAAM_CCWR_C2D_MASK   (0x4000000U)
#define	CAAM_CCWR_C2D_SHIFT   (26U)
#define	CAAM_CCWR_C2D(x)
#define	CAAM_CCWR_C1D_MASK   (0x8000000U)
#define	CAAM_CCWR_C1D_SHIFT   (27U)
#define	CAAM_CCWR_C1D(x)
#define	CAAM_CCWR_C2RST_MASK   (0x10000000U)
#define	CAAM_CCWR_C2RST_SHIFT   (28U)
#define	CAAM_CCWR_C2RST(x)
#define	CAAM_CCWR_C1RST_MASK   (0x20000000U)
#define	CAAM_CCWR_C1RST_SHIFT   (29U)
#define	CAAM_CCWR_C1RST(x)
#define	CAAM_CCWR_COF_MASK   (0x40000000U)
#define	CAAM_CCWR_COF_SHIFT   (30U)
#define	CAAM_CCWR_COF(x)
#define	CAAM_CCWR_CIF_MASK   (0x80000000U)
#define	CAAM_CCWR_CIF_SHIFT   (31U)
#define	CAAM_CCWR_CIF(x)
CCSTA_MS - CCB 0 Status and Error Register, most-significant half
#define	CAAM_CCSTA_MS_ERRID1_MASK   (0xFU)
#define	CAAM_CCSTA_MS_ERRID1_SHIFT   (0U)
#define	CAAM_CCSTA_MS_ERRID1(x)
#define	CAAM_CCSTA_MS_CL1_MASK   (0xF000U)
#define	CAAM_CCSTA_MS_CL1_SHIFT   (12U)
#define	CAAM_CCSTA_MS_CL1(x)
#define	CAAM_CCSTA_MS_ERRID2_MASK   (0xF0000U)
#define	CAAM_CCSTA_MS_ERRID2_SHIFT   (16U)
#define	CAAM_CCSTA_MS_ERRID2(x)
#define	CAAM_CCSTA_MS_CL2_MASK   (0xF0000000U)
#define	CAAM_CCSTA_MS_CL2_SHIFT   (28U)
#define	CAAM_CCSTA_MS_CL2(x)
CCSTA_LS - CCB 0 Status and Error Register, least-significant half
#define	CAAM_CCSTA_LS_AB_MASK   (0x2U)
#define	CAAM_CCSTA_LS_AB_SHIFT   (1U)
#define	CAAM_CCSTA_LS_AB(x)
#define	CAAM_CCSTA_LS_DB_MASK   (0x4U)
#define	CAAM_CCSTA_LS_DB_SHIFT   (2U)
#define	CAAM_CCSTA_LS_DB(x)
#define	CAAM_CCSTA_LS_PB_MASK   (0x40U)
#define	CAAM_CCSTA_LS_PB_SHIFT   (6U)
#define	CAAM_CCSTA_LS_PB(x)
#define	CAAM_CCSTA_LS_MB_MASK   (0x80U)
#define	CAAM_CCSTA_LS_MB_SHIFT   (7U)
#define	CAAM_CCSTA_LS_MB(x)
#define	CAAM_CCSTA_LS_CB_MASK   (0x100U)
#define	CAAM_CCSTA_LS_CB_SHIFT   (8U)
#define	CAAM_CCSTA_LS_CB(x)
#define	CAAM_CCSTA_LS_RNB_MASK   (0x200U)
#define	CAAM_CCSTA_LS_RNB_SHIFT   (9U)
#define	CAAM_CCSTA_LS_RNB(x)
#define	CAAM_CCSTA_LS_PDI_MASK   (0x10000U)
#define	CAAM_CCSTA_LS_PDI_SHIFT   (16U)
#define	CAAM_CCSTA_LS_PDI(x)
#define	CAAM_CCSTA_LS_SDI_MASK   (0x20000U)
#define	CAAM_CCSTA_LS_SDI_SHIFT   (17U)
#define	CAAM_CCSTA_LS_SDI(x)
#define	CAAM_CCSTA_LS_PEI_MASK   (0x100000U)
#define	CAAM_CCSTA_LS_PEI_SHIFT   (20U)
#define	CAAM_CCSTA_LS_PEI(x)
#define	CAAM_CCSTA_LS_SEI_MASK   (0x200000U)
#define	CAAM_CCSTA_LS_SEI_SHIFT   (21U)
#define	CAAM_CCSTA_LS_SEI(x)
#define	CAAM_CCSTA_LS_PRM_MASK   (0x10000000U)
#define	CAAM_CCSTA_LS_PRM_SHIFT   (28U)
#define	CAAM_CCSTA_LS_PRM(x)
#define	CAAM_CCSTA_LS_GCD_MASK   (0x20000000U)
#define	CAAM_CCSTA_LS_GCD_SHIFT   (29U)
#define	CAAM_CCSTA_LS_GCD(x)
#define	CAAM_CCSTA_LS_PIZ_MASK   (0x40000000U)
#define	CAAM_CCSTA_LS_PIZ_SHIFT   (30U)
#define	CAAM_CCSTA_LS_PIZ(x)
CC1AADSZR - CCB 0 Class 1 AAD Size Register
#define	CAAM_CC1AADSZR_AASZ_MASK   (0xFU)
#define	CAAM_CC1AADSZR_AASZ_SHIFT   (0U)
#define	CAAM_CC1AADSZR_AASZ(x)
CC1IVSZR - CCB 0 Class 1 IV Size Register
#define	CAAM_CC1IVSZR_IVSZ_MASK   (0xFU)
#define	CAAM_CC1IVSZR_IVSZ_SHIFT   (0U)
#define	CAAM_CC1IVSZR_IVSZ(x)
CPKASZR - PKHA A Size Register
#define	CAAM_CPKASZR_PKASZ_MASK   (0x3FFU)
#define	CAAM_CPKASZR_PKASZ_SHIFT   (0U)
#define	CAAM_CPKASZR_PKASZ(x)
CPKBSZR - PKHA B Size Register
#define	CAAM_CPKBSZR_PKBSZ_MASK   (0x3FFU)
#define	CAAM_CPKBSZR_PKBSZ_SHIFT   (0U)
#define	CAAM_CPKBSZR_PKBSZ(x)
CPKNSZR - PKHA N Size Register
#define	CAAM_CPKNSZR_PKNSZ_MASK   (0x3FFU)
#define	CAAM_CPKNSZR_PKNSZ_SHIFT   (0U)
#define	CAAM_CPKNSZR_PKNSZ(x)
CPKESZR - PKHA E Size Register
#define	CAAM_CPKESZR_PKESZ_MASK   (0x3FFU)
#define	CAAM_CPKESZR_PKESZ_SHIFT   (0U)
#define	CAAM_CPKESZR_PKESZ(x)
CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15
#define	CAAM_CC1CTXR_C1CTX_MASK   (0xFFFFFFFFU)
#define	CAAM_CC1CTXR_C1CTX_SHIFT   (0U)
#define	CAAM_CC1CTXR_C1CTX(x)
CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7
#define	CAAM_CC1KR_C1KEY_MASK   (0xFFFFFFFFU)
#define	CAAM_CC1KR_C1KEY_SHIFT   (0U)
#define	CAAM_CC1KR_C1KEY(x)
CC2MR - CCB 0 Class 2 Mode Register
#define	CAAM_CC2MR_AP_MASK   (0x1U)
#define	CAAM_CC2MR_AP_SHIFT   (0U)
#define	CAAM_CC2MR_AP(x)
#define	CAAM_CC2MR_ICV_MASK   (0x2U)
#define	CAAM_CC2MR_ICV_SHIFT   (1U)
#define	CAAM_CC2MR_ICV(x)
#define	CAAM_CC2MR_AS_MASK   (0xCU)
#define	CAAM_CC2MR_AS_SHIFT   (2U)
#define	CAAM_CC2MR_AS(x)
#define	CAAM_CC2MR_AAI_MASK   (0x1FF0U)
#define	CAAM_CC2MR_AAI_SHIFT   (4U)
#define	CAAM_CC2MR_AAI(x)
#define	CAAM_CC2MR_ALG_MASK   (0xFF0000U)
#define	CAAM_CC2MR_ALG_SHIFT   (16U)
#define	CAAM_CC2MR_ALG(x)
CC2KSR - CCB 0 Class 2 Key Size Register
#define	CAAM_CC2KSR_C2KS_MASK   (0xFFU)
#define	CAAM_CC2KSR_C2KS_SHIFT   (0U)
#define	CAAM_CC2KSR_C2KS(x)
CC2DSR - CCB 0 Class 2 Data Size Register
#define	CAAM_CC2DSR_C2DS_MASK   (0xFFFFFFFFU)
#define	CAAM_CC2DSR_C2DS_SHIFT   (0U)
#define	CAAM_CC2DSR_C2DS(x)
#define	CAAM_CC2DSR_C2CY_MASK   (0x100000000U)
#define	CAAM_CC2DSR_C2CY_SHIFT   (32U)
#define	CAAM_CC2DSR_C2CY(x)
#define	CAAM_CC2DSR_NUMBITS_MASK   (0xE000000000000000U)
#define	CAAM_CC2DSR_NUMBITS_SHIFT   (61U)
#define	CAAM_CC2DSR_NUMBITS(x)
CC2ICVSZR - CCB 0 Class 2 ICV Size Register
#define	CAAM_CC2ICVSZR_ICVSZ_MASK   (0xFU)
#define	CAAM_CC2ICVSZR_ICVSZ_SHIFT   (0U)
#define	CAAM_CC2ICVSZR_ICVSZ(x)
CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17
#define	CAAM_CC2CTXR_C2CTXR_MASK   (0xFFFFFFFFU)
#define	CAAM_CC2CTXR_C2CTXR_SHIFT   (0U)
#define	CAAM_CC2CTXR_C2CTXR(x)
CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31
#define	CAAM_CC2KEYR_C2KEY_MASK   (0xFFFFFFFFU)
#define	CAAM_CC2KEYR_C2KEY_SHIFT   (0U)
#define	CAAM_CC2KEYR_C2KEY(x)
CFIFOSTA - CCB 0 FIFO Status Register
#define	CAAM_CFIFOSTA_DECOOQHEAD_MASK   (0xFFU)
#define	CAAM_CFIFOSTA_DECOOQHEAD_SHIFT   (0U)
#define	CAAM_CFIFOSTA_DECOOQHEAD(x)
#define	CAAM_CFIFOSTA_DMAOQHEAD_MASK   (0xFF00U)
#define	CAAM_CFIFOSTA_DMAOQHEAD_SHIFT   (8U)
#define	CAAM_CFIFOSTA_DMAOQHEAD(x)
#define	CAAM_CFIFOSTA_C2IQHEAD_MASK   (0xFF0000U)
#define	CAAM_CFIFOSTA_C2IQHEAD_SHIFT   (16U)
#define	CAAM_CFIFOSTA_C2IQHEAD(x)
#define	CAAM_CFIFOSTA_C1IQHEAD_MASK   (0xFF000000U)
#define	CAAM_CFIFOSTA_C1IQHEAD_SHIFT   (24U)
#define	CAAM_CFIFOSTA_C1IQHEAD(x)
CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b
#define	CAAM_CNFIFO_DL_MASK   (0xFFFU)
#define	CAAM_CNFIFO_DL_SHIFT   (0U)
#define	CAAM_CNFIFO_DL(x)
#define	CAAM_CNFIFO_AST_MASK   (0x4000U)
#define	CAAM_CNFIFO_AST_SHIFT   (14U)
#define	CAAM_CNFIFO_AST(x)
#define	CAAM_CNFIFO_OC_MASK   (0x8000U)
#define	CAAM_CNFIFO_OC_SHIFT   (15U)
#define	CAAM_CNFIFO_OC(x)
#define	CAAM_CNFIFO_PTYPE_MASK   (0x70000U)
#define	CAAM_CNFIFO_PTYPE_SHIFT   (16U)
#define	CAAM_CNFIFO_PTYPE(x)
#define	CAAM_CNFIFO_BND_MASK   (0x80000U)
#define	CAAM_CNFIFO_BND_SHIFT   (19U)
#define	CAAM_CNFIFO_BND(x)
#define	CAAM_CNFIFO_DTYPE_MASK   (0xF00000U)
#define	CAAM_CNFIFO_DTYPE_SHIFT   (20U)
#define	CAAM_CNFIFO_DTYPE(x)
#define	CAAM_CNFIFO_STYPE_MASK   (0x3000000U)
#define	CAAM_CNFIFO_STYPE_SHIFT   (24U)
#define	CAAM_CNFIFO_STYPE(x)
#define	CAAM_CNFIFO_FC1_MASK   (0x4000000U)
#define	CAAM_CNFIFO_FC1_SHIFT   (26U)
#define	CAAM_CNFIFO_FC1(x)
#define	CAAM_CNFIFO_FC2_MASK   (0x8000000U)
#define	CAAM_CNFIFO_FC2_SHIFT   (27U)
#define	CAAM_CNFIFO_FC2(x)
#define	CAAM_CNFIFO_LC1_MASK   (0x10000000U)
#define	CAAM_CNFIFO_LC1_SHIFT   (28U)
#define	CAAM_CNFIFO_LC1(x)
#define	CAAM_CNFIFO_LC2_MASK   (0x20000000U)
#define	CAAM_CNFIFO_LC2_SHIFT   (29U)
#define	CAAM_CNFIFO_LC2(x)
#define	CAAM_CNFIFO_DEST_MASK   (0xC0000000U)
#define	CAAM_CNFIFO_DEST_SHIFT   (30U)
#define	CAAM_CNFIFO_DEST(x)
CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b
#define	CAAM_CNFIFO_2_PL_MASK   (0x7FU)
#define	CAAM_CNFIFO_2_PL_SHIFT   (0U)
#define	CAAM_CNFIFO_2_PL(x)
#define	CAAM_CNFIFO_2_PS_MASK   (0x400U)
#define	CAAM_CNFIFO_2_PS_SHIFT   (10U)
#define	CAAM_CNFIFO_2_PS(x)
#define	CAAM_CNFIFO_2_BM_MASK   (0x800U)
#define	CAAM_CNFIFO_2_BM_SHIFT   (11U)
#define	CAAM_CNFIFO_2_BM(x)
#define	CAAM_CNFIFO_2_PR_MASK   (0x8000U)
#define	CAAM_CNFIFO_2_PR_SHIFT   (15U)
#define	CAAM_CNFIFO_2_PR(x)
#define	CAAM_CNFIFO_2_PTYPE_MASK   (0x70000U)
#define	CAAM_CNFIFO_2_PTYPE_SHIFT   (16U)
#define	CAAM_CNFIFO_2_PTYPE(x)
#define	CAAM_CNFIFO_2_BND_MASK   (0x80000U)
#define	CAAM_CNFIFO_2_BND_SHIFT   (19U)
#define	CAAM_CNFIFO_2_BND(x)
#define	CAAM_CNFIFO_2_DTYPE_MASK   (0xF00000U)
#define	CAAM_CNFIFO_2_DTYPE_SHIFT   (20U)
#define	CAAM_CNFIFO_2_DTYPE(x)
#define	CAAM_CNFIFO_2_STYPE_MASK   (0x3000000U)
#define	CAAM_CNFIFO_2_STYPE_SHIFT   (24U)
#define	CAAM_CNFIFO_2_STYPE(x)
#define	CAAM_CNFIFO_2_FC1_MASK   (0x4000000U)
#define	CAAM_CNFIFO_2_FC1_SHIFT   (26U)
#define	CAAM_CNFIFO_2_FC1(x)
#define	CAAM_CNFIFO_2_FC2_MASK   (0x8000000U)
#define	CAAM_CNFIFO_2_FC2_SHIFT   (27U)
#define	CAAM_CNFIFO_2_FC2(x)
#define	CAAM_CNFIFO_2_LC1_MASK   (0x10000000U)
#define	CAAM_CNFIFO_2_LC1_SHIFT   (28U)
#define	CAAM_CNFIFO_2_LC1(x)
#define	CAAM_CNFIFO_2_LC2_MASK   (0x20000000U)
#define	CAAM_CNFIFO_2_LC2_SHIFT   (29U)
#define	CAAM_CNFIFO_2_LC2(x)
#define	CAAM_CNFIFO_2_DEST_MASK   (0xC0000000U)
#define	CAAM_CNFIFO_2_DEST_SHIFT   (30U)
#define	CAAM_CNFIFO_2_DEST(x)
CIFIFO - CCB 0 Input Data FIFO
#define	CAAM_CIFIFO_IFIFO_MASK   (0xFFFFFFFFU)
#define	CAAM_CIFIFO_IFIFO_SHIFT   (0U)
#define	CAAM_CIFIFO_IFIFO(x)
COFIFO - CCB 0 Output Data FIFO
#define	CAAM_COFIFO_OFIFO_MASK   (0xFFFFFFFFFFFFFFFFU)
#define	CAAM_COFIFO_OFIFO_SHIFT   (0U)
#define	CAAM_COFIFO_OFIFO(x)
DJQCR_MS - DECO0 Job Queue Control Register, most-significant half
#define	CAAM_DJQCR_MS_ID_MASK   (0x7U)
#define	CAAM_DJQCR_MS_ID_SHIFT   (0U)
#define	CAAM_DJQCR_MS_ID(x)
#define	CAAM_DJQCR_MS_SRC_MASK   (0x700U)
#define	CAAM_DJQCR_MS_SRC_SHIFT   (8U)
#define	CAAM_DJQCR_MS_SRC(x)
#define	CAAM_DJQCR_MS_AMTD_MASK   (0x8000U)
#define	CAAM_DJQCR_MS_AMTD_SHIFT   (15U)
#define	CAAM_DJQCR_MS_AMTD(x)
#define	CAAM_DJQCR_MS_SOB_MASK   (0x10000U)
#define	CAAM_DJQCR_MS_SOB_SHIFT   (16U)
#define	CAAM_DJQCR_MS_SOB(x)
#define	CAAM_DJQCR_MS_DWS_MASK   (0x80000U)
#define	CAAM_DJQCR_MS_DWS_SHIFT   (19U)
#define	CAAM_DJQCR_MS_DWS(x)
#define	CAAM_DJQCR_MS_SHR_FROM_MASK   (0x7000000U)
#define	CAAM_DJQCR_MS_SHR_FROM_SHIFT   (24U)
#define	CAAM_DJQCR_MS_SHR_FROM(x)
#define	CAAM_DJQCR_MS_ILE_MASK   (0x8000000U)
#define	CAAM_DJQCR_MS_ILE_SHIFT   (27U)
#define	CAAM_DJQCR_MS_ILE(x)
#define	CAAM_DJQCR_MS_FOUR_MASK   (0x10000000U)
#define	CAAM_DJQCR_MS_FOUR_SHIFT   (28U)
#define	CAAM_DJQCR_MS_FOUR(x)
#define	CAAM_DJQCR_MS_WHL_MASK   (0x20000000U)
#define	CAAM_DJQCR_MS_WHL_SHIFT   (29U)
#define	CAAM_DJQCR_MS_WHL(x)
#define	CAAM_DJQCR_MS_SING_MASK   (0x40000000U)
#define	CAAM_DJQCR_MS_SING_SHIFT   (30U)
#define	CAAM_DJQCR_MS_SING(x)
#define	CAAM_DJQCR_MS_STEP_MASK   (0x80000000U)
#define	CAAM_DJQCR_MS_STEP_SHIFT   (31U)
#define	CAAM_DJQCR_MS_STEP(x)
DJQCR_LS - DECO0 Job Queue Control Register, least-significant half
#define	CAAM_DJQCR_LS_CMD_MASK   (0xFFFFFFFFU)
#define	CAAM_DJQCR_LS_CMD_SHIFT   (0U)
#define	CAAM_DJQCR_LS_CMD(x)
DDAR - DECO0 Descriptor Address Register
#define	CAAM_DDAR_DPTR_MASK   (0xFFFFFFFFFU)
#define	CAAM_DDAR_DPTR_SHIFT   (0U)
#define	CAAM_DDAR_DPTR(x)
DOPSTA_MS - DECO0 Operation Status Register, most-significant half
#define	CAAM_DOPSTA_MS_STATUS_MASK   (0xFFU)
#define	CAAM_DOPSTA_MS_STATUS_SHIFT   (0U)
#define	CAAM_DOPSTA_MS_STATUS(x)
#define	CAAM_DOPSTA_MS_COMMAND_INDEX_MASK   (0x7F00U)
#define	CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT   (8U)
#define	CAAM_DOPSTA_MS_COMMAND_INDEX(x)
#define	CAAM_DOPSTA_MS_NLJ_MASK   (0x8000000U)
#define	CAAM_DOPSTA_MS_NLJ_SHIFT   (27U)
#define	CAAM_DOPSTA_MS_NLJ(x)
#define	CAAM_DOPSTA_MS_STATUS_TYPE_MASK   (0xF0000000U)
#define	CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT   (28U)
#define	CAAM_DOPSTA_MS_STATUS_TYPE(x)
DOPSTA_LS - DECO0 Operation Status Register, least-significant half
#define	CAAM_DOPSTA_LS_OUT_CT_MASK   (0xFFFFFFFFU)
#define	CAAM_DOPSTA_LS_OUT_CT_SHIFT   (0U)
#define	CAAM_DOPSTA_LS_OUT_CT(x)
DPDIDSR - DECO0 Primary DID Status Register
#define	CAAM_DPDIDSR_PRIM_DID_MASK   (0xFU)
#define	CAAM_DPDIDSR_PRIM_DID_SHIFT   (0U)
#define	CAAM_DPDIDSR_PRIM_DID(x)
#define	CAAM_DPDIDSR_PRIM_ICID_MASK   (0x3FF80000U)
#define	CAAM_DPDIDSR_PRIM_ICID_SHIFT   (19U)
#define	CAAM_DPDIDSR_PRIM_ICID(x)
DODIDSR - DECO0 Output DID Status Register
#define	CAAM_DODIDSR_OUT_DID_MASK   (0xFU)
#define	CAAM_DODIDSR_OUT_DID_SHIFT   (0U)
#define	CAAM_DODIDSR_OUT_DID(x)
#define	CAAM_DODIDSR_OUT_ICID_MASK   (0x3FF80000U)
#define	CAAM_DODIDSR_OUT_ICID_SHIFT   (19U)
#define	CAAM_DODIDSR_OUT_ICID(x)
DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS
#define	CAAM_DMTH_MS_MATH_MS_MASK   (0xFFFFFFFFU)
#define	CAAM_DMTH_MS_MATH_MS_SHIFT   (0U)
#define	CAAM_DMTH_MS_MATH_MS(x)
DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS
#define	CAAM_DMTH_LS_MATH_LS_MASK   (0xFFFFFFFFU)
#define	CAAM_DMTH_LS_MATH_LS_SHIFT   (0U)
#define	CAAM_DMTH_LS_MATH_LS(x)
DGTR_0 - DECO0 Gather Table Register 0 Word 0
#define	CAAM_DGTR_0_ADDRESS_POINTER_MASK   (0xFU)
#define	CAAM_DGTR_0_ADDRESS_POINTER_SHIFT   (0U)
#define	CAAM_DGTR_0_ADDRESS_POINTER(x)
DGTR_1 - DECO0 Gather Table Register 0 Word 1
#define	CAAM_DGTR_1_ADDRESS_POINTER_MASK   (0xFFFFFFFFU)
#define	CAAM_DGTR_1_ADDRESS_POINTER_SHIFT   (0U)
#define	CAAM_DGTR_1_ADDRESS_POINTER(x)
DGTR_2 - DECO0 Gather Table Register 0 Word 2
#define	CAAM_DGTR_2_Length_MASK   (0x3FFFFFFFU)
#define	CAAM_DGTR_2_Length_SHIFT   (0U)
#define	CAAM_DGTR_2_Length(x)
#define	CAAM_DGTR_2_F_MASK   (0x40000000U)
#define	CAAM_DGTR_2_F_SHIFT   (30U)
#define	CAAM_DGTR_2_F(x)
#define	CAAM_DGTR_2_E_MASK   (0x80000000U)
#define	CAAM_DGTR_2_E_SHIFT   (31U)
#define	CAAM_DGTR_2_E(x)
DGTR_3 - DECO0 Gather Table Register 0 Word 3
#define	CAAM_DGTR_3_Offset_MASK   (0x1FFFU)
#define	CAAM_DGTR_3_Offset_SHIFT   (0U)
#define	CAAM_DGTR_3_Offset(x)
DSTR_0 - DECO0 Scatter Table Register 0 Word 0
#define	CAAM_DSTR_0_ADDRESS_POINTER_MASK   (0xFU)
#define	CAAM_DSTR_0_ADDRESS_POINTER_SHIFT   (0U)
#define	CAAM_DSTR_0_ADDRESS_POINTER(x)
DSTR_1 - DECO0 Scatter Table Register 0 Word 1
#define	CAAM_DSTR_1_ADDRESS_POINTER_MASK   (0xFFFFFFFFU)
#define	CAAM_DSTR_1_ADDRESS_POINTER_SHIFT   (0U)
#define	CAAM_DSTR_1_ADDRESS_POINTER(x)
DSTR_2 - DECO0 Scatter Table Register 0 Word 2
#define	CAAM_DSTR_2_Length_MASK   (0x3FFFFFFFU)
#define	CAAM_DSTR_2_Length_SHIFT   (0U)
#define	CAAM_DSTR_2_Length(x)
#define	CAAM_DSTR_2_F_MASK   (0x40000000U)
#define	CAAM_DSTR_2_F_SHIFT   (30U)
#define	CAAM_DSTR_2_F(x)
#define	CAAM_DSTR_2_E_MASK   (0x80000000U)
#define	CAAM_DSTR_2_E_SHIFT   (31U)
#define	CAAM_DSTR_2_E(x)
DSTR_3 - DECO0 Scatter Table Register 0 Word 3
#define	CAAM_DSTR_3_Offset_MASK   (0x1FFFU)
#define	CAAM_DSTR_3_Offset_SHIFT   (0U)
#define	CAAM_DSTR_3_Offset(x)
DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63
#define	CAAM_DDESB_DESBW_MASK   (0xFFFFFFFFU)
#define	CAAM_DDESB_DESBW_SHIFT   (0U)
#define	CAAM_DDESB_DESBW(x)
DDJR - DECO0 Debug Job Register
#define	CAAM_DDJR_ID_MASK   (0x7U)
#define	CAAM_DDJR_ID_SHIFT   (0U)
#define	CAAM_DDJR_ID(x)
#define	CAAM_DDJR_SRC_MASK   (0x700U)
#define	CAAM_DDJR_SRC_SHIFT   (8U)
#define	CAAM_DDJR_SRC(x)
#define	CAAM_DDJR_JDDS_MASK   (0x4000U)
#define	CAAM_DDJR_JDDS_SHIFT   (14U)
#define	CAAM_DDJR_JDDS(x)
#define	CAAM_DDJR_AMTD_MASK   (0x8000U)
#define	CAAM_DDJR_AMTD_SHIFT   (15U)
#define	CAAM_DDJR_AMTD(x)
#define	CAAM_DDJR_GSD_MASK   (0x10000U)
#define	CAAM_DDJR_GSD_SHIFT   (16U)
#define	CAAM_DDJR_GSD(x)
#define	CAAM_DDJR_DWS_MASK   (0x80000U)
#define	CAAM_DDJR_DWS_SHIFT   (19U)
#define	CAAM_DDJR_DWS(x)
#define	CAAM_DDJR_SHR_FROM_MASK   (0x7000000U)
#define	CAAM_DDJR_SHR_FROM_SHIFT   (24U)
#define	CAAM_DDJR_SHR_FROM(x)
#define	CAAM_DDJR_ILE_MASK   (0x8000000U)
#define	CAAM_DDJR_ILE_SHIFT   (27U)
#define	CAAM_DDJR_ILE(x)
#define	CAAM_DDJR_FOUR_MASK   (0x10000000U)
#define	CAAM_DDJR_FOUR_SHIFT   (28U)
#define	CAAM_DDJR_FOUR(x)
#define	CAAM_DDJR_WHL_MASK   (0x20000000U)
#define	CAAM_DDJR_WHL_SHIFT   (29U)
#define	CAAM_DDJR_WHL(x)
#define	CAAM_DDJR_SING_MASK   (0x40000000U)
#define	CAAM_DDJR_SING_SHIFT   (30U)
#define	CAAM_DDJR_SING(x)
#define	CAAM_DDJR_STEP_MASK   (0x80000000U)
#define	CAAM_DDJR_STEP_SHIFT   (31U)
#define	CAAM_DDJR_STEP(x)
DDDR - DECO0 Debug DECO Register
#define	CAAM_DDDR_CT_MASK   (0x1U)
#define	CAAM_DDDR_CT_SHIFT   (0U)
#define	CAAM_DDDR_CT(x)
#define	CAAM_DDDR_BRB_MASK   (0x2U)
#define	CAAM_DDDR_BRB_SHIFT   (1U)
#define	CAAM_DDDR_BRB(x)
#define	CAAM_DDDR_BWB_MASK   (0x4U)
#define	CAAM_DDDR_BWB_SHIFT   (2U)
#define	CAAM_DDDR_BWB(x)
#define	CAAM_DDDR_NC_MASK   (0x8U)
#define	CAAM_DDDR_NC_SHIFT   (3U)
#define	CAAM_DDDR_NC(x)
#define	CAAM_DDDR_CSA_MASK   (0x10U)
#define	CAAM_DDDR_CSA_SHIFT   (4U)
#define	CAAM_DDDR_CSA(x)
#define	CAAM_DDDR_CMD_STAGE_MASK   (0xE0U)
#define	CAAM_DDDR_CMD_STAGE_SHIFT   (5U)
#define	CAAM_DDDR_CMD_STAGE(x)
#define	CAAM_DDDR_CMD_INDEX_MASK   (0x3F00U)
#define	CAAM_DDDR_CMD_INDEX_SHIFT   (8U)
#define	CAAM_DDDR_CMD_INDEX(x)
#define	CAAM_DDDR_NLJ_MASK   (0x4000U)
#define	CAAM_DDDR_NLJ_SHIFT   (14U)
#define	CAAM_DDDR_NLJ(x)
#define	CAAM_DDDR_PTCL_RUN_MASK   (0x8000U)
#define	CAAM_DDDR_PTCL_RUN_SHIFT   (15U)
#define	CAAM_DDDR_PTCL_RUN(x)
#define	CAAM_DDDR_PDB_STALL_MASK   (0x30000U)
#define	CAAM_DDDR_PDB_STALL_SHIFT   (16U)
#define	CAAM_DDDR_PDB_STALL(x)
#define	CAAM_DDDR_PDB_WB_ST_MASK   (0xC0000U)
#define	CAAM_DDDR_PDB_WB_ST_SHIFT   (18U)
#define	CAAM_DDDR_PDB_WB_ST(x)
#define	CAAM_DDDR_DECO_STATE_MASK   (0xF00000U)
#define	CAAM_DDDR_DECO_STATE_SHIFT   (20U)
#define	CAAM_DDDR_DECO_STATE(x)
#define	CAAM_DDDR_NSEQLSEL_MASK   (0x3000000U)
#define	CAAM_DDDR_NSEQLSEL_SHIFT   (24U)
#define	CAAM_DDDR_NSEQLSEL(x)
#define	CAAM_DDDR_SEQLSEL_MASK   (0xC000000U)
#define	CAAM_DDDR_SEQLSEL_SHIFT   (26U)
#define	CAAM_DDDR_SEQLSEL(x)
#define	CAAM_DDDR_TRCT_MASK   (0x30000000U)
#define	CAAM_DDDR_TRCT_SHIFT   (28U)
#define	CAAM_DDDR_TRCT(x)
#define	CAAM_DDDR_SD_MASK   (0x40000000U)
#define	CAAM_DDDR_SD_SHIFT   (30U)
#define	CAAM_DDDR_SD(x)
#define	CAAM_DDDR_VALID_MASK   (0x80000000U)
#define	CAAM_DDDR_VALID_SHIFT   (31U)
#define	CAAM_DDDR_VALID(x)
DDJP - DECO0 Debug Job Pointer
#define	CAAM_DDJP_JDPTR_MASK   (0xFFFFFFFFFU)
#define	CAAM_DDJP_JDPTR_SHIFT   (0U)
#define	CAAM_DDJP_JDPTR(x)
DSDP - DECO0 Debug Shared Pointer
#define	CAAM_DSDP_SDPTR_MASK   (0xFFFFFFFFFU)
#define	CAAM_DSDP_SDPTR_SHIFT   (0U)
#define	CAAM_DSDP_SDPTR(x)
DDDR_MS - DECO0 Debug DID, most-significant half
#define	CAAM_DDDR_MS_PRIM_DID_MASK   (0xFU)
#define	CAAM_DDDR_MS_PRIM_DID_SHIFT   (0U)
#define	CAAM_DDDR_MS_PRIM_DID(x)
#define	CAAM_DDDR_MS_PRIM_TZ_MASK   (0x10U)
#define	CAAM_DDDR_MS_PRIM_TZ_SHIFT   (4U)
#define	CAAM_DDDR_MS_PRIM_TZ(x)
#define	CAAM_DDDR_MS_PRIM_ICID_MASK   (0xFFE0U)
#define	CAAM_DDDR_MS_PRIM_ICID_SHIFT   (5U)
#define	CAAM_DDDR_MS_PRIM_ICID(x)
#define	CAAM_DDDR_MS_OUT_DID_MASK   (0xF0000U)
#define	CAAM_DDDR_MS_OUT_DID_SHIFT   (16U)
#define	CAAM_DDDR_MS_OUT_DID(x)
#define	CAAM_DDDR_MS_OUT_ICID_MASK   (0xFFE00000U)
#define	CAAM_DDDR_MS_OUT_ICID_SHIFT   (21U)
#define	CAAM_DDDR_MS_OUT_ICID(x)
DDDR_LS - DECO0 Debug DID, least-significant half
#define	CAAM_DDDR_LS_OUT_DID_MASK   (0xFU)
#define	CAAM_DDDR_LS_OUT_DID_SHIFT   (0U)
#define	CAAM_DDDR_LS_OUT_DID(x)
#define	CAAM_DDDR_LS_OUT_ICID_MASK   (0x3FF80000U)
#define	CAAM_DDDR_LS_OUT_ICID_SHIFT   (19U)
#define	CAAM_DDDR_LS_OUT_ICID(x)
SOL - Sequence Output Length Register
#define	CAAM_SOL_SOL_MASK   (0xFFFFFFFFU)
#define	CAAM_SOL_SOL_SHIFT   (0U)
#define	CAAM_SOL_SOL(x)
VSOL - Variable Sequence Output Length Register
#define	CAAM_VSOL_VSOL_MASK   (0xFFFFFFFFU)
#define	CAAM_VSOL_VSOL_SHIFT   (0U)
#define	CAAM_VSOL_VSOL(x)
SIL - Sequence Input Length Register
#define	CAAM_SIL_SIL_MASK   (0xFFFFFFFFU)
#define	CAAM_SIL_SIL_SHIFT   (0U)
#define	CAAM_SIL_SIL(x)
VSIL - Variable Sequence Input Length Register
#define	CAAM_VSIL_VSIL_MASK   (0xFFFFFFFFU)
#define	CAAM_VSIL_VSIL_SHIFT   (0U)
#define	CAAM_VSIL_VSIL(x)
DPOVRD - Protocol Override Register
#define	CAAM_DPOVRD_DPOVRD_MASK   (0xFFFFFFFFU)
#define	CAAM_DPOVRD_DPOVRD_SHIFT   (0U)
#define	CAAM_DPOVRD_DPOVRD(x)
UVSOL - Variable Sequence Output Length Register; Upper 32 bits
#define	CAAM_UVSOL_UVSOL_MASK   (0xFFFFFFFFU)
#define	CAAM_UVSOL_UVSOL_SHIFT   (0U)
#define	CAAM_UVSOL_UVSOL(x)
UVSIL - Variable Sequence Input Length Register; Upper 32 bits
#define	CAAM_UVSIL_UVSIL_MASK   (0xFFFFFFFFU)
#define	CAAM_UVSIL_UVSIL_SHIFT   (0U)
#define	CAAM_UVSIL_UVSIL(x)
MCR - Module Configuration register
#define	CAN_MCR_MAXMB_MASK   (0x7FU)
#define	CAN_MCR_MAXMB_SHIFT   (0U)
#define	CAN_MCR_MAXMB(x)
#define	CAN_MCR_IDAM_MASK   (0x300U)
#define	CAN_MCR_IDAM_SHIFT   (8U)
#define	CAN_MCR_IDAM(x)
#define	CAN_MCR_FDEN_MASK   (0x800U)
#define	CAN_MCR_FDEN_SHIFT   (11U)
#define	CAN_MCR_FDEN(x)
#define	CAN_MCR_AEN_MASK   (0x1000U)
#define	CAN_MCR_AEN_SHIFT   (12U)
#define	CAN_MCR_AEN(x)
#define	CAN_MCR_LPRIOEN_MASK   (0x2000U)
#define	CAN_MCR_LPRIOEN_SHIFT   (13U)
#define	CAN_MCR_LPRIOEN(x)
#define	CAN_MCR_DMA_MASK   (0x8000U)
#define	CAN_MCR_DMA_SHIFT   (15U)
#define	CAN_MCR_DMA(x)
#define	CAN_MCR_IRMQ_MASK   (0x10000U)
#define	CAN_MCR_IRMQ_SHIFT   (16U)
#define	CAN_MCR_IRMQ(x)
#define	CAN_MCR_SRXDIS_MASK   (0x20000U)
#define	CAN_MCR_SRXDIS_SHIFT   (17U)
#define	CAN_MCR_SRXDIS(x)
#define	CAN_MCR_DOZE_MASK   (0x40000U)
#define	CAN_MCR_DOZE_SHIFT   (18U)
#define	CAN_MCR_DOZE(x)
#define	CAN_MCR_WAKSRC_MASK   (0x80000U)
#define	CAN_MCR_WAKSRC_SHIFT   (19U)
#define	CAN_MCR_WAKSRC(x)
#define	CAN_MCR_LPMACK_MASK   (0x100000U)
#define	CAN_MCR_LPMACK_SHIFT   (20U)
#define	CAN_MCR_LPMACK(x)
#define	CAN_MCR_WRNEN_MASK   (0x200000U)
#define	CAN_MCR_WRNEN_SHIFT   (21U)
#define	CAN_MCR_WRNEN(x)
#define	CAN_MCR_SLFWAK_MASK   (0x400000U)
#define	CAN_MCR_SLFWAK_SHIFT   (22U)
#define	CAN_MCR_SLFWAK(x)
#define	CAN_MCR_SUPV_MASK   (0x800000U)
#define	CAN_MCR_SUPV_SHIFT   (23U)
#define	CAN_MCR_SUPV(x)
#define	CAN_MCR_FRZACK_MASK   (0x1000000U)
#define	CAN_MCR_FRZACK_SHIFT   (24U)
#define	CAN_MCR_FRZACK(x)
#define	CAN_MCR_SOFTRST_MASK   (0x2000000U)
#define	CAN_MCR_SOFTRST_SHIFT   (25U)
#define	CAN_MCR_SOFTRST(x)
#define	CAN_MCR_WAKMSK_MASK   (0x4000000U)
#define	CAN_MCR_WAKMSK_SHIFT   (26U)
#define	CAN_MCR_WAKMSK(x)
#define	CAN_MCR_NOTRDY_MASK   (0x8000000U)
#define	CAN_MCR_NOTRDY_SHIFT   (27U)
#define	CAN_MCR_NOTRDY(x)
#define	CAN_MCR_HALT_MASK   (0x10000000U)
#define	CAN_MCR_HALT_SHIFT   (28U)
#define	CAN_MCR_HALT(x)
#define	CAN_MCR_RFEN_MASK   (0x20000000U)
#define	CAN_MCR_RFEN_SHIFT   (29U)
#define	CAN_MCR_RFEN(x)
#define	CAN_MCR_FRZ_MASK   (0x40000000U)
#define	CAN_MCR_FRZ_SHIFT   (30U)
#define	CAN_MCR_FRZ(x)
#define	CAN_MCR_MDIS_MASK   (0x80000000U)
#define	CAN_MCR_MDIS_SHIFT   (31U)
#define	CAN_MCR_MDIS(x)
CTRL1 - Control 1 register
#define	CAN_CTRL1_PROPSEG_MASK   (0x7U)
#define	CAN_CTRL1_PROPSEG_SHIFT   (0U)
#define	CAN_CTRL1_PROPSEG(x)
#define	CAN_CTRL1_LOM_MASK   (0x8U)
#define	CAN_CTRL1_LOM_SHIFT   (3U)
#define	CAN_CTRL1_LOM(x)
#define	CAN_CTRL1_LBUF_MASK   (0x10U)
#define	CAN_CTRL1_LBUF_SHIFT   (4U)
#define	CAN_CTRL1_LBUF(x)
#define	CAN_CTRL1_TSYN_MASK   (0x20U)
#define	CAN_CTRL1_TSYN_SHIFT   (5U)
#define	CAN_CTRL1_TSYN(x)
#define	CAN_CTRL1_BOFFREC_MASK   (0x40U)
#define	CAN_CTRL1_BOFFREC_SHIFT   (6U)
#define	CAN_CTRL1_BOFFREC(x)
#define	CAN_CTRL1_SMP_MASK   (0x80U)
#define	CAN_CTRL1_SMP_SHIFT   (7U)
#define	CAN_CTRL1_SMP(x)
#define	CAN_CTRL1_RWRNMSK_MASK   (0x400U)
#define	CAN_CTRL1_RWRNMSK_SHIFT   (10U)
#define	CAN_CTRL1_RWRNMSK(x)
#define	CAN_CTRL1_TWRNMSK_MASK   (0x800U)
#define	CAN_CTRL1_TWRNMSK_SHIFT   (11U)
#define	CAN_CTRL1_TWRNMSK(x)
#define	CAN_CTRL1_LPB_MASK   (0x1000U)
#define	CAN_CTRL1_LPB_SHIFT   (12U)
#define	CAN_CTRL1_LPB(x)
#define	CAN_CTRL1_CLKSRC_MASK   (0x2000U)
#define	CAN_CTRL1_CLKSRC_SHIFT   (13U)
#define	CAN_CTRL1_CLKSRC(x)
#define	CAN_CTRL1_ERRMSK_MASK   (0x4000U)
#define	CAN_CTRL1_ERRMSK_SHIFT   (14U)
#define	CAN_CTRL1_ERRMSK(x)
#define	CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
#define	CAN_CTRL1_BOFFMSK_SHIFT   (15U)
#define	CAN_CTRL1_BOFFMSK(x)
#define	CAN_CTRL1_PSEG2_MASK   (0x70000U)
#define	CAN_CTRL1_PSEG2_SHIFT   (16U)
#define	CAN_CTRL1_PSEG2(x)
#define	CAN_CTRL1_PSEG1_MASK   (0x380000U)
#define	CAN_CTRL1_PSEG1_SHIFT   (19U)
#define	CAN_CTRL1_PSEG1(x)
#define	CAN_CTRL1_RJW_MASK   (0xC00000U)
#define	CAN_CTRL1_RJW_SHIFT   (22U)
#define	CAN_CTRL1_RJW(x)
#define	CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
#define	CAN_CTRL1_PRESDIV_SHIFT   (24U)
#define	CAN_CTRL1_PRESDIV(x)
TIMER - Free Running Timer
#define	CAN_TIMER_TIMER_MASK   (0xFFFFU)
#define	CAN_TIMER_TIMER_SHIFT   (0U)
#define	CAN_TIMER_TIMER(x)
RXMGMASK - Rx Mailboxes Global Mask register
#define	CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
#define	CAN_RXMGMASK_MG_SHIFT   (0U)
#define	CAN_RXMGMASK_MG(x)
RX14MASK - Rx 14 Mask register
#define	CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
#define	CAN_RX14MASK_RX14M_SHIFT   (0U)
#define	CAN_RX14MASK_RX14M(x)
RX15MASK - Rx 15 Mask register
#define	CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
#define	CAN_RX15MASK_RX15M_SHIFT   (0U)
#define	CAN_RX15MASK_RX15M(x)
ECR - Error Counter
#define	CAN_ECR_TXERRCNT_MASK   (0xFFU)
#define	CAN_ECR_TXERRCNT_SHIFT   (0U)
#define	CAN_ECR_TXERRCNT(x)
#define	CAN_ECR_RXERRCNT_MASK   (0xFF00U)
#define	CAN_ECR_RXERRCNT_SHIFT   (8U)
#define	CAN_ECR_RXERRCNT(x)
#define	CAN_ECR_TXERRCNT_FAST_MASK   (0xFF0000U)
#define	CAN_ECR_TXERRCNT_FAST_SHIFT   (16U)
#define	CAN_ECR_TXERRCNT_FAST(x)
#define	CAN_ECR_RXERRCNT_FAST_MASK   (0xFF000000U)
#define	CAN_ECR_RXERRCNT_FAST_SHIFT   (24U)
#define	CAN_ECR_RXERRCNT_FAST(x)
ESR1 - Error and Status 1 register
#define	CAN_ESR1_WAKINT_MASK   (0x1U)
#define	CAN_ESR1_WAKINT_SHIFT   (0U)
#define	CAN_ESR1_WAKINT(x)
#define	CAN_ESR1_ERRINT_MASK   (0x2U)
#define	CAN_ESR1_ERRINT_SHIFT   (1U)
#define	CAN_ESR1_ERRINT(x)
#define	CAN_ESR1_BOFFINT_MASK   (0x4U)
#define	CAN_ESR1_BOFFINT_SHIFT   (2U)
#define	CAN_ESR1_BOFFINT(x)
#define	CAN_ESR1_RX_MASK   (0x8U)
#define	CAN_ESR1_RX_SHIFT   (3U)
#define	CAN_ESR1_RX(x)
#define	CAN_ESR1_FLTCONF_MASK   (0x30U)
#define	CAN_ESR1_FLTCONF_SHIFT   (4U)
#define	CAN_ESR1_FLTCONF(x)
#define	CAN_ESR1_TX_MASK   (0x40U)
#define	CAN_ESR1_TX_SHIFT   (6U)
#define	CAN_ESR1_TX(x)
#define	CAN_ESR1_IDLE_MASK   (0x80U)
#define	CAN_ESR1_IDLE_SHIFT   (7U)
#define	CAN_ESR1_IDLE(x)
#define	CAN_ESR1_RXWRN_MASK   (0x100U)
#define	CAN_ESR1_RXWRN_SHIFT   (8U)
#define	CAN_ESR1_RXWRN(x)
#define	CAN_ESR1_TXWRN_MASK   (0x200U)
#define	CAN_ESR1_TXWRN_SHIFT   (9U)
#define	CAN_ESR1_TXWRN(x)
#define	CAN_ESR1_STFERR_MASK   (0x400U)
#define	CAN_ESR1_STFERR_SHIFT   (10U)
#define	CAN_ESR1_STFERR(x)
#define	CAN_ESR1_FRMERR_MASK   (0x800U)
#define	CAN_ESR1_FRMERR_SHIFT   (11U)
#define	CAN_ESR1_FRMERR(x)
#define	CAN_ESR1_CRCERR_MASK   (0x1000U)
#define	CAN_ESR1_CRCERR_SHIFT   (12U)
#define	CAN_ESR1_CRCERR(x)
#define	CAN_ESR1_ACKERR_MASK   (0x2000U)
#define	CAN_ESR1_ACKERR_SHIFT   (13U)
#define	CAN_ESR1_ACKERR(x)
#define	CAN_ESR1_BIT0ERR_MASK   (0x4000U)
#define	CAN_ESR1_BIT0ERR_SHIFT   (14U)
#define	CAN_ESR1_BIT0ERR(x)
#define	CAN_ESR1_BIT1ERR_MASK   (0x8000U)
#define	CAN_ESR1_BIT1ERR_SHIFT   (15U)
#define	CAN_ESR1_BIT1ERR(x)
#define	CAN_ESR1_RWRNINT_MASK   (0x10000U)
#define	CAN_ESR1_RWRNINT_SHIFT   (16U)
#define	CAN_ESR1_RWRNINT(x)
#define	CAN_ESR1_TWRNINT_MASK   (0x20000U)
#define	CAN_ESR1_TWRNINT_SHIFT   (17U)
#define	CAN_ESR1_TWRNINT(x)
#define	CAN_ESR1_SYNCH_MASK   (0x40000U)
#define	CAN_ESR1_SYNCH_SHIFT   (18U)
#define	CAN_ESR1_SYNCH(x)
#define	CAN_ESR1_BOFFDONEINT_MASK   (0x80000U)
#define	CAN_ESR1_BOFFDONEINT_SHIFT   (19U)
#define	CAN_ESR1_BOFFDONEINT(x)
#define	CAN_ESR1_ERRINT_FAST_MASK   (0x100000U)
#define	CAN_ESR1_ERRINT_FAST_SHIFT   (20U)
#define	CAN_ESR1_ERRINT_FAST(x)
#define	CAN_ESR1_ERROVR_MASK   (0x200000U)
#define	CAN_ESR1_ERROVR_SHIFT   (21U)
#define	CAN_ESR1_ERROVR(x)
#define	CAN_ESR1_STFERR_FAST_MASK   (0x4000000U)
#define	CAN_ESR1_STFERR_FAST_SHIFT   (26U)
#define	CAN_ESR1_STFERR_FAST(x)
#define	CAN_ESR1_FRMERR_FAST_MASK   (0x8000000U)
#define	CAN_ESR1_FRMERR_FAST_SHIFT   (27U)
#define	CAN_ESR1_FRMERR_FAST(x)
#define	CAN_ESR1_CRCERR_FAST_MASK   (0x10000000U)
#define	CAN_ESR1_CRCERR_FAST_SHIFT   (28U)
#define	CAN_ESR1_CRCERR_FAST(x)
#define	CAN_ESR1_BIT0ERR_FAST_MASK   (0x40000000U)
#define	CAN_ESR1_BIT0ERR_FAST_SHIFT   (30U)
#define	CAN_ESR1_BIT0ERR_FAST(x)
#define	CAN_ESR1_BIT1ERR_FAST_MASK   (0x80000000U)
#define	CAN_ESR1_BIT1ERR_FAST_SHIFT   (31U)
#define	CAN_ESR1_BIT1ERR_FAST(x)
IMASK2 - Interrupt Masks 2 register
#define	CAN_IMASK2_BUF63TO32M_MASK   (0xFFFFFFFFU)
#define	CAN_IMASK2_BUF63TO32M_SHIFT   (0U)
#define	CAN_IMASK2_BUF63TO32M(x)
IMASK1 - Interrupt Masks 1 register
#define	CAN_IMASK1_BUF31TO0M_MASK   (0xFFFFFFFFU)
#define	CAN_IMASK1_BUF31TO0M_SHIFT   (0U)
#define	CAN_IMASK1_BUF31TO0M(x)
IFLAG2 - Interrupt Flags 2 register
#define	CAN_IFLAG2_BUF63TO32I_MASK   (0xFFFFFFFFU)
#define	CAN_IFLAG2_BUF63TO32I_SHIFT   (0U)
#define	CAN_IFLAG2_BUF63TO32I(x)
IFLAG1 - Interrupt Flags 1 register
#define	CAN_IFLAG1_BUF0I_MASK   (0x1U)
#define	CAN_IFLAG1_BUF0I_SHIFT   (0U)
#define	CAN_IFLAG1_BUF0I(x)
#define	CAN_IFLAG1_BUF4TO1I_MASK   (0x1EU)
#define	CAN_IFLAG1_BUF4TO1I_SHIFT   (1U)
#define	CAN_IFLAG1_BUF4TO1I(x)
#define	CAN_IFLAG1_BUF5I_MASK   (0x20U)
#define	CAN_IFLAG1_BUF5I_SHIFT   (5U)
#define	CAN_IFLAG1_BUF5I(x)
#define	CAN_IFLAG1_BUF6I_MASK   (0x40U)
#define	CAN_IFLAG1_BUF6I_SHIFT   (6U)
#define	CAN_IFLAG1_BUF6I(x)
#define	CAN_IFLAG1_BUF7I_MASK   (0x80U)
#define	CAN_IFLAG1_BUF7I_SHIFT   (7U)
#define	CAN_IFLAG1_BUF7I(x)
#define	CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
#define	CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
#define	CAN_IFLAG1_BUF31TO8I(x)
CTRL2 - Control 2 register
#define	CAN_CTRL2_EDFLTDIS_MASK   (0x800U)
#define	CAN_CTRL2_EDFLTDIS_SHIFT   (11U)
#define	CAN_CTRL2_EDFLTDIS(x)
#define	CAN_CTRL2_ISOCANFDEN_MASK   (0x1000U)
#define	CAN_CTRL2_ISOCANFDEN_SHIFT   (12U)
#define	CAN_CTRL2_ISOCANFDEN(x)
#define	CAN_CTRL2_PREXCEN_MASK   (0x4000U)
#define	CAN_CTRL2_PREXCEN_SHIFT   (14U)
#define	CAN_CTRL2_PREXCEN(x)
#define	CAN_CTRL2_TIMER_SRC_MASK   (0x8000U)
#define	CAN_CTRL2_TIMER_SRC_SHIFT   (15U)
#define	CAN_CTRL2_TIMER_SRC(x)
#define	CAN_CTRL2_EACEN_MASK   (0x10000U)
#define	CAN_CTRL2_EACEN_SHIFT   (16U)
#define	CAN_CTRL2_EACEN(x)
#define	CAN_CTRL2_RRS_MASK   (0x20000U)
#define	CAN_CTRL2_RRS_SHIFT   (17U)
#define	CAN_CTRL2_RRS(x)
#define	CAN_CTRL2_MRP_MASK   (0x40000U)
#define	CAN_CTRL2_MRP_SHIFT   (18U)
#define	CAN_CTRL2_MRP(x)
#define	CAN_CTRL2_TASD_MASK   (0xF80000U)
#define	CAN_CTRL2_TASD_SHIFT   (19U)
#define	CAN_CTRL2_TASD(x)
#define	CAN_CTRL2_RFFN_MASK   (0xF000000U)
#define	CAN_CTRL2_RFFN_SHIFT   (24U)
#define	CAN_CTRL2_RFFN(x)
#define	CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)
#define	CAN_CTRL2_WRMFRZ_SHIFT   (28U)
#define	CAN_CTRL2_WRMFRZ(x)
#define	CAN_CTRL2_ECRWRE_MASK   (0x20000000U)
#define	CAN_CTRL2_ECRWRE_SHIFT   (29U)
#define	CAN_CTRL2_ECRWRE(x)
#define	CAN_CTRL2_BOFFDONEMSK_MASK   (0x40000000U)
#define	CAN_CTRL2_BOFFDONEMSK_SHIFT   (30U)
#define	CAN_CTRL2_BOFFDONEMSK(x)
#define	CAN_CTRL2_ERRMSK_FAST_MASK   (0x80000000U)
#define	CAN_CTRL2_ERRMSK_FAST_SHIFT   (31U)
#define	CAN_CTRL2_ERRMSK_FAST(x)
#define	ENC_CTRL2_UPDHLD_MASK   (0x1U)
#define	ENC_CTRL2_UPDHLD_SHIFT   (0U)
#define	ENC_CTRL2_UPDHLD(x)
#define	ENC_CTRL2_UPDPOS_MASK   (0x2U)
#define	ENC_CTRL2_UPDPOS_SHIFT   (1U)
#define	ENC_CTRL2_UPDPOS(x)
#define	ENC_CTRL2_MOD_MASK   (0x4U)
#define	ENC_CTRL2_MOD_SHIFT   (2U)
#define	ENC_CTRL2_MOD(x)
#define	ENC_CTRL2_DIR_MASK   (0x8U)
#define	ENC_CTRL2_DIR_SHIFT   (3U)
#define	ENC_CTRL2_DIR(x)
#define	ENC_CTRL2_RUIE_MASK   (0x10U)
#define	ENC_CTRL2_RUIE_SHIFT   (4U)
#define	ENC_CTRL2_RUIE(x)
#define	ENC_CTRL2_RUIRQ_MASK   (0x20U)
#define	ENC_CTRL2_RUIRQ_SHIFT   (5U)
#define	ENC_CTRL2_RUIRQ(x)
#define	ENC_CTRL2_ROIE_MASK   (0x40U)
#define	ENC_CTRL2_ROIE_SHIFT   (6U)
#define	ENC_CTRL2_ROIE(x)
#define	ENC_CTRL2_ROIRQ_MASK   (0x80U)
#define	ENC_CTRL2_ROIRQ_SHIFT   (7U)
#define	ENC_CTRL2_ROIRQ(x)
#define	ENC_CTRL2_REVMOD_MASK   (0x100U)
#define	ENC_CTRL2_REVMOD_SHIFT   (8U)
#define	ENC_CTRL2_REVMOD(x)
#define	ENC_CTRL2_OUTCTL_MASK   (0x200U)
#define	ENC_CTRL2_OUTCTL_SHIFT   (9U)
#define	ENC_CTRL2_OUTCTL(x)
#define	ENC_CTRL2_SABIE_MASK   (0x400U)
#define	ENC_CTRL2_SABIE_SHIFT   (10U)
#define	ENC_CTRL2_SABIE(x)
#define	ENC_CTRL2_SABIRQ_MASK   (0x800U)
#define	ENC_CTRL2_SABIRQ_SHIFT   (11U)
#define	ENC_CTRL2_SABIRQ(x)
#define	PWM_CTRL2_CLK_SEL_MASK   (0x3U)
#define	PWM_CTRL2_CLK_SEL_SHIFT   (0U)
#define	PWM_CTRL2_CLK_SEL(x)
#define	PWM_CTRL2_RELOAD_SEL_MASK   (0x4U)
#define	PWM_CTRL2_RELOAD_SEL_SHIFT   (2U)
#define	PWM_CTRL2_RELOAD_SEL(x)
#define	PWM_CTRL2_FORCE_SEL_MASK   (0x38U)
#define	PWM_CTRL2_FORCE_SEL_SHIFT   (3U)
#define	PWM_CTRL2_FORCE_SEL(x)
#define	PWM_CTRL2_FORCE_MASK   (0x40U)
#define	PWM_CTRL2_FORCE_SHIFT   (6U)
#define	PWM_CTRL2_FORCE(x)
#define	PWM_CTRL2_FRCEN_MASK   (0x80U)
#define	PWM_CTRL2_FRCEN_SHIFT   (7U)
#define	PWM_CTRL2_FRCEN(x)
#define	PWM_CTRL2_INIT_SEL_MASK   (0x300U)
#define	PWM_CTRL2_INIT_SEL_SHIFT   (8U)
#define	PWM_CTRL2_INIT_SEL(x)
#define	PWM_CTRL2_PWMX_INIT_MASK   (0x400U)
#define	PWM_CTRL2_PWMX_INIT_SHIFT   (10U)
#define	PWM_CTRL2_PWMX_INIT(x)
#define	PWM_CTRL2_PWM45_INIT_MASK   (0x800U)
#define	PWM_CTRL2_PWM45_INIT_SHIFT   (11U)
#define	PWM_CTRL2_PWM45_INIT(x)
#define	PWM_CTRL2_PWM23_INIT_MASK   (0x1000U)
#define	PWM_CTRL2_PWM23_INIT_SHIFT   (12U)
#define	PWM_CTRL2_PWM23_INIT(x)
#define	PWM_CTRL2_INDEP_MASK   (0x2000U)
#define	PWM_CTRL2_INDEP_SHIFT   (13U)
#define	PWM_CTRL2_INDEP(x)
#define	PWM_CTRL2_WAITEN_MASK   (0x4000U)
#define	PWM_CTRL2_WAITEN_SHIFT   (14U)
#define	PWM_CTRL2_WAITEN(x)
#define	PWM_CTRL2_DBGEN_MASK   (0x8000U)
#define	PWM_CTRL2_DBGEN_SHIFT   (15U)
#define	PWM_CTRL2_DBGEN(x)
ESR2 - Error and Status 2 register
#define	CAN_ESR2_IMB_MASK   (0x2000U)
#define	CAN_ESR2_IMB_SHIFT   (13U)
#define	CAN_ESR2_IMB(x)
#define	CAN_ESR2_VPS_MASK   (0x4000U)
#define	CAN_ESR2_VPS_SHIFT   (14U)
#define	CAN_ESR2_VPS(x)
#define	CAN_ESR2_LPTM_MASK   (0x7F0000U)
#define	CAN_ESR2_LPTM_SHIFT   (16U)
#define	CAN_ESR2_LPTM(x)
CRCR - CRC register
#define	CAN_CRCR_TXCRC_MASK   (0x7FFFU)
#define	CAN_CRCR_TXCRC_SHIFT   (0U)
#define	CAN_CRCR_TXCRC(x)
#define	CAN_CRCR_MBCRC_MASK   (0x7F0000U)
#define	CAN_CRCR_MBCRC_SHIFT   (16U)
#define	CAN_CRCR_MBCRC(x)
RXFGMASK - Rx FIFO Global Mask register
#define	CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
#define	CAN_RXFGMASK_FGM_SHIFT   (0U)
#define	CAN_RXFGMASK_FGM(x)
RXFIR - Rx FIFO Information register
#define	CAN_RXFIR_IDHIT_MASK   (0x1FFU)
#define	CAN_RXFIR_IDHIT_SHIFT   (0U)
#define	CAN_RXFIR_IDHIT(x)
CBT - CAN Bit Timing register
#define	CAN_CBT_EPSEG2_MASK   (0x1FU)
#define	CAN_CBT_EPSEG2_SHIFT   (0U)
#define	CAN_CBT_EPSEG2(x)
#define	CAN_CBT_EPSEG1_MASK   (0x3E0U)
#define	CAN_CBT_EPSEG1_SHIFT   (5U)
#define	CAN_CBT_EPSEG1(x)
#define	CAN_CBT_EPROPSEG_MASK   (0xFC00U)
#define	CAN_CBT_EPROPSEG_SHIFT   (10U)
#define	CAN_CBT_EPROPSEG(x)
#define	CAN_CBT_ERJW_MASK   (0x1F0000U)
#define	CAN_CBT_ERJW_SHIFT   (16U)
#define	CAN_CBT_ERJW(x)
#define	CAN_CBT_EPRESDIV_MASK   (0x7FE00000U)
#define	CAN_CBT_EPRESDIV_SHIFT   (21U)
#define	CAN_CBT_EPRESDIV(x)
#define	CAN_CBT_BTF_MASK   (0x80000000U)
#define	CAN_CBT_BTF_SHIFT   (31U)
#define	CAN_CBT_BTF(x)
CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register
#define	CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
#define	CAN_CS_TIME_STAMP_SHIFT   (0U)
#define	CAN_CS_TIME_STAMP(x)
#define	CAN_CS_DLC_MASK   (0xF0000U)
#define	CAN_CS_DLC_SHIFT   (16U)
#define	CAN_CS_DLC(x)
#define	CAN_CS_RTR_MASK   (0x100000U)
#define	CAN_CS_RTR_SHIFT   (20U)
#define	CAN_CS_RTR(x)
#define	CAN_CS_IDE_MASK   (0x200000U)
#define	CAN_CS_IDE_SHIFT   (21U)
#define	CAN_CS_IDE(x)
#define	CAN_CS_SRR_MASK   (0x400000U)
#define	CAN_CS_SRR_SHIFT   (22U)
#define	CAN_CS_SRR(x)
#define	CAN_CS_CODE_MASK   (0xF000000U)
#define	CAN_CS_CODE_SHIFT   (24U)
#define	CAN_CS_CODE(x)
#define	CAN_CS_ESI_MASK   (0x20000000U)
#define	CAN_CS_ESI_SHIFT   (29U)
#define	CAN_CS_ESI(x)
#define	CAN_CS_BRS_MASK   (0x40000000U)
#define	CAN_CS_BRS_SHIFT   (30U)
#define	CAN_CS_BRS(x)
#define	CAN_CS_EDL_MASK   (0x80000000U)
#define	CAN_CS_EDL_SHIFT   (31U)
#define	CAN_CS_EDL(x)
#define	CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
#define	CAN_CS_TIME_STAMP_SHIFT   (0U)
#define	CAN_CS_TIME_STAMP(x)
#define	CAN_CS_DLC_MASK   (0xF0000U)
#define	CAN_CS_DLC_SHIFT   (16U)
#define	CAN_CS_DLC(x)
#define	CAN_CS_RTR_MASK   (0x100000U)
#define	CAN_CS_RTR_SHIFT   (20U)
#define	CAN_CS_RTR(x)
#define	CAN_CS_IDE_MASK   (0x200000U)
#define	CAN_CS_IDE_SHIFT   (21U)
#define	CAN_CS_IDE(x)
#define	CAN_CS_SRR_MASK   (0x400000U)
#define	CAN_CS_SRR_SHIFT   (22U)
#define	CAN_CS_SRR(x)
#define	CAN_CS_CODE_MASK   (0xF000000U)
#define	CAN_CS_CODE_SHIFT   (24U)
#define	CAN_CS_CODE(x)
#define	CAN_CS_ESI_MASK   (0x20000000U)
#define	CAN_CS_ESI_SHIFT   (29U)
#define	CAN_CS_ESI(x)
#define	CAN_CS_BRS_MASK   (0x40000000U)
#define	CAN_CS_BRS_SHIFT   (30U)
#define	CAN_CS_BRS(x)
#define	CAN_CS_EDL_MASK   (0x80000000U)
#define	CAN_CS_EDL_SHIFT   (31U)
#define	CAN_CS_EDL(x)
ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register
#define	CAN_ID_EXT_MASK   (0x3FFFFU)
#define	CAN_ID_EXT_SHIFT   (0U)
#define	CAN_ID_EXT(x)
#define	CAN_ID_STD_MASK   (0x1FFC0000U)
#define	CAN_ID_STD_SHIFT   (18U)
#define	CAN_ID_STD(x)
#define	CAN_ID_PRIO_MASK   (0xE0000000U)
#define	CAN_ID_PRIO_SHIFT   (29U)
#define	CAN_ID_PRIO(x)
#define	CAN_ID_EXT_MASK   (0x3FFFFU)
#define	CAN_ID_EXT_SHIFT   (0U)
#define	CAN_ID_EXT(x)
#define	CAN_ID_STD_MASK   (0x1FFC0000U)
#define	CAN_ID_STD_SHIFT   (18U)
#define	CAN_ID_STD(x)
#define	CAN_ID_PRIO_MASK   (0xE0000000U)
#define	CAN_ID_PRIO_SHIFT   (29U)
#define	CAN_ID_PRIO(x)
WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register
#define	CAN_WORD_DATA_BYTE_3_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_3_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_3(x)
#define	CAN_WORD_DATA_BYTE_7_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_7_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_7(x)
#define	CAN_WORD_DATA_BYTE_11_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_11_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_11(x)
#define	CAN_WORD_DATA_BYTE_15_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_15_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_15(x)
#define	CAN_WORD_DATA_BYTE_19_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_19_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_19(x)
#define	CAN_WORD_DATA_BYTE_23_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_23_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_23(x)
#define	CAN_WORD_DATA_BYTE_27_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_27_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_27(x)
#define	CAN_WORD_DATA_BYTE_31_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_31_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_31(x)
#define	CAN_WORD_DATA_BYTE_35_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_35_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_35(x)
#define	CAN_WORD_DATA_BYTE_39_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_39_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_39(x)
#define	CAN_WORD_DATA_BYTE_43_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_43_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_43(x)
#define	CAN_WORD_DATA_BYTE_47_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_47_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_47(x)
#define	CAN_WORD_DATA_BYTE_51_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_51_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_51(x)
#define	CAN_WORD_DATA_BYTE_55_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_55_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_55(x)
#define	CAN_WORD_DATA_BYTE_59_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_59_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_59(x)
#define	CAN_WORD_DATA_BYTE_63_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_63_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_63(x)
#define	CAN_WORD_DATA_BYTE_2_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_2_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_2(x)
#define	CAN_WORD_DATA_BYTE_6_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_6_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_6(x)
#define	CAN_WORD_DATA_BYTE_10_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_10_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_10(x)
#define	CAN_WORD_DATA_BYTE_14_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_14_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_14(x)
#define	CAN_WORD_DATA_BYTE_18_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_18_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_18(x)
#define	CAN_WORD_DATA_BYTE_22_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_22_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_22(x)
#define	CAN_WORD_DATA_BYTE_26_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_26_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_26(x)
#define	CAN_WORD_DATA_BYTE_30_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_30_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_30(x)
#define	CAN_WORD_DATA_BYTE_34_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_34_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_34(x)
#define	CAN_WORD_DATA_BYTE_38_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_38_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_38(x)
#define	CAN_WORD_DATA_BYTE_42_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_42_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_42(x)
#define	CAN_WORD_DATA_BYTE_46_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_46_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_46(x)
#define	CAN_WORD_DATA_BYTE_50_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_50_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_50(x)
#define	CAN_WORD_DATA_BYTE_54_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_54_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_54(x)
#define	CAN_WORD_DATA_BYTE_58_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_58_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_58(x)
#define	CAN_WORD_DATA_BYTE_62_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_62_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_62(x)
#define	CAN_WORD_DATA_BYTE_1_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_1_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_1(x)
#define	CAN_WORD_DATA_BYTE_5_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_5_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_5(x)
#define	CAN_WORD_DATA_BYTE_9_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_9_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_9(x)
#define	CAN_WORD_DATA_BYTE_13_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_13_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_13(x)
#define	CAN_WORD_DATA_BYTE_17_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_17_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_17(x)
#define	CAN_WORD_DATA_BYTE_21_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_21_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_21(x)
#define	CAN_WORD_DATA_BYTE_25_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_25_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_25(x)
#define	CAN_WORD_DATA_BYTE_29_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_29_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_29(x)
#define	CAN_WORD_DATA_BYTE_33_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_33_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_33(x)
#define	CAN_WORD_DATA_BYTE_37_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_37_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_37(x)
#define	CAN_WORD_DATA_BYTE_41_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_41_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_41(x)
#define	CAN_WORD_DATA_BYTE_45_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_45_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_45(x)
#define	CAN_WORD_DATA_BYTE_49_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_49_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_49(x)
#define	CAN_WORD_DATA_BYTE_53_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_53_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_53(x)
#define	CAN_WORD_DATA_BYTE_57_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_57_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_57(x)
#define	CAN_WORD_DATA_BYTE_61_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_61_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_61(x)
#define	CAN_WORD_DATA_BYTE_0_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_0_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_0(x)
#define	CAN_WORD_DATA_BYTE_4_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_4_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_4(x)
#define	CAN_WORD_DATA_BYTE_8_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_8_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_8(x)
#define	CAN_WORD_DATA_BYTE_12_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_12_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_12(x)
#define	CAN_WORD_DATA_BYTE_16_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_16_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_16(x)
#define	CAN_WORD_DATA_BYTE_20_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_20_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_20(x)
#define	CAN_WORD_DATA_BYTE_24_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_24_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_24(x)
#define	CAN_WORD_DATA_BYTE_28_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_28_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_28(x)
#define	CAN_WORD_DATA_BYTE_32_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_32_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_32(x)
#define	CAN_WORD_DATA_BYTE_36_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_36_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_36(x)
#define	CAN_WORD_DATA_BYTE_40_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_40_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_40(x)
#define	CAN_WORD_DATA_BYTE_44_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_44_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_44(x)
#define	CAN_WORD_DATA_BYTE_48_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_48_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_48(x)
#define	CAN_WORD_DATA_BYTE_52_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_52_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_52(x)
#define	CAN_WORD_DATA_BYTE_56_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_56_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_56(x)
#define	CAN_WORD_DATA_BYTE_60_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_60_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_60(x)
#define	CAN_WORD_DATA_BYTE_3_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_3_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_3(x)
#define	CAN_WORD_DATA_BYTE_7_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_7_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_7(x)
#define	CAN_WORD_DATA_BYTE_11_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_11_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_11(x)
#define	CAN_WORD_DATA_BYTE_15_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_15_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_15(x)
#define	CAN_WORD_DATA_BYTE_19_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_19_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_19(x)
#define	CAN_WORD_DATA_BYTE_23_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_23_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_23(x)
#define	CAN_WORD_DATA_BYTE_27_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_27_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_27(x)
#define	CAN_WORD_DATA_BYTE_31_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_31_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_31(x)
#define	CAN_WORD_DATA_BYTE_35_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_35_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_35(x)
#define	CAN_WORD_DATA_BYTE_39_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_39_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_39(x)
#define	CAN_WORD_DATA_BYTE_43_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_43_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_43(x)
#define	CAN_WORD_DATA_BYTE_47_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_47_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_47(x)
#define	CAN_WORD_DATA_BYTE_51_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_51_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_51(x)
#define	CAN_WORD_DATA_BYTE_55_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_55_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_55(x)
#define	CAN_WORD_DATA_BYTE_59_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_59_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_59(x)
#define	CAN_WORD_DATA_BYTE_63_MASK   (0xFFU)
#define	CAN_WORD_DATA_BYTE_63_SHIFT   (0U)
#define	CAN_WORD_DATA_BYTE_63(x)
#define	CAN_WORD_DATA_BYTE_2_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_2_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_2(x)
#define	CAN_WORD_DATA_BYTE_6_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_6_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_6(x)
#define	CAN_WORD_DATA_BYTE_10_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_10_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_10(x)
#define	CAN_WORD_DATA_BYTE_14_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_14_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_14(x)
#define	CAN_WORD_DATA_BYTE_18_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_18_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_18(x)
#define	CAN_WORD_DATA_BYTE_22_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_22_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_22(x)
#define	CAN_WORD_DATA_BYTE_26_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_26_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_26(x)
#define	CAN_WORD_DATA_BYTE_30_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_30_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_30(x)
#define	CAN_WORD_DATA_BYTE_34_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_34_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_34(x)
#define	CAN_WORD_DATA_BYTE_38_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_38_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_38(x)
#define	CAN_WORD_DATA_BYTE_42_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_42_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_42(x)
#define	CAN_WORD_DATA_BYTE_46_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_46_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_46(x)
#define	CAN_WORD_DATA_BYTE_50_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_50_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_50(x)
#define	CAN_WORD_DATA_BYTE_54_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_54_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_54(x)
#define	CAN_WORD_DATA_BYTE_58_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_58_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_58(x)
#define	CAN_WORD_DATA_BYTE_62_MASK   (0xFF00U)
#define	CAN_WORD_DATA_BYTE_62_SHIFT   (8U)
#define	CAN_WORD_DATA_BYTE_62(x)
#define	CAN_WORD_DATA_BYTE_1_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_1_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_1(x)
#define	CAN_WORD_DATA_BYTE_5_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_5_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_5(x)
#define	CAN_WORD_DATA_BYTE_9_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_9_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_9(x)
#define	CAN_WORD_DATA_BYTE_13_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_13_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_13(x)
#define	CAN_WORD_DATA_BYTE_17_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_17_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_17(x)
#define	CAN_WORD_DATA_BYTE_21_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_21_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_21(x)
#define	CAN_WORD_DATA_BYTE_25_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_25_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_25(x)
#define	CAN_WORD_DATA_BYTE_29_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_29_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_29(x)
#define	CAN_WORD_DATA_BYTE_33_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_33_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_33(x)
#define	CAN_WORD_DATA_BYTE_37_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_37_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_37(x)
#define	CAN_WORD_DATA_BYTE_41_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_41_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_41(x)
#define	CAN_WORD_DATA_BYTE_45_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_45_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_45(x)
#define	CAN_WORD_DATA_BYTE_49_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_49_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_49(x)
#define	CAN_WORD_DATA_BYTE_53_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_53_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_53(x)
#define	CAN_WORD_DATA_BYTE_57_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_57_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_57(x)
#define	CAN_WORD_DATA_BYTE_61_MASK   (0xFF0000U)
#define	CAN_WORD_DATA_BYTE_61_SHIFT   (16U)
#define	CAN_WORD_DATA_BYTE_61(x)
#define	CAN_WORD_DATA_BYTE_0_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_0_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_0(x)
#define	CAN_WORD_DATA_BYTE_4_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_4_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_4(x)
#define	CAN_WORD_DATA_BYTE_8_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_8_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_8(x)
#define	CAN_WORD_DATA_BYTE_12_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_12_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_12(x)
#define	CAN_WORD_DATA_BYTE_16_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_16_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_16(x)
#define	CAN_WORD_DATA_BYTE_20_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_20_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_20(x)
#define	CAN_WORD_DATA_BYTE_24_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_24_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_24(x)
#define	CAN_WORD_DATA_BYTE_28_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_28_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_28(x)
#define	CAN_WORD_DATA_BYTE_32_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_32_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_32(x)
#define	CAN_WORD_DATA_BYTE_36_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_36_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_36(x)
#define	CAN_WORD_DATA_BYTE_40_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_40_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_40(x)
#define	CAN_WORD_DATA_BYTE_44_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_44_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_44(x)
#define	CAN_WORD_DATA_BYTE_48_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_48_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_48(x)
#define	CAN_WORD_DATA_BYTE_52_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_52_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_52(x)
#define	CAN_WORD_DATA_BYTE_56_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_56_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_56(x)
#define	CAN_WORD_DATA_BYTE_60_MASK   (0xFF000000U)
#define	CAN_WORD_DATA_BYTE_60_SHIFT   (24U)
#define	CAN_WORD_DATA_BYTE_60(x)
WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register
#define	CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
#define	CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
#define	CAN_WORD0_DATA_BYTE_3(x)
#define	CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
#define	CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
#define	CAN_WORD0_DATA_BYTE_2(x)
#define	CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
#define	CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
#define	CAN_WORD0_DATA_BYTE_1(x)
#define	CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
#define	CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
#define	CAN_WORD0_DATA_BYTE_0(x)
WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register
#define	CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
#define	CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
#define	CAN_WORD1_DATA_BYTE_7(x)
#define	CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
#define	CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
#define	CAN_WORD1_DATA_BYTE_6(x)
#define	CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
#define	CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
#define	CAN_WORD1_DATA_BYTE_5(x)
#define	CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
#define	CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
#define	CAN_WORD1_DATA_BYTE_4(x)
RXIMR - Rx Individual Mask registers
#define	CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
#define	CAN_RXIMR_MI_SHIFT   (0U)
#define	CAN_RXIMR_MI(x)
MECR - Memory Error Control register
#define	CAN_MECR_NCEFAFRZ_MASK   (0x80U)
#define	CAN_MECR_NCEFAFRZ_SHIFT   (7U)
#define	CAN_MECR_NCEFAFRZ(x)
#define	CAN_MECR_ECCDIS_MASK   (0x100U)
#define	CAN_MECR_ECCDIS_SHIFT   (8U)
#define	CAN_MECR_ECCDIS(x)
#define	CAN_MECR_RERRDIS_MASK   (0x200U)
#define	CAN_MECR_RERRDIS_SHIFT   (9U)
#define	CAN_MECR_RERRDIS(x)
#define	CAN_MECR_EXTERRIE_MASK   (0x2000U)
#define	CAN_MECR_EXTERRIE_SHIFT   (13U)
#define	CAN_MECR_EXTERRIE(x)
#define	CAN_MECR_FAERRIE_MASK   (0x4000U)
#define	CAN_MECR_FAERRIE_SHIFT   (14U)
#define	CAN_MECR_FAERRIE(x)
#define	CAN_MECR_HAERRIE_MASK   (0x8000U)
#define	CAN_MECR_HAERRIE_SHIFT   (15U)
#define	CAN_MECR_HAERRIE(x)
#define	CAN_MECR_CEI_MSK_MASK   (0x10000U)
#define	CAN_MECR_CEI_MSK_SHIFT   (16U)
#define	CAN_MECR_CEI_MSK(x)
#define	CAN_MECR_FANCEI_MSK_MASK   (0x40000U)
#define	CAN_MECR_FANCEI_MSK_SHIFT   (18U)
#define	CAN_MECR_FANCEI_MSK(x)
#define	CAN_MECR_HANCEI_MSK_MASK   (0x80000U)
#define	CAN_MECR_HANCEI_MSK_SHIFT   (19U)
#define	CAN_MECR_HANCEI_MSK(x)
#define	CAN_MECR_ECRWRDIS_MASK   (0x80000000U)
#define	CAN_MECR_ECRWRDIS_SHIFT   (31U)
#define	CAN_MECR_ECRWRDIS(x)
ERRIAR - Error Injection Address register
#define	CAN_ERRIAR_INJADDR_L_MASK   (0x3U)
#define	CAN_ERRIAR_INJADDR_L_SHIFT   (0U)
#define	CAN_ERRIAR_INJADDR_L(x)
#define	CAN_ERRIAR_INJADDR_H_MASK   (0x3FFCU)
#define	CAN_ERRIAR_INJADDR_H_SHIFT   (2U)
#define	CAN_ERRIAR_INJADDR_H(x)
ERRIDPR - Error Injection Data Pattern register
#define	CAN_ERRIDPR_DFLIP_MASK   (0xFFFFFFFFU)
#define	CAN_ERRIDPR_DFLIP_SHIFT   (0U)
#define	CAN_ERRIDPR_DFLIP(x)
ERRIPPR - Error Injection Parity Pattern register
#define	CAN_ERRIPPR_PFLIP0_MASK   (0x1FU)
#define	CAN_ERRIPPR_PFLIP0_SHIFT   (0U)
#define	CAN_ERRIPPR_PFLIP0(x)
#define	CAN_ERRIPPR_PFLIP1_MASK   (0x1F00U)
#define	CAN_ERRIPPR_PFLIP1_SHIFT   (8U)
#define	CAN_ERRIPPR_PFLIP1(x)
#define	CAN_ERRIPPR_PFLIP2_MASK   (0x1F0000U)
#define	CAN_ERRIPPR_PFLIP2_SHIFT   (16U)
#define	CAN_ERRIPPR_PFLIP2(x)
#define	CAN_ERRIPPR_PFLIP3_MASK   (0x1F000000U)
#define	CAN_ERRIPPR_PFLIP3_SHIFT   (24U)
#define	CAN_ERRIPPR_PFLIP3(x)
RERRAR - Error Report Address register
#define	CAN_RERRAR_ERRADDR_MASK   (0x3FFFU)
#define	CAN_RERRAR_ERRADDR_SHIFT   (0U)
#define	CAN_RERRAR_ERRADDR(x)
#define	CAN_RERRAR_SAID_MASK   (0x70000U)
#define	CAN_RERRAR_SAID_SHIFT   (16U)
#define	CAN_RERRAR_SAID(x)
#define	CAN_RERRAR_NCE_MASK   (0x1000000U)
#define	CAN_RERRAR_NCE_SHIFT   (24U)
#define	CAN_RERRAR_NCE(x)
RERRDR - Error Report Data register
#define	CAN_RERRDR_RDATA_MASK   (0xFFFFFFFFU)
#define	CAN_RERRDR_RDATA_SHIFT   (0U)
#define	CAN_RERRDR_RDATA(x)
RERRSYNR - Error Report Syndrome register
#define	CAN_RERRSYNR_SYND0_MASK   (0x1FU)
#define	CAN_RERRSYNR_SYND0_SHIFT   (0U)
#define	CAN_RERRSYNR_SYND0(x)
#define	CAN_RERRSYNR_BE0_MASK   (0x80U)
#define	CAN_RERRSYNR_BE0_SHIFT   (7U)
#define	CAN_RERRSYNR_BE0(x)
#define	CAN_RERRSYNR_SYND1_MASK   (0x1F00U)
#define	CAN_RERRSYNR_SYND1_SHIFT   (8U)
#define	CAN_RERRSYNR_SYND1(x)
#define	CAN_RERRSYNR_BE1_MASK   (0x8000U)
#define	CAN_RERRSYNR_BE1_SHIFT   (15U)
#define	CAN_RERRSYNR_BE1(x)
#define	CAN_RERRSYNR_SYND2_MASK   (0x1F0000U)
#define	CAN_RERRSYNR_SYND2_SHIFT   (16U)
#define	CAN_RERRSYNR_SYND2(x)
#define	CAN_RERRSYNR_BE2_MASK   (0x800000U)
#define	CAN_RERRSYNR_BE2_SHIFT   (23U)
#define	CAN_RERRSYNR_BE2(x)
#define	CAN_RERRSYNR_SYND3_MASK   (0x1F000000U)
#define	CAN_RERRSYNR_SYND3_SHIFT   (24U)
#define	CAN_RERRSYNR_SYND3(x)
#define	CAN_RERRSYNR_BE3_MASK   (0x80000000U)
#define	CAN_RERRSYNR_BE3_SHIFT   (31U)
#define	CAN_RERRSYNR_BE3(x)
ERRSR - Error Status register
#define	CAN_ERRSR_CEIOF_MASK   (0x1U)
#define	CAN_ERRSR_CEIOF_SHIFT   (0U)
#define	CAN_ERRSR_CEIOF(x)
#define	CAN_ERRSR_FANCEIOF_MASK   (0x4U)
#define	CAN_ERRSR_FANCEIOF_SHIFT   (2U)
#define	CAN_ERRSR_FANCEIOF(x)
#define	CAN_ERRSR_HANCEIOF_MASK   (0x8U)
#define	CAN_ERRSR_HANCEIOF_SHIFT   (3U)
#define	CAN_ERRSR_HANCEIOF(x)
#define	CAN_ERRSR_CEIF_MASK   (0x10000U)
#define	CAN_ERRSR_CEIF_SHIFT   (16U)
#define	CAN_ERRSR_CEIF(x)
#define	CAN_ERRSR_FANCEIF_MASK   (0x40000U)
#define	CAN_ERRSR_FANCEIF_SHIFT   (18U)
#define	CAN_ERRSR_FANCEIF(x)
#define	CAN_ERRSR_HANCEIF_MASK   (0x80000U)
#define	CAN_ERRSR_HANCEIF_SHIFT   (19U)
#define	CAN_ERRSR_HANCEIF(x)
FDCTRL - CAN FD Control register
#define	CAN_FDCTRL_TDCVAL_MASK   (0x3FU)
#define	CAN_FDCTRL_TDCVAL_SHIFT   (0U)
#define	CAN_FDCTRL_TDCVAL(x)
#define	CAN_FDCTRL_TDCOFF_MASK   (0x1F00U)
#define	CAN_FDCTRL_TDCOFF_SHIFT   (8U)
#define	CAN_FDCTRL_TDCOFF(x)
#define	CAN_FDCTRL_TDCFAIL_MASK   (0x4000U)
#define	CAN_FDCTRL_TDCFAIL_SHIFT   (14U)
#define	CAN_FDCTRL_TDCFAIL(x)
#define	CAN_FDCTRL_TDCEN_MASK   (0x8000U)
#define	CAN_FDCTRL_TDCEN_SHIFT   (15U)
#define	CAN_FDCTRL_TDCEN(x)
#define	CAN_FDCTRL_MBDSR0_MASK   (0x30000U)
#define	CAN_FDCTRL_MBDSR0_SHIFT   (16U)
#define	CAN_FDCTRL_MBDSR0(x)
#define	CAN_FDCTRL_MBDSR1_MASK   (0x180000U)
#define	CAN_FDCTRL_MBDSR1_SHIFT   (19U)
#define	CAN_FDCTRL_MBDSR1(x)
#define	CAN_FDCTRL_FDRATE_MASK   (0x80000000U)
#define	CAN_FDCTRL_FDRATE_SHIFT   (31U)
#define	CAN_FDCTRL_FDRATE(x)
FDCBT - CAN FD Bit Timing register
#define	CAN_FDCBT_FPSEG2_MASK   (0x7U)
#define	CAN_FDCBT_FPSEG2_SHIFT   (0U)
#define	CAN_FDCBT_FPSEG2(x)
#define	CAN_FDCBT_FPSEG1_MASK   (0xE0U)
#define	CAN_FDCBT_FPSEG1_SHIFT   (5U)
#define	CAN_FDCBT_FPSEG1(x)
#define	CAN_FDCBT_FPROPSEG_MASK   (0x7C00U)
#define	CAN_FDCBT_FPROPSEG_SHIFT   (10U)
#define	CAN_FDCBT_FPROPSEG(x)
#define	CAN_FDCBT_FRJW_MASK   (0x70000U)
#define	CAN_FDCBT_FRJW_SHIFT   (16U)
#define	CAN_FDCBT_FRJW(x)
#define	CAN_FDCBT_FPRESDIV_MASK   (0x3FF00000U)
#define	CAN_FDCBT_FPRESDIV_SHIFT   (20U)
#define	CAN_FDCBT_FPRESDIV(x)
FDCRC - CAN FD CRC register
#define	CAN_FDCRC_FD_TXCRC_MASK   (0x1FFFFFU)
#define	CAN_FDCRC_FD_TXCRC_SHIFT   (0U)
#define	CAN_FDCRC_FD_TXCRC(x)
#define	CAN_FDCRC_FD_MBCRC_MASK   (0x7F000000U)
#define	CAN_FDCRC_FD_MBCRC_SHIFT   (24U)
#define	CAN_FDCRC_FD_MBCRC(x)
GFWR - Glitch Filter Width Register
#define	CAN_WRAPPER_GFWR_GFWR_MASK   (0xFFU)
#define	CAN_WRAPPER_GFWR_GFWR_SHIFT   (0U)
#define	CAN_WRAPPER_GFWR_GFWR(x)
CLOCK_ROOT_CONTROL - Clock root control
#define	CCM_CLOCK_ROOT_CONTROL_DIV_MASK   (0xFFU)
#define	CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_CONTROL_DIV(x)
#define	CCM_CLOCK_ROOT_CONTROL_MUX_MASK   (0x700U)
#define	CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_CONTROL_MUX(x)
#define	CCM_CLOCK_ROOT_CONTROL_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_CONTROL_OFF(x)
CLOCK_ROOT_CONTROL_SET - Clock root control
#define	CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK   (0xFFU)
#define	CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_CONTROL_SET_DIV(x)
#define	CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK   (0x700U)
#define	CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_CONTROL_SET_MUX(x)
#define	CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_CONTROL_SET_OFF(x)
CLOCK_ROOT_CONTROL_CLR - Clock root control
#define	CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK   (0xFFU)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK   (0x700U)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x)
CLOCK_ROOT_CONTROL_TOG - Clock root control
#define	CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK   (0xFFU)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK   (0x700U)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x)
CLOCK_ROOT_STATUS0 - Clock root working status
#define	CCM_CLOCK_ROOT_STATUS0_DIV_MASK   (0xFFU)
#define	CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_STATUS0_DIV(x)
#define	CCM_CLOCK_ROOT_STATUS0_MUX_MASK   (0x700U)
#define	CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_STATUS0_MUX(x)
#define	CCM_CLOCK_ROOT_STATUS0_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_STATUS0_OFF(x)
#define	CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK   (0x8000000U)
#define	CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT   (27U)
#define	CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x)
#define	CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK   (0x10000000U)
#define	CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT   (28U)
#define	CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x)
#define	CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK   (0x20000000U)
#define	CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT   (29U)
#define	CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x)
#define	CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK   (0x40000000U)
#define	CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT   (30U)
#define	CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x)
#define	CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK   (0x80000000U)
#define	CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT   (31U)
#define	CCM_CLOCK_ROOT_STATUS0_CHANGING(x)
CLOCK_ROOT_STATUS1 - Clock root low power status
#define	CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK   (0xF0000U)
#define	CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
#define	CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x)
#define	CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
#define	CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT   (20U)
#define	CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x)
#define	CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x)
#define	CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK   (0x2000000U)
#define	CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT   (25U)
#define	CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x)
#define	CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK   (0x4000000U)
#define	CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT   (26U)
#define	CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x)
#define	CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK   (0x8000000U)
#define	CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT   (27U)
#define	CCM_CLOCK_ROOT_STATUS1_UP_DONE(x)
CLOCK_ROOT_CONFIG - Clock root configuration
#define	CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK   (0x10U)
#define	CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
#define	CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x)
CLOCK_ROOT_AUTHEN - Clock root access control
#define	CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x)
#define	CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x)
CLOCK_ROOT_AUTHEN_SET - Clock root access control
#define	CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x)
CLOCK_ROOT_AUTHEN_CLR - Clock root access control
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x)
CLOCK_ROOT_AUTHEN_TOG - Clock root access control
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x)
CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK   (0xFFU)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT   (0U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK   (0x700U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT   (8U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT   (24U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK   (0xF0000000U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT   (28U)
#define	CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x)
CLOCK_GROUP_CONTROL - Clock group control
#define	CCM_CLOCK_GROUP_CONTROL_DIV0_MASK   (0xFU)
#define	CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_CONTROL_DIV0(x)
#define	CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK   (0xFF0000U)
#define	CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_CONTROL_RSTDIV(x)
#define	CCM_CLOCK_GROUP_CONTROL_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_CONTROL_OFF(x)
CLOCK_GROUP_CONTROL_SET - Clock group control
#define	CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK   (0xFU)
#define	CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x)
#define	CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK   (0xFF0000U)
#define	CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x)
#define	CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_CONTROL_SET_OFF(x)
CLOCK_GROUP_CONTROL_CLR - Clock group control
#define	CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK   (0xFU)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK   (0xFF0000U)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x)
CLOCK_GROUP_CONTROL_TOG - Clock group control
#define	CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK   (0xFU)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK   (0xFF0000U)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x)
CLOCK_GROUP_STATUS0 - Clock group working status
#define	CCM_CLOCK_GROUP_STATUS0_DIV0_MASK   (0xFU)
#define	CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_STATUS0_DIV0(x)
#define	CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK   (0xFF0000U)
#define	CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_STATUS0_RSTDIV(x)
#define	CCM_CLOCK_GROUP_STATUS0_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_STATUS0_OFF(x)
#define	CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK   (0x8000000U)
#define	CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT   (27U)
#define	CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x)
#define	CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK   (0x10000000U)
#define	CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT   (28U)
#define	CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x)
#define	CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK   (0x20000000U)
#define	CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT   (29U)
#define	CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x)
#define	CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK   (0x40000000U)
#define	CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT   (30U)
#define	CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x)
#define	CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK   (0x80000000U)
#define	CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT   (31U)
#define	CCM_CLOCK_GROUP_STATUS0_CHANGING(x)
CLOCK_GROUP_STATUS1 - Clock group low power/extend status
#define	CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK   (0xF0000U)
#define	CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x)
#define	CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
#define	CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT   (20U)
#define	CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x)
#define	CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x)
#define	CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK   (0x2000000U)
#define	CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT   (25U)
#define	CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x)
#define	CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK   (0x4000000U)
#define	CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT   (26U)
#define	CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x)
#define	CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK   (0x8000000U)
#define	CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT   (27U)
#define	CCM_CLOCK_GROUP_STATUS1_UP_DONE(x)
CLOCK_GROUP_CONFIG - Clock group configuration
#define	CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK   (0x10U)
#define	CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
#define	CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x)
CLOCK_GROUP_AUTHEN - Clock group access control
#define	CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x)
#define	CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x)
CLOCK_GROUP_AUTHEN_SET - Clock group access control
#define	CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x)
CLOCK_GROUP_AUTHEN_CLR - Clock group access control
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x)
CLOCK_GROUP_AUTHEN_TOG - Clock group access control
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x)
CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK   (0xFU)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT   (0U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK   (0xFF0000U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT   (16U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK   (0x1000000U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT   (24U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK   (0xF0000000U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT   (28U)
#define	CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x)
GPR_SHARED - General Purpose Register
#define	CCM_GPR_SHARED_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_SHARED_GPR_SHIFT   (0U)
#define	CCM_GPR_SHARED_GPR(x)
GPR_SHARED_SET - General Purpose Register
#define	CCM_GPR_SHARED_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_SHARED_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_SHARED_SET_GPR(x)
GPR_SHARED_CLR - General Purpose Register
#define	CCM_GPR_SHARED_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_SHARED_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_SHARED_CLR_GPR(x)
GPR_SHARED_TOG - General Purpose Register
#define	CCM_GPR_SHARED_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_SHARED_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_SHARED_TOG_GPR(x)
GPR_SHARED_AUTHEN - GPR access control
#define	CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_SHARED_AUTHEN_TZ_USER(x)
#define	CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_SHARED_AUTHEN_TZ_NS(x)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x)
GPR_SHARED_AUTHEN_SET - GPR access control
#define	CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x)
GPR_SHARED_AUTHEN_CLR - GPR access control
#define	CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x)
GPR_SHARED_AUTHEN_TOG - GPR access control
#define	CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE1 - General Purpose Register
#define	CCM_GPR_PRIVATE1_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE1_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_GPR(x)
GPR_PRIVATE1_SET - General Purpose Register
#define	CCM_GPR_PRIVATE1_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE1_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_SET_GPR(x)
GPR_PRIVATE1_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE1_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE1_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_CLR_GPR(x)
GPR_PRIVATE1_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE1_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE1_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_TOG_GPR(x)
GPR_PRIVATE1_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE1_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE1_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE1_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE2 - General Purpose Register
#define	CCM_GPR_PRIVATE2_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE2_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_GPR(x)
GPR_PRIVATE2_SET - General Purpose Register
#define	CCM_GPR_PRIVATE2_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE2_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_SET_GPR(x)
GPR_PRIVATE2_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE2_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE2_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_CLR_GPR(x)
GPR_PRIVATE2_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE2_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE2_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_TOG_GPR(x)
GPR_PRIVATE2_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE2_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE2_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE2_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE3 - General Purpose Register
#define	CCM_GPR_PRIVATE3_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE3_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_GPR(x)
GPR_PRIVATE3_SET - General Purpose Register
#define	CCM_GPR_PRIVATE3_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE3_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_SET_GPR(x)
GPR_PRIVATE3_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE3_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE3_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_CLR_GPR(x)
GPR_PRIVATE3_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE3_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE3_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_TOG_GPR(x)
GPR_PRIVATE3_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE3_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE3_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE3_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE4 - General Purpose Register
#define	CCM_GPR_PRIVATE4_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE4_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_GPR(x)
GPR_PRIVATE4_SET - General Purpose Register
#define	CCM_GPR_PRIVATE4_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE4_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_SET_GPR(x)
GPR_PRIVATE4_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE4_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE4_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_CLR_GPR(x)
GPR_PRIVATE4_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE4_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE4_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_TOG_GPR(x)
GPR_PRIVATE4_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE4_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE4_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE4_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE5 - General Purpose Register
#define	CCM_GPR_PRIVATE5_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE5_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_GPR(x)
GPR_PRIVATE5_SET - General Purpose Register
#define	CCM_GPR_PRIVATE5_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE5_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_SET_GPR(x)
GPR_PRIVATE5_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE5_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE5_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_CLR_GPR(x)
GPR_PRIVATE5_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE5_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE5_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_TOG_GPR(x)
GPR_PRIVATE5_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE5_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE5_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE5_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE6 - General Purpose Register
#define	CCM_GPR_PRIVATE6_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE6_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_GPR(x)
GPR_PRIVATE6_SET - General Purpose Register
#define	CCM_GPR_PRIVATE6_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE6_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_SET_GPR(x)
GPR_PRIVATE6_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE6_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE6_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_CLR_GPR(x)
GPR_PRIVATE6_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE6_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE6_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_TOG_GPR(x)
GPR_PRIVATE6_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE6_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE6_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE6_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x)
GPR_PRIVATE7 - General Purpose Register
#define	CCM_GPR_PRIVATE7_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE7_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_GPR(x)
GPR_PRIVATE7_SET - General Purpose Register
#define	CCM_GPR_PRIVATE7_SET_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE7_SET_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_SET_GPR(x)
GPR_PRIVATE7_CLR - General Purpose Register
#define	CCM_GPR_PRIVATE7_CLR_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE7_CLR_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_CLR_GPR(x)
GPR_PRIVATE7_TOG - General Purpose Register
#define	CCM_GPR_PRIVATE7_TOG_GPR_MASK   (0xFFFFFFFFU)
#define	CCM_GPR_PRIVATE7_TOG_GPR_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_TOG_GPR(x)
GPR_PRIVATE7_AUTHEN - GPR access control
#define	CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x)
GPR_PRIVATE7_AUTHEN_SET - GPR access control
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x)
GPR_PRIVATE7_AUTHEN_CLR - GPR access control
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x)
GPR_PRIVATE7_AUTHEN_TOG - GPR access control
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x)
OSCPLL_DIRECT - Clock source direct control
#define	CCM_OSCPLL_DIRECT_ON_MASK   (0x1U)
#define	CCM_OSCPLL_DIRECT_ON_SHIFT   (0U)
#define	CCM_OSCPLL_DIRECT_ON(x)
OSCPLL_DOMAIN - Clock source domain control
#define	CCM_OSCPLL_DOMAIN_LEVEL_MASK   (0x7U)
#define	CCM_OSCPLL_DOMAIN_LEVEL_SHIFT   (0U)
#define	CCM_OSCPLL_DOMAIN_LEVEL(x)
#define	CCM_OSCPLL_DOMAIN_LEVEL0_MASK   (0x70000U)
#define	CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT   (16U)
#define	CCM_OSCPLL_DOMAIN_LEVEL0(x)
#define	CCM_OSCPLL_DOMAIN_LEVEL1_MASK   (0x700000U)
#define	CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT   (20U)
#define	CCM_OSCPLL_DOMAIN_LEVEL1(x)
#define	CCM_OSCPLL_DOMAIN_LEVEL2_MASK   (0x7000000U)
#define	CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT   (24U)
#define	CCM_OSCPLL_DOMAIN_LEVEL2(x)
#define	CCM_OSCPLL_DOMAIN_LEVEL3_MASK   (0x70000000U)
#define	CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT   (28U)
#define	CCM_OSCPLL_DOMAIN_LEVEL3(x)
OSCPLL_SETPOINT - Clock source Setpoint setting
#define	CCM_OSCPLL_SETPOINT_SETPOINT_MASK   (0xFFFFU)
#define	CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT   (0U)
#define	CCM_OSCPLL_SETPOINT_SETPOINT(x)
#define	CCM_OSCPLL_SETPOINT_STANDBY_MASK   (0xFFFF0000U)
#define	CCM_OSCPLL_SETPOINT_STANDBY_SHIFT   (16U)
#define	CCM_OSCPLL_SETPOINT_STANDBY(x)
OSCPLL_STATUS0 - Clock source working status
#define	CCM_OSCPLL_STATUS0_ON_MASK   (0x1U)
#define	CCM_OSCPLL_STATUS0_ON_SHIFT   (0U)
#define	CCM_OSCPLL_STATUS0_ON(x)
#define	CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK   (0x10U)
#define	CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT   (4U)
#define	CCM_OSCPLL_STATUS0_STATUS_EARLY(x)
#define	CCM_OSCPLL_STATUS0_STATUS_LATE_MASK   (0x20U)
#define	CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT   (5U)
#define	CCM_OSCPLL_STATUS0_STATUS_LATE(x)
#define	CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK   (0xF00U)
#define	CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT   (8U)
#define	CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x)
#define	CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK   (0xF000U)
#define	CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT   (12U)
#define	CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x)
#define	CCM_OSCPLL_STATUS0_IN_USE_MASK   (0x10000000U)
#define	CCM_OSCPLL_STATUS0_IN_USE_SHIFT   (28U)
#define	CCM_OSCPLL_STATUS0_IN_USE(x)
OSCPLL_STATUS1 - Clock source low power status
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_MASK   (0x3U)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT   (0U)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE(x)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK   (0x4U)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT   (2U)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK   (0x8U)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT   (3U)
#define	CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_MASK   (0x30U)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT   (4U)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE(x)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK   (0x40U)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT   (6U)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK   (0x80U)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT   (7U)
#define	CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_MASK   (0x300U)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT   (8U)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE(x)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK   (0x400U)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT   (10U)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK   (0x800U)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT   (11U)
#define	CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_MASK   (0x3000U)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT   (12U)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE(x)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK   (0x4000U)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT   (14U)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK   (0x8000U)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT   (15U)
#define	CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x)
#define	CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK   (0xF0000U)
#define	CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
#define	CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x)
#define	CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
#define	CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT   (20U)
#define	CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x)
#define	CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK   (0x1000000U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT   (24U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK   (0x2000000U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT   (25U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x)
#define	CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK   (0x4000000U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT   (26U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK   (0x8000000U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT   (27U)
#define	CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x)
#define	CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK   (0x10000000U)
#define	CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT   (28U)
#define	CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x)
#define	CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK   (0x20000000U)
#define	CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT   (29U)
#define	CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x)
#define	CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK   (0x40000000U)
#define	CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT   (30U)
#define	CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x)
#define	CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK   (0x80000000U)
#define	CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT   (31U)
#define	CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x)
OSCPLL_CONFIG - Clock source configuration
#define	CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK   (0x2U)
#define	CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT   (1U)
#define	CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x)
#define	CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK   (0x10U)
#define	CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
#define	CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x)
OSCPLL_AUTHEN - Clock source access control
#define	CCM_OSCPLL_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_OSCPLL_AUTHEN_TZ_USER(x)
#define	CCM_OSCPLL_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_OSCPLL_AUTHEN_TZ_NS(x)
#define	CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_OSCPLL_AUTHEN_LOCK_TZ(x)
#define	CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_OSCPLL_AUTHEN_WHITE_LIST(x)
#define	CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_OSCPLL_AUTHEN_LOCK_LIST(x)
#define	CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x)
#define	CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x)
#define	CCM_OSCPLL_AUTHEN_CPULPM_MASK   (0x40000U)
#define	CCM_OSCPLL_AUTHEN_CPULPM_SHIFT   (18U)
#define	CCM_OSCPLL_AUTHEN_CPULPM(x)
#define	CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_OSCPLL_AUTHEN_LOCK_MODE(x)
LPCG_DIRECT - LPCG direct control
#define	CCM_LPCG_DIRECT_ON_MASK   (0x1U)
#define	CCM_LPCG_DIRECT_ON_SHIFT   (0U)
#define	CCM_LPCG_DIRECT_ON(x)
LPCG_DOMAIN - LPCG domain control
#define	CCM_LPCG_DOMAIN_LEVEL_MASK   (0x7U)
#define	CCM_LPCG_DOMAIN_LEVEL_SHIFT   (0U)
#define	CCM_LPCG_DOMAIN_LEVEL(x)
#define	CCM_LPCG_DOMAIN_LEVEL0_MASK   (0x70000U)
#define	CCM_LPCG_DOMAIN_LEVEL0_SHIFT   (16U)
#define	CCM_LPCG_DOMAIN_LEVEL0(x)
#define	CCM_LPCG_DOMAIN_LEVEL1_MASK   (0x700000U)
#define	CCM_LPCG_DOMAIN_LEVEL1_SHIFT   (20U)
#define	CCM_LPCG_DOMAIN_LEVEL1(x)
#define	CCM_LPCG_DOMAIN_LEVEL2_MASK   (0x7000000U)
#define	CCM_LPCG_DOMAIN_LEVEL2_SHIFT   (24U)
#define	CCM_LPCG_DOMAIN_LEVEL2(x)
#define	CCM_LPCG_DOMAIN_LEVEL3_MASK   (0x70000000U)
#define	CCM_LPCG_DOMAIN_LEVEL3_SHIFT   (28U)
#define	CCM_LPCG_DOMAIN_LEVEL3(x)
LPCG_SETPOINT - LPCG Setpoint setting
#define	CCM_LPCG_SETPOINT_SETPOINT_MASK   (0xFFFFU)
#define	CCM_LPCG_SETPOINT_SETPOINT_SHIFT   (0U)
#define	CCM_LPCG_SETPOINT_SETPOINT(x)
#define	CCM_LPCG_SETPOINT_STANDBY_MASK   (0xFFFF0000U)
#define	CCM_LPCG_SETPOINT_STANDBY_SHIFT   (16U)
#define	CCM_LPCG_SETPOINT_STANDBY(x)
LPCG_STATUS0 - LPCG working status
#define	CCM_LPCG_STATUS0_ON_MASK   (0x1U)
#define	CCM_LPCG_STATUS0_ON_SHIFT   (0U)
#define	CCM_LPCG_STATUS0_ON(x)
#define	CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK   (0xF00U)
#define	CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT   (8U)
#define	CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x)
#define	CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK   (0xF000U)
#define	CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT   (12U)
#define	CCM_LPCG_STATUS0_DOMAIN_ENABLE(x)
LPCG_STATUS1 - LPCG low power status
#define	CCM_LPCG_STATUS1_CPU0_MODE_MASK   (0x3U)
#define	CCM_LPCG_STATUS1_CPU0_MODE_SHIFT   (0U)
#define	CCM_LPCG_STATUS1_CPU0_MODE(x)
#define	CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK   (0x4U)
#define	CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT   (2U)
#define	CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x)
#define	CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK   (0x8U)
#define	CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT   (3U)
#define	CCM_LPCG_STATUS1_CPU0_MODE_DONE(x)
#define	CCM_LPCG_STATUS1_CPU1_MODE_MASK   (0x30U)
#define	CCM_LPCG_STATUS1_CPU1_MODE_SHIFT   (4U)
#define	CCM_LPCG_STATUS1_CPU1_MODE(x)
#define	CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK   (0x40U)
#define	CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT   (6U)
#define	CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x)
#define	CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK   (0x80U)
#define	CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT   (7U)
#define	CCM_LPCG_STATUS1_CPU1_MODE_DONE(x)
#define	CCM_LPCG_STATUS1_CPU2_MODE_MASK   (0x300U)
#define	CCM_LPCG_STATUS1_CPU2_MODE_SHIFT   (8U)
#define	CCM_LPCG_STATUS1_CPU2_MODE(x)
#define	CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK   (0x400U)
#define	CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT   (10U)
#define	CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x)
#define	CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK   (0x800U)
#define	CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT   (11U)
#define	CCM_LPCG_STATUS1_CPU2_MODE_DONE(x)
#define	CCM_LPCG_STATUS1_CPU3_MODE_MASK   (0x3000U)
#define	CCM_LPCG_STATUS1_CPU3_MODE_SHIFT   (12U)
#define	CCM_LPCG_STATUS1_CPU3_MODE(x)
#define	CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK   (0x4000U)
#define	CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT   (14U)
#define	CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x)
#define	CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK   (0x8000U)
#define	CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT   (15U)
#define	CCM_LPCG_STATUS1_CPU3_MODE_DONE(x)
#define	CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK   (0xF0000U)
#define	CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
#define	CCM_LPCG_STATUS1_TARGET_SETPOINT(x)
#define	CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
#define	CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT   (20U)
#define	CCM_LPCG_STATUS1_CURRENT_SETPOINT(x)
#define	CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK   (0x1000000U)
#define	CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT   (24U)
#define	CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x)
#define	CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK   (0x2000000U)
#define	CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT   (25U)
#define	CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x)
#define	CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK   (0x4000000U)
#define	CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT   (26U)
#define	CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x)
#define	CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK   (0x8000000U)
#define	CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT   (27U)
#define	CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x)
LPCG_CONFIG - LPCG configuration
#define	CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK   (0x10U)
#define	CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
#define	CCM_LPCG_CONFIG_SETPOINT_PRESENT(x)
LPCG_AUTHEN - LPCG access control
#define	CCM_LPCG_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_LPCG_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_LPCG_AUTHEN_TZ_USER(x)
#define	CCM_LPCG_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_LPCG_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_LPCG_AUTHEN_TZ_NS(x)
#define	CCM_LPCG_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_LPCG_AUTHEN_LOCK_TZ(x)
#define	CCM_LPCG_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_LPCG_AUTHEN_WHITE_LIST(x)
#define	CCM_LPCG_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_LPCG_AUTHEN_LOCK_LIST(x)
#define	CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_LPCG_AUTHEN_DOMAIN_MODE(x)
#define	CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK   (0x20000U)
#define	CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT   (17U)
#define	CCM_LPCG_AUTHEN_SETPOINT_MODE(x)
#define	CCM_LPCG_AUTHEN_CPULPM_MASK   (0x40000U)
#define	CCM_LPCG_AUTHEN_CPULPM_SHIFT   (18U)
#define	CCM_LPCG_AUTHEN_CPULPM(x)
#define	CCM_LPCG_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_LPCG_AUTHEN_LOCK_MODE(x)
OBSERVE_CONTROL - Observe control
#define	CCM_OBS_OBSERVE_CONTROL_SELECT_MASK   (0x1FFU)
#define	CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_CONTROL_SELECT(x)
#define	CCM_OBS_OBSERVE_CONTROL_RAW_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_CONTROL_RAW(x)
#define	CCM_OBS_OBSERVE_CONTROL_INV_MASK   (0x2000U)
#define	CCM_OBS_OBSERVE_CONTROL_INV_SHIFT   (13U)
#define	CCM_OBS_OBSERVE_CONTROL_INV(x)
#define	CCM_OBS_OBSERVE_CONTROL_RESET_MASK   (0x8000U)
#define	CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT   (15U)
#define	CCM_OBS_OBSERVE_CONTROL_RESET(x)
#define	CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK   (0xFF0000U)
#define	CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_CONTROL_DIVIDE(x)
#define	CCM_OBS_OBSERVE_CONTROL_OFF_MASK   (0x1000000U)
#define	CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT   (24U)
#define	CCM_OBS_OBSERVE_CONTROL_OFF(x)
OBSERVE_CONTROL_SET - Observe control
#define	CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK   (0x1FFU)
#define	CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x)
#define	CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_RAW(x)
#define	CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK   (0x2000U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT   (13U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_INV(x)
#define	CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK   (0x8000U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT   (15U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_RESET(x)
#define	CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK   (0xFF0000U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x)
#define	CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK   (0x1000000U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT   (24U)
#define	CCM_OBS_OBSERVE_CONTROL_SET_OFF(x)
OBSERVE_CONTROL_CLR - Observe control
#define	CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK   (0x1FFU)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK   (0x2000U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT   (13U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_INV(x)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK   (0x8000U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT   (15U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK   (0xFF0000U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK   (0x1000000U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT   (24U)
#define	CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x)
OBSERVE_CONTROL_TOG - Observe control
#define	CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK   (0x1FFU)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK   (0x2000U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT   (13U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_INV(x)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK   (0x8000U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT   (15U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK   (0xFF0000U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK   (0x1000000U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT   (24U)
#define	CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x)
OBSERVE_STATUS0 - Observe status
#define	CCM_OBS_OBSERVE_STATUS0_SELECT_MASK   (0x1FFU)
#define	CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_STATUS0_SELECT(x)
#define	CCM_OBS_OBSERVE_STATUS0_RAW_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_STATUS0_RAW(x)
#define	CCM_OBS_OBSERVE_STATUS0_INV_MASK   (0x2000U)
#define	CCM_OBS_OBSERVE_STATUS0_INV_SHIFT   (13U)
#define	CCM_OBS_OBSERVE_STATUS0_INV(x)
#define	CCM_OBS_OBSERVE_STATUS0_RESET_MASK   (0x8000U)
#define	CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT   (15U)
#define	CCM_OBS_OBSERVE_STATUS0_RESET(x)
#define	CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK   (0xFF0000U)
#define	CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_STATUS0_DIVIDE(x)
#define	CCM_OBS_OBSERVE_STATUS0_OFF_MASK   (0x1000000U)
#define	CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT   (24U)
#define	CCM_OBS_OBSERVE_STATUS0_OFF(x)
OBSERVE_AUTHEN - Observe access control
#define	CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK   (0x1U)
#define	CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK   (0x2U)
#define	CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT   (1U)
#define	CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK   (0x10U)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT   (4U)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x)
#define	CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK   (0xF00U)
#define	CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT   (8U)
#define	CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK   (0x100000U)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT   (20U)
#define	CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x)
OBSERVE_AUTHEN_SET - Observe access control
#define	CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK   (0x1U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK   (0x2U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT   (1U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT   (4U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK   (0xF00U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT   (8U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK   (0x100000U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT   (20U)
#define	CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x)
OBSERVE_AUTHEN_CLR - Observe access control
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT   (4U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK   (0xF00U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT   (8U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK   (0x100000U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT   (20U)
#define	CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x)
OBSERVE_AUTHEN_TOG - Observe access control
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT   (4U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK   (0xF00U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT   (8U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK   (0x1000U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT   (12U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK   (0x10000U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT   (16U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK   (0x100000U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT   (20U)
#define	CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x)
OBSERVE_FREQUENCY_CURRENT - Current frequency detected
#define	CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK   (0xFFFFFFFFU)
#define	CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x)
OBSERVE_FREQUENCY_MIN - Minimum frequency detected
#define	CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK   (0xFFFFFFFFU)
#define	CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x)
OBSERVE_FREQUENCY_MAX - Maximum frequency detected
#define	CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK   (0xFFFFFFFFU)
#define	CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT   (0U)
#define	CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x)
CONTROL - Control
#define	CDOG_CONTROL_LOCK_CTRL_MASK   (0x3U)
#define	CDOG_CONTROL_LOCK_CTRL_SHIFT   (0U)
#define	CDOG_CONTROL_LOCK_CTRL(x)
#define	CDOG_CONTROL_TIMEOUT_CTRL_MASK   (0x1CU)
#define	CDOG_CONTROL_TIMEOUT_CTRL_SHIFT   (2U)
#define	CDOG_CONTROL_TIMEOUT_CTRL(x)
#define	CDOG_CONTROL_MISCOMPARE_CTRL_MASK   (0xE0U)
#define	CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT   (5U)
#define	CDOG_CONTROL_MISCOMPARE_CTRL(x)
#define	CDOG_CONTROL_SEQUENCE_CTRL_MASK   (0x700U)
#define	CDOG_CONTROL_SEQUENCE_CTRL_SHIFT   (8U)
#define	CDOG_CONTROL_SEQUENCE_CTRL(x)
#define	CDOG_CONTROL_CONTROL_CTRL_MASK   (0x3800U)
#define	CDOG_CONTROL_CONTROL_CTRL_SHIFT   (11U)
#define	CDOG_CONTROL_CONTROL_CTRL(x)
#define	CDOG_CONTROL_STATE_CTRL_MASK   (0x1C000U)
#define	CDOG_CONTROL_STATE_CTRL_SHIFT   (14U)
#define	CDOG_CONTROL_STATE_CTRL(x)
#define	CDOG_CONTROL_ADDRESS_CTRL_MASK   (0xE0000U)
#define	CDOG_CONTROL_ADDRESS_CTRL_SHIFT   (17U)
#define	CDOG_CONTROL_ADDRESS_CTRL(x)
#define	CDOG_CONTROL_IRQ_PAUSE_MASK   (0x30000000U)
#define	CDOG_CONTROL_IRQ_PAUSE_SHIFT   (28U)
#define	CDOG_CONTROL_IRQ_PAUSE(x)
#define	CDOG_CONTROL_DEBUG_HALT_CTRL_MASK   (0xC0000000U)
#define	CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT   (30U)
#define	CDOG_CONTROL_DEBUG_HALT_CTRL(x)
RELOAD - Instruction Timer reload
#define	CDOG_RELOAD_RLOAD_MASK   (0xFFFFFFFFU)
#define	CDOG_RELOAD_RLOAD_SHIFT   (0U)
#define	CDOG_RELOAD_RLOAD(x)
INSTRUCTION_TIMER - Instruction Timer
#define	CDOG_INSTRUCTION_TIMER_INSTIM_MASK   (0xFFFFFFFFU)
#define	CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT   (0U)
#define	CDOG_INSTRUCTION_TIMER_INSTIM(x)
SECURE_COUNTER - Secure Counter
#define	CDOG_SECURE_COUNTER_SECCNT_MASK   (0xFFFFFFFFU)
#define	CDOG_SECURE_COUNTER_SECCNT_SHIFT   (0U)
#define	CDOG_SECURE_COUNTER_SECCNT(x)
STATUS - Status 1
#define	CDOG_STATUS_NUMTOF_MASK   (0xFFU)
#define	CDOG_STATUS_NUMTOF_SHIFT   (0U)
#define	CDOG_STATUS_NUMTOF(x)
#define	CDOG_STATUS_NUMMISCOMPF_MASK   (0xFF00U)
#define	CDOG_STATUS_NUMMISCOMPF_SHIFT   (8U)
#define	CDOG_STATUS_NUMMISCOMPF(x)
#define	CDOG_STATUS_NUMILSEQF_MASK   (0xFF0000U)
#define	CDOG_STATUS_NUMILSEQF_SHIFT   (16U)
#define	CDOG_STATUS_NUMILSEQF(x)
#define	CDOG_STATUS_CURST_MASK   (0xF0000000U)
#define	CDOG_STATUS_CURST_SHIFT   (28U)
#define	CDOG_STATUS_CURST(x)
STATUS2 - Status 2
#define	CDOG_STATUS2_NUMCNTF_MASK   (0xFFU)
#define	CDOG_STATUS2_NUMCNTF_SHIFT   (0U)
#define	CDOG_STATUS2_NUMCNTF(x)
#define	CDOG_STATUS2_NUMILLSTF_MASK   (0xFF00U)
#define	CDOG_STATUS2_NUMILLSTF_SHIFT   (8U)
#define	CDOG_STATUS2_NUMILLSTF(x)
#define	CDOG_STATUS2_NUMILLA_MASK   (0xFF0000U)
#define	CDOG_STATUS2_NUMILLA_SHIFT   (16U)
#define	CDOG_STATUS2_NUMILLA(x)
FLAGS - Flags
#define	CDOG_FLAGS_TO_FLAG_MASK   (0x1U)
#define	CDOG_FLAGS_TO_FLAG_SHIFT   (0U)
#define	CDOG_FLAGS_TO_FLAG(x)
#define	CDOG_FLAGS_MISCOM_FLAG_MASK   (0x2U)
#define	CDOG_FLAGS_MISCOM_FLAG_SHIFT   (1U)
#define	CDOG_FLAGS_MISCOM_FLAG(x)
#define	CDOG_FLAGS_SEQ_FLAG_MASK   (0x4U)
#define	CDOG_FLAGS_SEQ_FLAG_SHIFT   (2U)
#define	CDOG_FLAGS_SEQ_FLAG(x)
#define	CDOG_FLAGS_CNT_FLAG_MASK   (0x8U)
#define	CDOG_FLAGS_CNT_FLAG_SHIFT   (3U)
#define	CDOG_FLAGS_CNT_FLAG(x)
#define	CDOG_FLAGS_STATE_FLAG_MASK   (0x10U)
#define	CDOG_FLAGS_STATE_FLAG_SHIFT   (4U)
#define	CDOG_FLAGS_STATE_FLAG(x)
#define	CDOG_FLAGS_ADDR_FLAG_MASK   (0x20U)
#define	CDOG_FLAGS_ADDR_FLAG_SHIFT   (5U)
#define	CDOG_FLAGS_ADDR_FLAG(x)
#define	CDOG_FLAGS_POR_FLAG_MASK   (0x10000U)
#define	CDOG_FLAGS_POR_FLAG_SHIFT   (16U)
#define	CDOG_FLAGS_POR_FLAG(x)
PERSISTENT - Persistent Data Storage
#define	CDOG_PERSISTENT_PERSIS_MASK   (0xFFFFFFFFU)
#define	CDOG_PERSISTENT_PERSIS_SHIFT   (0U)
#define	CDOG_PERSISTENT_PERSIS(x)
START - START Command
#define	CDOG_START_STRT_MASK   (0xFFFFFFFFU)
#define	CDOG_START_STRT_SHIFT   (0U)
#define	CDOG_START_STRT(x)
STOP - STOP Command
#define	CDOG_STOP_STP_MASK   (0xFFFFFFFFU)
#define	CDOG_STOP_STP_SHIFT   (0U)
#define	CDOG_STOP_STP(x)
RESTART - RESTART Command
#define	CDOG_RESTART_RSTRT_MASK   (0xFFFFFFFFU)
#define	CDOG_RESTART_RSTRT_SHIFT   (0U)
#define	CDOG_RESTART_RSTRT(x)
ADD - ADD Command
#define	CDOG_ADD_AD_MASK   (0xFFFFFFFFU)
#define	CDOG_ADD_AD_SHIFT   (0U)
#define	CDOG_ADD_AD(x)
ADD1 - ADD1 Command
#define	CDOG_ADD1_AD1_MASK   (0xFFFFFFFFU)
#define	CDOG_ADD1_AD1_SHIFT   (0U)
#define	CDOG_ADD1_AD1(x)
ADD16 - ADD16 Command
#define	CDOG_ADD16_AD16_MASK   (0xFFFFFFFFU)
#define	CDOG_ADD16_AD16_SHIFT   (0U)
#define	CDOG_ADD16_AD16(x)
ADD256 - ADD256 Command
#define	CDOG_ADD256_AD256_MASK   (0xFFFFFFFFU)
#define	CDOG_ADD256_AD256_SHIFT   (0U)
#define	CDOG_ADD256_AD256(x)
SUB - SUB Command
#define	CDOG_SUB_S0B_MASK   (0xFFFFFFFFU)
#define	CDOG_SUB_S0B_SHIFT   (0U)
#define	CDOG_SUB_S0B(x)
SUB1 - SUB1 Command
#define	CDOG_SUB1_S1B_MASK   (0xFFFFFFFFU)
#define	CDOG_SUB1_S1B_SHIFT   (0U)
#define	CDOG_SUB1_S1B(x)
SUB16 - SUB16 Command
#define	CDOG_SUB16_SB16_MASK   (0xFFFFFFFFU)
#define	CDOG_SUB16_SB16_SHIFT   (0U)
#define	CDOG_SUB16_SB16(x)
SUB256 - SUB256 Command
#define	CDOG_SUB256_SB256_MASK   (0xFFFFFFFFU)
#define	CDOG_SUB256_SB256_SHIFT   (0U)
#define	CDOG_SUB256_SB256(x)
C0 - CMP Control Register 0
#define	CMP_C0_HYSTCTR_MASK   (0x3U)
#define	CMP_C0_HYSTCTR_SHIFT   (0U)
#define	CMP_C0_HYSTCTR(x)
#define	CMP_C0_FILTER_CNT_MASK   (0x70U)
#define	CMP_C0_FILTER_CNT_SHIFT   (4U)
#define	CMP_C0_FILTER_CNT(x)
#define	CMP_C0_EN_MASK   (0x100U)
#define	CMP_C0_EN_SHIFT   (8U)
#define	CMP_C0_EN(x)
#define	CMP_C0_OPE_MASK   (0x200U)
#define	CMP_C0_OPE_SHIFT   (9U)
#define	CMP_C0_OPE(x)
#define	CMP_C0_COS_MASK   (0x400U)
#define	CMP_C0_COS_SHIFT   (10U)
#define	CMP_C0_COS(x)
#define	CMP_C0_INVT_MASK   (0x800U)
#define	CMP_C0_INVT_SHIFT   (11U)
#define	CMP_C0_INVT(x)
#define	CMP_C0_PMODE_MASK   (0x1000U)
#define	CMP_C0_PMODE_SHIFT   (12U)
#define	CMP_C0_PMODE(x)
#define	CMP_C0_WE_MASK   (0x4000U)
#define	CMP_C0_WE_SHIFT   (14U)
#define	CMP_C0_WE(x)
#define	CMP_C0_SE_MASK   (0x8000U)
#define	CMP_C0_SE_SHIFT   (15U)
#define	CMP_C0_SE(x)
#define	CMP_C0_FPR_MASK   (0xFF0000U)
#define	CMP_C0_FPR_SHIFT   (16U)
#define	CMP_C0_FPR(x)
#define	CMP_C0_COUT_MASK   (0x1000000U)
#define	CMP_C0_COUT_SHIFT   (24U)
#define	CMP_C0_COUT(x)
#define	CMP_C0_CFF_MASK   (0x2000000U)
#define	CMP_C0_CFF_SHIFT   (25U)
#define	CMP_C0_CFF(x)
#define	CMP_C0_CFR_MASK   (0x4000000U)
#define	CMP_C0_CFR_SHIFT   (26U)
#define	CMP_C0_CFR(x)
#define	CMP_C0_IEF_MASK   (0x8000000U)
#define	CMP_C0_IEF_SHIFT   (27U)
#define	CMP_C0_IEF(x)
#define	CMP_C0_IER_MASK   (0x10000000U)
#define	CMP_C0_IER_SHIFT   (28U)
#define	CMP_C0_IER(x)
#define	CMP_C0_DMAEN_MASK   (0x40000000U)
#define	CMP_C0_DMAEN_SHIFT   (30U)
#define	CMP_C0_DMAEN(x)
#define	CMP_C0_LINKEN_MASK   (0x80000000U)
#define	CMP_C0_LINKEN_SHIFT   (31U)
#define	CMP_C0_LINKEN(x)
C1 - CMP Control Register 1
#define	CMP_C1_VOSEL_MASK   (0xFFU)
#define	CMP_C1_VOSEL_SHIFT   (0U)
#define	CMP_C1_VOSEL(x)
#define	CMP_C1_DMODE_MASK   (0x100U)
#define	CMP_C1_DMODE_SHIFT   (8U)
#define	CMP_C1_DMODE(x)
#define	CMP_C1_VRSEL_MASK   (0x200U)
#define	CMP_C1_VRSEL_SHIFT   (9U)
#define	CMP_C1_VRSEL(x)
#define	CMP_C1_DACEN_MASK   (0x400U)
#define	CMP_C1_DACEN_SHIFT   (10U)
#define	CMP_C1_DACEN(x)
#define	CMP_C1_CHN0_MASK   (0x10000U)
#define	CMP_C1_CHN0_SHIFT   (16U)
#define	CMP_C1_CHN0(x)
#define	CMP_C1_CHN1_MASK   (0x20000U)
#define	CMP_C1_CHN1_SHIFT   (17U)
#define	CMP_C1_CHN1(x)
#define	CMP_C1_CHN2_MASK   (0x40000U)
#define	CMP_C1_CHN2_SHIFT   (18U)
#define	CMP_C1_CHN2(x)
#define	CMP_C1_CHN3_MASK   (0x80000U)
#define	CMP_C1_CHN3_SHIFT   (19U)
#define	CMP_C1_CHN3(x)
#define	CMP_C1_CHN4_MASK   (0x100000U)
#define	CMP_C1_CHN4_SHIFT   (20U)
#define	CMP_C1_CHN4(x)
#define	CMP_C1_CHN5_MASK   (0x200000U)
#define	CMP_C1_CHN5_SHIFT   (21U)
#define	CMP_C1_CHN5(x)
#define	CMP_C1_MSEL_MASK   (0x7000000U)
#define	CMP_C1_MSEL_SHIFT   (24U)
#define	CMP_C1_MSEL(x)
#define	CMP_C1_PSEL_MASK   (0x70000000U)
#define	CMP_C1_PSEL_SHIFT   (28U)
#define	CMP_C1_PSEL(x)
C2 - CMP Control Register 2
#define	CMP_C2_ACOn_MASK   (0x3FU)
#define	CMP_C2_ACOn_SHIFT   (0U)
#define	CMP_C2_ACOn(x)
#define	CMP_C2_INITMOD_MASK   (0x3F00U)
#define	CMP_C2_INITMOD_SHIFT   (8U)
#define	CMP_C2_INITMOD(x)
#define	CMP_C2_NSAM_MASK   (0xC000U)
#define	CMP_C2_NSAM_SHIFT   (14U)
#define	CMP_C2_NSAM(x)
#define	CMP_C2_CH0F_MASK   (0x10000U)
#define	CMP_C2_CH0F_SHIFT   (16U)
#define	CMP_C2_CH0F(x)
#define	CMP_C2_CH1F_MASK   (0x20000U)
#define	CMP_C2_CH1F_SHIFT   (17U)
#define	CMP_C2_CH1F(x)
#define	CMP_C2_CH2F_MASK   (0x40000U)
#define	CMP_C2_CH2F_SHIFT   (18U)
#define	CMP_C2_CH2F(x)
#define	CMP_C2_CH3F_MASK   (0x80000U)
#define	CMP_C2_CH3F_SHIFT   (19U)
#define	CMP_C2_CH3F(x)
#define	CMP_C2_CH4F_MASK   (0x100000U)
#define	CMP_C2_CH4F_SHIFT   (20U)
#define	CMP_C2_CH4F(x)
#define	CMP_C2_CH5F_MASK   (0x200000U)
#define	CMP_C2_CH5F_SHIFT   (21U)
#define	CMP_C2_CH5F(x)
#define	CMP_C2_FXMXCH_MASK   (0xE000000U)
#define	CMP_C2_FXMXCH_SHIFT   (25U)
#define	CMP_C2_FXMXCH(x)
#define	CMP_C2_FXMP_MASK   (0x20000000U)
#define	CMP_C2_FXMP_SHIFT   (29U)
#define	CMP_C2_FXMP(x)
#define	CMP_C2_RRIE_MASK   (0x40000000U)
#define	CMP_C2_RRIE_SHIFT   (30U)
#define	CMP_C2_RRIE(x)
C3 - CMP Control Register 3
#define	CMP_C3_ACPH2TC_MASK   (0x70U)
#define	CMP_C3_ACPH2TC_SHIFT   (4U)
#define	CMP_C3_ACPH2TC(x)
#define	CMP_C3_ACPH1TC_MASK   (0x700U)
#define	CMP_C3_ACPH1TC_SHIFT   (8U)
#define	CMP_C3_ACPH1TC(x)
#define	CMP_C3_ACSAT_MASK   (0x7000U)
#define	CMP_C3_ACSAT_SHIFT   (12U)
#define	CMP_C3_ACSAT(x)
#define	CMP_C3_DMCS_MASK   (0x10000U)
#define	CMP_C3_DMCS_SHIFT   (16U)
#define	CMP_C3_DMCS(x)
#define	CMP_C3_RDIVE_MASK   (0x100000U)
#define	CMP_C3_RDIVE_SHIFT   (20U)
#define	CMP_C3_RDIVE(x)
#define	CMP_C3_NCHCTEN_MASK   (0x1000000U)
#define	CMP_C3_NCHCTEN_SHIFT   (24U)
#define	CMP_C3_NCHCTEN(x)
#define	CMP_C3_PCHCTEN_MASK   (0x10000000U)
#define	CMP_C3_PCHCTEN_SHIFT   (28U)
#define	CMP_C3_PCHCTEN(x)
CR1 - CSI Control Register 1
#define	CSI_CR1_PIXEL_BIT_MASK   (0x1U)
#define	CSI_CR1_PIXEL_BIT_SHIFT   (0U)
#define	CSI_CR1_PIXEL_BIT(x)
#define	CSI_CR1_REDGE_MASK   (0x2U)
#define	CSI_CR1_REDGE_SHIFT   (1U)
#define	CSI_CR1_REDGE(x)
#define	CSI_CR1_INV_PCLK_MASK   (0x4U)
#define	CSI_CR1_INV_PCLK_SHIFT   (2U)
#define	CSI_CR1_INV_PCLK(x)
#define	CSI_CR1_INV_DATA_MASK   (0x8U)
#define	CSI_CR1_INV_DATA_SHIFT   (3U)
#define	CSI_CR1_INV_DATA(x)
#define	CSI_CR1_GCLK_MODE_MASK   (0x10U)
#define	CSI_CR1_GCLK_MODE_SHIFT   (4U)
#define	CSI_CR1_GCLK_MODE(x)
#define	CSI_CR1_CLR_RXFIFO_MASK   (0x20U)
#define	CSI_CR1_CLR_RXFIFO_SHIFT   (5U)
#define	CSI_CR1_CLR_RXFIFO(x)
#define	CSI_CR1_CLR_STATFIFO_MASK   (0x40U)
#define	CSI_CR1_CLR_STATFIFO_SHIFT   (6U)
#define	CSI_CR1_CLR_STATFIFO(x)
#define	CSI_CR1_PACK_DIR_MASK   (0x80U)
#define	CSI_CR1_PACK_DIR_SHIFT   (7U)
#define	CSI_CR1_PACK_DIR(x)
#define	CSI_CR1_FCC_MASK   (0x100U)
#define	CSI_CR1_FCC_SHIFT   (8U)
#define	CSI_CR1_FCC(x)
#define	CSI_CR1_CCIR_EN_MASK   (0x400U)
#define	CSI_CR1_CCIR_EN_SHIFT   (10U)
#define	CSI_CR1_CCIR_EN(x)
#define	CSI_CR1_HSYNC_POL_MASK   (0x800U)
#define	CSI_CR1_HSYNC_POL_SHIFT   (11U)
#define	CSI_CR1_HSYNC_POL(x)
#define	CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK   (0x1000U)
#define	CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT   (12U)
#define	CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)
#define	CSI_CR1_SOF_INTEN_MASK   (0x10000U)
#define	CSI_CR1_SOF_INTEN_SHIFT   (16U)
#define	CSI_CR1_SOF_INTEN(x)
#define	CSI_CR1_SOF_POL_MASK   (0x20000U)
#define	CSI_CR1_SOF_POL_SHIFT   (17U)
#define	CSI_CR1_SOF_POL(x)
#define	CSI_CR1_RXFF_INTEN_MASK   (0x40000U)
#define	CSI_CR1_RXFF_INTEN_SHIFT   (18U)
#define	CSI_CR1_RXFF_INTEN(x)
#define	CSI_CR1_FB1_DMA_DONE_INTEN_MASK   (0x80000U)
#define	CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT   (19U)
#define	CSI_CR1_FB1_DMA_DONE_INTEN(x)
#define	CSI_CR1_FB2_DMA_DONE_INTEN_MASK   (0x100000U)
#define	CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT   (20U)
#define	CSI_CR1_FB2_DMA_DONE_INTEN(x)
#define	CSI_CR1_STATFF_INTEN_MASK   (0x200000U)
#define	CSI_CR1_STATFF_INTEN_SHIFT   (21U)
#define	CSI_CR1_STATFF_INTEN(x)
#define	CSI_CR1_SFF_DMA_DONE_INTEN_MASK   (0x400000U)
#define	CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT   (22U)
#define	CSI_CR1_SFF_DMA_DONE_INTEN(x)
#define	CSI_CR1_RF_OR_INTEN_MASK   (0x1000000U)
#define	CSI_CR1_RF_OR_INTEN_SHIFT   (24U)
#define	CSI_CR1_RF_OR_INTEN(x)
#define	CSI_CR1_SF_OR_INTEN_MASK   (0x2000000U)
#define	CSI_CR1_SF_OR_INTEN_SHIFT   (25U)
#define	CSI_CR1_SF_OR_INTEN(x)
#define	CSI_CR1_COF_INT_EN_MASK   (0x4000000U)
#define	CSI_CR1_COF_INT_EN_SHIFT   (26U)
#define	CSI_CR1_COF_INT_EN(x)
#define	CSI_CR1_VIDEO_MODE_MASK   (0x8000000U)
#define	CSI_CR1_VIDEO_MODE_SHIFT   (27U)
#define	CSI_CR1_VIDEO_MODE(x)
#define	CSI_CR1_EOF_INT_EN_MASK   (0x20000000U)
#define	CSI_CR1_EOF_INT_EN_SHIFT   (29U)
#define	CSI_CR1_EOF_INT_EN(x)
#define	CSI_CR1_EXT_VSYNC_MASK   (0x40000000U)
#define	CSI_CR1_EXT_VSYNC_SHIFT   (30U)
#define	CSI_CR1_EXT_VSYNC(x)
#define	CSI_CR1_SWAP16_EN_MASK   (0x80000000U)
#define	CSI_CR1_SWAP16_EN_SHIFT   (31U)
#define	CSI_CR1_SWAP16_EN(x)
CR2 - CSI Control Register 2
#define	CSI_CR2_HSC_MASK   (0xFFU)
#define	CSI_CR2_HSC_SHIFT   (0U)
#define	CSI_CR2_HSC(x)
#define	CSI_CR2_VSC_MASK   (0xFF00U)
#define	CSI_CR2_VSC_SHIFT   (8U)
#define	CSI_CR2_VSC(x)
#define	CSI_CR2_LVRM_MASK   (0x70000U)
#define	CSI_CR2_LVRM_SHIFT   (16U)
#define	CSI_CR2_LVRM(x)
#define	CSI_CR2_BTS_MASK   (0x180000U)
#define	CSI_CR2_BTS_SHIFT   (19U)
#define	CSI_CR2_BTS(x)
#define	CSI_CR2_SCE_MASK   (0x800000U)
#define	CSI_CR2_SCE_SHIFT   (23U)
#define	CSI_CR2_SCE(x)
#define	CSI_CR2_AFS_MASK   (0x3000000U)
#define	CSI_CR2_AFS_SHIFT   (24U)
#define	CSI_CR2_AFS(x)
#define	CSI_CR2_DRM_MASK   (0x4000000U)
#define	CSI_CR2_DRM_SHIFT   (26U)
#define	CSI_CR2_DRM(x)
#define	CSI_CR2_DMA_BURST_TYPE_SFF_MASK   (0x30000000U)
#define	CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT   (28U)
#define	CSI_CR2_DMA_BURST_TYPE_SFF(x)
#define	CSI_CR2_DMA_BURST_TYPE_RFF_MASK   (0xC0000000U)
#define	CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT   (30U)
#define	CSI_CR2_DMA_BURST_TYPE_RFF(x)
CR3 - CSI Control Register 3
#define	CSI_CR3_ECC_AUTO_EN_MASK   (0x1U)
#define	CSI_CR3_ECC_AUTO_EN_SHIFT   (0U)
#define	CSI_CR3_ECC_AUTO_EN(x)
#define	CSI_CR3_ECC_INT_EN_MASK   (0x2U)
#define	CSI_CR3_ECC_INT_EN_SHIFT   (1U)
#define	CSI_CR3_ECC_INT_EN(x)
#define	CSI_CR3_ZERO_PACK_EN_MASK   (0x4U)
#define	CSI_CR3_ZERO_PACK_EN_SHIFT   (2U)
#define	CSI_CR3_ZERO_PACK_EN(x)
#define	CSI_CR3_SENSOR_16BITS_MASK   (0x8U)
#define	CSI_CR3_SENSOR_16BITS_SHIFT   (3U)
#define	CSI_CR3_SENSOR_16BITS(x)
#define	CSI_CR3_RxFF_LEVEL_MASK   (0x70U)
#define	CSI_CR3_RxFF_LEVEL_SHIFT   (4U)
#define	CSI_CR3_RxFF_LEVEL(x)
#define	CSI_CR3_HRESP_ERR_EN_MASK   (0x80U)
#define	CSI_CR3_HRESP_ERR_EN_SHIFT   (7U)
#define	CSI_CR3_HRESP_ERR_EN(x)
#define	CSI_CR3_STATFF_LEVEL_MASK   (0x700U)
#define	CSI_CR3_STATFF_LEVEL_SHIFT   (8U)
#define	CSI_CR3_STATFF_LEVEL(x)
#define	CSI_CR3_DMA_REQ_EN_SFF_MASK   (0x800U)
#define	CSI_CR3_DMA_REQ_EN_SFF_SHIFT   (11U)
#define	CSI_CR3_DMA_REQ_EN_SFF(x)
#define	CSI_CR3_DMA_REQ_EN_RFF_MASK   (0x1000U)
#define	CSI_CR3_DMA_REQ_EN_RFF_SHIFT   (12U)
#define	CSI_CR3_DMA_REQ_EN_RFF(x)
#define	CSI_CR3_DMA_REFLASH_SFF_MASK   (0x2000U)
#define	CSI_CR3_DMA_REFLASH_SFF_SHIFT   (13U)
#define	CSI_CR3_DMA_REFLASH_SFF(x)
#define	CSI_CR3_DMA_REFLASH_RFF_MASK   (0x4000U)
#define	CSI_CR3_DMA_REFLASH_RFF_SHIFT   (14U)
#define	CSI_CR3_DMA_REFLASH_RFF(x)
#define	CSI_CR3_FRMCNT_RST_MASK   (0x8000U)
#define	CSI_CR3_FRMCNT_RST_SHIFT   (15U)
#define	CSI_CR3_FRMCNT_RST(x)
#define	CSI_CR3_FRMCNT_MASK   (0xFFFF0000U)
#define	CSI_CR3_FRMCNT_SHIFT   (16U)
#define	CSI_CR3_FRMCNT(x)
STATFIFO - CSI Statistic FIFO Register
#define	CSI_STATFIFO_STAT_MASK   (0xFFFFFFFFU)
#define	CSI_STATFIFO_STAT_SHIFT   (0U)
#define	CSI_STATFIFO_STAT(x)
RFIFO - CSI RX FIFO Register
#define	CSI_RFIFO_IMAGE_MASK   (0xFFFFFFFFU)
#define	CSI_RFIFO_IMAGE_SHIFT   (0U)
#define	CSI_RFIFO_IMAGE(x)
RXCNT - CSI RX Count Register
#define	CSI_RXCNT_RXCNT_MASK   (0x3FFFFFU)
#define	CSI_RXCNT_RXCNT_SHIFT   (0U)
#define	CSI_RXCNT_RXCNT(x)
SR - CSI Status Register
#define	CSI_SR_DRDY_MASK   (0x1U)
#define	CSI_SR_DRDY_SHIFT   (0U)
#define	CSI_SR_DRDY(x)
#define	CSI_SR_ECC_INT_MASK   (0x2U)
#define	CSI_SR_ECC_INT_SHIFT   (1U)
#define	CSI_SR_ECC_INT(x)
#define	CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK   (0x4U)
#define	CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT   (2U)
#define	CSI_SR_HISTOGRAM_CALC_DONE_INT(x)
#define	CSI_SR_HRESP_ERR_INT_MASK   (0x80U)
#define	CSI_SR_HRESP_ERR_INT_SHIFT   (7U)
#define	CSI_SR_HRESP_ERR_INT(x)
#define	CSI_SR_COF_INT_MASK   (0x2000U)
#define	CSI_SR_COF_INT_SHIFT   (13U)
#define	CSI_SR_COF_INT(x)
#define	CSI_SR_F1_INT_MASK   (0x4000U)
#define	CSI_SR_F1_INT_SHIFT   (14U)
#define	CSI_SR_F1_INT(x)
#define	CSI_SR_F2_INT_MASK   (0x8000U)
#define	CSI_SR_F2_INT_SHIFT   (15U)
#define	CSI_SR_F2_INT(x)
#define	CSI_SR_SOF_INT_MASK   (0x10000U)
#define	CSI_SR_SOF_INT_SHIFT   (16U)
#define	CSI_SR_SOF_INT(x)
#define	CSI_SR_EOF_INT_MASK   (0x20000U)
#define	CSI_SR_EOF_INT_SHIFT   (17U)
#define	CSI_SR_EOF_INT(x)
#define	CSI_SR_RxFF_INT_MASK   (0x40000U)
#define	CSI_SR_RxFF_INT_SHIFT   (18U)
#define	CSI_SR_RxFF_INT(x)
#define	CSI_SR_DMA_TSF_DONE_FB1_MASK   (0x80000U)
#define	CSI_SR_DMA_TSF_DONE_FB1_SHIFT   (19U)
#define	CSI_SR_DMA_TSF_DONE_FB1(x)
#define	CSI_SR_DMA_TSF_DONE_FB2_MASK   (0x100000U)
#define	CSI_SR_DMA_TSF_DONE_FB2_SHIFT   (20U)
#define	CSI_SR_DMA_TSF_DONE_FB2(x)
#define	CSI_SR_STATFF_INT_MASK   (0x200000U)
#define	CSI_SR_STATFF_INT_SHIFT   (21U)
#define	CSI_SR_STATFF_INT(x)
#define	CSI_SR_DMA_TSF_DONE_SFF_MASK   (0x400000U)
#define	CSI_SR_DMA_TSF_DONE_SFF_SHIFT   (22U)
#define	CSI_SR_DMA_TSF_DONE_SFF(x)
#define	CSI_SR_RF_OR_INT_MASK   (0x1000000U)
#define	CSI_SR_RF_OR_INT_SHIFT   (24U)
#define	CSI_SR_RF_OR_INT(x)
#define	CSI_SR_SF_OR_INT_MASK   (0x2000000U)
#define	CSI_SR_SF_OR_INT_SHIFT   (25U)
#define	CSI_SR_SF_OR_INT(x)
#define	CSI_SR_DMA_FIELD1_DONE_MASK   (0x4000000U)
#define	CSI_SR_DMA_FIELD1_DONE_SHIFT   (26U)
#define	CSI_SR_DMA_FIELD1_DONE(x)
#define	CSI_SR_DMA_FIELD0_DONE_MASK   (0x8000000U)
#define	CSI_SR_DMA_FIELD0_DONE_SHIFT   (27U)
#define	CSI_SR_DMA_FIELD0_DONE(x)
#define	CSI_SR_BASEADDR_CHHANGE_ERROR_MASK   (0x10000000U)
#define	CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT   (28U)
#define	CSI_SR_BASEADDR_CHHANGE_ERROR(x)
DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO
#define	CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK   (0xFFFFFFFCU)
#define	CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT   (2U)
#define	CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x)
DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO
#define	CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK   (0xFFFFFFFFU)
#define	CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT   (0U)
#define	CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1
#define	CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK   (0xFFFFFFFCU)
#define	CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT   (2U)
#define	CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)
DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2
#define	CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK   (0xFFFFFFFCU)
#define	CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT   (2U)
#define	CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)
FBUF_PARA - CSI Frame Buffer Parameter Register
#define	CSI_FBUF_PARA_FBUF_STRIDE_MASK   (0xFFFFU)
#define	CSI_FBUF_PARA_FBUF_STRIDE_SHIFT   (0U)
#define	CSI_FBUF_PARA_FBUF_STRIDE(x)
#define	CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK   (0xFFFF0000U)
#define	CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT   (16U)
#define	CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)
IMAG_PARA - CSI Image Parameter Register
#define	CSI_IMAG_PARA_IMAGE_HEIGHT_MASK   (0xFFFFU)
#define	CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT   (0U)
#define	CSI_IMAG_PARA_IMAGE_HEIGHT(x)
#define	CSI_IMAG_PARA_IMAGE_WIDTH_MASK   (0xFFFF0000U)
#define	CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT   (16U)
#define	CSI_IMAG_PARA_IMAGE_WIDTH(x)
CR18 - CSI Control Register 18
#define	CSI_CR18_NTSC_EN_MASK   (0x1U)
#define	CSI_CR18_NTSC_EN_SHIFT   (0U)
#define	CSI_CR18_NTSC_EN(x)
#define	CSI_CR18_TVDECODER_IN_EN_MASK   (0x2U)
#define	CSI_CR18_TVDECODER_IN_EN_SHIFT   (1U)
#define	CSI_CR18_TVDECODER_IN_EN(x)
#define	CSI_CR18_DEINTERLACE_EN_MASK   (0x4U)
#define	CSI_CR18_DEINTERLACE_EN_SHIFT   (2U)
#define	CSI_CR18_DEINTERLACE_EN(x)
#define	CSI_CR18_PARALLEL24_EN_MASK   (0x8U)
#define	CSI_CR18_PARALLEL24_EN_SHIFT   (3U)
#define	CSI_CR18_PARALLEL24_EN(x)
#define	CSI_CR18_BASEADDR_SWITCH_EN_MASK   (0x10U)
#define	CSI_CR18_BASEADDR_SWITCH_EN_SHIFT   (4U)
#define	CSI_CR18_BASEADDR_SWITCH_EN(x)
#define	CSI_CR18_BASEADDR_SWITCH_SEL_MASK   (0x20U)
#define	CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT   (5U)
#define	CSI_CR18_BASEADDR_SWITCH_SEL(x)
#define	CSI_CR18_FIELD0_DONE_IE_MASK   (0x40U)
#define	CSI_CR18_FIELD0_DONE_IE_SHIFT   (6U)
#define	CSI_CR18_FIELD0_DONE_IE(x)
#define	CSI_CR18_DMA_FIELD1_DONE_IE_MASK   (0x80U)
#define	CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT   (7U)
#define	CSI_CR18_DMA_FIELD1_DONE_IE(x)
#define	CSI_CR18_LAST_DMA_REQ_SEL_MASK   (0x100U)
#define	CSI_CR18_LAST_DMA_REQ_SEL_SHIFT   (8U)
#define	CSI_CR18_LAST_DMA_REQ_SEL(x)
#define	CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK   (0x200U)
#define	CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT   (9U)
#define	CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)
#define	CSI_CR18_RGB888A_FORMAT_SEL_MASK   (0x400U)
#define	CSI_CR18_RGB888A_FORMAT_SEL_SHIFT   (10U)
#define	CSI_CR18_RGB888A_FORMAT_SEL(x)
#define	CSI_CR18_AHB_HPROT_MASK   (0xF000U)
#define	CSI_CR18_AHB_HPROT_SHIFT   (12U)
#define	CSI_CR18_AHB_HPROT(x)
#define	CSI_CR18_MASK_OPTION_MASK   (0xC0000U)
#define	CSI_CR18_MASK_OPTION_SHIFT   (18U)
#define	CSI_CR18_MASK_OPTION(x)
#define	CSI_CR18_MIPI_DOUBLE_CMPNT_MASK   (0x100000U)
#define	CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT   (20U)
#define	CSI_CR18_MIPI_DOUBLE_CMPNT(x)
#define	CSI_CR18_MIPI_YU_SWAP_MASK   (0x200000U)
#define	CSI_CR18_MIPI_YU_SWAP_SHIFT   (21U)
#define	CSI_CR18_MIPI_YU_SWAP(x)
#define	CSI_CR18_DATA_FROM_MIPI_MASK   (0x400000U)
#define	CSI_CR18_DATA_FROM_MIPI_SHIFT   (22U)
#define	CSI_CR18_DATA_FROM_MIPI(x)
#define	CSI_CR18_LINE_STRIDE_EN_MASK   (0x1000000U)
#define	CSI_CR18_LINE_STRIDE_EN_SHIFT   (24U)
#define	CSI_CR18_LINE_STRIDE_EN(x)
#define	CSI_CR18_MIPI_DATA_FORMAT_MASK   (0x7E000000U)
#define	CSI_CR18_MIPI_DATA_FORMAT_SHIFT   (25U)
#define	CSI_CR18_MIPI_DATA_FORMAT(x)
#define	CSI_CR18_CSI_ENABLE_MASK   (0x80000000U)
#define	CSI_CR18_CSI_ENABLE_SHIFT   (31U)
#define	CSI_CR18_CSI_ENABLE(x)
CR19 - CSI Control Register 19
#define	CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK   (0xFFU)
#define	CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT   (0U)
#define	CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
CR20 - CSI Control Register 20
#define	CSI_CR20_THRESHOLD_MASK   (0xFFU)
#define	CSI_CR20_THRESHOLD_SHIFT   (0U)
#define	CSI_CR20_THRESHOLD(x)
#define	CSI_CR20_BINARY_EN_MASK   (0x100U)
#define	CSI_CR20_BINARY_EN_SHIFT   (8U)
#define	CSI_CR20_BINARY_EN(x)
#define	CSI_CR20_QR_DATA_FORMAT_MASK   (0xE00U)
#define	CSI_CR20_QR_DATA_FORMAT_SHIFT   (9U)
#define	CSI_CR20_QR_DATA_FORMAT(x)
#define	CSI_CR20_BIG_END_MASK   (0x1000U)
#define	CSI_CR20_BIG_END_SHIFT   (12U)
#define	CSI_CR20_BIG_END(x)
#define	CSI_CR20_10BIT_NEW_EN_MASK   (0x20000000U)
#define	CSI_CR20_10BIT_NEW_EN_SHIFT   (29U)
#define	CSI_CR20_10BIT_NEW_EN(x)
#define	CSI_CR20_HISTOGRAM_EN_MASK   (0x40000000U)
#define	CSI_CR20_HISTOGRAM_EN_SHIFT   (30U)
#define	CSI_CR20_HISTOGRAM_EN(x)
#define	CSI_CR20_QRCODE_EN_MASK   (0x80000000U)
#define	CSI_CR20_QRCODE_EN_SHIFT   (31U)
#define	CSI_CR20_QRCODE_EN(x)
CR - CSI Control Register
#define	CSI_CR_PIXEL_COUNTERS_MASK   (0xFFFFFFU)
#define	CSI_CR_PIXEL_COUNTERS_SHIFT   (0U)
#define	CSI_CR_PIXEL_COUNTERS(x)
VERID - Version Identifier Register
#define	DAC_VERID_FEATURE_MASK   (0xFFFFU)
#define	DAC_VERID_FEATURE_SHIFT   (0U)
#define	DAC_VERID_FEATURE(x)
#define	DAC_VERID_MINOR_MASK   (0xFF0000U)
#define	DAC_VERID_MINOR_SHIFT   (16U)
#define	DAC_VERID_MINOR(x)
#define	DAC_VERID_MAJOR_MASK   (0xFF000000U)
#define	DAC_VERID_MAJOR_SHIFT   (24U)
#define	DAC_VERID_MAJOR(x)
DATA - DAC Data Register
#define	DAC_DATA_DATA0_MASK   (0xFFFU)
#define	DAC_DATA_DATA0_SHIFT   (0U)
#define	DAC_DATA_DATA0(x)
CR - DAC Status and Control Register
#define	DAC_CR_FULLF_MASK   (0x1U)
#define	DAC_CR_FULLF_SHIFT   (0U)
#define	DAC_CR_FULLF(x)
#define	DAC_CR_NEMPTF_MASK   (0x2U)
#define	DAC_CR_NEMPTF_SHIFT   (1U)
#define	DAC_CR_NEMPTF(x)
#define	DAC_CR_WMF_MASK   (0x4U)
#define	DAC_CR_WMF_SHIFT   (2U)
#define	DAC_CR_WMF(x)
#define	DAC_CR_UDFF_MASK   (0x8U)
#define	DAC_CR_UDFF_SHIFT   (3U)
#define	DAC_CR_UDFF(x)
#define	DAC_CR_OVFF_MASK   (0x10U)
#define	DAC_CR_OVFF_SHIFT   (4U)
#define	DAC_CR_OVFF(x)
#define	DAC_CR_FULLIE_MASK   (0x100U)
#define	DAC_CR_FULLIE_SHIFT   (8U)
#define	DAC_CR_FULLIE(x)
#define	DAC_CR_EMPTIE_MASK   (0x200U)
#define	DAC_CR_EMPTIE_SHIFT   (9U)
#define	DAC_CR_EMPTIE(x)
#define	DAC_CR_WTMIE_MASK   (0x400U)
#define	DAC_CR_WTMIE_SHIFT   (10U)
#define	DAC_CR_WTMIE(x)
#define	DAC_CR_SWTRG_MASK   (0x1000U)
#define	DAC_CR_SWTRG_SHIFT   (12U)
#define	DAC_CR_SWTRG(x)
#define	DAC_CR_TRGSEL_MASK   (0x2000U)
#define	DAC_CR_TRGSEL_SHIFT   (13U)
#define	DAC_CR_TRGSEL(x)
#define	DAC_CR_DACRFS_MASK   (0x4000U)
#define	DAC_CR_DACRFS_SHIFT   (14U)
#define	DAC_CR_DACRFS(x)
#define	DAC_CR_DACEN_MASK   (0x8000U)
#define	DAC_CR_DACEN_SHIFT   (15U)
#define	DAC_CR_DACEN(x)
#define	DAC_CR_FIFOEN_MASK   (0x10000U)
#define	DAC_CR_FIFOEN_SHIFT   (16U)
#define	DAC_CR_FIFOEN(x)
#define	DAC_CR_SWMD_MASK   (0x20000U)
#define	DAC_CR_SWMD_SHIFT   (17U)
#define	DAC_CR_SWMD(x)
#define	DAC_CR_UVIE_MASK   (0x40000U)
#define	DAC_CR_UVIE_SHIFT   (18U)
#define	DAC_CR_UVIE(x)
#define	DAC_CR_FIFORST_MASK   (0x200000U)
#define	DAC_CR_FIFORST_SHIFT   (21U)
#define	DAC_CR_FIFORST(x)
#define	DAC_CR_SWRST_MASK   (0x400000U)
#define	DAC_CR_SWRST_SHIFT   (22U)
#define	DAC_CR_SWRST(x)
#define	DAC_CR_DMAEN_MASK   (0x800000U)
#define	DAC_CR_DMAEN_SHIFT   (23U)
#define	DAC_CR_DMAEN(x)
#define	DAC_CR_WML_MASK   (0xFF000000U)
#define	DAC_CR_WML_SHIFT   (24U)
#define	DAC_CR_WML(x)
PTR - DAC FIFO Pointer Register
#define	DAC_PTR_DACWFP_MASK   (0xFFU)
#define	DAC_PTR_DACWFP_SHIFT   (0U)
#define	DAC_PTR_DACWFP(x)
#define	DAC_PTR_DACRFP_MASK   (0xFF0000U)
#define	DAC_PTR_DACRFP_SHIFT   (16U)
#define	DAC_PTR_DACRFP(x)
CR2 - DAC Status and Control Register 2
#define	DAC_CR2_BFEN_MASK   (0x1U)
#define	DAC_CR2_BFEN_SHIFT   (0U)
#define	DAC_CR2_BFEN(x)
#define	DAC_CR2_OEN_MASK   (0x2U)
#define	DAC_CR2_OEN_SHIFT   (1U)
#define	DAC_CR2_OEN(x)
#define	DAC_CR2_BFMS_MASK   (0x4U)
#define	DAC_CR2_BFMS_SHIFT   (2U)
#define	DAC_CR2_BFMS(x)
#define	DAC_CR2_BFHS_MASK   (0x8U)
#define	DAC_CR2_BFHS_SHIFT   (3U)
#define	DAC_CR2_BFHS(x)
#define	DAC_CR2_IREF2_MASK   (0x10U)
#define	DAC_CR2_IREF2_SHIFT   (4U)
#define	DAC_CR2_IREF2(x)
#define	DAC_CR2_IREF1_MASK   (0x20U)
#define	DAC_CR2_IREF1_SHIFT   (5U)
#define	DAC_CR2_IREF1(x)
#define	DAC_CR2_IREF_MASK   (0x40U)
#define	DAC_CR2_IREF_SHIFT   (6U)
#define	DAC_CR2_IREF(x)
CTRL0 - DCDC Control Register 0
#define	DCDC_CTRL0_ENABLE_MASK   (0x1U)
#define	DCDC_CTRL0_ENABLE_SHIFT   (0U)
#define	DCDC_CTRL0_ENABLE(x)
#define	DCDC_CTRL0_DIG_EN_MASK   (0x2U)
#define	DCDC_CTRL0_DIG_EN_SHIFT   (1U)
#define	DCDC_CTRL0_DIG_EN(x)
#define	DCDC_CTRL0_STBY_EN_MASK   (0x4U)
#define	DCDC_CTRL0_STBY_EN_SHIFT   (2U)
#define	DCDC_CTRL0_STBY_EN(x)
#define	DCDC_CTRL0_LP_MODE_EN_MASK   (0x8U)
#define	DCDC_CTRL0_LP_MODE_EN_SHIFT   (3U)
#define	DCDC_CTRL0_LP_MODE_EN(x)
#define	DCDC_CTRL0_STBY_LP_MODE_EN_MASK   (0x10U)
#define	DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT   (4U)
#define	DCDC_CTRL0_STBY_LP_MODE_EN(x)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT_MASK   (0x20U)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT   (5U)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT(x)
#define	DCDC_CTRL0_TRIM_HOLD_MASK   (0x40U)
#define	DCDC_CTRL0_TRIM_HOLD_SHIFT   (6U)
#define	DCDC_CTRL0_TRIM_HOLD(x)
#define	DCDC_CTRL0_DEBUG_BITS_MASK   (0x7FF80000U)
#define	DCDC_CTRL0_DEBUG_BITS_SHIFT   (19U)
#define	DCDC_CTRL0_DEBUG_BITS(x)
#define	DCDC_CTRL0_CONTROL_MODE_MASK   (0x80000000U)
#define	DCDC_CTRL0_CONTROL_MODE_SHIFT   (31U)
#define	DCDC_CTRL0_CONTROL_MODE(x)
CTRL1 - DCDC Control Register 1
#define	DCDC_CTRL1_VDD1P8CTRL_TRG_MASK   (0x1FU)
#define	DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT   (0U)
#define	DCDC_CTRL1_VDD1P8CTRL_TRG(x)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG_MASK   (0x1F00U)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT   (8U)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG(x)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK   (0x1F0000U)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT   (16U)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK   (0x1F000000U)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT   (24U)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)
REG0 - DCDC Register 0
#define	DCDC_REG0_PWD_ZCD_MASK   (0x1U)
#define	DCDC_REG0_PWD_ZCD_SHIFT   (0U)
#define	DCDC_REG0_PWD_ZCD(x)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT   (1U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)
#define	DCDC_REG0_SEL_CLK_MASK   (0x4U)
#define	DCDC_REG0_SEL_CLK_SHIFT   (2U)
#define	DCDC_REG0_SEL_CLK(x)
#define	DCDC_REG0_PWD_OSC_INT_MASK   (0x8U)
#define	DCDC_REG0_PWD_OSC_INT_SHIFT   (3U)
#define	DCDC_REG0_PWD_OSC_INT(x)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_MASK   (0x10U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT   (4U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP(x)
#define	DCDC_REG0_CUR_SNS_THRSH_MASK   (0xE0U)
#define	DCDC_REG0_CUR_SNS_THRSH_SHIFT   (5U)
#define	DCDC_REG0_CUR_SNS_THRSH(x)
#define	DCDC_REG0_PWD_OVERCUR_DET_MASK   (0x100U)
#define	DCDC_REG0_PWD_OVERCUR_DET_SHIFT   (8U)
#define	DCDC_REG0_PWD_OVERCUR_DET(x)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK   (0x800U)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT   (11U)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK   (0x10000U)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT   (16U)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK   (0x20000U)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT   (17U)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)
#define	DCDC_REG0_LP_HIGH_HYS_MASK   (0x200000U)
#define	DCDC_REG0_LP_HIGH_HYS_SHIFT   (21U)
#define	DCDC_REG0_LP_HIGH_HYS(x)
#define	DCDC_REG0_PWD_CMP_OFFSET_MASK   (0x4000000U)
#define	DCDC_REG0_PWD_CMP_OFFSET_SHIFT   (26U)
#define	DCDC_REG0_PWD_CMP_OFFSET(x)
#define	DCDC_REG0_XTALOK_DISABLE_MASK   (0x8000000U)
#define	DCDC_REG0_XTALOK_DISABLE_SHIFT   (27U)
#define	DCDC_REG0_XTALOK_DISABLE(x)
#define	DCDC_REG0_XTAL_24M_OK_MASK   (0x20000000U)
#define	DCDC_REG0_XTAL_24M_OK_SHIFT   (29U)
#define	DCDC_REG0_XTAL_24M_OK(x)
#define	DCDC_REG0_STS_DC_OK_MASK   (0x80000000U)
#define	DCDC_REG0_STS_DC_OK_SHIFT   (31U)
#define	DCDC_REG0_STS_DC_OK(x)
REG1 - DCDC Register 1
#define	DCDC_REG1_DM_CTRL_MASK   (0x8U)
#define	DCDC_REG1_DM_CTRL_SHIFT   (3U)
#define	DCDC_REG1_DM_CTRL(x)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR_MASK   (0x10U)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT   (4U)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR(x)
#define	DCDC_REG1_VBG_TRIM_MASK   (0x7C0U)
#define	DCDC_REG1_VBG_TRIM_SHIFT   (6U)
#define	DCDC_REG1_VBG_TRIM(x)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_MASK   (0x1800U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT   (11U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL(x)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK   (0x8000000U)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK   (0x10000000U)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK   (0x20000000U)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT   (29U)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK   (0x40000000U)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT   (30U)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)
REG2 - DCDC Register 2
#define	DCDC_REG2_LOOPCTRL_DC_C_MASK   (0x3U)
#define	DCDC_REG2_LOOPCTRL_DC_C_SHIFT   (0U)
#define	DCDC_REG2_LOOPCTRL_DC_C(x)
#define	DCDC_REG2_LOOPCTRL_DC_R_MASK   (0x3CU)
#define	DCDC_REG2_LOOPCTRL_DC_R_SHIFT   (2U)
#define	DCDC_REG2_LOOPCTRL_DC_R(x)
#define	DCDC_REG2_LOOPCTRL_DC_FF_MASK   (0x1C0U)
#define	DCDC_REG2_LOOPCTRL_DC_FF_SHIFT   (6U)
#define	DCDC_REG2_LOOPCTRL_DC_FF(x)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK   (0xE00U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT   (9U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK   (0x1000U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK   (0x2000U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT   (13U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN(x)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK   (0x8000U)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT   (15U)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ(x)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL_MASK   (0x3FF0000U)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT   (16U)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL(x)
#define	DCDC_REG2_DCM_SET_CTRL_MASK   (0x10000000U)
#define	DCDC_REG2_DCM_SET_CTRL_SHIFT   (28U)
#define	DCDC_REG2_DCM_SET_CTRL(x)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK   (0x40000000U)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT   (30U)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)
REG3 - DCDC Register 3
#define	DCDC_REG3_IN_BROWNOUT_MASK   (0x4000U)
#define	DCDC_REG3_IN_BROWNOUT_SHIFT   (14U)
#define	DCDC_REG3_IN_BROWNOUT(x)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK   (0x8000U)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT   (15U)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK   (0x10000U)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT   (16U)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x)
#define	DCDC_REG3_OVERCUR_DETECT_OUT_MASK   (0x20000U)
#define	DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT   (17U)
#define	DCDC_REG3_OVERCUR_DETECT_OUT(x)
#define	DCDC_REG3_ENABLE_FF_MASK   (0x40000U)
#define	DCDC_REG3_ENABLE_FF_SHIFT   (18U)
#define	DCDC_REG3_ENABLE_FF(x)
#define	DCDC_REG3_DISABLE_PULSE_SKIP_MASK   (0x80000U)
#define	DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT   (19U)
#define	DCDC_REG3_DISABLE_PULSE_SKIP(x)
#define	DCDC_REG3_DISABLE_IDLE_SKIP_MASK   (0x100000U)
#define	DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT   (20U)
#define	DCDC_REG3_DISABLE_IDLE_SKIP(x)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK   (0x200000U)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT   (21U)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x)
#define	DCDC_REG3_REG_FBK_SEL_MASK   (0xC00000U)
#define	DCDC_REG3_REG_FBK_SEL_SHIFT   (22U)
#define	DCDC_REG3_REG_FBK_SEL(x)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_MASK   (0x1000000U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT   (24U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK(x)
#define	DCDC_REG3_MINPWR_HALF_FETS_MASK   (0x4000000U)
#define	DCDC_REG3_MINPWR_HALF_FETS_SHIFT   (26U)
#define	DCDC_REG3_MINPWR_HALF_FETS(x)
#define	DCDC_REG3_MISC_DELAY_TIMING_MASK   (0x8000000U)
#define	DCDC_REG3_MISC_DELAY_TIMING_SHIFT   (27U)
#define	DCDC_REG3_MISC_DELAY_TIMING(x)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT   (29U)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK   (0x40000000U)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT   (30U)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x)
REG4 - DCDC Register 4
#define	DCDC_REG4_ENABLE_SP_MASK   (0xFFFFU)
#define	DCDC_REG4_ENABLE_SP_SHIFT   (0U)
#define	DCDC_REG4_ENABLE_SP(x)
REG5 - DCDC Register 5
#define	DCDC_REG5_DIG_EN_SP_MASK   (0xFFFFU)
#define	DCDC_REG5_DIG_EN_SP_SHIFT   (0U)
#define	DCDC_REG5_DIG_EN_SP(x)
REG6 - DCDC Register 6
#define	DCDC_REG6_LP_MODE_SP_MASK   (0xFFFFU)
#define	DCDC_REG6_LP_MODE_SP_SHIFT   (0U)
#define	DCDC_REG6_LP_MODE_SP(x)
REG7 - DCDC Register 7
#define	DCDC_REG7_STBY_EN_SP_MASK   (0xFFFFU)
#define	DCDC_REG7_STBY_EN_SP_SHIFT   (0U)
#define	DCDC_REG7_STBY_EN_SP(x)
REG7P - DCDC Register 7 plus
#define	DCDC_REG7P_STBY_LP_MODE_SP_MASK   (0xFFFFU)
#define	DCDC_REG7P_STBY_LP_MODE_SP_SHIFT   (0U)
#define	DCDC_REG7P_STBY_LP_MODE_SP(x)
REG8 - DCDC Register 8
#define	DCDC_REG8_ANA_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG8_ANA_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG8_ANA_TRG_SP0(x)
REG9 - DCDC Register 9
#define	DCDC_REG9_ANA_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG9_ANA_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG9_ANA_TRG_SP1(x)
REG10 - DCDC Register 10
#define	DCDC_REG10_ANA_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG10_ANA_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG10_ANA_TRG_SP2(x)
REG11 - DCDC Register 11
#define	DCDC_REG11_ANA_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG11_ANA_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG11_ANA_TRG_SP3(x)
REG12 - DCDC Register 12
#define	DCDC_REG12_DIG_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG12_DIG_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG12_DIG_TRG_SP0(x)
REG13 - DCDC Register 13
#define	DCDC_REG13_DIG_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG13_DIG_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG13_DIG_TRG_SP1(x)
REG14 - DCDC Register 14
#define	DCDC_REG14_DIG_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG14_DIG_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG14_DIG_TRG_SP2(x)
REG15 - DCDC Register 15
#define	DCDC_REG15_DIG_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG15_DIG_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG15_DIG_TRG_SP3(x)
REG16 - DCDC Register 16
#define	DCDC_REG16_ANA_STBY_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG16_ANA_STBY_TRG_SP0(x)
REG17 - DCDC Register 17
#define	DCDC_REG17_ANA_STBY_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG17_ANA_STBY_TRG_SP1(x)
REG18 - DCDC Register 18
#define	DCDC_REG18_ANA_STBY_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG18_ANA_STBY_TRG_SP2(x)
REG19 - DCDC Register 19
#define	DCDC_REG19_ANA_STBY_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG19_ANA_STBY_TRG_SP3(x)
REG20 - DCDC Register 20
#define	DCDC_REG20_DIG_STBY_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG20_DIG_STBY_TRG_SP0(x)
REG21 - DCDC Register 21
#define	DCDC_REG21_DIG_STBY_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG21_DIG_STBY_TRG_SP1(x)
REG22 - DCDC Register 22
#define	DCDC_REG22_DIG_STBY_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG22_DIG_STBY_TRG_SP2(x)
REG23 - DCDC Register 23
#define	DCDC_REG23_DIG_STBY_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG23_DIG_STBY_TRG_SP3(x)
REG24 - DCDC Register 24
#define	DCDC_REG24_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	DCDC_REG24_OK_COUNT_SHIFT   (0U)
#define	DCDC_REG24_OK_COUNT(x)
DCICC - DCIC Control Register
#define	DCIC_DCICC_IC_EN_MASK   (0x1U)
#define	DCIC_DCICC_IC_EN_SHIFT   (0U)
#define	DCIC_DCICC_IC_EN(x)
#define	DCIC_DCICC_DE_POL_MASK   (0x10U)
#define	DCIC_DCICC_DE_POL_SHIFT   (4U)
#define	DCIC_DCICC_DE_POL(x)
#define	DCIC_DCICC_HSYNC_POL_MASK   (0x20U)
#define	DCIC_DCICC_HSYNC_POL_SHIFT   (5U)
#define	DCIC_DCICC_HSYNC_POL(x)
#define	DCIC_DCICC_VSYNC_POL_MASK   (0x40U)
#define	DCIC_DCICC_VSYNC_POL_SHIFT   (6U)
#define	DCIC_DCICC_VSYNC_POL(x)
#define	DCIC_DCICC_CLK_POL_MASK   (0x80U)
#define	DCIC_DCICC_CLK_POL_SHIFT   (7U)
#define	DCIC_DCICC_CLK_POL(x)
DCICIC - DCIC Interrupt Control Register
#define	DCIC_DCICIC_EI_MASK_MASK   (0x1U)
#define	DCIC_DCICIC_EI_MASK_SHIFT   (0U)
#define	DCIC_DCICIC_EI_MASK(x)
#define	DCIC_DCICIC_FI_MASK_MASK   (0x2U)
#define	DCIC_DCICIC_FI_MASK_SHIFT   (1U)
#define	DCIC_DCICIC_FI_MASK(x)
#define	DCIC_DCICIC_FREEZE_MASK_MASK   (0x8U)
#define	DCIC_DCICIC_FREEZE_MASK_SHIFT   (3U)
#define	DCIC_DCICIC_FREEZE_MASK(x)
#define	DCIC_DCICIC_EXT_SIG_EN_MASK   (0x10000U)
#define	DCIC_DCICIC_EXT_SIG_EN_SHIFT   (16U)
#define	DCIC_DCICIC_EXT_SIG_EN(x)
DCICS - DCIC Status Register
#define	DCIC_DCICS_ROI_MATCH_STAT_MASK   (0xFFFFU)
#define	DCIC_DCICS_ROI_MATCH_STAT_SHIFT   (0U)
#define	DCIC_DCICS_ROI_MATCH_STAT(x)
#define	DCIC_DCICS_EI_STAT_MASK   (0x10000U)
#define	DCIC_DCICS_EI_STAT_SHIFT   (16U)
#define	DCIC_DCICS_EI_STAT(x)
#define	DCIC_DCICS_FI_STAT_MASK   (0x20000U)
#define	DCIC_DCICS_FI_STAT_SHIFT   (17U)
#define	DCIC_DCICS_FI_STAT(x)
DCICRC - DCIC ROI Config Register
#define	DCIC_DCICRC_START_OFFSET_X_MASK   (0x1FFFU)
#define	DCIC_DCICRC_START_OFFSET_X_SHIFT   (0U)
#define	DCIC_DCICRC_START_OFFSET_X(x)
#define	DCIC_DCICRC_START_OFFSET_Y_MASK   (0xFFF0000U)
#define	DCIC_DCICRC_START_OFFSET_Y_SHIFT   (16U)
#define	DCIC_DCICRC_START_OFFSET_Y(x)
#define	DCIC_DCICRC_ROI_FREEZE_MASK   (0x40000000U)
#define	DCIC_DCICRC_ROI_FREEZE_SHIFT   (30U)
#define	DCIC_DCICRC_ROI_FREEZE(x)
#define	DCIC_DCICRC_ROI_EN_MASK   (0x80000000U)
#define	DCIC_DCICRC_ROI_EN_SHIFT   (31U)
#define	DCIC_DCICRC_ROI_EN(x)
DCICRS - DCIC ROI Size Register
#define	DCIC_DCICRS_END_OFFSET_X_MASK   (0x1FFFU)
#define	DCIC_DCICRS_END_OFFSET_X_SHIFT   (0U)
#define	DCIC_DCICRS_END_OFFSET_X(x)
#define	DCIC_DCICRS_END_OFFSET_Y_MASK   (0xFFF0000U)
#define	DCIC_DCICRS_END_OFFSET_Y_SHIFT   (16U)
#define	DCIC_DCICRS_END_OFFSET_Y(x)
DCICRRS - DCIC ROI Reference Signature Register
#define	DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK   (0xFFFFFFFFU)
#define	DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT   (0U)
#define	DCIC_DCICRRS_REFERENCE_SIGNATURE(x)
DCICRCS - DCIC ROI Calculated Signature Register
#define	DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK   (0xFFFFFFFFU)
#define	DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT   (0U)
#define	DCIC_DCICRCS_CALCULATED_SIGNATURE(x)
CR - Control
#define	DMA_CR_EDBG_MASK   (0x2U)
#define	DMA_CR_EDBG_SHIFT   (1U)
#define	DMA_CR_EDBG(x)
#define	DMA_CR_ERCA_MASK   (0x4U)
#define	DMA_CR_ERCA_SHIFT   (2U)
#define	DMA_CR_ERCA(x)
#define	DMA_CR_ERGA_MASK   (0x8U)
#define	DMA_CR_ERGA_SHIFT   (3U)
#define	DMA_CR_ERGA(x)
#define	DMA_CR_HOE_MASK   (0x10U)
#define	DMA_CR_HOE_SHIFT   (4U)
#define	DMA_CR_HOE(x)
#define	DMA_CR_HALT_MASK   (0x20U)
#define	DMA_CR_HALT_SHIFT   (5U)
#define	DMA_CR_HALT(x)
#define	DMA_CR_CLM_MASK   (0x40U)
#define	DMA_CR_CLM_SHIFT   (6U)
#define	DMA_CR_CLM(x)
#define	DMA_CR_EMLM_MASK   (0x80U)
#define	DMA_CR_EMLM_SHIFT   (7U)
#define	DMA_CR_EMLM(x)
#define	DMA_CR_GRP0PRI_MASK   (0x100U)
#define	DMA_CR_GRP0PRI_SHIFT   (8U)
#define	DMA_CR_GRP0PRI(x)
#define	DMA_CR_GRP1PRI_MASK   (0x400U)
#define	DMA_CR_GRP1PRI_SHIFT   (10U)
#define	DMA_CR_GRP1PRI(x)
#define	DMA_CR_ECX_MASK   (0x10000U)
#define	DMA_CR_ECX_SHIFT   (16U)
#define	DMA_CR_ECX(x)
#define	DMA_CR_CX_MASK   (0x20000U)
#define	DMA_CR_CX_SHIFT   (17U)
#define	DMA_CR_CX(x)
#define	DMA_CR_VERSION_MASK   (0x7F000000U)
#define	DMA_CR_VERSION_SHIFT   (24U)
#define	DMA_CR_VERSION(x)
#define	DMA_CR_ACTIVE_MASK   (0x80000000U)
#define	DMA_CR_ACTIVE_SHIFT   (31U)
#define	DMA_CR_ACTIVE(x)
#define	LPSPI_CR_MEN_MASK   (0x1U)
#define	LPSPI_CR_MEN_SHIFT   (0U)
#define	LPSPI_CR_MEN(x)
#define	LPSPI_CR_RST_MASK   (0x2U)
#define	LPSPI_CR_RST_SHIFT   (1U)
#define	LPSPI_CR_RST(x)
#define	LPSPI_CR_DOZEN_MASK   (0x4U)
#define	LPSPI_CR_DOZEN_SHIFT   (2U)
#define	LPSPI_CR_DOZEN(x)
#define	LPSPI_CR_DBGEN_MASK   (0x8U)
#define	LPSPI_CR_DBGEN_SHIFT   (3U)
#define	LPSPI_CR_DBGEN(x)
#define	LPSPI_CR_RTF_MASK   (0x100U)
#define	LPSPI_CR_RTF_SHIFT   (8U)
#define	LPSPI_CR_RTF(x)
#define	LPSPI_CR_RRF_MASK   (0x200U)
#define	LPSPI_CR_RRF_SHIFT   (9U)
#define	LPSPI_CR_RRF(x)
ES - Error Status
#define	DMA_ES_DBE_MASK   (0x1U)
#define	DMA_ES_DBE_SHIFT   (0U)
#define	DMA_ES_DBE(x)
#define	DMA_ES_SBE_MASK   (0x2U)
#define	DMA_ES_SBE_SHIFT   (1U)
#define	DMA_ES_SBE(x)
#define	DMA_ES_SGE_MASK   (0x4U)
#define	DMA_ES_SGE_SHIFT   (2U)
#define	DMA_ES_SGE(x)
#define	DMA_ES_NCE_MASK   (0x8U)
#define	DMA_ES_NCE_SHIFT   (3U)
#define	DMA_ES_NCE(x)
#define	DMA_ES_DOE_MASK   (0x10U)
#define	DMA_ES_DOE_SHIFT   (4U)
#define	DMA_ES_DOE(x)
#define	DMA_ES_DAE_MASK   (0x20U)
#define	DMA_ES_DAE_SHIFT   (5U)
#define	DMA_ES_DAE(x)
#define	DMA_ES_SOE_MASK   (0x40U)
#define	DMA_ES_SOE_SHIFT   (6U)
#define	DMA_ES_SOE(x)
#define	DMA_ES_SAE_MASK   (0x80U)
#define	DMA_ES_SAE_SHIFT   (7U)
#define	DMA_ES_SAE(x)
#define	DMA_ES_ERRCHN_MASK   (0x1F00U)
#define	DMA_ES_ERRCHN_SHIFT   (8U)
#define	DMA_ES_ERRCHN(x)
#define	DMA_ES_CPE_MASK   (0x4000U)
#define	DMA_ES_CPE_SHIFT   (14U)
#define	DMA_ES_CPE(x)
#define	DMA_ES_GPE_MASK   (0x8000U)
#define	DMA_ES_GPE_SHIFT   (15U)
#define	DMA_ES_GPE(x)
#define	DMA_ES_ECX_MASK   (0x10000U)
#define	DMA_ES_ECX_SHIFT   (16U)
#define	DMA_ES_ECX(x)
#define	DMA_ES_VLD_MASK   (0x80000000U)
#define	DMA_ES_VLD_SHIFT   (31U)
#define	DMA_ES_VLD(x)
ERQ - Enable Request
#define	DMA_ERQ_ERQ0_MASK   (0x1U)
#define	DMA_ERQ_ERQ0_SHIFT   (0U)
#define	DMA_ERQ_ERQ0(x)
#define	DMA_ERQ_ERQ1_MASK   (0x2U)
#define	DMA_ERQ_ERQ1_SHIFT   (1U)
#define	DMA_ERQ_ERQ1(x)
#define	DMA_ERQ_ERQ2_MASK   (0x4U)
#define	DMA_ERQ_ERQ2_SHIFT   (2U)
#define	DMA_ERQ_ERQ2(x)
#define	DMA_ERQ_ERQ3_MASK   (0x8U)
#define	DMA_ERQ_ERQ3_SHIFT   (3U)
#define	DMA_ERQ_ERQ3(x)
#define	DMA_ERQ_ERQ4_MASK   (0x10U)
#define	DMA_ERQ_ERQ4_SHIFT   (4U)
#define	DMA_ERQ_ERQ4(x)
#define	DMA_ERQ_ERQ5_MASK   (0x20U)
#define	DMA_ERQ_ERQ5_SHIFT   (5U)
#define	DMA_ERQ_ERQ5(x)
#define	DMA_ERQ_ERQ6_MASK   (0x40U)
#define	DMA_ERQ_ERQ6_SHIFT   (6U)
#define	DMA_ERQ_ERQ6(x)
#define	DMA_ERQ_ERQ7_MASK   (0x80U)
#define	DMA_ERQ_ERQ7_SHIFT   (7U)
#define	DMA_ERQ_ERQ7(x)
#define	DMA_ERQ_ERQ8_MASK   (0x100U)
#define	DMA_ERQ_ERQ8_SHIFT   (8U)
#define	DMA_ERQ_ERQ8(x)
#define	DMA_ERQ_ERQ9_MASK   (0x200U)
#define	DMA_ERQ_ERQ9_SHIFT   (9U)
#define	DMA_ERQ_ERQ9(x)
#define	DMA_ERQ_ERQ10_MASK   (0x400U)
#define	DMA_ERQ_ERQ10_SHIFT   (10U)
#define	DMA_ERQ_ERQ10(x)
#define	DMA_ERQ_ERQ11_MASK   (0x800U)
#define	DMA_ERQ_ERQ11_SHIFT   (11U)
#define	DMA_ERQ_ERQ11(x)
#define	DMA_ERQ_ERQ12_MASK   (0x1000U)
#define	DMA_ERQ_ERQ12_SHIFT   (12U)
#define	DMA_ERQ_ERQ12(x)
#define	DMA_ERQ_ERQ13_MASK   (0x2000U)
#define	DMA_ERQ_ERQ13_SHIFT   (13U)
#define	DMA_ERQ_ERQ13(x)
#define	DMA_ERQ_ERQ14_MASK   (0x4000U)
#define	DMA_ERQ_ERQ14_SHIFT   (14U)
#define	DMA_ERQ_ERQ14(x)
#define	DMA_ERQ_ERQ15_MASK   (0x8000U)
#define	DMA_ERQ_ERQ15_SHIFT   (15U)
#define	DMA_ERQ_ERQ15(x)
#define	DMA_ERQ_ERQ16_MASK   (0x10000U)
#define	DMA_ERQ_ERQ16_SHIFT   (16U)
#define	DMA_ERQ_ERQ16(x)
#define	DMA_ERQ_ERQ17_MASK   (0x20000U)
#define	DMA_ERQ_ERQ17_SHIFT   (17U)
#define	DMA_ERQ_ERQ17(x)
#define	DMA_ERQ_ERQ18_MASK   (0x40000U)
#define	DMA_ERQ_ERQ18_SHIFT   (18U)
#define	DMA_ERQ_ERQ18(x)
#define	DMA_ERQ_ERQ19_MASK   (0x80000U)
#define	DMA_ERQ_ERQ19_SHIFT   (19U)
#define	DMA_ERQ_ERQ19(x)
#define	DMA_ERQ_ERQ20_MASK   (0x100000U)
#define	DMA_ERQ_ERQ20_SHIFT   (20U)
#define	DMA_ERQ_ERQ20(x)
#define	DMA_ERQ_ERQ21_MASK   (0x200000U)
#define	DMA_ERQ_ERQ21_SHIFT   (21U)
#define	DMA_ERQ_ERQ21(x)
#define	DMA_ERQ_ERQ22_MASK   (0x400000U)
#define	DMA_ERQ_ERQ22_SHIFT   (22U)
#define	DMA_ERQ_ERQ22(x)
#define	DMA_ERQ_ERQ23_MASK   (0x800000U)
#define	DMA_ERQ_ERQ23_SHIFT   (23U)
#define	DMA_ERQ_ERQ23(x)
#define	DMA_ERQ_ERQ24_MASK   (0x1000000U)
#define	DMA_ERQ_ERQ24_SHIFT   (24U)
#define	DMA_ERQ_ERQ24(x)
#define	DMA_ERQ_ERQ25_MASK   (0x2000000U)
#define	DMA_ERQ_ERQ25_SHIFT   (25U)
#define	DMA_ERQ_ERQ25(x)
#define	DMA_ERQ_ERQ26_MASK   (0x4000000U)
#define	DMA_ERQ_ERQ26_SHIFT   (26U)
#define	DMA_ERQ_ERQ26(x)
#define	DMA_ERQ_ERQ27_MASK   (0x8000000U)
#define	DMA_ERQ_ERQ27_SHIFT   (27U)
#define	DMA_ERQ_ERQ27(x)
#define	DMA_ERQ_ERQ28_MASK   (0x10000000U)
#define	DMA_ERQ_ERQ28_SHIFT   (28U)
#define	DMA_ERQ_ERQ28(x)
#define	DMA_ERQ_ERQ29_MASK   (0x20000000U)
#define	DMA_ERQ_ERQ29_SHIFT   (29U)
#define	DMA_ERQ_ERQ29(x)
#define	DMA_ERQ_ERQ30_MASK   (0x40000000U)
#define	DMA_ERQ_ERQ30_SHIFT   (30U)
#define	DMA_ERQ_ERQ30(x)
#define	DMA_ERQ_ERQ31_MASK   (0x80000000U)
#define	DMA_ERQ_ERQ31_SHIFT   (31U)
#define	DMA_ERQ_ERQ31(x)
EEI - Enable Error Interrupt
#define	DMA_EEI_EEI0_MASK   (0x1U)
#define	DMA_EEI_EEI0_SHIFT   (0U)
#define	DMA_EEI_EEI0(x)
#define	DMA_EEI_EEI1_MASK   (0x2U)
#define	DMA_EEI_EEI1_SHIFT   (1U)
#define	DMA_EEI_EEI1(x)
#define	DMA_EEI_EEI2_MASK   (0x4U)
#define	DMA_EEI_EEI2_SHIFT   (2U)
#define	DMA_EEI_EEI2(x)
#define	DMA_EEI_EEI3_MASK   (0x8U)
#define	DMA_EEI_EEI3_SHIFT   (3U)
#define	DMA_EEI_EEI3(x)
#define	DMA_EEI_EEI4_MASK   (0x10U)
#define	DMA_EEI_EEI4_SHIFT   (4U)
#define	DMA_EEI_EEI4(x)
#define	DMA_EEI_EEI5_MASK   (0x20U)
#define	DMA_EEI_EEI5_SHIFT   (5U)
#define	DMA_EEI_EEI5(x)
#define	DMA_EEI_EEI6_MASK   (0x40U)
#define	DMA_EEI_EEI6_SHIFT   (6U)
#define	DMA_EEI_EEI6(x)
#define	DMA_EEI_EEI7_MASK   (0x80U)
#define	DMA_EEI_EEI7_SHIFT   (7U)
#define	DMA_EEI_EEI7(x)
#define	DMA_EEI_EEI8_MASK   (0x100U)
#define	DMA_EEI_EEI8_SHIFT   (8U)
#define	DMA_EEI_EEI8(x)
#define	DMA_EEI_EEI9_MASK   (0x200U)
#define	DMA_EEI_EEI9_SHIFT   (9U)
#define	DMA_EEI_EEI9(x)
#define	DMA_EEI_EEI10_MASK   (0x400U)
#define	DMA_EEI_EEI10_SHIFT   (10U)
#define	DMA_EEI_EEI10(x)
#define	DMA_EEI_EEI11_MASK   (0x800U)
#define	DMA_EEI_EEI11_SHIFT   (11U)
#define	DMA_EEI_EEI11(x)
#define	DMA_EEI_EEI12_MASK   (0x1000U)
#define	DMA_EEI_EEI12_SHIFT   (12U)
#define	DMA_EEI_EEI12(x)
#define	DMA_EEI_EEI13_MASK   (0x2000U)
#define	DMA_EEI_EEI13_SHIFT   (13U)
#define	DMA_EEI_EEI13(x)
#define	DMA_EEI_EEI14_MASK   (0x4000U)
#define	DMA_EEI_EEI14_SHIFT   (14U)
#define	DMA_EEI_EEI14(x)
#define	DMA_EEI_EEI15_MASK   (0x8000U)
#define	DMA_EEI_EEI15_SHIFT   (15U)
#define	DMA_EEI_EEI15(x)
#define	DMA_EEI_EEI16_MASK   (0x10000U)
#define	DMA_EEI_EEI16_SHIFT   (16U)
#define	DMA_EEI_EEI16(x)
#define	DMA_EEI_EEI17_MASK   (0x20000U)
#define	DMA_EEI_EEI17_SHIFT   (17U)
#define	DMA_EEI_EEI17(x)
#define	DMA_EEI_EEI18_MASK   (0x40000U)
#define	DMA_EEI_EEI18_SHIFT   (18U)
#define	DMA_EEI_EEI18(x)
#define	DMA_EEI_EEI19_MASK   (0x80000U)
#define	DMA_EEI_EEI19_SHIFT   (19U)
#define	DMA_EEI_EEI19(x)
#define	DMA_EEI_EEI20_MASK   (0x100000U)
#define	DMA_EEI_EEI20_SHIFT   (20U)
#define	DMA_EEI_EEI20(x)
#define	DMA_EEI_EEI21_MASK   (0x200000U)
#define	DMA_EEI_EEI21_SHIFT   (21U)
#define	DMA_EEI_EEI21(x)
#define	DMA_EEI_EEI22_MASK   (0x400000U)
#define	DMA_EEI_EEI22_SHIFT   (22U)
#define	DMA_EEI_EEI22(x)
#define	DMA_EEI_EEI23_MASK   (0x800000U)
#define	DMA_EEI_EEI23_SHIFT   (23U)
#define	DMA_EEI_EEI23(x)
#define	DMA_EEI_EEI24_MASK   (0x1000000U)
#define	DMA_EEI_EEI24_SHIFT   (24U)
#define	DMA_EEI_EEI24(x)
#define	DMA_EEI_EEI25_MASK   (0x2000000U)
#define	DMA_EEI_EEI25_SHIFT   (25U)
#define	DMA_EEI_EEI25(x)
#define	DMA_EEI_EEI26_MASK   (0x4000000U)
#define	DMA_EEI_EEI26_SHIFT   (26U)
#define	DMA_EEI_EEI26(x)
#define	DMA_EEI_EEI27_MASK   (0x8000000U)
#define	DMA_EEI_EEI27_SHIFT   (27U)
#define	DMA_EEI_EEI27(x)
#define	DMA_EEI_EEI28_MASK   (0x10000000U)
#define	DMA_EEI_EEI28_SHIFT   (28U)
#define	DMA_EEI_EEI28(x)
#define	DMA_EEI_EEI29_MASK   (0x20000000U)
#define	DMA_EEI_EEI29_SHIFT   (29U)
#define	DMA_EEI_EEI29(x)
#define	DMA_EEI_EEI30_MASK   (0x40000000U)
#define	DMA_EEI_EEI30_SHIFT   (30U)
#define	DMA_EEI_EEI30(x)
#define	DMA_EEI_EEI31_MASK   (0x80000000U)
#define	DMA_EEI_EEI31_SHIFT   (31U)
#define	DMA_EEI_EEI31(x)
CEEI - Clear Enable Error Interrupt
#define	DMA_CEEI_CEEI_MASK   (0x1FU)
#define	DMA_CEEI_CEEI_SHIFT   (0U)
#define	DMA_CEEI_CEEI(x)
#define	DMA_CEEI_CAEE_MASK   (0x40U)
#define	DMA_CEEI_CAEE_SHIFT   (6U)
#define	DMA_CEEI_CAEE(x)
#define	DMA_CEEI_NOP_MASK   (0x80U)
#define	DMA_CEEI_NOP_SHIFT   (7U)
#define	DMA_CEEI_NOP(x)
SEEI - Set Enable Error Interrupt
#define	DMA_SEEI_SEEI_MASK   (0x1FU)
#define	DMA_SEEI_SEEI_SHIFT   (0U)
#define	DMA_SEEI_SEEI(x)
#define	DMA_SEEI_SAEE_MASK   (0x40U)
#define	DMA_SEEI_SAEE_SHIFT   (6U)
#define	DMA_SEEI_SAEE(x)
#define	DMA_SEEI_NOP_MASK   (0x80U)
#define	DMA_SEEI_NOP_SHIFT   (7U)
#define	DMA_SEEI_NOP(x)
CERQ - Clear Enable Request
#define	DMA_CERQ_CERQ_MASK   (0x1FU)
#define	DMA_CERQ_CERQ_SHIFT   (0U)
#define	DMA_CERQ_CERQ(x)
#define	DMA_CERQ_CAER_MASK   (0x40U)
#define	DMA_CERQ_CAER_SHIFT   (6U)
#define	DMA_CERQ_CAER(x)
#define	DMA_CERQ_NOP_MASK   (0x80U)
#define	DMA_CERQ_NOP_SHIFT   (7U)
#define	DMA_CERQ_NOP(x)
SERQ - Set Enable Request
#define	DMA_SERQ_SERQ_MASK   (0x1FU)
#define	DMA_SERQ_SERQ_SHIFT   (0U)
#define	DMA_SERQ_SERQ(x)
#define	DMA_SERQ_SAER_MASK   (0x40U)
#define	DMA_SERQ_SAER_SHIFT   (6U)
#define	DMA_SERQ_SAER(x)
#define	DMA_SERQ_NOP_MASK   (0x80U)
#define	DMA_SERQ_NOP_SHIFT   (7U)
#define	DMA_SERQ_NOP(x)
CDNE - Clear DONE Status Bit
#define	DMA_CDNE_CDNE_MASK   (0x1FU)
#define	DMA_CDNE_CDNE_SHIFT   (0U)
#define	DMA_CDNE_CDNE(x)
#define	DMA_CDNE_CADN_MASK   (0x40U)
#define	DMA_CDNE_CADN_SHIFT   (6U)
#define	DMA_CDNE_CADN(x)
#define	DMA_CDNE_NOP_MASK   (0x80U)
#define	DMA_CDNE_NOP_SHIFT   (7U)
#define	DMA_CDNE_NOP(x)
SSRT - Set START Bit
#define	DMA_SSRT_SSRT_MASK   (0x1FU)
#define	DMA_SSRT_SSRT_SHIFT   (0U)
#define	DMA_SSRT_SSRT(x)
#define	DMA_SSRT_SAST_MASK   (0x40U)
#define	DMA_SSRT_SAST_SHIFT   (6U)
#define	DMA_SSRT_SAST(x)
#define	DMA_SSRT_NOP_MASK   (0x80U)
#define	DMA_SSRT_NOP_SHIFT   (7U)
#define	DMA_SSRT_NOP(x)
CERR - Clear Error
#define	DMA_CERR_CERR_MASK   (0x1FU)
#define	DMA_CERR_CERR_SHIFT   (0U)
#define	DMA_CERR_CERR(x)
#define	DMA_CERR_CAEI_MASK   (0x40U)
#define	DMA_CERR_CAEI_SHIFT   (6U)
#define	DMA_CERR_CAEI(x)
#define	DMA_CERR_NOP_MASK   (0x80U)
#define	DMA_CERR_NOP_SHIFT   (7U)
#define	DMA_CERR_NOP(x)
CINT - Clear Interrupt Request
#define	DMA_CINT_CINT_MASK   (0x1FU)
#define	DMA_CINT_CINT_SHIFT   (0U)
#define	DMA_CINT_CINT(x)
#define	DMA_CINT_CAIR_MASK   (0x40U)
#define	DMA_CINT_CAIR_SHIFT   (6U)
#define	DMA_CINT_CAIR(x)
#define	DMA_CINT_NOP_MASK   (0x80U)
#define	DMA_CINT_NOP_SHIFT   (7U)
#define	DMA_CINT_NOP(x)
INT - Interrupt Request
#define	DMA_INT_INT0_MASK   (0x1U)
#define	DMA_INT_INT0_SHIFT   (0U)
#define	DMA_INT_INT0(x)
#define	DMA_INT_INT1_MASK   (0x2U)
#define	DMA_INT_INT1_SHIFT   (1U)
#define	DMA_INT_INT1(x)
#define	DMA_INT_INT2_MASK   (0x4U)
#define	DMA_INT_INT2_SHIFT   (2U)
#define	DMA_INT_INT2(x)
#define	DMA_INT_INT3_MASK   (0x8U)
#define	DMA_INT_INT3_SHIFT   (3U)
#define	DMA_INT_INT3(x)
#define	DMA_INT_INT4_MASK   (0x10U)
#define	DMA_INT_INT4_SHIFT   (4U)
#define	DMA_INT_INT4(x)
#define	DMA_INT_INT5_MASK   (0x20U)
#define	DMA_INT_INT5_SHIFT   (5U)
#define	DMA_INT_INT5(x)
#define	DMA_INT_INT6_MASK   (0x40U)
#define	DMA_INT_INT6_SHIFT   (6U)
#define	DMA_INT_INT6(x)
#define	DMA_INT_INT7_MASK   (0x80U)
#define	DMA_INT_INT7_SHIFT   (7U)
#define	DMA_INT_INT7(x)
#define	DMA_INT_INT8_MASK   (0x100U)
#define	DMA_INT_INT8_SHIFT   (8U)
#define	DMA_INT_INT8(x)
#define	DMA_INT_INT9_MASK   (0x200U)
#define	DMA_INT_INT9_SHIFT   (9U)
#define	DMA_INT_INT9(x)
#define	DMA_INT_INT10_MASK   (0x400U)
#define	DMA_INT_INT10_SHIFT   (10U)
#define	DMA_INT_INT10(x)
#define	DMA_INT_INT11_MASK   (0x800U)
#define	DMA_INT_INT11_SHIFT   (11U)
#define	DMA_INT_INT11(x)
#define	DMA_INT_INT12_MASK   (0x1000U)
#define	DMA_INT_INT12_SHIFT   (12U)
#define	DMA_INT_INT12(x)
#define	DMA_INT_INT13_MASK   (0x2000U)
#define	DMA_INT_INT13_SHIFT   (13U)
#define	DMA_INT_INT13(x)
#define	DMA_INT_INT14_MASK   (0x4000U)
#define	DMA_INT_INT14_SHIFT   (14U)
#define	DMA_INT_INT14(x)
#define	DMA_INT_INT15_MASK   (0x8000U)
#define	DMA_INT_INT15_SHIFT   (15U)
#define	DMA_INT_INT15(x)
#define	DMA_INT_INT16_MASK   (0x10000U)
#define	DMA_INT_INT16_SHIFT   (16U)
#define	DMA_INT_INT16(x)
#define	DMA_INT_INT17_MASK   (0x20000U)
#define	DMA_INT_INT17_SHIFT   (17U)
#define	DMA_INT_INT17(x)
#define	DMA_INT_INT18_MASK   (0x40000U)
#define	DMA_INT_INT18_SHIFT   (18U)
#define	DMA_INT_INT18(x)
#define	DMA_INT_INT19_MASK   (0x80000U)
#define	DMA_INT_INT19_SHIFT   (19U)
#define	DMA_INT_INT19(x)
#define	DMA_INT_INT20_MASK   (0x100000U)
#define	DMA_INT_INT20_SHIFT   (20U)
#define	DMA_INT_INT20(x)
#define	DMA_INT_INT21_MASK   (0x200000U)
#define	DMA_INT_INT21_SHIFT   (21U)
#define	DMA_INT_INT21(x)
#define	DMA_INT_INT22_MASK   (0x400000U)
#define	DMA_INT_INT22_SHIFT   (22U)
#define	DMA_INT_INT22(x)
#define	DMA_INT_INT23_MASK   (0x800000U)
#define	DMA_INT_INT23_SHIFT   (23U)
#define	DMA_INT_INT23(x)
#define	DMA_INT_INT24_MASK   (0x1000000U)
#define	DMA_INT_INT24_SHIFT   (24U)
#define	DMA_INT_INT24(x)
#define	DMA_INT_INT25_MASK   (0x2000000U)
#define	DMA_INT_INT25_SHIFT   (25U)
#define	DMA_INT_INT25(x)
#define	DMA_INT_INT26_MASK   (0x4000000U)
#define	DMA_INT_INT26_SHIFT   (26U)
#define	DMA_INT_INT26(x)
#define	DMA_INT_INT27_MASK   (0x8000000U)
#define	DMA_INT_INT27_SHIFT   (27U)
#define	DMA_INT_INT27(x)
#define	DMA_INT_INT28_MASK   (0x10000000U)
#define	DMA_INT_INT28_SHIFT   (28U)
#define	DMA_INT_INT28(x)
#define	DMA_INT_INT29_MASK   (0x20000000U)
#define	DMA_INT_INT29_SHIFT   (29U)
#define	DMA_INT_INT29(x)
#define	DMA_INT_INT30_MASK   (0x40000000U)
#define	DMA_INT_INT30_SHIFT   (30U)
#define	DMA_INT_INT30(x)
#define	DMA_INT_INT31_MASK   (0x80000000U)
#define	DMA_INT_INT31_SHIFT   (31U)
#define	DMA_INT_INT31(x)
ERR - Error
#define	DMA_ERR_ERR0_MASK   (0x1U)
#define	DMA_ERR_ERR0_SHIFT   (0U)
#define	DMA_ERR_ERR0(x)
#define	DMA_ERR_ERR1_MASK   (0x2U)
#define	DMA_ERR_ERR1_SHIFT   (1U)
#define	DMA_ERR_ERR1(x)
#define	DMA_ERR_ERR2_MASK   (0x4U)
#define	DMA_ERR_ERR2_SHIFT   (2U)
#define	DMA_ERR_ERR2(x)
#define	DMA_ERR_ERR3_MASK   (0x8U)
#define	DMA_ERR_ERR3_SHIFT   (3U)
#define	DMA_ERR_ERR3(x)
#define	DMA_ERR_ERR4_MASK   (0x10U)
#define	DMA_ERR_ERR4_SHIFT   (4U)
#define	DMA_ERR_ERR4(x)
#define	DMA_ERR_ERR5_MASK   (0x20U)
#define	DMA_ERR_ERR5_SHIFT   (5U)
#define	DMA_ERR_ERR5(x)
#define	DMA_ERR_ERR6_MASK   (0x40U)
#define	DMA_ERR_ERR6_SHIFT   (6U)
#define	DMA_ERR_ERR6(x)
#define	DMA_ERR_ERR7_MASK   (0x80U)
#define	DMA_ERR_ERR7_SHIFT   (7U)
#define	DMA_ERR_ERR7(x)
#define	DMA_ERR_ERR8_MASK   (0x100U)
#define	DMA_ERR_ERR8_SHIFT   (8U)
#define	DMA_ERR_ERR8(x)
#define	DMA_ERR_ERR9_MASK   (0x200U)
#define	DMA_ERR_ERR9_SHIFT   (9U)
#define	DMA_ERR_ERR9(x)
#define	DMA_ERR_ERR10_MASK   (0x400U)
#define	DMA_ERR_ERR10_SHIFT   (10U)
#define	DMA_ERR_ERR10(x)
#define	DMA_ERR_ERR11_MASK   (0x800U)
#define	DMA_ERR_ERR11_SHIFT   (11U)
#define	DMA_ERR_ERR11(x)
#define	DMA_ERR_ERR12_MASK   (0x1000U)
#define	DMA_ERR_ERR12_SHIFT   (12U)
#define	DMA_ERR_ERR12(x)
#define	DMA_ERR_ERR13_MASK   (0x2000U)
#define	DMA_ERR_ERR13_SHIFT   (13U)
#define	DMA_ERR_ERR13(x)
#define	DMA_ERR_ERR14_MASK   (0x4000U)
#define	DMA_ERR_ERR14_SHIFT   (14U)
#define	DMA_ERR_ERR14(x)
#define	DMA_ERR_ERR15_MASK   (0x8000U)
#define	DMA_ERR_ERR15_SHIFT   (15U)
#define	DMA_ERR_ERR15(x)
#define	DMA_ERR_ERR16_MASK   (0x10000U)
#define	DMA_ERR_ERR16_SHIFT   (16U)
#define	DMA_ERR_ERR16(x)
#define	DMA_ERR_ERR17_MASK   (0x20000U)
#define	DMA_ERR_ERR17_SHIFT   (17U)
#define	DMA_ERR_ERR17(x)
#define	DMA_ERR_ERR18_MASK   (0x40000U)
#define	DMA_ERR_ERR18_SHIFT   (18U)
#define	DMA_ERR_ERR18(x)
#define	DMA_ERR_ERR19_MASK   (0x80000U)
#define	DMA_ERR_ERR19_SHIFT   (19U)
#define	DMA_ERR_ERR19(x)
#define	DMA_ERR_ERR20_MASK   (0x100000U)
#define	DMA_ERR_ERR20_SHIFT   (20U)
#define	DMA_ERR_ERR20(x)
#define	DMA_ERR_ERR21_MASK   (0x200000U)
#define	DMA_ERR_ERR21_SHIFT   (21U)
#define	DMA_ERR_ERR21(x)
#define	DMA_ERR_ERR22_MASK   (0x400000U)
#define	DMA_ERR_ERR22_SHIFT   (22U)
#define	DMA_ERR_ERR22(x)
#define	DMA_ERR_ERR23_MASK   (0x800000U)
#define	DMA_ERR_ERR23_SHIFT   (23U)
#define	DMA_ERR_ERR23(x)
#define	DMA_ERR_ERR24_MASK   (0x1000000U)
#define	DMA_ERR_ERR24_SHIFT   (24U)
#define	DMA_ERR_ERR24(x)
#define	DMA_ERR_ERR25_MASK   (0x2000000U)
#define	DMA_ERR_ERR25_SHIFT   (25U)
#define	DMA_ERR_ERR25(x)
#define	DMA_ERR_ERR26_MASK   (0x4000000U)
#define	DMA_ERR_ERR26_SHIFT   (26U)
#define	DMA_ERR_ERR26(x)
#define	DMA_ERR_ERR27_MASK   (0x8000000U)
#define	DMA_ERR_ERR27_SHIFT   (27U)
#define	DMA_ERR_ERR27(x)
#define	DMA_ERR_ERR28_MASK   (0x10000000U)
#define	DMA_ERR_ERR28_SHIFT   (28U)
#define	DMA_ERR_ERR28(x)
#define	DMA_ERR_ERR29_MASK   (0x20000000U)
#define	DMA_ERR_ERR29_SHIFT   (29U)
#define	DMA_ERR_ERR29(x)
#define	DMA_ERR_ERR30_MASK   (0x40000000U)
#define	DMA_ERR_ERR30_SHIFT   (30U)
#define	DMA_ERR_ERR30(x)
#define	DMA_ERR_ERR31_MASK   (0x80000000U)
#define	DMA_ERR_ERR31_SHIFT   (31U)
#define	DMA_ERR_ERR31(x)
HRS - Hardware Request Status
#define	DMA_HRS_HRS0_MASK   (0x1U)
#define	DMA_HRS_HRS0_SHIFT   (0U)
#define	DMA_HRS_HRS0(x)
#define	DMA_HRS_HRS1_MASK   (0x2U)
#define	DMA_HRS_HRS1_SHIFT   (1U)
#define	DMA_HRS_HRS1(x)
#define	DMA_HRS_HRS2_MASK   (0x4U)
#define	DMA_HRS_HRS2_SHIFT   (2U)
#define	DMA_HRS_HRS2(x)
#define	DMA_HRS_HRS3_MASK   (0x8U)
#define	DMA_HRS_HRS3_SHIFT   (3U)
#define	DMA_HRS_HRS3(x)
#define	DMA_HRS_HRS4_MASK   (0x10U)
#define	DMA_HRS_HRS4_SHIFT   (4U)
#define	DMA_HRS_HRS4(x)
#define	DMA_HRS_HRS5_MASK   (0x20U)
#define	DMA_HRS_HRS5_SHIFT   (5U)
#define	DMA_HRS_HRS5(x)
#define	DMA_HRS_HRS6_MASK   (0x40U)
#define	DMA_HRS_HRS6_SHIFT   (6U)
#define	DMA_HRS_HRS6(x)
#define	DMA_HRS_HRS7_MASK   (0x80U)
#define	DMA_HRS_HRS7_SHIFT   (7U)
#define	DMA_HRS_HRS7(x)
#define	DMA_HRS_HRS8_MASK   (0x100U)
#define	DMA_HRS_HRS8_SHIFT   (8U)
#define	DMA_HRS_HRS8(x)
#define	DMA_HRS_HRS9_MASK   (0x200U)
#define	DMA_HRS_HRS9_SHIFT   (9U)
#define	DMA_HRS_HRS9(x)
#define	DMA_HRS_HRS10_MASK   (0x400U)
#define	DMA_HRS_HRS10_SHIFT   (10U)
#define	DMA_HRS_HRS10(x)
#define	DMA_HRS_HRS11_MASK   (0x800U)
#define	DMA_HRS_HRS11_SHIFT   (11U)
#define	DMA_HRS_HRS11(x)
#define	DMA_HRS_HRS12_MASK   (0x1000U)
#define	DMA_HRS_HRS12_SHIFT   (12U)
#define	DMA_HRS_HRS12(x)
#define	DMA_HRS_HRS13_MASK   (0x2000U)
#define	DMA_HRS_HRS13_SHIFT   (13U)
#define	DMA_HRS_HRS13(x)
#define	DMA_HRS_HRS14_MASK   (0x4000U)
#define	DMA_HRS_HRS14_SHIFT   (14U)
#define	DMA_HRS_HRS14(x)
#define	DMA_HRS_HRS15_MASK   (0x8000U)
#define	DMA_HRS_HRS15_SHIFT   (15U)
#define	DMA_HRS_HRS15(x)
#define	DMA_HRS_HRS16_MASK   (0x10000U)
#define	DMA_HRS_HRS16_SHIFT   (16U)
#define	DMA_HRS_HRS16(x)
#define	DMA_HRS_HRS17_MASK   (0x20000U)
#define	DMA_HRS_HRS17_SHIFT   (17U)
#define	DMA_HRS_HRS17(x)
#define	DMA_HRS_HRS18_MASK   (0x40000U)
#define	DMA_HRS_HRS18_SHIFT   (18U)
#define	DMA_HRS_HRS18(x)
#define	DMA_HRS_HRS19_MASK   (0x80000U)
#define	DMA_HRS_HRS19_SHIFT   (19U)
#define	DMA_HRS_HRS19(x)
#define	DMA_HRS_HRS20_MASK   (0x100000U)
#define	DMA_HRS_HRS20_SHIFT   (20U)
#define	DMA_HRS_HRS20(x)
#define	DMA_HRS_HRS21_MASK   (0x200000U)
#define	DMA_HRS_HRS21_SHIFT   (21U)
#define	DMA_HRS_HRS21(x)
#define	DMA_HRS_HRS22_MASK   (0x400000U)
#define	DMA_HRS_HRS22_SHIFT   (22U)
#define	DMA_HRS_HRS22(x)
#define	DMA_HRS_HRS23_MASK   (0x800000U)
#define	DMA_HRS_HRS23_SHIFT   (23U)
#define	DMA_HRS_HRS23(x)
#define	DMA_HRS_HRS24_MASK   (0x1000000U)
#define	DMA_HRS_HRS24_SHIFT   (24U)
#define	DMA_HRS_HRS24(x)
#define	DMA_HRS_HRS25_MASK   (0x2000000U)
#define	DMA_HRS_HRS25_SHIFT   (25U)
#define	DMA_HRS_HRS25(x)
#define	DMA_HRS_HRS26_MASK   (0x4000000U)
#define	DMA_HRS_HRS26_SHIFT   (26U)
#define	DMA_HRS_HRS26(x)
#define	DMA_HRS_HRS27_MASK   (0x8000000U)
#define	DMA_HRS_HRS27_SHIFT   (27U)
#define	DMA_HRS_HRS27(x)
#define	DMA_HRS_HRS28_MASK   (0x10000000U)
#define	DMA_HRS_HRS28_SHIFT   (28U)
#define	DMA_HRS_HRS28(x)
#define	DMA_HRS_HRS29_MASK   (0x20000000U)
#define	DMA_HRS_HRS29_SHIFT   (29U)
#define	DMA_HRS_HRS29(x)
#define	DMA_HRS_HRS30_MASK   (0x40000000U)
#define	DMA_HRS_HRS30_SHIFT   (30U)
#define	DMA_HRS_HRS30(x)
#define	DMA_HRS_HRS31_MASK   (0x80000000U)
#define	DMA_HRS_HRS31_SHIFT   (31U)
#define	DMA_HRS_HRS31(x)
EARS - Enable Asynchronous Request in Stop
#define	DMA_EARS_EDREQ_0_MASK   (0x1U)
#define	DMA_EARS_EDREQ_0_SHIFT   (0U)
#define	DMA_EARS_EDREQ_0(x)
#define	DMA_EARS_EDREQ_1_MASK   (0x2U)
#define	DMA_EARS_EDREQ_1_SHIFT   (1U)
#define	DMA_EARS_EDREQ_1(x)
#define	DMA_EARS_EDREQ_2_MASK   (0x4U)
#define	DMA_EARS_EDREQ_2_SHIFT   (2U)
#define	DMA_EARS_EDREQ_2(x)
#define	DMA_EARS_EDREQ_3_MASK   (0x8U)
#define	DMA_EARS_EDREQ_3_SHIFT   (3U)
#define	DMA_EARS_EDREQ_3(x)
#define	DMA_EARS_EDREQ_4_MASK   (0x10U)
#define	DMA_EARS_EDREQ_4_SHIFT   (4U)
#define	DMA_EARS_EDREQ_4(x)
#define	DMA_EARS_EDREQ_5_MASK   (0x20U)
#define	DMA_EARS_EDREQ_5_SHIFT   (5U)
#define	DMA_EARS_EDREQ_5(x)
#define	DMA_EARS_EDREQ_6_MASK   (0x40U)
#define	DMA_EARS_EDREQ_6_SHIFT   (6U)
#define	DMA_EARS_EDREQ_6(x)
#define	DMA_EARS_EDREQ_7_MASK   (0x80U)
#define	DMA_EARS_EDREQ_7_SHIFT   (7U)
#define	DMA_EARS_EDREQ_7(x)
#define	DMA_EARS_EDREQ_8_MASK   (0x100U)
#define	DMA_EARS_EDREQ_8_SHIFT   (8U)
#define	DMA_EARS_EDREQ_8(x)
#define	DMA_EARS_EDREQ_9_MASK   (0x200U)
#define	DMA_EARS_EDREQ_9_SHIFT   (9U)
#define	DMA_EARS_EDREQ_9(x)
#define	DMA_EARS_EDREQ_10_MASK   (0x400U)
#define	DMA_EARS_EDREQ_10_SHIFT   (10U)
#define	DMA_EARS_EDREQ_10(x)
#define	DMA_EARS_EDREQ_11_MASK   (0x800U)
#define	DMA_EARS_EDREQ_11_SHIFT   (11U)
#define	DMA_EARS_EDREQ_11(x)
#define	DMA_EARS_EDREQ_12_MASK   (0x1000U)
#define	DMA_EARS_EDREQ_12_SHIFT   (12U)
#define	DMA_EARS_EDREQ_12(x)
#define	DMA_EARS_EDREQ_13_MASK   (0x2000U)
#define	DMA_EARS_EDREQ_13_SHIFT   (13U)
#define	DMA_EARS_EDREQ_13(x)
#define	DMA_EARS_EDREQ_14_MASK   (0x4000U)
#define	DMA_EARS_EDREQ_14_SHIFT   (14U)
#define	DMA_EARS_EDREQ_14(x)
#define	DMA_EARS_EDREQ_15_MASK   (0x8000U)
#define	DMA_EARS_EDREQ_15_SHIFT   (15U)
#define	DMA_EARS_EDREQ_15(x)
#define	DMA_EARS_EDREQ_16_MASK   (0x10000U)
#define	DMA_EARS_EDREQ_16_SHIFT   (16U)
#define	DMA_EARS_EDREQ_16(x)
#define	DMA_EARS_EDREQ_17_MASK   (0x20000U)
#define	DMA_EARS_EDREQ_17_SHIFT   (17U)
#define	DMA_EARS_EDREQ_17(x)
#define	DMA_EARS_EDREQ_18_MASK   (0x40000U)
#define	DMA_EARS_EDREQ_18_SHIFT   (18U)
#define	DMA_EARS_EDREQ_18(x)
#define	DMA_EARS_EDREQ_19_MASK   (0x80000U)
#define	DMA_EARS_EDREQ_19_SHIFT   (19U)
#define	DMA_EARS_EDREQ_19(x)
#define	DMA_EARS_EDREQ_20_MASK   (0x100000U)
#define	DMA_EARS_EDREQ_20_SHIFT   (20U)
#define	DMA_EARS_EDREQ_20(x)
#define	DMA_EARS_EDREQ_21_MASK   (0x200000U)
#define	DMA_EARS_EDREQ_21_SHIFT   (21U)
#define	DMA_EARS_EDREQ_21(x)
#define	DMA_EARS_EDREQ_22_MASK   (0x400000U)
#define	DMA_EARS_EDREQ_22_SHIFT   (22U)
#define	DMA_EARS_EDREQ_22(x)
#define	DMA_EARS_EDREQ_23_MASK   (0x800000U)
#define	DMA_EARS_EDREQ_23_SHIFT   (23U)
#define	DMA_EARS_EDREQ_23(x)
#define	DMA_EARS_EDREQ_24_MASK   (0x1000000U)
#define	DMA_EARS_EDREQ_24_SHIFT   (24U)
#define	DMA_EARS_EDREQ_24(x)
#define	DMA_EARS_EDREQ_25_MASK   (0x2000000U)
#define	DMA_EARS_EDREQ_25_SHIFT   (25U)
#define	DMA_EARS_EDREQ_25(x)
#define	DMA_EARS_EDREQ_26_MASK   (0x4000000U)
#define	DMA_EARS_EDREQ_26_SHIFT   (26U)
#define	DMA_EARS_EDREQ_26(x)
#define	DMA_EARS_EDREQ_27_MASK   (0x8000000U)
#define	DMA_EARS_EDREQ_27_SHIFT   (27U)
#define	DMA_EARS_EDREQ_27(x)
#define	DMA_EARS_EDREQ_28_MASK   (0x10000000U)
#define	DMA_EARS_EDREQ_28_SHIFT   (28U)
#define	DMA_EARS_EDREQ_28(x)
#define	DMA_EARS_EDREQ_29_MASK   (0x20000000U)
#define	DMA_EARS_EDREQ_29_SHIFT   (29U)
#define	DMA_EARS_EDREQ_29(x)
#define	DMA_EARS_EDREQ_30_MASK   (0x40000000U)
#define	DMA_EARS_EDREQ_30_SHIFT   (30U)
#define	DMA_EARS_EDREQ_30(x)
#define	DMA_EARS_EDREQ_31_MASK   (0x80000000U)
#define	DMA_EARS_EDREQ_31_SHIFT   (31U)
#define	DMA_EARS_EDREQ_31(x)
DCHPRI3 - Channel Priority
#define	DMA_DCHPRI3_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI3_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI3_CHPRI(x)
#define	DMA_DCHPRI3_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI3_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI3_GRPPRI(x)
#define	DMA_DCHPRI3_DPA_MASK   (0x40U)
#define	DMA_DCHPRI3_DPA_SHIFT   (6U)
#define	DMA_DCHPRI3_DPA(x)
#define	DMA_DCHPRI3_ECP_MASK   (0x80U)
#define	DMA_DCHPRI3_ECP_SHIFT   (7U)
#define	DMA_DCHPRI3_ECP(x)
DCHPRI2 - Channel Priority
#define	DMA_DCHPRI2_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI2_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI2_CHPRI(x)
#define	DMA_DCHPRI2_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI2_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI2_GRPPRI(x)
#define	DMA_DCHPRI2_DPA_MASK   (0x40U)
#define	DMA_DCHPRI2_DPA_SHIFT   (6U)
#define	DMA_DCHPRI2_DPA(x)
#define	DMA_DCHPRI2_ECP_MASK   (0x80U)
#define	DMA_DCHPRI2_ECP_SHIFT   (7U)
#define	DMA_DCHPRI2_ECP(x)
DCHPRI1 - Channel Priority
#define	DMA_DCHPRI1_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI1_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI1_CHPRI(x)
#define	DMA_DCHPRI1_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI1_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI1_GRPPRI(x)
#define	DMA_DCHPRI1_DPA_MASK   (0x40U)
#define	DMA_DCHPRI1_DPA_SHIFT   (6U)
#define	DMA_DCHPRI1_DPA(x)
#define	DMA_DCHPRI1_ECP_MASK   (0x80U)
#define	DMA_DCHPRI1_ECP_SHIFT   (7U)
#define	DMA_DCHPRI1_ECP(x)
DCHPRI0 - Channel Priority
#define	DMA_DCHPRI0_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI0_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI0_CHPRI(x)
#define	DMA_DCHPRI0_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI0_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI0_GRPPRI(x)
#define	DMA_DCHPRI0_DPA_MASK   (0x40U)
#define	DMA_DCHPRI0_DPA_SHIFT   (6U)
#define	DMA_DCHPRI0_DPA(x)
#define	DMA_DCHPRI0_ECP_MASK   (0x80U)
#define	DMA_DCHPRI0_ECP_SHIFT   (7U)
#define	DMA_DCHPRI0_ECP(x)
DCHPRI7 - Channel Priority
#define	DMA_DCHPRI7_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI7_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI7_CHPRI(x)
#define	DMA_DCHPRI7_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI7_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI7_GRPPRI(x)
#define	DMA_DCHPRI7_DPA_MASK   (0x40U)
#define	DMA_DCHPRI7_DPA_SHIFT   (6U)
#define	DMA_DCHPRI7_DPA(x)
#define	DMA_DCHPRI7_ECP_MASK   (0x80U)
#define	DMA_DCHPRI7_ECP_SHIFT   (7U)
#define	DMA_DCHPRI7_ECP(x)
DCHPRI6 - Channel Priority
#define	DMA_DCHPRI6_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI6_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI6_CHPRI(x)
#define	DMA_DCHPRI6_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI6_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI6_GRPPRI(x)
#define	DMA_DCHPRI6_DPA_MASK   (0x40U)
#define	DMA_DCHPRI6_DPA_SHIFT   (6U)
#define	DMA_DCHPRI6_DPA(x)
#define	DMA_DCHPRI6_ECP_MASK   (0x80U)
#define	DMA_DCHPRI6_ECP_SHIFT   (7U)
#define	DMA_DCHPRI6_ECP(x)
DCHPRI5 - Channel Priority
#define	DMA_DCHPRI5_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI5_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI5_CHPRI(x)
#define	DMA_DCHPRI5_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI5_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI5_GRPPRI(x)
#define	DMA_DCHPRI5_DPA_MASK   (0x40U)
#define	DMA_DCHPRI5_DPA_SHIFT   (6U)
#define	DMA_DCHPRI5_DPA(x)
#define	DMA_DCHPRI5_ECP_MASK   (0x80U)
#define	DMA_DCHPRI5_ECP_SHIFT   (7U)
#define	DMA_DCHPRI5_ECP(x)
DCHPRI4 - Channel Priority
#define	DMA_DCHPRI4_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI4_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI4_CHPRI(x)
#define	DMA_DCHPRI4_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI4_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI4_GRPPRI(x)
#define	DMA_DCHPRI4_DPA_MASK   (0x40U)
#define	DMA_DCHPRI4_DPA_SHIFT   (6U)
#define	DMA_DCHPRI4_DPA(x)
#define	DMA_DCHPRI4_ECP_MASK   (0x80U)
#define	DMA_DCHPRI4_ECP_SHIFT   (7U)
#define	DMA_DCHPRI4_ECP(x)
DCHPRI11 - Channel Priority
#define	DMA_DCHPRI11_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI11_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI11_CHPRI(x)
#define	DMA_DCHPRI11_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI11_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI11_GRPPRI(x)
#define	DMA_DCHPRI11_DPA_MASK   (0x40U)
#define	DMA_DCHPRI11_DPA_SHIFT   (6U)
#define	DMA_DCHPRI11_DPA(x)
#define	DMA_DCHPRI11_ECP_MASK   (0x80U)
#define	DMA_DCHPRI11_ECP_SHIFT   (7U)
#define	DMA_DCHPRI11_ECP(x)
DCHPRI10 - Channel Priority
#define	DMA_DCHPRI10_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI10_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI10_CHPRI(x)
#define	DMA_DCHPRI10_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI10_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI10_GRPPRI(x)
#define	DMA_DCHPRI10_DPA_MASK   (0x40U)
#define	DMA_DCHPRI10_DPA_SHIFT   (6U)
#define	DMA_DCHPRI10_DPA(x)
#define	DMA_DCHPRI10_ECP_MASK   (0x80U)
#define	DMA_DCHPRI10_ECP_SHIFT   (7U)
#define	DMA_DCHPRI10_ECP(x)
DCHPRI9 - Channel Priority
#define	DMA_DCHPRI9_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI9_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI9_CHPRI(x)
#define	DMA_DCHPRI9_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI9_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI9_GRPPRI(x)
#define	DMA_DCHPRI9_DPA_MASK   (0x40U)
#define	DMA_DCHPRI9_DPA_SHIFT   (6U)
#define	DMA_DCHPRI9_DPA(x)
#define	DMA_DCHPRI9_ECP_MASK   (0x80U)
#define	DMA_DCHPRI9_ECP_SHIFT   (7U)
#define	DMA_DCHPRI9_ECP(x)
DCHPRI8 - Channel Priority
#define	DMA_DCHPRI8_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI8_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI8_CHPRI(x)
#define	DMA_DCHPRI8_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI8_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI8_GRPPRI(x)
#define	DMA_DCHPRI8_DPA_MASK   (0x40U)
#define	DMA_DCHPRI8_DPA_SHIFT   (6U)
#define	DMA_DCHPRI8_DPA(x)
#define	DMA_DCHPRI8_ECP_MASK   (0x80U)
#define	DMA_DCHPRI8_ECP_SHIFT   (7U)
#define	DMA_DCHPRI8_ECP(x)
DCHPRI15 - Channel Priority
#define	DMA_DCHPRI15_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI15_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI15_CHPRI(x)
#define	DMA_DCHPRI15_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI15_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI15_GRPPRI(x)
#define	DMA_DCHPRI15_DPA_MASK   (0x40U)
#define	DMA_DCHPRI15_DPA_SHIFT   (6U)
#define	DMA_DCHPRI15_DPA(x)
#define	DMA_DCHPRI15_ECP_MASK   (0x80U)
#define	DMA_DCHPRI15_ECP_SHIFT   (7U)
#define	DMA_DCHPRI15_ECP(x)
DCHPRI14 - Channel Priority
#define	DMA_DCHPRI14_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI14_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI14_CHPRI(x)
#define	DMA_DCHPRI14_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI14_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI14_GRPPRI(x)
#define	DMA_DCHPRI14_DPA_MASK   (0x40U)
#define	DMA_DCHPRI14_DPA_SHIFT   (6U)
#define	DMA_DCHPRI14_DPA(x)
#define	DMA_DCHPRI14_ECP_MASK   (0x80U)
#define	DMA_DCHPRI14_ECP_SHIFT   (7U)
#define	DMA_DCHPRI14_ECP(x)
DCHPRI13 - Channel Priority
#define	DMA_DCHPRI13_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI13_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI13_CHPRI(x)
#define	DMA_DCHPRI13_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI13_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI13_GRPPRI(x)
#define	DMA_DCHPRI13_DPA_MASK   (0x40U)
#define	DMA_DCHPRI13_DPA_SHIFT   (6U)
#define	DMA_DCHPRI13_DPA(x)
#define	DMA_DCHPRI13_ECP_MASK   (0x80U)
#define	DMA_DCHPRI13_ECP_SHIFT   (7U)
#define	DMA_DCHPRI13_ECP(x)
DCHPRI12 - Channel Priority
#define	DMA_DCHPRI12_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI12_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI12_CHPRI(x)
#define	DMA_DCHPRI12_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI12_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI12_GRPPRI(x)
#define	DMA_DCHPRI12_DPA_MASK   (0x40U)
#define	DMA_DCHPRI12_DPA_SHIFT   (6U)
#define	DMA_DCHPRI12_DPA(x)
#define	DMA_DCHPRI12_ECP_MASK   (0x80U)
#define	DMA_DCHPRI12_ECP_SHIFT   (7U)
#define	DMA_DCHPRI12_ECP(x)
DCHPRI19 - Channel Priority
#define	DMA_DCHPRI19_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI19_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI19_CHPRI(x)
#define	DMA_DCHPRI19_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI19_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI19_GRPPRI(x)
#define	DMA_DCHPRI19_DPA_MASK   (0x40U)
#define	DMA_DCHPRI19_DPA_SHIFT   (6U)
#define	DMA_DCHPRI19_DPA(x)
#define	DMA_DCHPRI19_ECP_MASK   (0x80U)
#define	DMA_DCHPRI19_ECP_SHIFT   (7U)
#define	DMA_DCHPRI19_ECP(x)
DCHPRI18 - Channel Priority
#define	DMA_DCHPRI18_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI18_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI18_CHPRI(x)
#define	DMA_DCHPRI18_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI18_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI18_GRPPRI(x)
#define	DMA_DCHPRI18_DPA_MASK   (0x40U)
#define	DMA_DCHPRI18_DPA_SHIFT   (6U)
#define	DMA_DCHPRI18_DPA(x)
#define	DMA_DCHPRI18_ECP_MASK   (0x80U)
#define	DMA_DCHPRI18_ECP_SHIFT   (7U)
#define	DMA_DCHPRI18_ECP(x)
DCHPRI17 - Channel Priority
#define	DMA_DCHPRI17_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI17_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI17_CHPRI(x)
#define	DMA_DCHPRI17_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI17_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI17_GRPPRI(x)
#define	DMA_DCHPRI17_DPA_MASK   (0x40U)
#define	DMA_DCHPRI17_DPA_SHIFT   (6U)
#define	DMA_DCHPRI17_DPA(x)
#define	DMA_DCHPRI17_ECP_MASK   (0x80U)
#define	DMA_DCHPRI17_ECP_SHIFT   (7U)
#define	DMA_DCHPRI17_ECP(x)
DCHPRI16 - Channel Priority
#define	DMA_DCHPRI16_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI16_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI16_CHPRI(x)
#define	DMA_DCHPRI16_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI16_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI16_GRPPRI(x)
#define	DMA_DCHPRI16_DPA_MASK   (0x40U)
#define	DMA_DCHPRI16_DPA_SHIFT   (6U)
#define	DMA_DCHPRI16_DPA(x)
#define	DMA_DCHPRI16_ECP_MASK   (0x80U)
#define	DMA_DCHPRI16_ECP_SHIFT   (7U)
#define	DMA_DCHPRI16_ECP(x)
DCHPRI23 - Channel Priority
#define	DMA_DCHPRI23_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI23_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI23_CHPRI(x)
#define	DMA_DCHPRI23_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI23_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI23_GRPPRI(x)
#define	DMA_DCHPRI23_DPA_MASK   (0x40U)
#define	DMA_DCHPRI23_DPA_SHIFT   (6U)
#define	DMA_DCHPRI23_DPA(x)
#define	DMA_DCHPRI23_ECP_MASK   (0x80U)
#define	DMA_DCHPRI23_ECP_SHIFT   (7U)
#define	DMA_DCHPRI23_ECP(x)
DCHPRI22 - Channel Priority
#define	DMA_DCHPRI22_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI22_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI22_CHPRI(x)
#define	DMA_DCHPRI22_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI22_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI22_GRPPRI(x)
#define	DMA_DCHPRI22_DPA_MASK   (0x40U)
#define	DMA_DCHPRI22_DPA_SHIFT   (6U)
#define	DMA_DCHPRI22_DPA(x)
#define	DMA_DCHPRI22_ECP_MASK   (0x80U)
#define	DMA_DCHPRI22_ECP_SHIFT   (7U)
#define	DMA_DCHPRI22_ECP(x)
DCHPRI21 - Channel Priority
#define	DMA_DCHPRI21_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI21_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI21_CHPRI(x)
#define	DMA_DCHPRI21_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI21_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI21_GRPPRI(x)
#define	DMA_DCHPRI21_DPA_MASK   (0x40U)
#define	DMA_DCHPRI21_DPA_SHIFT   (6U)
#define	DMA_DCHPRI21_DPA(x)
#define	DMA_DCHPRI21_ECP_MASK   (0x80U)
#define	DMA_DCHPRI21_ECP_SHIFT   (7U)
#define	DMA_DCHPRI21_ECP(x)
DCHPRI20 - Channel Priority
#define	DMA_DCHPRI20_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI20_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI20_CHPRI(x)
#define	DMA_DCHPRI20_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI20_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI20_GRPPRI(x)
#define	DMA_DCHPRI20_DPA_MASK   (0x40U)
#define	DMA_DCHPRI20_DPA_SHIFT   (6U)
#define	DMA_DCHPRI20_DPA(x)
#define	DMA_DCHPRI20_ECP_MASK   (0x80U)
#define	DMA_DCHPRI20_ECP_SHIFT   (7U)
#define	DMA_DCHPRI20_ECP(x)
DCHPRI27 - Channel Priority
#define	DMA_DCHPRI27_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI27_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI27_CHPRI(x)
#define	DMA_DCHPRI27_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI27_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI27_GRPPRI(x)
#define	DMA_DCHPRI27_DPA_MASK   (0x40U)
#define	DMA_DCHPRI27_DPA_SHIFT   (6U)
#define	DMA_DCHPRI27_DPA(x)
#define	DMA_DCHPRI27_ECP_MASK   (0x80U)
#define	DMA_DCHPRI27_ECP_SHIFT   (7U)
#define	DMA_DCHPRI27_ECP(x)
DCHPRI26 - Channel Priority
#define	DMA_DCHPRI26_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI26_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI26_CHPRI(x)
#define	DMA_DCHPRI26_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI26_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI26_GRPPRI(x)
#define	DMA_DCHPRI26_DPA_MASK   (0x40U)
#define	DMA_DCHPRI26_DPA_SHIFT   (6U)
#define	DMA_DCHPRI26_DPA(x)
#define	DMA_DCHPRI26_ECP_MASK   (0x80U)
#define	DMA_DCHPRI26_ECP_SHIFT   (7U)
#define	DMA_DCHPRI26_ECP(x)
DCHPRI25 - Channel Priority
#define	DMA_DCHPRI25_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI25_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI25_CHPRI(x)
#define	DMA_DCHPRI25_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI25_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI25_GRPPRI(x)
#define	DMA_DCHPRI25_DPA_MASK   (0x40U)
#define	DMA_DCHPRI25_DPA_SHIFT   (6U)
#define	DMA_DCHPRI25_DPA(x)
#define	DMA_DCHPRI25_ECP_MASK   (0x80U)
#define	DMA_DCHPRI25_ECP_SHIFT   (7U)
#define	DMA_DCHPRI25_ECP(x)
DCHPRI24 - Channel Priority
#define	DMA_DCHPRI24_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI24_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI24_CHPRI(x)
#define	DMA_DCHPRI24_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI24_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI24_GRPPRI(x)
#define	DMA_DCHPRI24_DPA_MASK   (0x40U)
#define	DMA_DCHPRI24_DPA_SHIFT   (6U)
#define	DMA_DCHPRI24_DPA(x)
#define	DMA_DCHPRI24_ECP_MASK   (0x80U)
#define	DMA_DCHPRI24_ECP_SHIFT   (7U)
#define	DMA_DCHPRI24_ECP(x)
DCHPRI31 - Channel Priority
#define	DMA_DCHPRI31_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI31_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI31_CHPRI(x)
#define	DMA_DCHPRI31_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI31_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI31_GRPPRI(x)
#define	DMA_DCHPRI31_DPA_MASK   (0x40U)
#define	DMA_DCHPRI31_DPA_SHIFT   (6U)
#define	DMA_DCHPRI31_DPA(x)
#define	DMA_DCHPRI31_ECP_MASK   (0x80U)
#define	DMA_DCHPRI31_ECP_SHIFT   (7U)
#define	DMA_DCHPRI31_ECP(x)
DCHPRI30 - Channel Priority
#define	DMA_DCHPRI30_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI30_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI30_CHPRI(x)
#define	DMA_DCHPRI30_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI30_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI30_GRPPRI(x)
#define	DMA_DCHPRI30_DPA_MASK   (0x40U)
#define	DMA_DCHPRI30_DPA_SHIFT   (6U)
#define	DMA_DCHPRI30_DPA(x)
#define	DMA_DCHPRI30_ECP_MASK   (0x80U)
#define	DMA_DCHPRI30_ECP_SHIFT   (7U)
#define	DMA_DCHPRI30_ECP(x)
DCHPRI29 - Channel Priority
#define	DMA_DCHPRI29_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI29_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI29_CHPRI(x)
#define	DMA_DCHPRI29_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI29_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI29_GRPPRI(x)
#define	DMA_DCHPRI29_DPA_MASK   (0x40U)
#define	DMA_DCHPRI29_DPA_SHIFT   (6U)
#define	DMA_DCHPRI29_DPA(x)
#define	DMA_DCHPRI29_ECP_MASK   (0x80U)
#define	DMA_DCHPRI29_ECP_SHIFT   (7U)
#define	DMA_DCHPRI29_ECP(x)
DCHPRI28 - Channel Priority
#define	DMA_DCHPRI28_CHPRI_MASK   (0xFU)
#define	DMA_DCHPRI28_CHPRI_SHIFT   (0U)
#define	DMA_DCHPRI28_CHPRI(x)
#define	DMA_DCHPRI28_GRPPRI_MASK   (0x30U)
#define	DMA_DCHPRI28_GRPPRI_SHIFT   (4U)
#define	DMA_DCHPRI28_GRPPRI(x)
#define	DMA_DCHPRI28_DPA_MASK   (0x40U)
#define	DMA_DCHPRI28_DPA_SHIFT   (6U)
#define	DMA_DCHPRI28_DPA(x)
#define	DMA_DCHPRI28_ECP_MASK   (0x80U)
#define	DMA_DCHPRI28_ECP_SHIFT   (7U)
#define	DMA_DCHPRI28_ECP(x)
SADDR - TCD Source Address
#define	DMA_SADDR_SADDR_MASK   (0xFFFFFFFFU)
#define	DMA_SADDR_SADDR_SHIFT   (0U)
#define	DMA_SADDR_SADDR(x)
SOFF - TCD Signed Source Address Offset
#define	DMA_SOFF_SOFF_MASK   (0xFFFFU)
#define	DMA_SOFF_SOFF_SHIFT   (0U)
#define	DMA_SOFF_SOFF(x)
ATTR - TCD Transfer Attributes
#define	DMA_ATTR_DSIZE_MASK   (0x7U)
#define	DMA_ATTR_DSIZE_SHIFT   (0U)
#define	DMA_ATTR_DSIZE(x)
#define	DMA_ATTR_DMOD_MASK   (0xF8U)
#define	DMA_ATTR_DMOD_SHIFT   (3U)
#define	DMA_ATTR_DMOD(x)
#define	DMA_ATTR_SSIZE_MASK   (0x700U)
#define	DMA_ATTR_SSIZE_SHIFT   (8U)
#define	DMA_ATTR_SSIZE(x)
#define	DMA_ATTR_SMOD_MASK   (0xF800U)
#define	DMA_ATTR_SMOD_SHIFT   (11U)
#define	DMA_ATTR_SMOD(x)
NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)
#define	DMA_NBYTES_MLNO_NBYTES_MASK   (0xFFFFFFFFU)
#define	DMA_NBYTES_MLNO_NBYTES_SHIFT   (0U)
#define	DMA_NBYTES_MLNO_NBYTES(x)
NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK   (0x3FFFFFFFU)
#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT   (0U)
#define	DMA_NBYTES_MLOFFNO_NBYTES(x)
#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK   (0x40000000U)
#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT   (30U)
#define	DMA_NBYTES_MLOFFNO_DMLOE(x)
#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK   (0x80000000U)
#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT   (31U)
#define	DMA_NBYTES_MLOFFNO_SMLOE(x)
NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK   (0x3FFU)
#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT   (0U)
#define	DMA_NBYTES_MLOFFYES_NBYTES(x)
#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK   (0x3FFFFC00U)
#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT   (10U)
#define	DMA_NBYTES_MLOFFYES_MLOFF(x)
#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK   (0x40000000U)
#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT   (30U)
#define	DMA_NBYTES_MLOFFYES_DMLOE(x)
#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK   (0x80000000U)
#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT   (31U)
#define	DMA_NBYTES_MLOFFYES_SMLOE(x)
SLAST - TCD Last Source Address Adjustment
#define	DMA_SLAST_SLAST_MASK   (0xFFFFFFFFU)
#define	DMA_SLAST_SLAST_SHIFT   (0U)
#define	DMA_SLAST_SLAST(x)
DADDR - TCD Destination Address
#define	DMA_DADDR_DADDR_MASK   (0xFFFFFFFFU)
#define	DMA_DADDR_DADDR_SHIFT   (0U)
#define	DMA_DADDR_DADDR(x)
DOFF - TCD Signed Destination Address Offset
#define	DMA_DOFF_DOFF_MASK   (0xFFFFU)
#define	DMA_DOFF_DOFF_SHIFT   (0U)
#define	DMA_DOFF_DOFF(x)
CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_CITER_ELINKNO_CITER_MASK   (0x7FFFU)
#define	DMA_CITER_ELINKNO_CITER_SHIFT   (0U)
#define	DMA_CITER_ELINKNO_CITER(x)
#define	DMA_CITER_ELINKNO_ELINK_MASK   (0x8000U)
#define	DMA_CITER_ELINKNO_ELINK_SHIFT   (15U)
#define	DMA_CITER_ELINKNO_ELINK(x)
CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_CITER_ELINKYES_CITER_MASK   (0x1FFU)
#define	DMA_CITER_ELINKYES_CITER_SHIFT   (0U)
#define	DMA_CITER_ELINKYES_CITER(x)
#define	DMA_CITER_ELINKYES_LINKCH_MASK   (0x3E00U)
#define	DMA_CITER_ELINKYES_LINKCH_SHIFT   (9U)
#define	DMA_CITER_ELINKYES_LINKCH(x)
#define	DMA_CITER_ELINKYES_ELINK_MASK   (0x8000U)
#define	DMA_CITER_ELINKYES_ELINK_SHIFT   (15U)
#define	DMA_CITER_ELINKYES_ELINK(x)
DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
#define	DMA_DLAST_SGA_DLASTSGA_MASK   (0xFFFFFFFFU)
#define	DMA_DLAST_SGA_DLASTSGA_SHIFT   (0U)
#define	DMA_DLAST_SGA_DLASTSGA(x)
CSR - TCD Control and Status
#define	DMA_CSR_START_MASK   (0x1U)
#define	DMA_CSR_START_SHIFT   (0U)
#define	DMA_CSR_START(x)
#define	DMA_CSR_INTMAJOR_MASK   (0x2U)
#define	DMA_CSR_INTMAJOR_SHIFT   (1U)
#define	DMA_CSR_INTMAJOR(x)
#define	DMA_CSR_INTHALF_MASK   (0x4U)
#define	DMA_CSR_INTHALF_SHIFT   (2U)
#define	DMA_CSR_INTHALF(x)
#define	DMA_CSR_DREQ_MASK   (0x8U)
#define	DMA_CSR_DREQ_SHIFT   (3U)
#define	DMA_CSR_DREQ(x)
#define	DMA_CSR_ESG_MASK   (0x10U)
#define	DMA_CSR_ESG_SHIFT   (4U)
#define	DMA_CSR_ESG(x)
#define	DMA_CSR_MAJORELINK_MASK   (0x20U)
#define	DMA_CSR_MAJORELINK_SHIFT   (5U)
#define	DMA_CSR_MAJORELINK(x)
#define	DMA_CSR_ACTIVE_MASK   (0x40U)
#define	DMA_CSR_ACTIVE_SHIFT   (6U)
#define	DMA_CSR_ACTIVE(x)
#define	DMA_CSR_DONE_MASK   (0x80U)
#define	DMA_CSR_DONE_SHIFT   (7U)
#define	DMA_CSR_DONE(x)
#define	DMA_CSR_MAJORLINKCH_MASK   (0x1F00U)
#define	DMA_CSR_MAJORLINKCH_SHIFT   (8U)
#define	DMA_CSR_MAJORLINKCH(x)
#define	DMA_CSR_BWC_MASK   (0xC000U)
#define	DMA_CSR_BWC_SHIFT   (14U)
#define	DMA_CSR_BWC(x)
BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_BITER_ELINKNO_BITER_MASK   (0x7FFFU)
#define	DMA_BITER_ELINKNO_BITER_SHIFT   (0U)
#define	DMA_BITER_ELINKNO_BITER(x)
#define	DMA_BITER_ELINKNO_ELINK_MASK   (0x8000U)
#define	DMA_BITER_ELINKNO_ELINK_SHIFT   (15U)
#define	DMA_BITER_ELINKNO_ELINK(x)
BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_BITER_ELINKYES_BITER_MASK   (0x1FFU)
#define	DMA_BITER_ELINKYES_BITER_SHIFT   (0U)
#define	DMA_BITER_ELINKYES_BITER(x)
#define	DMA_BITER_ELINKYES_LINKCH_MASK   (0x3E00U)
#define	DMA_BITER_ELINKYES_LINKCH_SHIFT   (9U)
#define	DMA_BITER_ELINKYES_LINKCH(x)
#define	DMA_BITER_ELINKYES_ELINK_MASK   (0x8000U)
#define	DMA_BITER_ELINKYES_ELINK_SHIFT   (15U)
#define	DMA_BITER_ELINKYES_ELINK(x)
CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register
#define	DMAMUX_CHCFG_SOURCE_MASK   (0xFFU)
#define	DMAMUX_CHCFG_SOURCE_SHIFT   (0U)
#define	DMAMUX_CHCFG_SOURCE(x)
#define	DMAMUX_CHCFG_A_ON_MASK   (0x20000000U)
#define	DMAMUX_CHCFG_A_ON_SHIFT   (29U)
#define	DMAMUX_CHCFG_A_ON(x)
#define	DMAMUX_CHCFG_TRIG_MASK   (0x40000000U)
#define	DMAMUX_CHCFG_TRIG_SHIFT   (30U)
#define	DMAMUX_CHCFG_TRIG(x)
#define	DMAMUX_CHCFG_ENBL_MASK   (0x80000000U)
#define	DMAMUX_CHCFG_ENBL_SHIFT   (31U)
#define	DMAMUX_CHCFG_ENBL(x)
CFG_NUM_LANES - CFG_NUM_LANES
#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK   (0x3U)
#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT   (0U)
#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES(x)
CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK
#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK   (0x1U)
#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT   (0U)
#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x)
CFG_T_PRE - CFG_T_PRE
#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK   (0xFFU)
#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT   (0U)
#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS(x)
CFG_T_POST - CFG_T_POST
#define	DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK   (0xFFU)
#define	DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT   (0U)
#define	DSI_HOST_CFG_T_POST_NUM_PERIODS(x)
CFG_TX_GAP - CFG_TX_GAP
#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK   (0xFFU)
#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT   (0U)
#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x)
CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP
#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK   (0x1U)
#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT   (0U)
#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x)
CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP
#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK   (0xFFU)
#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT   (0U)
#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x)
CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT
#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT   (0U)
#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x)
CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT
#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT   (0U)
#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x)
CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT
#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT   (0U)
#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x)
CFG_TWAKEUP - CFG_TWAKEUP
#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK   (0x7FFFFU)
#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT   (0U)
#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x)
CFG_STATUS_OUT - CFG_STATUS_OUT
#define	DSI_HOST_CFG_STATUS_OUT_STATUS_MASK   (0xFFFFFFFFU)
#define	DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT   (0U)
#define	DSI_HOST_CFG_STATUS_OUT_STATUS(x)
RX_ERROR_STATUS - RX_ERROR_STATUS
#define	DSI_HOST_RX_ERROR_STATUS_STATUS_MASK   (0x7FFU)
#define	DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT   (0U)
#define	DSI_HOST_RX_ERROR_STATUS_STATUS(x)
TX_PAYLOAD - TX_PAYLOAD
#define	DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK   (0xFFFFFFFFU)
#define	DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x)
PKT_CONTROL - PKT_CONTROL
#define	DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK   (0x7FFFFFFU)
#define	DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x)
SEND_PACKET - SEND_PACKET
#define	DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK   (0x1U)
#define	DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x)
PKT_STATUS - PKT_STATUS
#define	DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK   (0x1FFU)
#define	DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x)
PKT_FIFO_WR_LEVEL - PKT_FIFO_WR_LEVEL
#define	DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK   (0xFFFFU)
#define	DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x)
PKT_FIFO_RD_LEVEL - PKT_FIFO_RD_LEVEL
#define	DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK   (0xFFFFU)
#define	DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x)
PKT_RX_PAYLOAD - PKT_RX_PAYLOAD
#define	DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK   (0xFFFFFFFFU)
#define	DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x)
PKT_RX_PKT_HEADER - PKT_RX_PKT_HEADER
#define	DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK   (0xFFFFFFU)
#define	DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x)
IRQ_STATUS - IRQ_STATUS
#define	DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK   (0xFFFFFFFFU)
#define	DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x)
IRQ_STATUS2 - IRQ_STATUS2
#define	DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK   (0x7U)
#define	DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x)
IRQ_MASK - IRQ_MASK
#define	DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK   (0xFFFFFFFFU)
#define	DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x)
IRQ_MASK2 - IRQ_MASK2
#define	DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK   (0x7U)
#define	DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT   (0U)
#define	DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x)
PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE
#define	DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK   (0xFFFFU)
#define	DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x)
PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL
#define	DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK   (0xFFFFU)
#define	DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x)
INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING
#define	DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK   (0x7U)
#define	DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x)
PIXEL_FORMAT - PIXEL_FORMAT
#define	DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK   (0x3U)
#define	DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x)
VSYNC_POLARITY - VSYNC_POLARITY
#define	DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK   (0x1U)
#define	DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x)
HSYNC_POLARITY - HSYNC_POLARITY
#define	DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK   (0x1U)
#define	DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x)
VIDEO_MODE - VIDEO_MODE
#define	DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK   (0x3U)
#define	DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x)
HFP - HFP
#define	DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK   (0xFFFFU)
#define	DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x)
HBP - HBP
#define	DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK   (0xFFFFU)
#define	DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x)
HSA - HSA
#define	DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK   (0xFFFFU)
#define	DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x)
ENABLE_MULT_PKTS - ENABLE_MULT_PKTS
#define	DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK   (0x1U)
#define	DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x)
VBP - VBP
#define	DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK   (0xFFU)
#define	DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x)
VFP - VFP
#define	DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK   (0xFFU)
#define	DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x)
BLLP_MODE - BLLP_MODE
#define	DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK   (0x1U)
#define	DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x)
USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP
#define	DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK   (0x1U)
#define	DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x)
VACTIVE - VACTIVE
#define	DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK   (0x3FFFU)
#define	DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT   (0U)
#define	DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x)
PD_TX - PD_TX
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK   (0x1U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x)
M_PRG_HS_PREPARE - M_PRG_HS_PREPARE
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK   (0x3U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x)
MC_PRG_HS_PREPARE - MC_PRG_HS_PREPARE
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK   (0x1U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x)
M_PRG_HS_ZERO - M_PRG_HS_ZERO
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK   (0x1FU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x)
MC_PRG_HS_ZERO - MC_PRG_HS_ZERO
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK   (0x3FU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x)
M_PRG_HS_TRAIL - M_PRG_HS_TRAIL
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK   (0xFU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x)
MC_PRG_HS_TRAIL - MC_PRG_HS_TRAIL
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK   (0xFU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x)
PD_PLL - PD_PLL
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK   (0x1U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x)
TST - TST
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK   (0x3FU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x)
CN - CN
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK   (0x1FU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x)
CM - CM
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK   (0xFFU)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x)
CO - CO
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK   (0x3U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x)
LOCK - LOCK
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK   (0x1U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x)
LOCK_BYP - LOCK_BYP
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK   (0x1U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x)
TX_RCAL - TX_RCAL
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK   (0x3U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x)
AUTO_PD_EN - AUTO_PD_EN
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK   (0x1U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x)
RXLPRP - RXLPRP
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK   (0x3U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x)
RXCDRP - RXCDRP
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK   (0x3U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT   (0U)
#define	DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x)
VER_ID - Version ID Register
#define	EMVSIM_VER_ID_VER_MASK   (0xFFFFFFFFU)
#define	EMVSIM_VER_ID_VER_SHIFT   (0U)
#define	EMVSIM_VER_ID_VER(x)
CLKCFG - Clock Configuration Register
#define	EMVSIM_CLKCFG_CLK_PRSC_MASK   (0xFFU)
#define	EMVSIM_CLKCFG_CLK_PRSC_SHIFT   (0U)
#define	EMVSIM_CLKCFG_CLK_PRSC(x)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK   (0x300U)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT   (8U)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK   (0xC00U)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT   (10U)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)
DIVISOR - Baud Rate Divisor Register
#define	EMVSIM_DIVISOR_DIVISOR_VALUE_MASK   (0x1FFU)
#define	EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT   (0U)
#define	EMVSIM_DIVISOR_DIVISOR_VALUE(x)
CTRL - Control Register
#define	EMVSIM_CTRL_IC_MASK   (0x1U)
#define	EMVSIM_CTRL_IC_SHIFT   (0U)
#define	EMVSIM_CTRL_IC(x)
#define	EMVSIM_CTRL_ICM_MASK   (0x2U)
#define	EMVSIM_CTRL_ICM_SHIFT   (1U)
#define	EMVSIM_CTRL_ICM(x)
#define	EMVSIM_CTRL_ANACK_MASK   (0x4U)
#define	EMVSIM_CTRL_ANACK_SHIFT   (2U)
#define	EMVSIM_CTRL_ANACK(x)
#define	EMVSIM_CTRL_ONACK_MASK   (0x8U)
#define	EMVSIM_CTRL_ONACK_SHIFT   (3U)
#define	EMVSIM_CTRL_ONACK(x)
#define	EMVSIM_CTRL_FLSH_RX_MASK   (0x100U)
#define	EMVSIM_CTRL_FLSH_RX_SHIFT   (8U)
#define	EMVSIM_CTRL_FLSH_RX(x)
#define	EMVSIM_CTRL_FLSH_TX_MASK   (0x200U)
#define	EMVSIM_CTRL_FLSH_TX_SHIFT   (9U)
#define	EMVSIM_CTRL_FLSH_TX(x)
#define	EMVSIM_CTRL_SW_RST_MASK   (0x400U)
#define	EMVSIM_CTRL_SW_RST_SHIFT   (10U)
#define	EMVSIM_CTRL_SW_RST(x)
#define	EMVSIM_CTRL_KILL_CLOCKS_MASK   (0x800U)
#define	EMVSIM_CTRL_KILL_CLOCKS_SHIFT   (11U)
#define	EMVSIM_CTRL_KILL_CLOCKS(x)
#define	EMVSIM_CTRL_DOZE_EN_MASK   (0x1000U)
#define	EMVSIM_CTRL_DOZE_EN_SHIFT   (12U)
#define	EMVSIM_CTRL_DOZE_EN(x)
#define	EMVSIM_CTRL_STOP_EN_MASK   (0x2000U)
#define	EMVSIM_CTRL_STOP_EN_SHIFT   (13U)
#define	EMVSIM_CTRL_STOP_EN(x)
#define	EMVSIM_CTRL_RCV_EN_MASK   (0x10000U)
#define	EMVSIM_CTRL_RCV_EN_SHIFT   (16U)
#define	EMVSIM_CTRL_RCV_EN(x)
#define	EMVSIM_CTRL_XMT_EN_MASK   (0x20000U)
#define	EMVSIM_CTRL_XMT_EN_SHIFT   (17U)
#define	EMVSIM_CTRL_XMT_EN(x)
#define	EMVSIM_CTRL_RCVR_11_MASK   (0x40000U)
#define	EMVSIM_CTRL_RCVR_11_SHIFT   (18U)
#define	EMVSIM_CTRL_RCVR_11(x)
#define	EMVSIM_CTRL_RX_DMA_EN_MASK   (0x80000U)
#define	EMVSIM_CTRL_RX_DMA_EN_SHIFT   (19U)
#define	EMVSIM_CTRL_RX_DMA_EN(x)
#define	EMVSIM_CTRL_TX_DMA_EN_MASK   (0x100000U)
#define	EMVSIM_CTRL_TX_DMA_EN_SHIFT   (20U)
#define	EMVSIM_CTRL_TX_DMA_EN(x)
#define	EMVSIM_CTRL_INV_CRC_VAL_MASK   (0x1000000U)
#define	EMVSIM_CTRL_INV_CRC_VAL_SHIFT   (24U)
#define	EMVSIM_CTRL_INV_CRC_VAL(x)
#define	EMVSIM_CTRL_CRC_OUT_FLIP_MASK   (0x2000000U)
#define	EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT   (25U)
#define	EMVSIM_CTRL_CRC_OUT_FLIP(x)
#define	EMVSIM_CTRL_CRC_IN_FLIP_MASK   (0x4000000U)
#define	EMVSIM_CTRL_CRC_IN_FLIP_SHIFT   (26U)
#define	EMVSIM_CTRL_CRC_IN_FLIP(x)
#define	EMVSIM_CTRL_CWT_EN_MASK   (0x8000000U)
#define	EMVSIM_CTRL_CWT_EN_SHIFT   (27U)
#define	EMVSIM_CTRL_CWT_EN(x)
#define	EMVSIM_CTRL_LRC_EN_MASK   (0x10000000U)
#define	EMVSIM_CTRL_LRC_EN_SHIFT   (28U)
#define	EMVSIM_CTRL_LRC_EN(x)
#define	EMVSIM_CTRL_CRC_EN_MASK   (0x20000000U)
#define	EMVSIM_CTRL_CRC_EN_SHIFT   (29U)
#define	EMVSIM_CTRL_CRC_EN(x)
#define	EMVSIM_CTRL_XMT_CRC_LRC_MASK   (0x40000000U)
#define	EMVSIM_CTRL_XMT_CRC_LRC_SHIFT   (30U)
#define	EMVSIM_CTRL_XMT_CRC_LRC(x)
#define	EMVSIM_CTRL_BWT_EN_MASK   (0x80000000U)
#define	EMVSIM_CTRL_BWT_EN_SHIFT   (31U)
#define	EMVSIM_CTRL_BWT_EN(x)
#define	ENC_CTRL_CMPIE_MASK   (0x1U)
#define	ENC_CTRL_CMPIE_SHIFT   (0U)
#define	ENC_CTRL_CMPIE(x)
#define	ENC_CTRL_CMPIRQ_MASK   (0x2U)
#define	ENC_CTRL_CMPIRQ_SHIFT   (1U)
#define	ENC_CTRL_CMPIRQ(x)
#define	ENC_CTRL_WDE_MASK   (0x4U)
#define	ENC_CTRL_WDE_SHIFT   (2U)
#define	ENC_CTRL_WDE(x)
#define	ENC_CTRL_DIE_MASK   (0x8U)
#define	ENC_CTRL_DIE_SHIFT   (3U)
#define	ENC_CTRL_DIE(x)
#define	ENC_CTRL_DIRQ_MASK   (0x10U)
#define	ENC_CTRL_DIRQ_SHIFT   (4U)
#define	ENC_CTRL_DIRQ(x)
#define	ENC_CTRL_XNE_MASK   (0x20U)
#define	ENC_CTRL_XNE_SHIFT   (5U)
#define	ENC_CTRL_XNE(x)
#define	ENC_CTRL_XIP_MASK   (0x40U)
#define	ENC_CTRL_XIP_SHIFT   (6U)
#define	ENC_CTRL_XIP(x)
#define	ENC_CTRL_XIE_MASK   (0x80U)
#define	ENC_CTRL_XIE_SHIFT   (7U)
#define	ENC_CTRL_XIE(x)
#define	ENC_CTRL_XIRQ_MASK   (0x100U)
#define	ENC_CTRL_XIRQ_SHIFT   (8U)
#define	ENC_CTRL_XIRQ(x)
#define	ENC_CTRL_PH1_MASK   (0x200U)
#define	ENC_CTRL_PH1_SHIFT   (9U)
#define	ENC_CTRL_PH1(x)
#define	ENC_CTRL_REV_MASK   (0x400U)
#define	ENC_CTRL_REV_SHIFT   (10U)
#define	ENC_CTRL_REV(x)
#define	ENC_CTRL_SWIP_MASK   (0x800U)
#define	ENC_CTRL_SWIP_SHIFT   (11U)
#define	ENC_CTRL_SWIP(x)
#define	ENC_CTRL_HNE_MASK   (0x1000U)
#define	ENC_CTRL_HNE_SHIFT   (12U)
#define	ENC_CTRL_HNE(x)
#define	ENC_CTRL_HIP_MASK   (0x2000U)
#define	ENC_CTRL_HIP_SHIFT   (13U)
#define	ENC_CTRL_HIP(x)
#define	ENC_CTRL_HIE_MASK   (0x4000U)
#define	ENC_CTRL_HIE_SHIFT   (14U)
#define	ENC_CTRL_HIE(x)
#define	ENC_CTRL_HIRQ_MASK   (0x8000U)
#define	ENC_CTRL_HIRQ_SHIFT   (15U)
#define	ENC_CTRL_HIRQ(x)
#define	EWM_CTRL_EWMEN_MASK   (0x1U)
#define	EWM_CTRL_EWMEN_SHIFT   (0U)
#define	EWM_CTRL_EWMEN(x)
#define	EWM_CTRL_ASSIN_MASK   (0x2U)
#define	EWM_CTRL_ASSIN_SHIFT   (1U)
#define	EWM_CTRL_ASSIN(x)
#define	EWM_CTRL_INEN_MASK   (0x4U)
#define	EWM_CTRL_INEN_SHIFT   (2U)
#define	EWM_CTRL_INEN(x)
#define	EWM_CTRL_INTEN_MASK   (0x8U)
#define	EWM_CTRL_INTEN_SHIFT   (3U)
#define	EWM_CTRL_INTEN(x)
#define	PWM_CTRL_DBLEN_MASK   (0x1U)
#define	PWM_CTRL_DBLEN_SHIFT   (0U)
#define	PWM_CTRL_DBLEN(x)
#define	PWM_CTRL_DBLX_MASK   (0x2U)
#define	PWM_CTRL_DBLX_SHIFT   (1U)
#define	PWM_CTRL_DBLX(x)
#define	PWM_CTRL_LDMOD_MASK   (0x4U)
#define	PWM_CTRL_LDMOD_SHIFT   (2U)
#define	PWM_CTRL_LDMOD(x)
#define	PWM_CTRL_SPLIT_MASK   (0x8U)
#define	PWM_CTRL_SPLIT_SHIFT   (3U)
#define	PWM_CTRL_SPLIT(x)
#define	PWM_CTRL_PRSC_MASK   (0x70U)
#define	PWM_CTRL_PRSC_SHIFT   (4U)
#define	PWM_CTRL_PRSC(x)
#define	PWM_CTRL_COMPMODE_MASK   (0x80U)
#define	PWM_CTRL_COMPMODE_SHIFT   (7U)
#define	PWM_CTRL_COMPMODE(x)
#define	PWM_CTRL_DT_MASK   (0x300U)
#define	PWM_CTRL_DT_SHIFT   (8U)
#define	PWM_CTRL_DT(x)
#define	PWM_CTRL_FULL_MASK   (0x400U)
#define	PWM_CTRL_FULL_SHIFT   (10U)
#define	PWM_CTRL_FULL(x)
#define	PWM_CTRL_HALF_MASK   (0x800U)
#define	PWM_CTRL_HALF_SHIFT   (11U)
#define	PWM_CTRL_HALF(x)
#define	PWM_CTRL_LDFQ_MASK   (0xF000U)
#define	PWM_CTRL_LDFQ_SHIFT   (12U)
#define	PWM_CTRL_LDFQ(x)
#define	SRAM_CTRL_RAM_RD_EN_MASK   (0x1U)
#define	SRAM_CTRL_RAM_RD_EN_SHIFT   (0U)
#define	SRAM_CTRL_RAM_RD_EN(x)
#define	SRAM_CTRL_RAM_WR_EN_MASK   (0x2U)
#define	SRAM_CTRL_RAM_WR_EN_SHIFT   (1U)
#define	SRAM_CTRL_RAM_WR_EN(x)
#define	SRAM_CTRL_PWR_EN_MASK   (0x3CU)
#define	SRAM_CTRL_PWR_EN_SHIFT   (2U)
#define	SRAM_CTRL_PWR_EN(x)
#define	SRAM_CTRL_TAMPER_BLOCK_EN_MASK   (0x40U)
#define	SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT   (6U)
#define	SRAM_CTRL_TAMPER_BLOCK_EN(x)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK   (0x80U)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT   (7U)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN(x)
#define	SRAM_CTRL_LOCK_BIT_MASK   (0xFF0000U)
#define	SRAM_CTRL_LOCK_BIT_SHIFT   (16U)
#define	SRAM_CTRL_LOCK_BIT(x)
#define	SSARC_LP_CTRL_DIS_HW_REQ_MASK   (0x8000000U)
#define	SSARC_LP_CTRL_DIS_HW_REQ_SHIFT   (27U)
#define	SSARC_LP_CTRL_DIS_HW_REQ(x)
#define	SSARC_LP_CTRL_SW_RESET_MASK   (0x80000000U)
#define	SSARC_LP_CTRL_SW_RESET_SHIFT   (31U)
#define	SSARC_LP_CTRL_SW_RESET(x)
INT_MASK - Interrupt Mask Register
#define	EMVSIM_INT_MASK_RDT_IM_MASK   (0x1U)
#define	EMVSIM_INT_MASK_RDT_IM_SHIFT   (0U)
#define	EMVSIM_INT_MASK_RDT_IM(x)
#define	EMVSIM_INT_MASK_TC_IM_MASK   (0x2U)
#define	EMVSIM_INT_MASK_TC_IM_SHIFT   (1U)
#define	EMVSIM_INT_MASK_TC_IM(x)
#define	EMVSIM_INT_MASK_RFO_IM_MASK   (0x4U)
#define	EMVSIM_INT_MASK_RFO_IM_SHIFT   (2U)
#define	EMVSIM_INT_MASK_RFO_IM(x)
#define	EMVSIM_INT_MASK_ETC_IM_MASK   (0x8U)
#define	EMVSIM_INT_MASK_ETC_IM_SHIFT   (3U)
#define	EMVSIM_INT_MASK_ETC_IM(x)
#define	EMVSIM_INT_MASK_TFE_IM_MASK   (0x10U)
#define	EMVSIM_INT_MASK_TFE_IM_SHIFT   (4U)
#define	EMVSIM_INT_MASK_TFE_IM(x)
#define	EMVSIM_INT_MASK_TNACK_IM_MASK   (0x20U)
#define	EMVSIM_INT_MASK_TNACK_IM_SHIFT   (5U)
#define	EMVSIM_INT_MASK_TNACK_IM(x)
#define	EMVSIM_INT_MASK_TFF_IM_MASK   (0x40U)
#define	EMVSIM_INT_MASK_TFF_IM_SHIFT   (6U)
#define	EMVSIM_INT_MASK_TFF_IM(x)
#define	EMVSIM_INT_MASK_TDT_IM_MASK   (0x80U)
#define	EMVSIM_INT_MASK_TDT_IM_SHIFT   (7U)
#define	EMVSIM_INT_MASK_TDT_IM(x)
#define	EMVSIM_INT_MASK_GPCNT0_IM_MASK   (0x100U)
#define	EMVSIM_INT_MASK_GPCNT0_IM_SHIFT   (8U)
#define	EMVSIM_INT_MASK_GPCNT0_IM(x)
#define	EMVSIM_INT_MASK_CWT_ERR_IM_MASK   (0x200U)
#define	EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT   (9U)
#define	EMVSIM_INT_MASK_CWT_ERR_IM(x)
#define	EMVSIM_INT_MASK_RNACK_IM_MASK   (0x400U)
#define	EMVSIM_INT_MASK_RNACK_IM_SHIFT   (10U)
#define	EMVSIM_INT_MASK_RNACK_IM(x)
#define	EMVSIM_INT_MASK_BWT_ERR_IM_MASK   (0x800U)
#define	EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT   (11U)
#define	EMVSIM_INT_MASK_BWT_ERR_IM(x)
#define	EMVSIM_INT_MASK_BGT_ERR_IM_MASK   (0x1000U)
#define	EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT   (12U)
#define	EMVSIM_INT_MASK_BGT_ERR_IM(x)
#define	EMVSIM_INT_MASK_GPCNT1_IM_MASK   (0x2000U)
#define	EMVSIM_INT_MASK_GPCNT1_IM_SHIFT   (13U)
#define	EMVSIM_INT_MASK_GPCNT1_IM(x)
#define	EMVSIM_INT_MASK_RX_DATA_IM_MASK   (0x4000U)
#define	EMVSIM_INT_MASK_RX_DATA_IM_SHIFT   (14U)
#define	EMVSIM_INT_MASK_RX_DATA_IM(x)
#define	EMVSIM_INT_MASK_PEF_IM_MASK   (0x8000U)
#define	EMVSIM_INT_MASK_PEF_IM_SHIFT   (15U)
#define	EMVSIM_INT_MASK_PEF_IM(x)
RX_THD - Receiver Threshold Register
#define	EMVSIM_RX_THD_RDT_MASK   (0xFU)
#define	EMVSIM_RX_THD_RDT_SHIFT   (0U)
#define	EMVSIM_RX_THD_RDT(x)
#define	EMVSIM_RX_THD_RNCK_THD_MASK   (0xF00U)
#define	EMVSIM_RX_THD_RNCK_THD_SHIFT   (8U)
#define	EMVSIM_RX_THD_RNCK_THD(x)
TX_THD - Transmitter Threshold Register
#define	EMVSIM_TX_THD_TDT_MASK   (0xFU)
#define	EMVSIM_TX_THD_TDT_SHIFT   (0U)
#define	EMVSIM_TX_THD_TDT(x)
#define	EMVSIM_TX_THD_TNCK_THD_MASK   (0xF00U)
#define	EMVSIM_TX_THD_TNCK_THD_SHIFT   (8U)
#define	EMVSIM_TX_THD_TNCK_THD(x)
RX_STATUS - Receive Status Register
#define	EMVSIM_RX_STATUS_RFO_MASK   (0x1U)
#define	EMVSIM_RX_STATUS_RFO_SHIFT   (0U)
#define	EMVSIM_RX_STATUS_RFO(x)
#define	EMVSIM_RX_STATUS_RX_DATA_MASK   (0x10U)
#define	EMVSIM_RX_STATUS_RX_DATA_SHIFT   (4U)
#define	EMVSIM_RX_STATUS_RX_DATA(x)
#define	EMVSIM_RX_STATUS_RDTF_MASK   (0x20U)
#define	EMVSIM_RX_STATUS_RDTF_SHIFT   (5U)
#define	EMVSIM_RX_STATUS_RDTF(x)
#define	EMVSIM_RX_STATUS_LRC_OK_MASK   (0x40U)
#define	EMVSIM_RX_STATUS_LRC_OK_SHIFT   (6U)
#define	EMVSIM_RX_STATUS_LRC_OK(x)
#define	EMVSIM_RX_STATUS_CRC_OK_MASK   (0x80U)
#define	EMVSIM_RX_STATUS_CRC_OK_SHIFT   (7U)
#define	EMVSIM_RX_STATUS_CRC_OK(x)
#define	EMVSIM_RX_STATUS_CWT_ERR_MASK   (0x100U)
#define	EMVSIM_RX_STATUS_CWT_ERR_SHIFT   (8U)
#define	EMVSIM_RX_STATUS_CWT_ERR(x)
#define	EMVSIM_RX_STATUS_RTE_MASK   (0x200U)
#define	EMVSIM_RX_STATUS_RTE_SHIFT   (9U)
#define	EMVSIM_RX_STATUS_RTE(x)
#define	EMVSIM_RX_STATUS_BWT_ERR_MASK   (0x400U)
#define	EMVSIM_RX_STATUS_BWT_ERR_SHIFT   (10U)
#define	EMVSIM_RX_STATUS_BWT_ERR(x)
#define	EMVSIM_RX_STATUS_BGT_ERR_MASK   (0x800U)
#define	EMVSIM_RX_STATUS_BGT_ERR_SHIFT   (11U)
#define	EMVSIM_RX_STATUS_BGT_ERR(x)
#define	EMVSIM_RX_STATUS_PEF_MASK   (0x1000U)
#define	EMVSIM_RX_STATUS_PEF_SHIFT   (12U)
#define	EMVSIM_RX_STATUS_PEF(x)
#define	EMVSIM_RX_STATUS_FEF_MASK   (0x2000U)
#define	EMVSIM_RX_STATUS_FEF_SHIFT   (13U)
#define	EMVSIM_RX_STATUS_FEF(x)
#define	EMVSIM_RX_STATUS_RX_WPTR_MASK   (0xF0000U)
#define	EMVSIM_RX_STATUS_RX_WPTR_SHIFT   (16U)
#define	EMVSIM_RX_STATUS_RX_WPTR(x)
#define	EMVSIM_RX_STATUS_RX_CNT_MASK   (0xF000000U)
#define	EMVSIM_RX_STATUS_RX_CNT_SHIFT   (24U)
#define	EMVSIM_RX_STATUS_RX_CNT(x)
TX_STATUS - Transmitter Status Register
#define	EMVSIM_TX_STATUS_TNTE_MASK   (0x1U)
#define	EMVSIM_TX_STATUS_TNTE_SHIFT   (0U)
#define	EMVSIM_TX_STATUS_TNTE(x)
#define	EMVSIM_TX_STATUS_TFE_MASK   (0x8U)
#define	EMVSIM_TX_STATUS_TFE_SHIFT   (3U)
#define	EMVSIM_TX_STATUS_TFE(x)
#define	EMVSIM_TX_STATUS_ETCF_MASK   (0x10U)
#define	EMVSIM_TX_STATUS_ETCF_SHIFT   (4U)
#define	EMVSIM_TX_STATUS_ETCF(x)
#define	EMVSIM_TX_STATUS_TCF_MASK   (0x20U)
#define	EMVSIM_TX_STATUS_TCF_SHIFT   (5U)
#define	EMVSIM_TX_STATUS_TCF(x)
#define	EMVSIM_TX_STATUS_TFF_MASK   (0x40U)
#define	EMVSIM_TX_STATUS_TFF_SHIFT   (6U)
#define	EMVSIM_TX_STATUS_TFF(x)
#define	EMVSIM_TX_STATUS_TDTF_MASK   (0x80U)
#define	EMVSIM_TX_STATUS_TDTF_SHIFT   (7U)
#define	EMVSIM_TX_STATUS_TDTF(x)
#define	EMVSIM_TX_STATUS_GPCNT0_TO_MASK   (0x100U)
#define	EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT   (8U)
#define	EMVSIM_TX_STATUS_GPCNT0_TO(x)
#define	EMVSIM_TX_STATUS_GPCNT1_TO_MASK   (0x200U)
#define	EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT   (9U)
#define	EMVSIM_TX_STATUS_GPCNT1_TO(x)
#define	EMVSIM_TX_STATUS_TX_RPTR_MASK   (0xF0000U)
#define	EMVSIM_TX_STATUS_TX_RPTR_SHIFT   (16U)
#define	EMVSIM_TX_STATUS_TX_RPTR(x)
#define	EMVSIM_TX_STATUS_TX_CNT_MASK   (0xF000000U)
#define	EMVSIM_TX_STATUS_TX_CNT_SHIFT   (24U)
#define	EMVSIM_TX_STATUS_TX_CNT(x)
PCSR - Port Control and Status Register
#define	EMVSIM_PCSR_SAPD_MASK   (0x1U)
#define	EMVSIM_PCSR_SAPD_SHIFT   (0U)
#define	EMVSIM_PCSR_SAPD(x)
#define	EMVSIM_PCSR_SVCC_EN_MASK   (0x2U)
#define	EMVSIM_PCSR_SVCC_EN_SHIFT   (1U)
#define	EMVSIM_PCSR_SVCC_EN(x)
#define	EMVSIM_PCSR_VCCENP_MASK   (0x4U)
#define	EMVSIM_PCSR_VCCENP_SHIFT   (2U)
#define	EMVSIM_PCSR_VCCENP(x)
#define	EMVSIM_PCSR_SRST_MASK   (0x8U)
#define	EMVSIM_PCSR_SRST_SHIFT   (3U)
#define	EMVSIM_PCSR_SRST(x)
#define	EMVSIM_PCSR_SCEN_MASK   (0x10U)
#define	EMVSIM_PCSR_SCEN_SHIFT   (4U)
#define	EMVSIM_PCSR_SCEN(x)
#define	EMVSIM_PCSR_SCSP_MASK   (0x20U)
#define	EMVSIM_PCSR_SCSP_SHIFT   (5U)
#define	EMVSIM_PCSR_SCSP(x)
#define	EMVSIM_PCSR_SPD_MASK   (0x80U)
#define	EMVSIM_PCSR_SPD_SHIFT   (7U)
#define	EMVSIM_PCSR_SPD(x)
#define	EMVSIM_PCSR_SPDIM_MASK   (0x1000000U)
#define	EMVSIM_PCSR_SPDIM_SHIFT   (24U)
#define	EMVSIM_PCSR_SPDIM(x)
#define	EMVSIM_PCSR_SPDIF_MASK   (0x2000000U)
#define	EMVSIM_PCSR_SPDIF_SHIFT   (25U)
#define	EMVSIM_PCSR_SPDIF(x)
#define	EMVSIM_PCSR_SPDP_MASK   (0x4000000U)
#define	EMVSIM_PCSR_SPDP_SHIFT   (26U)
#define	EMVSIM_PCSR_SPDP(x)
#define	EMVSIM_PCSR_SPDES_MASK   (0x8000000U)
#define	EMVSIM_PCSR_SPDES_SHIFT   (27U)
#define	EMVSIM_PCSR_SPDES(x)
RX_BUF - Receive Data Read Buffer
#define	EMVSIM_RX_BUF_RX_BYTE_MASK   (0xFFU)
#define	EMVSIM_RX_BUF_RX_BYTE_SHIFT   (0U)
#define	EMVSIM_RX_BUF_RX_BYTE(x)
TX_BUF - Transmit Data Buffer
#define	EMVSIM_TX_BUF_TX_BYTE_MASK   (0xFFU)
#define	EMVSIM_TX_BUF_TX_BYTE_SHIFT   (0U)
#define	EMVSIM_TX_BUF_TX_BYTE(x)
TX_GETU - Transmitter Guard ETU Value Register
#define	EMVSIM_TX_GETU_GETU_MASK   (0xFFU)
#define	EMVSIM_TX_GETU_GETU_SHIFT   (0U)
#define	EMVSIM_TX_GETU_GETU(x)
CWT_VAL - Character Wait Time Value Register
#define	EMVSIM_CWT_VAL_CWT_MASK   (0xFFFFU)
#define	EMVSIM_CWT_VAL_CWT_SHIFT   (0U)
#define	EMVSIM_CWT_VAL_CWT(x)
BWT_VAL - Block Wait Time Value Register
#define	EMVSIM_BWT_VAL_BWT_MASK   (0xFFFFFFFFU)
#define	EMVSIM_BWT_VAL_BWT_SHIFT   (0U)
#define	EMVSIM_BWT_VAL_BWT(x)
BGT_VAL - Block Guard Time Value Register
#define	EMVSIM_BGT_VAL_BGT_MASK   (0xFFFFU)
#define	EMVSIM_BGT_VAL_BGT_SHIFT   (0U)
#define	EMVSIM_BGT_VAL_BGT(x)
GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register
#define	EMVSIM_GPCNT0_VAL_GPCNT0_MASK   (0xFFFFU)
#define	EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT   (0U)
#define	EMVSIM_GPCNT0_VAL_GPCNT0(x)
GPCNT1_VAL - General Purpose Counter 1 Timeout Value
#define	EMVSIM_GPCNT1_VAL_GPCNT1_MASK   (0xFFFFU)
#define	EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT   (0U)
#define	EMVSIM_GPCNT1_VAL_GPCNT1(x)
FILT - Input Filter Register
#define	ENC_FILT_FILT_PER_MASK   (0xFFU)
#define	ENC_FILT_FILT_PER_SHIFT   (0U)
#define	ENC_FILT_FILT_PER(x)
#define	ENC_FILT_FILT_CNT_MASK   (0x700U)
#define	ENC_FILT_FILT_CNT_SHIFT   (8U)
#define	ENC_FILT_FILT_CNT(x)
#define	ENC_FILT_FILT_PRSC_MASK   (0xE000U)
#define	ENC_FILT_FILT_PRSC_SHIFT   (13U)
#define	ENC_FILT_FILT_PRSC(x)
WTR - Watchdog Timeout Register
#define	ENC_WTR_WDOG_MASK   (0xFFFFU)
#define	ENC_WTR_WDOG_SHIFT   (0U)
#define	ENC_WTR_WDOG(x)
POSD - Position Difference Counter Register
#define	ENC_POSD_POSD_MASK   (0xFFFFU)
#define	ENC_POSD_POSD_SHIFT   (0U)
#define	ENC_POSD_POSD(x)
POSDH - Position Difference Hold Register
#define	ENC_POSDH_POSDH_MASK   (0xFFFFU)
#define	ENC_POSDH_POSDH_SHIFT   (0U)
#define	ENC_POSDH_POSDH(x)
REV - Revolution Counter Register
#define	ENC_REV_REV_MASK   (0xFFFFU)
#define	ENC_REV_REV_SHIFT   (0U)
#define	ENC_REV_REV(x)
REVH - Revolution Hold Register
#define	ENC_REVH_REVH_MASK   (0xFFFFU)
#define	ENC_REVH_REVH_SHIFT   (0U)
#define	ENC_REVH_REVH(x)
UPOS - Upper Position Counter Register
#define	ENC_UPOS_POS_MASK   (0xFFFFU)
#define	ENC_UPOS_POS_SHIFT   (0U)
#define	ENC_UPOS_POS(x)
LPOS - Lower Position Counter Register
#define	ENC_LPOS_POS_MASK   (0xFFFFU)
#define	ENC_LPOS_POS_SHIFT   (0U)
#define	ENC_LPOS_POS(x)
UPOSH - Upper Position Hold Register
#define	ENC_UPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_UPOSH_POSH_SHIFT   (0U)
#define	ENC_UPOSH_POSH(x)
LPOSH - Lower Position Hold Register
#define	ENC_LPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_LPOSH_POSH_SHIFT   (0U)
#define	ENC_LPOSH_POSH(x)
UINIT - Upper Initialization Register
#define	ENC_UINIT_INIT_MASK   (0xFFFFU)
#define	ENC_UINIT_INIT_SHIFT   (0U)
#define	ENC_UINIT_INIT(x)
LINIT - Lower Initialization Register
#define	ENC_LINIT_INIT_MASK   (0xFFFFU)
#define	ENC_LINIT_INIT_SHIFT   (0U)
#define	ENC_LINIT_INIT(x)
IMR - Input Monitor Register
#define	ENC_IMR_HOME_MASK   (0x1U)
#define	ENC_IMR_HOME_SHIFT   (0U)
#define	ENC_IMR_HOME(x)
#define	ENC_IMR_INDEX_MASK   (0x2U)
#define	ENC_IMR_INDEX_SHIFT   (1U)
#define	ENC_IMR_INDEX(x)
#define	ENC_IMR_PHB_MASK   (0x4U)
#define	ENC_IMR_PHB_SHIFT   (2U)
#define	ENC_IMR_PHB(x)
#define	ENC_IMR_PHA_MASK   (0x8U)
#define	ENC_IMR_PHA_SHIFT   (3U)
#define	ENC_IMR_PHA(x)
#define	ENC_IMR_FHOM_MASK   (0x10U)
#define	ENC_IMR_FHOM_SHIFT   (4U)
#define	ENC_IMR_FHOM(x)
#define	ENC_IMR_FIND_MASK   (0x20U)
#define	ENC_IMR_FIND_SHIFT   (5U)
#define	ENC_IMR_FIND(x)
#define	ENC_IMR_FPHB_MASK   (0x40U)
#define	ENC_IMR_FPHB_SHIFT   (6U)
#define	ENC_IMR_FPHB(x)
#define	ENC_IMR_FPHA_MASK   (0x80U)
#define	ENC_IMR_FPHA_SHIFT   (7U)
#define	ENC_IMR_FPHA(x)
TST - Test Register
#define	ENC_TST_TEST_COUNT_MASK   (0xFFU)
#define	ENC_TST_TEST_COUNT_SHIFT   (0U)
#define	ENC_TST_TEST_COUNT(x)
#define	ENC_TST_TEST_PERIOD_MASK   (0x1F00U)
#define	ENC_TST_TEST_PERIOD_SHIFT   (8U)
#define	ENC_TST_TEST_PERIOD(x)
#define	ENC_TST_QDN_MASK   (0x2000U)
#define	ENC_TST_QDN_SHIFT   (13U)
#define	ENC_TST_QDN(x)
#define	ENC_TST_TCE_MASK   (0x4000U)
#define	ENC_TST_TCE_SHIFT   (14U)
#define	ENC_TST_TCE(x)
#define	ENC_TST_TEN_MASK   (0x8000U)
#define	ENC_TST_TEN_SHIFT   (15U)
#define	ENC_TST_TEN(x)
UMOD - Upper Modulus Register
#define	ENC_UMOD_MOD_MASK   (0xFFFFU)
#define	ENC_UMOD_MOD_SHIFT   (0U)
#define	ENC_UMOD_MOD(x)
LMOD - Lower Modulus Register
#define	ENC_LMOD_MOD_MASK   (0xFFFFU)
#define	ENC_LMOD_MOD_SHIFT   (0U)
#define	ENC_LMOD_MOD(x)
UCOMP - Upper Position Compare Register
#define	ENC_UCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_UCOMP_COMP_SHIFT   (0U)
#define	ENC_UCOMP_COMP(x)
LCOMP - Lower Position Compare Register
#define	ENC_LCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_LCOMP_COMP_SHIFT   (0U)
#define	ENC_LCOMP_COMP(x)
LASTEDGE - Last Edge Time Register
#define	ENC_LASTEDGE_LASTEDGE_MASK   (0xFFFFU)
#define	ENC_LASTEDGE_LASTEDGE_SHIFT   (0U)
#define	ENC_LASTEDGE_LASTEDGE(x)
LASTEDGEH - Last Edge Time Hold Register
#define	ENC_LASTEDGEH_LASTEDGEH_MASK   (0xFFFFU)
#define	ENC_LASTEDGEH_LASTEDGEH_SHIFT   (0U)
#define	ENC_LASTEDGEH_LASTEDGEH(x)
POSDPER - Position Difference Period Counter Register
#define	ENC_POSDPER_POSDPER_MASK   (0xFFFFU)
#define	ENC_POSDPER_POSDPER_SHIFT   (0U)
#define	ENC_POSDPER_POSDPER(x)
POSDPERBFR - Position Difference Period Buffer Register
#define	ENC_POSDPERBFR_POSDPERBFR_MASK   (0xFFFFU)
#define	ENC_POSDPERBFR_POSDPERBFR_SHIFT   (0U)
#define	ENC_POSDPERBFR_POSDPERBFR(x)
POSDPERH - Position Difference Period Hold Register
#define	ENC_POSDPERH_POSDPERH_MASK   (0xFFFFU)
#define	ENC_POSDPERH_POSDPERH_SHIFT   (0U)
#define	ENC_POSDPERH_POSDPERH(x)
CTRL3 - Control 3 Register
#define	ENC_CTRL3_PMEN_MASK   (0x1U)
#define	ENC_CTRL3_PMEN_SHIFT   (0U)
#define	ENC_CTRL3_PMEN(x)
#define	ENC_CTRL3_PRSC_MASK   (0xF0U)
#define	ENC_CTRL3_PRSC_SHIFT   (4U)
#define	ENC_CTRL3_PRSC(x)
EIR - Interrupt Event Register
#define	ENET_EIR_RXB1_MASK   (0x1U)
#define	ENET_EIR_RXB1_SHIFT   (0U)
#define	ENET_EIR_RXB1(x)
#define	ENET_EIR_RXF1_MASK   (0x2U)
#define	ENET_EIR_RXF1_SHIFT   (1U)
#define	ENET_EIR_RXF1(x)
#define	ENET_EIR_TXB1_MASK   (0x4U)
#define	ENET_EIR_TXB1_SHIFT   (2U)
#define	ENET_EIR_TXB1(x)
#define	ENET_EIR_TXF1_MASK   (0x8U)
#define	ENET_EIR_TXF1_SHIFT   (3U)
#define	ENET_EIR_TXF1(x)
#define	ENET_EIR_RXB2_MASK   (0x10U)
#define	ENET_EIR_RXB2_SHIFT   (4U)
#define	ENET_EIR_RXB2(x)
#define	ENET_EIR_RXF2_MASK   (0x20U)
#define	ENET_EIR_RXF2_SHIFT   (5U)
#define	ENET_EIR_RXF2(x)
#define	ENET_EIR_TXB2_MASK   (0x40U)
#define	ENET_EIR_TXB2_SHIFT   (6U)
#define	ENET_EIR_TXB2(x)
#define	ENET_EIR_TXF2_MASK   (0x80U)
#define	ENET_EIR_TXF2_SHIFT   (7U)
#define	ENET_EIR_TXF2(x)
#define	ENET_EIR_RXFLUSH_0_MASK   (0x1000U)
#define	ENET_EIR_RXFLUSH_0_SHIFT   (12U)
#define	ENET_EIR_RXFLUSH_0(x)
#define	ENET_EIR_RXFLUSH_1_MASK   (0x2000U)
#define	ENET_EIR_RXFLUSH_1_SHIFT   (13U)
#define	ENET_EIR_RXFLUSH_1(x)
#define	ENET_EIR_RXFLUSH_2_MASK   (0x4000U)
#define	ENET_EIR_RXFLUSH_2_SHIFT   (14U)
#define	ENET_EIR_RXFLUSH_2(x)
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)
EIMR - Interrupt Mask Register
#define	ENET_EIMR_RXB1_MASK   (0x1U)
#define	ENET_EIMR_RXB1_SHIFT   (0U)
#define	ENET_EIMR_RXB1(x)
#define	ENET_EIMR_RXF1_MASK   (0x2U)
#define	ENET_EIMR_RXF1_SHIFT   (1U)
#define	ENET_EIMR_RXF1(x)
#define	ENET_EIMR_TXB1_MASK   (0x4U)
#define	ENET_EIMR_TXB1_SHIFT   (2U)
#define	ENET_EIMR_TXB1(x)
#define	ENET_EIMR_TXF1_MASK   (0x8U)
#define	ENET_EIMR_TXF1_SHIFT   (3U)
#define	ENET_EIMR_TXF1(x)
#define	ENET_EIMR_RXB2_MASK   (0x10U)
#define	ENET_EIMR_RXB2_SHIFT   (4U)
#define	ENET_EIMR_RXB2(x)
#define	ENET_EIMR_RXF2_MASK   (0x20U)
#define	ENET_EIMR_RXF2_SHIFT   (5U)
#define	ENET_EIMR_RXF2(x)
#define	ENET_EIMR_TXB2_MASK   (0x40U)
#define	ENET_EIMR_TXB2_SHIFT   (6U)
#define	ENET_EIMR_TXB2(x)
#define	ENET_EIMR_TXF2_MASK   (0x80U)
#define	ENET_EIMR_TXF2_SHIFT   (7U)
#define	ENET_EIMR_TXF2(x)
#define	ENET_EIMR_RXFLUSH_0_MASK   (0x1000U)
#define	ENET_EIMR_RXFLUSH_0_SHIFT   (12U)
#define	ENET_EIMR_RXFLUSH_0(x)
#define	ENET_EIMR_RXFLUSH_1_MASK   (0x2000U)
#define	ENET_EIMR_RXFLUSH_1_SHIFT   (13U)
#define	ENET_EIMR_RXFLUSH_1(x)
#define	ENET_EIMR_RXFLUSH_2_MASK   (0x4000U)
#define	ENET_EIMR_RXFLUSH_2_SHIFT   (14U)
#define	ENET_EIMR_RXFLUSH_2(x)
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)
RDAR - Receive Descriptor Active Register - Ring 0
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)
TDAR - Transmit Descriptor Active Register - Ring 0
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)
ECR - Ethernet Control Register
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)
#define	ENET_ECR_SPEED_MASK   (0x20U)
#define	ENET_ECR_SPEED_SHIFT   (5U)
#define	ENET_ECR_SPEED(x)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)
#define	ENET_ECR_SVLANEN_MASK   (0x200U)
#define	ENET_ECR_SVLANEN_SHIFT   (9U)
#define	ENET_ECR_SVLANEN(x)
#define	ENET_ECR_VLANUSE2ND_MASK   (0x400U)
#define	ENET_ECR_VLANUSE2ND_SHIFT   (10U)
#define	ENET_ECR_VLANUSE2ND(x)
#define	ENET_ECR_SVLANDBL_MASK   (0x800U)
#define	ENET_ECR_SVLANDBL_SHIFT   (11U)
#define	ENET_ECR_SVLANDBL(x)
#define	ENET_ECR_TXC_DLY_MASK   (0x10000U)
#define	ENET_ECR_TXC_DLY_SHIFT   (16U)
#define	ENET_ECR_TXC_DLY(x)
MMFR - MII Management Frame Register
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)
MSCR - MII Speed Control Register
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)
MIBC - MIB Control Register
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)
RCR - Receive Control Register
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)
#define	ENET_RCR_RGMII_EN_MASK   (0x40U)
#define	ENET_RCR_RGMII_EN_SHIFT   (6U)
#define	ENET_RCR_RGMII_EN(x)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)
TCR - Transmit Control Register
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)
PALR - Physical Address Lower Register
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)
PAUR - Physical Address Upper Register
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)
OPD - Opcode/Pause Duration Register
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)
TXIC - Transmit Interrupt Coalescing Register
#define	ENET_TXIC_ICTT_MASK   (0xFFFFU)
#define	ENET_TXIC_ICTT_SHIFT   (0U)
#define	ENET_TXIC_ICTT(x)
#define	ENET_TXIC_ICFT_MASK   (0xFF00000U)
#define	ENET_TXIC_ICFT_SHIFT   (20U)
#define	ENET_TXIC_ICFT(x)
#define	ENET_TXIC_ICCS_MASK   (0x40000000U)
#define	ENET_TXIC_ICCS_SHIFT   (30U)
#define	ENET_TXIC_ICCS(x)
#define	ENET_TXIC_ICEN_MASK   (0x80000000U)
#define	ENET_TXIC_ICEN_SHIFT   (31U)
#define	ENET_TXIC_ICEN(x)
RXIC - Receive Interrupt Coalescing Register
#define	ENET_RXIC_ICTT_MASK   (0xFFFFU)
#define	ENET_RXIC_ICTT_SHIFT   (0U)
#define	ENET_RXIC_ICTT(x)
#define	ENET_RXIC_ICFT_MASK   (0xFF00000U)
#define	ENET_RXIC_ICFT_SHIFT   (20U)
#define	ENET_RXIC_ICFT(x)
#define	ENET_RXIC_ICCS_MASK   (0x40000000U)
#define	ENET_RXIC_ICCS_SHIFT   (30U)
#define	ENET_RXIC_ICCS(x)
#define	ENET_RXIC_ICEN_MASK   (0x80000000U)
#define	ENET_RXIC_ICEN_SHIFT   (31U)
#define	ENET_RXIC_ICEN(x)
IAUR - Descriptor Individual Upper Address Register
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)
IALR - Descriptor Individual Lower Address Register
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)
GAUR - Descriptor Group Upper Address Register
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)
GALR - Descriptor Group Lower Address Register
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)
TFWR - Transmit FIFO Watermark Register
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)
RDSR1 - Receive Descriptor Ring 1 Start Register
#define	ENET_RDSR1_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR1_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR1_R_DES_START(x)
TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register
#define	ENET_TDSR1_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR1_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR1_X_DES_START(x)
MRBR1 - Maximum Receive Buffer Size Register - Ring 1
#define	ENET_MRBR1_R_BUF_SIZE_MASK   (0x7F0U)
#define	ENET_MRBR1_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR1_R_BUF_SIZE(x)
RDSR2 - Receive Descriptor Ring 2 Start Register
#define	ENET_RDSR2_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR2_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR2_R_DES_START(x)
TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register
#define	ENET_TDSR2_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR2_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR2_X_DES_START(x)
MRBR2 - Maximum Receive Buffer Size Register - Ring 2
#define	ENET_MRBR2_R_BUF_SIZE_MASK   (0x7F0U)
#define	ENET_MRBR2_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR2_R_BUF_SIZE(x)
RDSR - Receive Descriptor Ring 0 Start Register
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)
TDSR - Transmit Buffer Descriptor Ring 0 Start Register
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)
MRBR - Maximum Receive Buffer Size Register - Ring 0
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x3FF0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)
RSFL - Receive FIFO Section Full Threshold
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0x3FFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)
RSEM - Receive FIFO Section Empty Threshold
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0x3FFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)
#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)
#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)
#define	ENET_RSEM_STAT_SECTION_EMPTY(x)
RAEM - Receive FIFO Almost Empty Threshold
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0x3FFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)
RAFL - Receive FIFO Almost Full Threshold
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0x3FFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)
TSEM - Transmit FIFO Section Empty Threshold
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0x3FFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)
TAEM - Transmit FIFO Almost Empty Threshold
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0x3FFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)
TAFL - Transmit FIFO Almost Full Threshold
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0x3FFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)
TIPG - Transmit Inter-Packet Gap
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)
FTRL - Frame Truncation Length
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)
TACC - Transmit Accelerator Function Configuration
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)
RACC - Receive Accelerator Function Configuration
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)
RCMR - Receive Classification Match Register for Class n
#define	ENET_RCMR_CMP0_MASK   (0x7U)
#define	ENET_RCMR_CMP0_SHIFT   (0U)
#define	ENET_RCMR_CMP0(x)
#define	ENET_RCMR_CMP1_MASK   (0x70U)
#define	ENET_RCMR_CMP1_SHIFT   (4U)
#define	ENET_RCMR_CMP1(x)
#define	ENET_RCMR_CMP2_MASK   (0x700U)
#define	ENET_RCMR_CMP2_SHIFT   (8U)
#define	ENET_RCMR_CMP2(x)
#define	ENET_RCMR_CMP3_MASK   (0x7000U)
#define	ENET_RCMR_CMP3_SHIFT   (12U)
#define	ENET_RCMR_CMP3(x)
#define	ENET_RCMR_MATCHEN_MASK   (0x10000U)
#define	ENET_RCMR_MATCHEN_SHIFT   (16U)
#define	ENET_RCMR_MATCHEN(x)
DMACFG - DMA Class Based Configuration
#define	ENET_DMACFG_IDLE_SLOPE_MASK   (0xFFFFU)
#define	ENET_DMACFG_IDLE_SLOPE_SHIFT   (0U)
#define	ENET_DMACFG_IDLE_SLOPE(x)
#define	ENET_DMACFG_DMA_CLASS_EN_MASK   (0x10000U)
#define	ENET_DMACFG_DMA_CLASS_EN_SHIFT   (16U)
#define	ENET_DMACFG_DMA_CLASS_EN(x)
#define	ENET_DMACFG_CALC_NOIPG_MASK   (0x20000U)
#define	ENET_DMACFG_CALC_NOIPG_SHIFT   (17U)
#define	ENET_DMACFG_CALC_NOIPG(x)
RDAR1 - Receive Descriptor Active Register - Ring 1
#define	ENET_RDAR1_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR1_RDAR_SHIFT   (24U)
#define	ENET_RDAR1_RDAR(x)
TDAR1 - Transmit Descriptor Active Register - Ring 1
#define	ENET_TDAR1_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR1_TDAR_SHIFT   (24U)
#define	ENET_TDAR1_TDAR(x)
RDAR2 - Receive Descriptor Active Register - Ring 2
#define	ENET_RDAR2_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR2_RDAR_SHIFT   (24U)
#define	ENET_RDAR2_RDAR(x)
TDAR2 - Transmit Descriptor Active Register - Ring 2
#define	ENET_TDAR2_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR2_TDAR_SHIFT   (24U)
#define	ENET_TDAR2_TDAR(x)
QOS - QOS Scheme
#define	ENET_QOS_TX_SCHEME_MASK   (0x7U)
#define	ENET_QOS_TX_SCHEME_SHIFT   (0U)
#define	ENET_QOS_TX_SCHEME(x)
#define	ENET_QOS_RX_FLUSH0_MASK   (0x8U)
#define	ENET_QOS_RX_FLUSH0_SHIFT   (3U)
#define	ENET_QOS_RX_FLUSH0(x)
#define	ENET_QOS_RX_FLUSH1_MASK   (0x10U)
#define	ENET_QOS_RX_FLUSH1_SHIFT   (4U)
#define	ENET_QOS_RX_FLUSH1(x)
#define	ENET_QOS_RX_FLUSH2_MASK   (0x20U)
#define	ENET_QOS_RX_FLUSH2_SHIFT   (5U)
#define	ENET_QOS_RX_FLUSH2(x)
RMON_T_PACKETS - Tx Packet Count Statistic Register
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)
RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)
RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)
RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)
RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)
RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)
RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)
RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)
RMON_T_COL - Tx Collision Count Statistic Register
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)
RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)
RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)
RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)
RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)
RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)
RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)
RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)
RMON_T_OCTETS - Tx Octets Statistic Register
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)
IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)
IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)
IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)
IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)
IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)
IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)
IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)
IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)
IEEE_T_SQE - Reserved Statistic Register
#define	ENET_IEEE_T_SQE_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_SQE_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_SQE_COUNT(x)
IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)
IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)
RMON_R_PACKETS - Rx Packet Count Statistic Register
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)
RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)
RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)
RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)
RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)
RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)
RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)
RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)
RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)
RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)
RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)
RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)
RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)
RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)
RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)
RMON_R_OCTETS - Rx Octets Statistic Register
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)
IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)
IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)
IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)
IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)
IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)
IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)
IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)
ATCR - Adjustable Timer Control Register
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)
ATVR - Timer Value Register
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)
ATOFF - Timer Offset Register
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)
ATPER - Timer Period Register
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)
ATCOR - Timer Correction Register
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)
ATINC - Time-Stamping Clock Period Register
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)
ATSTMP - Timestamp of Last Transmitted Frame
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)
TGSR - Timer Global Status Register
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)
TCSR - Timer Control Status Register
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)
#define	ENET_TCSR_TPWC_MASK   (0xF800U)
#define	ENET_TCSR_TPWC_SHIFT   (11U)
#define	ENET_TCSR_TPWC(x)
TCCR - Timer Compare Capture Register
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)
SERV - Service Register
#define	EWM_SERV_SERVICE_MASK   (0xFFU)
#define	EWM_SERV_SERVICE_SHIFT   (0U)
#define	EWM_SERV_SERVICE(x)
CMPL - Compare Low Register
#define	EWM_CMPL_COMPAREL_MASK   (0xFFU)
#define	EWM_CMPL_COMPAREL_SHIFT   (0U)
#define	EWM_CMPL_COMPAREL(x)
CMPH - Compare High Register
#define	EWM_CMPH_COMPAREH_MASK   (0xFFU)
#define	EWM_CMPH_COMPAREH_SHIFT   (0U)
#define	EWM_CMPH_COMPAREH(x)
CLKCTRL - Clock Control Register
#define	EWM_CLKCTRL_CLKSEL_MASK   (0x3U)
#define	EWM_CLKCTRL_CLKSEL_SHIFT   (0U)
#define	EWM_CLKCTRL_CLKSEL(x)
CLKPRESCALER - Clock Prescaler Register
#define	EWM_CLKPRESCALER_CLK_DIV_MASK   (0xFFU)
#define	EWM_CLKPRESCALER_CLK_DIV_SHIFT   (0U)
#define	EWM_CLKPRESCALER_CLK_DIV(x)
CTRL - FlexIO Control Register
#define	FLEXIO_CTRL_FLEXEN_MASK   (0x1U)
#define	FLEXIO_CTRL_FLEXEN_SHIFT   (0U)
#define	FLEXIO_CTRL_FLEXEN(x)
#define	FLEXIO_CTRL_SWRST_MASK   (0x2U)
#define	FLEXIO_CTRL_SWRST_SHIFT   (1U)
#define	FLEXIO_CTRL_SWRST(x)
#define	FLEXIO_CTRL_FASTACC_MASK   (0x4U)
#define	FLEXIO_CTRL_FASTACC_SHIFT   (2U)
#define	FLEXIO_CTRL_FASTACC(x)
#define	FLEXIO_CTRL_DBGE_MASK   (0x40000000U)
#define	FLEXIO_CTRL_DBGE_SHIFT   (30U)
#define	FLEXIO_CTRL_DBGE(x)
#define	FLEXIO_CTRL_DOZEN_MASK   (0x80000000U)
#define	FLEXIO_CTRL_DOZEN_SHIFT   (31U)
#define	FLEXIO_CTRL_DOZEN(x)
PIN - Pin State Register
#define	FLEXIO_PIN_PDI_MASK   (0xFFFFFFFFU)
#define	FLEXIO_PIN_PDI_SHIFT   (0U)
#define	FLEXIO_PIN_PDI(x)
SHIFTSTAT - Shifter Status Register
#define	FLEXIO_SHIFTSTAT_SSF_MASK   (0xFFU)
#define	FLEXIO_SHIFTSTAT_SSF_SHIFT   (0U)
#define	FLEXIO_SHIFTSTAT_SSF(x)
SHIFTERR - Shifter Error Register
#define	FLEXIO_SHIFTERR_SEF_MASK   (0xFFU)
#define	FLEXIO_SHIFTERR_SEF_SHIFT   (0U)
#define	FLEXIO_SHIFTERR_SEF(x)
TIMSTAT - Timer Status Register
#define	FLEXIO_TIMSTAT_TSF_MASK   (0xFFU)
#define	FLEXIO_TIMSTAT_TSF_SHIFT   (0U)
#define	FLEXIO_TIMSTAT_TSF(x)
SHIFTSIEN - Shifter Status Interrupt Enable
#define	FLEXIO_SHIFTSIEN_SSIE_MASK   (0xFFU)
#define	FLEXIO_SHIFTSIEN_SSIE_SHIFT   (0U)
#define	FLEXIO_SHIFTSIEN_SSIE(x)
SHIFTEIEN - Shifter Error Interrupt Enable
#define	FLEXIO_SHIFTEIEN_SEIE_MASK   (0xFFU)
#define	FLEXIO_SHIFTEIEN_SEIE_SHIFT   (0U)
#define	FLEXIO_SHIFTEIEN_SEIE(x)
TIMIEN - Timer Interrupt Enable Register
#define	FLEXIO_TIMIEN_TEIE_MASK   (0xFFU)
#define	FLEXIO_TIMIEN_TEIE_SHIFT   (0U)
#define	FLEXIO_TIMIEN_TEIE(x)
SHIFTSDEN - Shifter Status DMA Enable
#define	FLEXIO_SHIFTSDEN_SSDE_MASK   (0xFFU)
#define	FLEXIO_SHIFTSDEN_SSDE_SHIFT   (0U)
#define	FLEXIO_SHIFTSDEN_SSDE(x)
TIMERSDEN - Timer Status DMA Enable
#define	FLEXIO_TIMERSDEN_TSDE_MASK   (0xFFU)
#define	FLEXIO_TIMERSDEN_TSDE_SHIFT   (0U)
#define	FLEXIO_TIMERSDEN_TSDE(x)
SHIFTSTATE - Shifter State Register
#define	FLEXIO_SHIFTSTATE_STATE_MASK   (0x7U)
#define	FLEXIO_SHIFTSTATE_STATE_SHIFT   (0U)
#define	FLEXIO_SHIFTSTATE_STATE(x)
SHIFTCTL - Shifter Control N Register
#define	FLEXIO_SHIFTCTL_SMOD_MASK   (0x7U)
#define	FLEXIO_SHIFTCTL_SMOD_SHIFT   (0U)
#define	FLEXIO_SHIFTCTL_SMOD(x)
#define	FLEXIO_SHIFTCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_SHIFTCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_SHIFTCTL_PINPOL(x)
#define	FLEXIO_SHIFTCTL_PINSEL_MASK   (0x1F00U)
#define	FLEXIO_SHIFTCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_SHIFTCTL_PINSEL(x)
#define	FLEXIO_SHIFTCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_SHIFTCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_SHIFTCTL_PINCFG(x)
#define	FLEXIO_SHIFTCTL_TIMPOL_MASK   (0x800000U)
#define	FLEXIO_SHIFTCTL_TIMPOL_SHIFT   (23U)
#define	FLEXIO_SHIFTCTL_TIMPOL(x)
#define	FLEXIO_SHIFTCTL_TIMSEL_MASK   (0x7000000U)
#define	FLEXIO_SHIFTCTL_TIMSEL_SHIFT   (24U)
#define	FLEXIO_SHIFTCTL_TIMSEL(x)
SHIFTCFG - Shifter Configuration N Register
#define	FLEXIO_SHIFTCFG_SSTART_MASK   (0x3U)
#define	FLEXIO_SHIFTCFG_SSTART_SHIFT   (0U)
#define	FLEXIO_SHIFTCFG_SSTART(x)
#define	FLEXIO_SHIFTCFG_SSTOP_MASK   (0x30U)
#define	FLEXIO_SHIFTCFG_SSTOP_SHIFT   (4U)
#define	FLEXIO_SHIFTCFG_SSTOP(x)
#define	FLEXIO_SHIFTCFG_INSRC_MASK   (0x100U)
#define	FLEXIO_SHIFTCFG_INSRC_SHIFT   (8U)
#define	FLEXIO_SHIFTCFG_INSRC(x)
#define	FLEXIO_SHIFTCFG_LATST_MASK   (0x200U)
#define	FLEXIO_SHIFTCFG_LATST_SHIFT   (9U)
#define	FLEXIO_SHIFTCFG_LATST(x)
#define	FLEXIO_SHIFTCFG_PWIDTH_MASK   (0x1F0000U)
#define	FLEXIO_SHIFTCFG_PWIDTH_SHIFT   (16U)
#define	FLEXIO_SHIFTCFG_PWIDTH(x)
SHIFTBUF - Shifter Buffer N Register
#define	FLEXIO_SHIFTBUF_SHIFTBUF_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT   (0U)
#define	FLEXIO_SHIFTBUF_SHIFTBUF(x)
SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)
SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)
SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)
TIMCTL - Timer Control N Register
#define	FLEXIO_TIMCTL_TIMOD_MASK   (0x7U)
#define	FLEXIO_TIMCTL_TIMOD_SHIFT   (0U)
#define	FLEXIO_TIMCTL_TIMOD(x)
#define	FLEXIO_TIMCTL_ONETIM_MASK   (0x20U)
#define	FLEXIO_TIMCTL_ONETIM_SHIFT   (5U)
#define	FLEXIO_TIMCTL_ONETIM(x)
#define	FLEXIO_TIMCTL_PININS_MASK   (0x40U)
#define	FLEXIO_TIMCTL_PININS_SHIFT   (6U)
#define	FLEXIO_TIMCTL_PININS(x)
#define	FLEXIO_TIMCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_TIMCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_TIMCTL_PINPOL(x)
#define	FLEXIO_TIMCTL_PINSEL_MASK   (0x1F00U)
#define	FLEXIO_TIMCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_TIMCTL_PINSEL(x)
#define	FLEXIO_TIMCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_TIMCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_TIMCTL_PINCFG(x)
#define	FLEXIO_TIMCTL_TRGSRC_MASK   (0x400000U)
#define	FLEXIO_TIMCTL_TRGSRC_SHIFT   (22U)
#define	FLEXIO_TIMCTL_TRGSRC(x)
#define	FLEXIO_TIMCTL_TRGPOL_MASK   (0x800000U)
#define	FLEXIO_TIMCTL_TRGPOL_SHIFT   (23U)
#define	FLEXIO_TIMCTL_TRGPOL(x)
#define	FLEXIO_TIMCTL_TRGSEL_MASK   (0x3F000000U)
#define	FLEXIO_TIMCTL_TRGSEL_SHIFT   (24U)
#define	FLEXIO_TIMCTL_TRGSEL(x)
TIMCFG - Timer Configuration N Register
#define	FLEXIO_TIMCFG_TSTART_MASK   (0x2U)
#define	FLEXIO_TIMCFG_TSTART_SHIFT   (1U)
#define	FLEXIO_TIMCFG_TSTART(x)
#define	FLEXIO_TIMCFG_TSTOP_MASK   (0x30U)
#define	FLEXIO_TIMCFG_TSTOP_SHIFT   (4U)
#define	FLEXIO_TIMCFG_TSTOP(x)
#define	FLEXIO_TIMCFG_TIMENA_MASK   (0x700U)
#define	FLEXIO_TIMCFG_TIMENA_SHIFT   (8U)
#define	FLEXIO_TIMCFG_TIMENA(x)
#define	FLEXIO_TIMCFG_TIMDIS_MASK   (0x7000U)
#define	FLEXIO_TIMCFG_TIMDIS_SHIFT   (12U)
#define	FLEXIO_TIMCFG_TIMDIS(x)
#define	FLEXIO_TIMCFG_TIMRST_MASK   (0x70000U)
#define	FLEXIO_TIMCFG_TIMRST_SHIFT   (16U)
#define	FLEXIO_TIMCFG_TIMRST(x)
#define	FLEXIO_TIMCFG_TIMDEC_MASK   (0x700000U)
#define	FLEXIO_TIMCFG_TIMDEC_SHIFT   (20U)
#define	FLEXIO_TIMCFG_TIMDEC(x)
#define	FLEXIO_TIMCFG_TIMOUT_MASK   (0x3000000U)
#define	FLEXIO_TIMCFG_TIMOUT_SHIFT   (24U)
#define	FLEXIO_TIMCFG_TIMOUT(x)
TIMCMP - Timer Compare N Register
#define	FLEXIO_TIMCMP_CMP_MASK   (0xFFFFU)
#define	FLEXIO_TIMCMP_CMP_SHIFT   (0U)
#define	FLEXIO_TIMCMP_CMP(x)
SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)
SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)
SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)
SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)
SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)
TCM_CTRL - TCM CRTL Register
#define	FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK   (0x1U)
#define	FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT   (0U)
#define	FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x)
#define	FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK   (0x2U)
#define	FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT   (1U)
#define	FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x)
#define	FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK   (0x4U)
#define	FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT   (2U)
#define	FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x)
#define	FLEXRAM_TCM_CTRL_Reserved_MASK   (0xFFFFFFF8U)
#define	FLEXRAM_TCM_CTRL_Reserved_SHIFT   (3U)
#define	FLEXRAM_TCM_CTRL_Reserved(x)
OCRAM_MAGIC_ADDR - OCRAM Magic Address Register
#define	FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK   (0x1U)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT   (0U)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK   (0x3FFFEU)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT   (1U)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK   (0xFFFC0000U)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT   (18U)
#define	FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x)
DTCM_MAGIC_ADDR - DTCM Magic Address Register
#define	FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK   (0x1U)
#define	FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT   (0U)
#define	FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x)
#define	FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK   (0x1FFFEU)
#define	FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT   (1U)
#define	FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x)
#define	FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK   (0xFFFE0000U)
#define	FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
#define	FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x)
ITCM_MAGIC_ADDR - ITCM Magic Address Register
#define	FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK   (0x1U)
#define	FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT   (0U)
#define	FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x)
#define	FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK   (0x1FFFEU)
#define	FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT   (1U)
#define	FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x)
#define	FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK   (0xFFFE0000U)
#define	FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
#define	FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x)
INT_STATUS - Interrupt Status Register
#define	FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK   (0x1U)
#define	FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT   (0U)
#define	FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x)
#define	FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK   (0x2U)
#define	FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT   (1U)
#define	FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x)
#define	FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK   (0x4U)
#define	FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT   (2U)
#define	FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x)
#define	FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK   (0x8U)
#define	FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT   (3U)
#define	FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x)
#define	FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK   (0x10U)
#define	FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT   (4U)
#define	FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x)
#define	FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK   (0x20U)
#define	FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT   (5U)
#define	FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x)
#define	FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK   (0x40U)
#define	FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT   (6U)
#define	FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x)
#define	FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK   (0x80U)
#define	FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT   (7U)
#define	FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x)
#define	FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK   (0x100U)
#define	FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT   (8U)
#define	FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x)
#define	FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK   (0x200U)
#define	FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT   (9U)
#define	FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x)
#define	FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK   (0x400U)
#define	FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT   (10U)
#define	FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x)
#define	FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK   (0x800U)
#define	FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT   (11U)
#define	FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x)
#define	FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK   (0x1000U)
#define	FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT   (12U)
#define	FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x)
#define	FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK   (0x2000U)
#define	FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT   (13U)
#define	FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x)
#define	FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK   (0x4000U)
#define	FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT   (14U)
#define	FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x)
#define	FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK   (0x8000U)
#define	FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT   (15U)
#define	FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x)
#define	FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK   (0x10000U)
#define	FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT   (16U)
#define	FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x)
#define	FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK   (0x20000U)
#define	FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT   (17U)
#define	FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x)
#define	FLEXRAM_INT_STATUS_Reserved_MASK   (0xFFFC0000U)
#define	FLEXRAM_INT_STATUS_Reserved_SHIFT   (18U)
#define	FLEXRAM_INT_STATUS_Reserved(x)
#define	SSARC_LP_INT_STATUS_ERR_INDEX_MASK   (0x3FFU)
#define	SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT   (0U)
#define	SSARC_LP_INT_STATUS_ERR_INDEX(x)
#define	SSARC_LP_INT_STATUS_AHB_RESP_MASK   (0xC00U)
#define	SSARC_LP_INT_STATUS_AHB_RESP_SHIFT   (10U)
#define	SSARC_LP_INT_STATUS_AHB_RESP(x)
#define	SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK   (0x8000000U)
#define	SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT   (27U)
#define	SSARC_LP_INT_STATUS_GROUP_CONFLICT(x)
#define	SSARC_LP_INT_STATUS_TIMEOUT_MASK   (0x10000000U)
#define	SSARC_LP_INT_STATUS_TIMEOUT_SHIFT   (28U)
#define	SSARC_LP_INT_STATUS_TIMEOUT(x)
#define	SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK   (0x20000000U)
#define	SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT   (29U)
#define	SSARC_LP_INT_STATUS_SW_REQ_DONE(x)
#define	SSARC_LP_INT_STATUS_AHB_ERR_MASK   (0x40000000U)
#define	SSARC_LP_INT_STATUS_AHB_ERR_SHIFT   (30U)
#define	SSARC_LP_INT_STATUS_AHB_ERR(x)
#define	SSARC_LP_INT_STATUS_ADDR_ERR_MASK   (0x80000000U)
#define	SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT   (31U)
#define	SSARC_LP_INT_STATUS_ADDR_ERR(x)
INT_STAT_EN - Interrupt Status Enable Register
#define	FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK   (0x1U)
#define	FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT   (0U)
#define	FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x)
#define	FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK   (0x2U)
#define	FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT   (1U)
#define	FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x)
#define	FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK   (0x4U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT   (2U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK   (0x8U)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT   (3U)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x)
#define	FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK   (0x10U)
#define	FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT   (4U)
#define	FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK   (0x20U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT   (5U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK   (0x40U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT   (6U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK   (0x80U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT   (7U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK   (0x100U)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT   (8U)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK   (0x200U)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT   (9U)
#define	FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK   (0x400U)
#define	FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT   (10U)
#define	FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK   (0x800U)
#define	FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT   (11U)
#define	FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK   (0x1000U)
#define	FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT   (12U)
#define	FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK   (0x2000U)
#define	FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT   (13U)
#define	FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x)
#define	FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK   (0x4000U)
#define	FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT   (14U)
#define	FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x)
#define	FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK   (0x8000U)
#define	FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT   (15U)
#define	FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x)
#define	FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK   (0x10000U)
#define	FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT   (16U)
#define	FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x)
#define	FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK   (0x20000U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT   (17U)
#define	FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x)
#define	FLEXRAM_INT_STAT_EN_Reserved_MASK   (0xFFFC0000U)
#define	FLEXRAM_INT_STAT_EN_Reserved_SHIFT   (18U)
#define	FLEXRAM_INT_STAT_EN_Reserved(x)
INT_SIG_EN - Interrupt Enable Register
#define	FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK   (0x1U)
#define	FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT   (0U)
#define	FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK   (0x2U)
#define	FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT   (1U)
#define	FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK   (0x4U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT   (2U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK   (0x8U)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT   (3U)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK   (0x10U)
#define	FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT   (4U)
#define	FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK   (0x20U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT   (5U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK   (0x40U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT   (6U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK   (0x80U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT   (7U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK   (0x100U)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT   (8U)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK   (0x200U)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT   (9U)
#define	FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK   (0x400U)
#define	FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT   (10U)
#define	FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK   (0x800U)
#define	FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT   (11U)
#define	FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK   (0x1000U)
#define	FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT   (12U)
#define	FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK   (0x2000U)
#define	FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT   (13U)
#define	FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK   (0x4000U)
#define	FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT   (14U)
#define	FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK   (0x8000U)
#define	FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT   (15U)
#define	FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK   (0x10000U)
#define	FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT   (16U)
#define	FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK   (0x20000U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT   (17U)
#define	FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x)
#define	FLEXRAM_INT_SIG_EN_Reserved_MASK   (0xFFFC0000U)
#define	FLEXRAM_INT_SIG_EN_Reserved_SHIFT   (18U)
#define	FLEXRAM_INT_SIG_EN_Reserved(x)
OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK   (0xFFU)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK   (0xFF00U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT   (8U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK   (0xFFFF0000U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT   (16U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x)
OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x)
OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x)
OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x)
OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK   (0xFFU)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK   (0xFFFFFF00U)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT   (8U)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x)
OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x)
OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x)
OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT   (0U)
#define	FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x)
ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK   (0x1U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK   (0xEU)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT   (1U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK   (0xF0U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT   (4U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK   (0xF00U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT   (8U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK   (0xFF000U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT   (12U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK   (0xFFF00000U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT   (20U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x)
ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x)
ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x)
ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x)
ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK   (0x1U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK   (0xEU)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT   (1U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK   (0xF0U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT   (4U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK   (0xF00U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT   (8U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK   (0xFF000U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT   (12U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK   (0xFFF00000U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT   (20U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x)
ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x)
ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x)
ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT   (0U)
#define	FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x)
D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK   (0x1U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT   (0U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK   (0xEU)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT   (1U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK   (0xF0U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT   (4U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK   (0xF00U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT   (8U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK   (0x7F000U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT   (12U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK   (0xFFF80000U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT   (19U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x)
D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x)
D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT   (0U)
#define	FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x)
D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK   (0x1U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT   (0U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK   (0xEU)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT   (1U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK   (0xF0U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT   (4U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK   (0xF00U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT   (8U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK   (0x7F000U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT   (12U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK   (0xFFF80000U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT   (19U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x)
D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x)
D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT   (0U)
#define	FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x)
D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK   (0x1U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT   (0U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK   (0xEU)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT   (1U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK   (0xF0U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT   (4U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK   (0xF00U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT   (8U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK   (0x7F000U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT   (12U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK   (0xFFF80000U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT   (19U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x)
D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x)
D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT   (0U)
#define	FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x)
D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK   (0x1U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT   (0U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK   (0xEU)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT   (1U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK   (0xF0U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT   (4U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK   (0xF00U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT   (8U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK   (0x7F000U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT   (12U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK   (0xFFF80000U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT   (19U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x)
D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT   (0U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x)
D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK   (0xFFFFFFFFU)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT   (0U)
#define	FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x)
FLEXRAM_CTRL - FlexRAM feature Control register
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK   (0x1U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT   (0U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK   (0x2U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT   (1U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK   (0x4U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT   (2U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK   (0x8U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT   (3U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK   (0x10U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT   (4U)
#define	FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x)
#define	FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK   (0x20U)
#define	FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT   (5U)
#define	FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x)
#define	FLEXRAM_FLEXRAM_CTRL_Reserved_MASK   (0xFFFFFFC0U)
#define	FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT   (6U)
#define	FLEXRAM_FLEXRAM_CTRL_Reserved(x)
OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK   (0x1U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT   (0U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK   (0x2U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT   (1U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK   (0x4U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT   (2U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK   (0x8U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT   (3U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK   (0xFFFFFFF0U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT   (4U)
#define	FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x)
MCR0 - Module Control Register 0
#define	FLEXSPI_MCR0_SWRESET_MASK   (0x1U)
#define	FLEXSPI_MCR0_SWRESET_SHIFT   (0U)
#define	FLEXSPI_MCR0_SWRESET(x)
#define	FLEXSPI_MCR0_MDIS_MASK   (0x2U)
#define	FLEXSPI_MCR0_MDIS_SHIFT   (1U)
#define	FLEXSPI_MCR0_MDIS(x)
#define	FLEXSPI_MCR0_RXCLKSRC_MASK   (0x30U)
#define	FLEXSPI_MCR0_RXCLKSRC_SHIFT   (4U)
#define	FLEXSPI_MCR0_RXCLKSRC(x)
#define	FLEXSPI_MCR0_ARDFEN_MASK   (0x40U)
#define	FLEXSPI_MCR0_ARDFEN_SHIFT   (6U)
#define	FLEXSPI_MCR0_ARDFEN(x)
#define	FLEXSPI_MCR0_ATDFEN_MASK   (0x80U)
#define	FLEXSPI_MCR0_ATDFEN_SHIFT   (7U)
#define	FLEXSPI_MCR0_ATDFEN(x)
#define	FLEXSPI_MCR0_SERCLKDIV_MASK   (0x700U)
#define	FLEXSPI_MCR0_SERCLKDIV_SHIFT   (8U)
#define	FLEXSPI_MCR0_SERCLKDIV(x)
#define	FLEXSPI_MCR0_HSEN_MASK   (0x800U)
#define	FLEXSPI_MCR0_HSEN_SHIFT   (11U)
#define	FLEXSPI_MCR0_HSEN(x)
#define	FLEXSPI_MCR0_DOZEEN_MASK   (0x1000U)
#define	FLEXSPI_MCR0_DOZEEN_SHIFT   (12U)
#define	FLEXSPI_MCR0_DOZEEN(x)
#define	FLEXSPI_MCR0_COMBINATIONEN_MASK   (0x2000U)
#define	FLEXSPI_MCR0_COMBINATIONEN_SHIFT   (13U)
#define	FLEXSPI_MCR0_COMBINATIONEN(x)
#define	FLEXSPI_MCR0_SCKFREERUNEN_MASK   (0x4000U)
#define	FLEXSPI_MCR0_SCKFREERUNEN_SHIFT   (14U)
#define	FLEXSPI_MCR0_SCKFREERUNEN(x)
#define	FLEXSPI_MCR0_IPGRANTWAIT_MASK   (0xFF0000U)
#define	FLEXSPI_MCR0_IPGRANTWAIT_SHIFT   (16U)
#define	FLEXSPI_MCR0_IPGRANTWAIT(x)
#define	FLEXSPI_MCR0_AHBGRANTWAIT_MASK   (0xFF000000U)
#define	FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT   (24U)
#define	FLEXSPI_MCR0_AHBGRANTWAIT(x)
MCR1 - Module Control Register 1
#define	FLEXSPI_MCR1_AHBBUSWAIT_MASK   (0xFFFFU)
#define	FLEXSPI_MCR1_AHBBUSWAIT_SHIFT   (0U)
#define	FLEXSPI_MCR1_AHBBUSWAIT(x)
#define	FLEXSPI_MCR1_SEQWAIT_MASK   (0xFFFF0000U)
#define	FLEXSPI_MCR1_SEQWAIT_SHIFT   (16U)
#define	FLEXSPI_MCR1_SEQWAIT(x)
MCR2 - Module Control Register 2
#define	FLEXSPI_MCR2_CLRAHBBUFOPT_MASK   (0x800U)
#define	FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT   (11U)
#define	FLEXSPI_MCR2_CLRAHBBUFOPT(x)
#define	FLEXSPI_MCR2_SAMEDEVICEEN_MASK   (0x8000U)
#define	FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT   (15U)
#define	FLEXSPI_MCR2_SAMEDEVICEEN(x)
#define	FLEXSPI_MCR2_SCKBDIFFOPT_MASK   (0x80000U)
#define	FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT   (19U)
#define	FLEXSPI_MCR2_SCKBDIFFOPT(x)
#define	FLEXSPI_MCR2_RESUMEWAIT_MASK   (0xFF000000U)
#define	FLEXSPI_MCR2_RESUMEWAIT_SHIFT   (24U)
#define	FLEXSPI_MCR2_RESUMEWAIT(x)
AHBCR - AHB Bus Control Register
#define	FLEXSPI_AHBCR_APAREN_MASK   (0x1U)
#define	FLEXSPI_AHBCR_APAREN_SHIFT   (0U)
#define	FLEXSPI_AHBCR_APAREN(x)
#define	FLEXSPI_AHBCR_CLRAHBRXBUF_MASK   (0x2U)
#define	FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT   (1U)
#define	FLEXSPI_AHBCR_CLRAHBRXBUF(x)
#define	FLEXSPI_AHBCR_CACHABLEEN_MASK   (0x8U)
#define	FLEXSPI_AHBCR_CACHABLEEN_SHIFT   (3U)
#define	FLEXSPI_AHBCR_CACHABLEEN(x)
#define	FLEXSPI_AHBCR_BUFFERABLEEN_MASK   (0x10U)
#define	FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT   (4U)
#define	FLEXSPI_AHBCR_BUFFERABLEEN(x)
#define	FLEXSPI_AHBCR_PREFETCHEN_MASK   (0x20U)
#define	FLEXSPI_AHBCR_PREFETCHEN_SHIFT   (5U)
#define	FLEXSPI_AHBCR_PREFETCHEN(x)
#define	FLEXSPI_AHBCR_READADDROPT_MASK   (0x40U)
#define	FLEXSPI_AHBCR_READADDROPT_SHIFT   (6U)
#define	FLEXSPI_AHBCR_READADDROPT(x)
#define	FLEXSPI_AHBCR_READSZALIGN_MASK   (0x400U)
#define	FLEXSPI_AHBCR_READSZALIGN_SHIFT   (10U)
#define	FLEXSPI_AHBCR_READSZALIGN(x)
#define	FLEXSPI_AHBCR_ECCEN_MASK   (0x800U)
#define	FLEXSPI_AHBCR_ECCEN_SHIFT   (11U)
#define	FLEXSPI_AHBCR_ECCEN(x)
#define	FLEXSPI_AHBCR_SPLITEN_MASK   (0x1000U)
#define	FLEXSPI_AHBCR_SPLITEN_SHIFT   (12U)
#define	FLEXSPI_AHBCR_SPLITEN(x)
#define	FLEXSPI_AHBCR_SPLIT_LIMIT_MASK   (0x6000U)
#define	FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT   (13U)
#define	FLEXSPI_AHBCR_SPLIT_LIMIT(x)
#define	FLEXSPI_AHBCR_KEYECCEN_MASK   (0x8000U)
#define	FLEXSPI_AHBCR_KEYECCEN_SHIFT   (15U)
#define	FLEXSPI_AHBCR_KEYECCEN(x)
#define	FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK   (0x10000U)
#define	FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT   (16U)
#define	FLEXSPI_AHBCR_ECCSINGLEERRCLR(x)
#define	FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK   (0x20000U)
#define	FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT   (17U)
#define	FLEXSPI_AHBCR_ECCMULTIERRCLR(x)
#define	FLEXSPI_AHBCR_HMSTRIDREMAP_MASK   (0x40000U)
#define	FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT   (18U)
#define	FLEXSPI_AHBCR_HMSTRIDREMAP(x)
#define	FLEXSPI_AHBCR_ECCSWAPEN_MASK   (0x80000U)
#define	FLEXSPI_AHBCR_ECCSWAPEN_SHIFT   (19U)
#define	FLEXSPI_AHBCR_ECCSWAPEN(x)
#define	FLEXSPI_AHBCR_ALIGNMENT_MASK   (0x300000U)
#define	FLEXSPI_AHBCR_ALIGNMENT_SHIFT   (20U)
#define	FLEXSPI_AHBCR_ALIGNMENT(x)
INTEN - Interrupt Enable Register
#define	FLEXSPI_INTEN_IPCMDDONEEN_MASK   (0x1U)
#define	FLEXSPI_INTEN_IPCMDDONEEN_SHIFT   (0U)
#define	FLEXSPI_INTEN_IPCMDDONEEN(x)
#define	FLEXSPI_INTEN_IPCMDGEEN_MASK   (0x2U)
#define	FLEXSPI_INTEN_IPCMDGEEN_SHIFT   (1U)
#define	FLEXSPI_INTEN_IPCMDGEEN(x)
#define	FLEXSPI_INTEN_AHBCMDGEEN_MASK   (0x4U)
#define	FLEXSPI_INTEN_AHBCMDGEEN_SHIFT   (2U)
#define	FLEXSPI_INTEN_AHBCMDGEEN(x)
#define	FLEXSPI_INTEN_IPCMDERREN_MASK   (0x8U)
#define	FLEXSPI_INTEN_IPCMDERREN_SHIFT   (3U)
#define	FLEXSPI_INTEN_IPCMDERREN(x)
#define	FLEXSPI_INTEN_AHBCMDERREN_MASK   (0x10U)
#define	FLEXSPI_INTEN_AHBCMDERREN_SHIFT   (4U)
#define	FLEXSPI_INTEN_AHBCMDERREN(x)
#define	FLEXSPI_INTEN_IPRXWAEN_MASK   (0x20U)
#define	FLEXSPI_INTEN_IPRXWAEN_SHIFT   (5U)
#define	FLEXSPI_INTEN_IPRXWAEN(x)
#define	FLEXSPI_INTEN_IPTXWEEN_MASK   (0x40U)
#define	FLEXSPI_INTEN_IPTXWEEN_SHIFT   (6U)
#define	FLEXSPI_INTEN_IPTXWEEN(x)
#define	FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK   (0x100U)
#define	FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT   (8U)
#define	FLEXSPI_INTEN_SCKSTOPBYRDEN(x)
#define	FLEXSPI_INTEN_SCKSTOPBYWREN_MASK   (0x200U)
#define	FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT   (9U)
#define	FLEXSPI_INTEN_SCKSTOPBYWREN(x)
#define	FLEXSPI_INTEN_AHBBUSERROREN_MASK   (0x400U)
#define	FLEXSPI_INTEN_AHBBUSERROREN_SHIFT   (10U)
#define	FLEXSPI_INTEN_AHBBUSERROREN(x)
#define	FLEXSPI_INTEN_SEQTIMEOUTEN_MASK   (0x800U)
#define	FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT   (11U)
#define	FLEXSPI_INTEN_SEQTIMEOUTEN(x)
#define	FLEXSPI_INTEN_KEYDONEEN_MASK   (0x1000U)
#define	FLEXSPI_INTEN_KEYDONEEN_SHIFT   (12U)
#define	FLEXSPI_INTEN_KEYDONEEN(x)
#define	FLEXSPI_INTEN_KEYERROREN_MASK   (0x2000U)
#define	FLEXSPI_INTEN_KEYERROREN_SHIFT   (13U)
#define	FLEXSPI_INTEN_KEYERROREN(x)
#define	FLEXSPI_INTEN_ECCMULTIERREN_MASK   (0x4000U)
#define	FLEXSPI_INTEN_ECCMULTIERREN_SHIFT   (14U)
#define	FLEXSPI_INTEN_ECCMULTIERREN(x)
#define	FLEXSPI_INTEN_ECCSINGLEERREN_MASK   (0x8000U)
#define	FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT   (15U)
#define	FLEXSPI_INTEN_ECCSINGLEERREN(x)
#define	FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK   (0x10000U)
#define	FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT   (16U)
#define	FLEXSPI_INTEN_IPCMDSECUREVIOEN(x)
#define	PWM_INTEN_CMPIE_MASK   (0x3FU)
#define	PWM_INTEN_CMPIE_SHIFT   (0U)
#define	PWM_INTEN_CMPIE(x)
#define	PWM_INTEN_CX0IE_MASK   (0x40U)
#define	PWM_INTEN_CX0IE_SHIFT   (6U)
#define	PWM_INTEN_CX0IE(x)
#define	PWM_INTEN_CX1IE_MASK   (0x80U)
#define	PWM_INTEN_CX1IE_SHIFT   (7U)
#define	PWM_INTEN_CX1IE(x)
#define	PWM_INTEN_CB0IE_MASK   (0x100U)
#define	PWM_INTEN_CB0IE_SHIFT   (8U)
#define	PWM_INTEN_CB0IE(x)
#define	PWM_INTEN_CB1IE_MASK   (0x200U)
#define	PWM_INTEN_CB1IE_SHIFT   (9U)
#define	PWM_INTEN_CB1IE(x)
#define	PWM_INTEN_CA0IE_MASK   (0x400U)
#define	PWM_INTEN_CA0IE_SHIFT   (10U)
#define	PWM_INTEN_CA0IE(x)
#define	PWM_INTEN_CA1IE_MASK   (0x800U)
#define	PWM_INTEN_CA1IE_SHIFT   (11U)
#define	PWM_INTEN_CA1IE(x)
#define	PWM_INTEN_RIE_MASK   (0x1000U)
#define	PWM_INTEN_RIE_SHIFT   (12U)
#define	PWM_INTEN_RIE(x)
#define	PWM_INTEN_REIE_MASK   (0x2000U)
#define	PWM_INTEN_REIE_SHIFT   (13U)
#define	PWM_INTEN_REIE(x)
#define	SEMC_INTEN_IPCMDDONEEN_MASK   (0x1U)
#define	SEMC_INTEN_IPCMDDONEEN_SHIFT   (0U)
#define	SEMC_INTEN_IPCMDDONEEN(x)
#define	SEMC_INTEN_IPCMDERREN_MASK   (0x2U)
#define	SEMC_INTEN_IPCMDERREN_SHIFT   (1U)
#define	SEMC_INTEN_IPCMDERREN(x)
#define	SEMC_INTEN_AXICMDERREN_MASK   (0x4U)
#define	SEMC_INTEN_AXICMDERREN_SHIFT   (2U)
#define	SEMC_INTEN_AXICMDERREN(x)
#define	SEMC_INTEN_AXIBUSERREN_MASK   (0x8U)
#define	SEMC_INTEN_AXIBUSERREN_SHIFT   (3U)
#define	SEMC_INTEN_AXIBUSERREN(x)
#define	SEMC_INTEN_NDPAGEENDEN_MASK   (0x10U)
#define	SEMC_INTEN_NDPAGEENDEN_SHIFT   (4U)
#define	SEMC_INTEN_NDPAGEENDEN(x)
#define	SEMC_INTEN_NDNOPENDEN_MASK   (0x20U)
#define	SEMC_INTEN_NDNOPENDEN_SHIFT   (5U)
#define	SEMC_INTEN_NDNOPENDEN(x)
INTR - Interrupt Register
#define	FLEXSPI_INTR_IPCMDDONE_MASK   (0x1U)
#define	FLEXSPI_INTR_IPCMDDONE_SHIFT   (0U)
#define	FLEXSPI_INTR_IPCMDDONE(x)
#define	FLEXSPI_INTR_IPCMDGE_MASK   (0x2U)
#define	FLEXSPI_INTR_IPCMDGE_SHIFT   (1U)
#define	FLEXSPI_INTR_IPCMDGE(x)
#define	FLEXSPI_INTR_AHBCMDGE_MASK   (0x4U)
#define	FLEXSPI_INTR_AHBCMDGE_SHIFT   (2U)
#define	FLEXSPI_INTR_AHBCMDGE(x)
#define	FLEXSPI_INTR_IPCMDERR_MASK   (0x8U)
#define	FLEXSPI_INTR_IPCMDERR_SHIFT   (3U)
#define	FLEXSPI_INTR_IPCMDERR(x)
#define	FLEXSPI_INTR_AHBCMDERR_MASK   (0x10U)
#define	FLEXSPI_INTR_AHBCMDERR_SHIFT   (4U)
#define	FLEXSPI_INTR_AHBCMDERR(x)
#define	FLEXSPI_INTR_IPRXWA_MASK   (0x20U)
#define	FLEXSPI_INTR_IPRXWA_SHIFT   (5U)
#define	FLEXSPI_INTR_IPRXWA(x)
#define	FLEXSPI_INTR_IPTXWE_MASK   (0x40U)
#define	FLEXSPI_INTR_IPTXWE_SHIFT   (6U)
#define	FLEXSPI_INTR_IPTXWE(x)
#define	FLEXSPI_INTR_SCKSTOPBYRD_MASK   (0x100U)
#define	FLEXSPI_INTR_SCKSTOPBYRD_SHIFT   (8U)
#define	FLEXSPI_INTR_SCKSTOPBYRD(x)
#define	FLEXSPI_INTR_SCKSTOPBYWR_MASK   (0x200U)
#define	FLEXSPI_INTR_SCKSTOPBYWR_SHIFT   (9U)
#define	FLEXSPI_INTR_SCKSTOPBYWR(x)
#define	FLEXSPI_INTR_AHBBUSERROR_MASK   (0x400U)
#define	FLEXSPI_INTR_AHBBUSERROR_SHIFT   (10U)
#define	FLEXSPI_INTR_AHBBUSERROR(x)
#define	FLEXSPI_INTR_SEQTIMEOUT_MASK   (0x800U)
#define	FLEXSPI_INTR_SEQTIMEOUT_SHIFT   (11U)
#define	FLEXSPI_INTR_SEQTIMEOUT(x)
#define	FLEXSPI_INTR_KEYDONE_MASK   (0x1000U)
#define	FLEXSPI_INTR_KEYDONE_SHIFT   (12U)
#define	FLEXSPI_INTR_KEYDONE(x)
#define	FLEXSPI_INTR_KEYERROR_MASK   (0x2000U)
#define	FLEXSPI_INTR_KEYERROR_SHIFT   (13U)
#define	FLEXSPI_INTR_KEYERROR(x)
#define	FLEXSPI_INTR_ECCMULTIERR_MASK   (0x4000U)
#define	FLEXSPI_INTR_ECCMULTIERR_SHIFT   (14U)
#define	FLEXSPI_INTR_ECCMULTIERR(x)
#define	FLEXSPI_INTR_ECCSINGLEERR_MASK   (0x8000U)
#define	FLEXSPI_INTR_ECCSINGLEERR_SHIFT   (15U)
#define	FLEXSPI_INTR_ECCSINGLEERR(x)
#define	FLEXSPI_INTR_IPCMDSECUREVIO_MASK   (0x10000U)
#define	FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT   (16U)
#define	FLEXSPI_INTR_IPCMDSECUREVIO(x)
#define	SEMC_INTR_IPCMDDONE_MASK   (0x1U)
#define	SEMC_INTR_IPCMDDONE_SHIFT   (0U)
#define	SEMC_INTR_IPCMDDONE(x)
#define	SEMC_INTR_IPCMDERR_MASK   (0x2U)
#define	SEMC_INTR_IPCMDERR_SHIFT   (1U)
#define	SEMC_INTR_IPCMDERR(x)
#define	SEMC_INTR_AXICMDERR_MASK   (0x4U)
#define	SEMC_INTR_AXICMDERR_SHIFT   (2U)
#define	SEMC_INTR_AXICMDERR(x)
#define	SEMC_INTR_AXIBUSERR_MASK   (0x8U)
#define	SEMC_INTR_AXIBUSERR_SHIFT   (3U)
#define	SEMC_INTR_AXIBUSERR(x)
#define	SEMC_INTR_NDPAGEEND_MASK   (0x10U)
#define	SEMC_INTR_NDPAGEEND_SHIFT   (4U)
#define	SEMC_INTR_NDPAGEEND(x)
#define	SEMC_INTR_NDNOPEND_MASK   (0x20U)
#define	SEMC_INTR_NDNOPEND_SHIFT   (5U)
#define	SEMC_INTR_NDNOPEND(x)
LUTKEY - LUT Key Register
#define	FLEXSPI_LUTKEY_KEY_MASK   (0xFFFFFFFFU)
#define	FLEXSPI_LUTKEY_KEY_SHIFT   (0U)
#define	FLEXSPI_LUTKEY_KEY(x)
LUTCR - LUT Control Register
#define	FLEXSPI_LUTCR_LOCK_MASK   (0x1U)
#define	FLEXSPI_LUTCR_LOCK_SHIFT   (0U)
#define	FLEXSPI_LUTCR_LOCK(x)
#define	FLEXSPI_LUTCR_UNLOCK_MASK   (0x2U)
#define	FLEXSPI_LUTCR_UNLOCK_SHIFT   (1U)
#define	FLEXSPI_LUTCR_UNLOCK(x)
#define	FLEXSPI_LUTCR_PROTECT_MASK   (0x4U)
#define	FLEXSPI_LUTCR_PROTECT_SHIFT   (2U)
#define	FLEXSPI_LUTCR_PROTECT(x)
AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0
#define	FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK   (0x3FFU)
#define	FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT   (0U)
#define	FLEXSPI_AHBRXBUFCR0_BUFSZ(x)
#define	FLEXSPI_AHBRXBUFCR0_MSTRID_MASK   (0xF0000U)
#define	FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT   (16U)
#define	FLEXSPI_AHBRXBUFCR0_MSTRID(x)
#define	FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK   (0x7000000U)
#define	FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT   (24U)
#define	FLEXSPI_AHBRXBUFCR0_PRIORITY(x)
#define	FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK   (0x40000000U)
#define	FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT   (30U)
#define	FLEXSPI_AHBRXBUFCR0_REGIONEN(x)
#define	FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK   (0x80000000U)
#define	FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT   (31U)
#define	FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)
FLSHCR0 - Flash Control Register 0
#define	FLEXSPI_FLSHCR0_FLSHSZ_MASK   (0x7FFFFFU)
#define	FLEXSPI_FLSHCR0_FLSHSZ_SHIFT   (0U)
#define	FLEXSPI_FLSHCR0_FLSHSZ(x)
#define	FLEXSPI_FLSHCR0_SPLITWREN_MASK   (0x40000000U)
#define	FLEXSPI_FLSHCR0_SPLITWREN_SHIFT   (30U)
#define	FLEXSPI_FLSHCR0_SPLITWREN(x)
#define	FLEXSPI_FLSHCR0_SPLITRDEN_MASK   (0x80000000U)
#define	FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT   (31U)
#define	FLEXSPI_FLSHCR0_SPLITRDEN(x)
FLSHCR1 - Flash Control Register 1
#define	FLEXSPI_FLSHCR1_TCSS_MASK   (0x1FU)
#define	FLEXSPI_FLSHCR1_TCSS_SHIFT   (0U)
#define	FLEXSPI_FLSHCR1_TCSS(x)
#define	FLEXSPI_FLSHCR1_TCSH_MASK   (0x3E0U)
#define	FLEXSPI_FLSHCR1_TCSH_SHIFT   (5U)
#define	FLEXSPI_FLSHCR1_TCSH(x)
#define	FLEXSPI_FLSHCR1_WA_MASK   (0x400U)
#define	FLEXSPI_FLSHCR1_WA_SHIFT   (10U)
#define	FLEXSPI_FLSHCR1_WA(x)
#define	FLEXSPI_FLSHCR1_CAS_MASK   (0x7800U)
#define	FLEXSPI_FLSHCR1_CAS_SHIFT   (11U)
#define	FLEXSPI_FLSHCR1_CAS(x)
#define	FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK   (0x8000U)
#define	FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT   (15U)
#define	FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)
#define	FLEXSPI_FLSHCR1_CSINTERVAL_MASK   (0xFFFF0000U)
#define	FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT   (16U)
#define	FLEXSPI_FLSHCR1_CSINTERVAL(x)
FLSHCR2 - Flash Control Register 2
#define	FLEXSPI_FLSHCR2_ARDSEQID_MASK   (0xFU)
#define	FLEXSPI_FLSHCR2_ARDSEQID_SHIFT   (0U)
#define	FLEXSPI_FLSHCR2_ARDSEQID(x)
#define	FLEXSPI_FLSHCR2_ARDSEQNUM_MASK   (0xE0U)
#define	FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT   (5U)
#define	FLEXSPI_FLSHCR2_ARDSEQNUM(x)
#define	FLEXSPI_FLSHCR2_AWRSEQID_MASK   (0xF00U)
#define	FLEXSPI_FLSHCR2_AWRSEQID_SHIFT   (8U)
#define	FLEXSPI_FLSHCR2_AWRSEQID(x)
#define	FLEXSPI_FLSHCR2_AWRSEQNUM_MASK   (0xE000U)
#define	FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT   (13U)
#define	FLEXSPI_FLSHCR2_AWRSEQNUM(x)
#define	FLEXSPI_FLSHCR2_AWRWAIT_MASK   (0xFFF0000U)
#define	FLEXSPI_FLSHCR2_AWRWAIT_SHIFT   (16U)
#define	FLEXSPI_FLSHCR2_AWRWAIT(x)
#define	FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK   (0x70000000U)
#define	FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT   (28U)
#define	FLEXSPI_FLSHCR2_AWRWAITUNIT(x)
#define	FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK   (0x80000000U)
#define	FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT   (31U)
#define	FLEXSPI_FLSHCR2_CLRINSTRPTR(x)
FLSHCR4 - Flash Control Register 4
#define	FLEXSPI_FLSHCR4_WMOPT1_MASK   (0x1U)
#define	FLEXSPI_FLSHCR4_WMOPT1_SHIFT   (0U)
#define	FLEXSPI_FLSHCR4_WMOPT1(x)
#define	FLEXSPI_FLSHCR4_WMOPT2_MASK   (0x2U)
#define	FLEXSPI_FLSHCR4_WMOPT2_SHIFT   (1U)
#define	FLEXSPI_FLSHCR4_WMOPT2(x)
#define	FLEXSPI_FLSHCR4_WMENA_MASK   (0x4U)
#define	FLEXSPI_FLSHCR4_WMENA_SHIFT   (2U)
#define	FLEXSPI_FLSHCR4_WMENA(x)
#define	FLEXSPI_FLSHCR4_WMENB_MASK   (0x8U)
#define	FLEXSPI_FLSHCR4_WMENB_SHIFT   (3U)
#define	FLEXSPI_FLSHCR4_WMENB(x)
#define	FLEXSPI_FLSHCR4_PAR_WM_MASK   (0x600U)
#define	FLEXSPI_FLSHCR4_PAR_WM_SHIFT   (9U)
#define	FLEXSPI_FLSHCR4_PAR_WM(x)
#define	FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK   (0x800U)
#define	FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT   (11U)
#define	FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x)
IPCR0 - IP Control Register 0
#define	FLEXSPI_IPCR0_SFAR_MASK   (0xFFFFFFFFU)
#define	FLEXSPI_IPCR0_SFAR_SHIFT   (0U)
#define	FLEXSPI_IPCR0_SFAR(x)
IPCR1 - IP Control Register 1
#define	FLEXSPI_IPCR1_IDATSZ_MASK   (0xFFFFU)
#define	FLEXSPI_IPCR1_IDATSZ_SHIFT   (0U)
#define	FLEXSPI_IPCR1_IDATSZ(x)
#define	FLEXSPI_IPCR1_ISEQID_MASK   (0xF0000U)
#define	FLEXSPI_IPCR1_ISEQID_SHIFT   (16U)
#define	FLEXSPI_IPCR1_ISEQID(x)
#define	FLEXSPI_IPCR1_ISEQNUM_MASK   (0x7000000U)
#define	FLEXSPI_IPCR1_ISEQNUM_SHIFT   (24U)
#define	FLEXSPI_IPCR1_ISEQNUM(x)
#define	FLEXSPI_IPCR1_IPAREN_MASK   (0x80000000U)
#define	FLEXSPI_IPCR1_IPAREN_SHIFT   (31U)
#define	FLEXSPI_IPCR1_IPAREN(x)
IPCMD - IP Command Register
#define	FLEXSPI_IPCMD_TRG_MASK   (0x1U)
#define	FLEXSPI_IPCMD_TRG_SHIFT   (0U)
#define	FLEXSPI_IPCMD_TRG(x)
#define	SEMC_IPCMD_CMD_MASK   (0xFFFFU)
#define	SEMC_IPCMD_CMD_SHIFT   (0U)
#define	SEMC_IPCMD_CMD(x)
#define	SEMC_IPCMD_KEY_MASK   (0xFFFF0000U)
#define	SEMC_IPCMD_KEY_SHIFT   (16U)
#define	SEMC_IPCMD_KEY(x)
IPRXFCR - IP RX FIFO Control Register
#define	FLEXSPI_IPRXFCR_CLRIPRXF_MASK   (0x1U)
#define	FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT   (0U)
#define	FLEXSPI_IPRXFCR_CLRIPRXF(x)
#define	FLEXSPI_IPRXFCR_RXDMAEN_MASK   (0x2U)
#define	FLEXSPI_IPRXFCR_RXDMAEN_SHIFT   (1U)
#define	FLEXSPI_IPRXFCR_RXDMAEN(x)
#define	FLEXSPI_IPRXFCR_RXWMRK_MASK   (0x7CU)
#define	FLEXSPI_IPRXFCR_RXWMRK_SHIFT   (2U)
#define	FLEXSPI_IPRXFCR_RXWMRK(x)
IPTXFCR - IP TX FIFO Control Register
#define	FLEXSPI_IPTXFCR_CLRIPTXF_MASK   (0x1U)
#define	FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT   (0U)
#define	FLEXSPI_IPTXFCR_CLRIPTXF(x)
#define	FLEXSPI_IPTXFCR_TXDMAEN_MASK   (0x2U)
#define	FLEXSPI_IPTXFCR_TXDMAEN_SHIFT   (1U)
#define	FLEXSPI_IPTXFCR_TXDMAEN(x)
#define	FLEXSPI_IPTXFCR_TXWMRK_MASK   (0x7CU)
#define	FLEXSPI_IPTXFCR_TXWMRK_SHIFT   (2U)
#define	FLEXSPI_IPTXFCR_TXWMRK(x)
DLLCR - DLL Control Register 0
#define	FLEXSPI_DLLCR_DLLEN_MASK   (0x1U)
#define	FLEXSPI_DLLCR_DLLEN_SHIFT   (0U)
#define	FLEXSPI_DLLCR_DLLEN(x)
#define	FLEXSPI_DLLCR_DLLRESET_MASK   (0x2U)
#define	FLEXSPI_DLLCR_DLLRESET_SHIFT   (1U)
#define	FLEXSPI_DLLCR_DLLRESET(x)
#define	FLEXSPI_DLLCR_SLVDLYTARGET_MASK   (0x78U)
#define	FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT   (3U)
#define	FLEXSPI_DLLCR_SLVDLYTARGET(x)
#define	FLEXSPI_DLLCR_OVRDEN_MASK   (0x100U)
#define	FLEXSPI_DLLCR_OVRDEN_SHIFT   (8U)
#define	FLEXSPI_DLLCR_OVRDEN(x)
#define	FLEXSPI_DLLCR_OVRDVAL_MASK   (0x7E00U)
#define	FLEXSPI_DLLCR_OVRDVAL_SHIFT   (9U)
#define	FLEXSPI_DLLCR_OVRDVAL(x)
MISCCR4 - Misc Control Register 4
#define	FLEXSPI_MISCCR4_AHBADDRESS_MASK   (0xFFFFFFFFU)
#define	FLEXSPI_MISCCR4_AHBADDRESS_SHIFT   (0U)
#define	FLEXSPI_MISCCR4_AHBADDRESS(x)
MISCCR5 - Misc Control Register 5
#define	FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK   (0xFFFFFFFFU)
#define	FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT   (0U)
#define	FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x)
MISCCR6 - Misc Control Register 6
#define	FLEXSPI_MISCCR6_VALID_MASK   (0x1U)
#define	FLEXSPI_MISCCR6_VALID_SHIFT   (0U)
#define	FLEXSPI_MISCCR6_VALID(x)
#define	FLEXSPI_MISCCR6_HIT_MASK   (0x2U)
#define	FLEXSPI_MISCCR6_HIT_SHIFT   (1U)
#define	FLEXSPI_MISCCR6_HIT(x)
#define	FLEXSPI_MISCCR6_ADDRESS_MASK   (0xFFFFFFFCU)
#define	FLEXSPI_MISCCR6_ADDRESS_SHIFT   (2U)
#define	FLEXSPI_MISCCR6_ADDRESS(x)
MISCCR7 - Misc Control Register 7
#define	FLEXSPI_MISCCR7_VALID_MASK   (0x1U)
#define	FLEXSPI_MISCCR7_VALID_SHIFT   (0U)
#define	FLEXSPI_MISCCR7_VALID(x)
#define	FLEXSPI_MISCCR7_HIT_MASK   (0x2U)
#define	FLEXSPI_MISCCR7_HIT_SHIFT   (1U)
#define	FLEXSPI_MISCCR7_HIT(x)
#define	FLEXSPI_MISCCR7_ADDRESS_MASK   (0xFFFFFFFCU)
#define	FLEXSPI_MISCCR7_ADDRESS_SHIFT   (2U)
#define	FLEXSPI_MISCCR7_ADDRESS(x)
STS0 - Status Register 0
#define	FLEXSPI_STS0_SEQIDLE_MASK   (0x1U)
#define	FLEXSPI_STS0_SEQIDLE_SHIFT   (0U)
#define	FLEXSPI_STS0_SEQIDLE(x)
#define	FLEXSPI_STS0_ARBIDLE_MASK   (0x2U)
#define	FLEXSPI_STS0_ARBIDLE_SHIFT   (1U)
#define	FLEXSPI_STS0_ARBIDLE(x)
#define	FLEXSPI_STS0_ARBCMDSRC_MASK   (0xCU)
#define	FLEXSPI_STS0_ARBCMDSRC_SHIFT   (2U)
#define	FLEXSPI_STS0_ARBCMDSRC(x)
#define	SEMC_STS0_IDLE_MASK   (0x1U)
#define	SEMC_STS0_IDLE_SHIFT   (0U)
#define	SEMC_STS0_IDLE(x)
#define	SEMC_STS0_NARDY_MASK   (0x2U)
#define	SEMC_STS0_NARDY_SHIFT   (1U)
#define	SEMC_STS0_NARDY(x)
STS1 - Status Register 1
#define	FLEXSPI_STS1_AHBCMDERRID_MASK   (0xFU)
#define	FLEXSPI_STS1_AHBCMDERRID_SHIFT   (0U)
#define	FLEXSPI_STS1_AHBCMDERRID(x)
#define	FLEXSPI_STS1_AHBCMDERRCODE_MASK   (0xF00U)
#define	FLEXSPI_STS1_AHBCMDERRCODE_SHIFT   (8U)
#define	FLEXSPI_STS1_AHBCMDERRCODE(x)
#define	FLEXSPI_STS1_IPCMDERRID_MASK   (0xF0000U)
#define	FLEXSPI_STS1_IPCMDERRID_SHIFT   (16U)
#define	FLEXSPI_STS1_IPCMDERRID(x)
#define	FLEXSPI_STS1_IPCMDERRCODE_MASK   (0xF000000U)
#define	FLEXSPI_STS1_IPCMDERRCODE_SHIFT   (24U)
#define	FLEXSPI_STS1_IPCMDERRCODE(x)
STS2 - Status Register 2
#define	FLEXSPI_STS2_ASLVLOCK_MASK   (0x1U)
#define	FLEXSPI_STS2_ASLVLOCK_SHIFT   (0U)
#define	FLEXSPI_STS2_ASLVLOCK(x)
#define	FLEXSPI_STS2_AREFLOCK_MASK   (0x2U)
#define	FLEXSPI_STS2_AREFLOCK_SHIFT   (1U)
#define	FLEXSPI_STS2_AREFLOCK(x)
#define	FLEXSPI_STS2_ASLVSEL_MASK   (0xFCU)
#define	FLEXSPI_STS2_ASLVSEL_SHIFT   (2U)
#define	FLEXSPI_STS2_ASLVSEL(x)
#define	FLEXSPI_STS2_AREFSEL_MASK   (0x3F00U)
#define	FLEXSPI_STS2_AREFSEL_SHIFT   (8U)
#define	FLEXSPI_STS2_AREFSEL(x)
#define	FLEXSPI_STS2_BSLVLOCK_MASK   (0x10000U)
#define	FLEXSPI_STS2_BSLVLOCK_SHIFT   (16U)
#define	FLEXSPI_STS2_BSLVLOCK(x)
#define	FLEXSPI_STS2_BREFLOCK_MASK   (0x20000U)
#define	FLEXSPI_STS2_BREFLOCK_SHIFT   (17U)
#define	FLEXSPI_STS2_BREFLOCK(x)
#define	FLEXSPI_STS2_BSLVSEL_MASK   (0xFC0000U)
#define	FLEXSPI_STS2_BSLVSEL_SHIFT   (18U)
#define	FLEXSPI_STS2_BSLVSEL(x)
#define	FLEXSPI_STS2_BREFSEL_MASK   (0x3F000000U)
#define	FLEXSPI_STS2_BREFSEL_SHIFT   (24U)
#define	FLEXSPI_STS2_BREFSEL(x)
#define	SEMC_STS2_NDWRPEND_MASK   (0x8U)
#define	SEMC_STS2_NDWRPEND_SHIFT   (3U)
#define	SEMC_STS2_NDWRPEND(x)
AHBSPNDSTS - AHB Suspend Status Register
#define	FLEXSPI_AHBSPNDSTS_ACTIVE_MASK   (0x1U)
#define	FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT   (0U)
#define	FLEXSPI_AHBSPNDSTS_ACTIVE(x)
#define	FLEXSPI_AHBSPNDSTS_BUFID_MASK   (0xEU)
#define	FLEXSPI_AHBSPNDSTS_BUFID_SHIFT   (1U)
#define	FLEXSPI_AHBSPNDSTS_BUFID(x)
#define	FLEXSPI_AHBSPNDSTS_DATLFT_MASK   (0xFFFF0000U)
#define	FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT   (16U)
#define	FLEXSPI_AHBSPNDSTS_DATLFT(x)
IPRXFSTS - IP RX FIFO Status Register
#define	FLEXSPI_IPRXFSTS_FILL_MASK   (0xFFU)
#define	FLEXSPI_IPRXFSTS_FILL_SHIFT   (0U)
#define	FLEXSPI_IPRXFSTS_FILL(x)
#define	FLEXSPI_IPRXFSTS_RDCNTR_MASK   (0xFFFF0000U)
#define	FLEXSPI_IPRXFSTS_RDCNTR_SHIFT   (16U)
#define	FLEXSPI_IPRXFSTS_RDCNTR(x)
IPTXFSTS - IP TX FIFO Status Register
#define	FLEXSPI_IPTXFSTS_FILL_MASK   (0xFFU)
#define	FLEXSPI_IPTXFSTS_FILL_SHIFT   (0U)
#define	FLEXSPI_IPTXFSTS_FILL(x)
#define	FLEXSPI_IPTXFSTS_WRCNTR_MASK   (0xFFFF0000U)
#define	FLEXSPI_IPTXFSTS_WRCNTR_SHIFT   (16U)
#define	FLEXSPI_IPTXFSTS_WRCNTR(x)
RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31
#define	FLEXSPI_RFDR_RXDATA_MASK   (0xFFFFFFFFU)
#define	FLEXSPI_RFDR_RXDATA_SHIFT   (0U)
#define	FLEXSPI_RFDR_RXDATA(x)
TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31
#define	FLEXSPI_TFDR_TXDATA_MASK   (0xFFFFFFFFU)
#define	FLEXSPI_TFDR_TXDATA_SHIFT   (0U)
#define	FLEXSPI_TFDR_TXDATA(x)
LUT - LUT 0..LUT 63
#define	FLEXSPI_LUT_OPERAND0_MASK   (0xFFU)
#define	FLEXSPI_LUT_OPERAND0_SHIFT   (0U)
#define	FLEXSPI_LUT_OPERAND0(x)
#define	FLEXSPI_LUT_NUM_PADS0_MASK   (0x300U)
#define	FLEXSPI_LUT_NUM_PADS0_SHIFT   (8U)
#define	FLEXSPI_LUT_NUM_PADS0(x)
#define	FLEXSPI_LUT_OPCODE0_MASK   (0xFC00U)
#define	FLEXSPI_LUT_OPCODE0_SHIFT   (10U)
#define	FLEXSPI_LUT_OPCODE0(x)
#define	FLEXSPI_LUT_OPERAND1_MASK   (0xFF0000U)
#define	FLEXSPI_LUT_OPERAND1_SHIFT   (16U)
#define	FLEXSPI_LUT_OPERAND1(x)
#define	FLEXSPI_LUT_NUM_PADS1_MASK   (0x3000000U)
#define	FLEXSPI_LUT_NUM_PADS1_SHIFT   (24U)
#define	FLEXSPI_LUT_NUM_PADS1(x)
#define	FLEXSPI_LUT_OPCODE1_MASK   (0xFC000000U)
#define	FLEXSPI_LUT_OPCODE1_SHIFT   (26U)
#define	FLEXSPI_LUT_OPCODE1(x)
HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register
#define	FLEXSPI_HMSTRCR_MASK_MASK   (0xFFFFU)
#define	FLEXSPI_HMSTRCR_MASK_SHIFT   (0U)
#define	FLEXSPI_HMSTRCR_MASK(x)
#define	FLEXSPI_HMSTRCR_MSTRID_MASK   (0xFFFF0000U)
#define	FLEXSPI_HMSTRCR_MSTRID_SHIFT   (16U)
#define	FLEXSPI_HMSTRCR_MSTRID(x)
HADDRSTART - HADDR REMAP START ADDR
#define	FLEXSPI_HADDRSTART_REMAPEN_MASK   (0x1U)
#define	FLEXSPI_HADDRSTART_REMAPEN_SHIFT   (0U)
#define	FLEXSPI_HADDRSTART_REMAPEN(x)
#define	FLEXSPI_HADDRSTART_KBINECC_MASK   (0x2U)
#define	FLEXSPI_HADDRSTART_KBINECC_SHIFT   (1U)
#define	FLEXSPI_HADDRSTART_KBINECC(x)
#define	FLEXSPI_HADDRSTART_ADDRSTART_MASK   (0xFFFFF000U)
#define	FLEXSPI_HADDRSTART_ADDRSTART_SHIFT   (12U)
#define	FLEXSPI_HADDRSTART_ADDRSTART(x)
HADDREND - HADDR REMAP END ADDR
#define	FLEXSPI_HADDREND_ENDSTART_MASK   (0xFFFFF000U)
#define	FLEXSPI_HADDREND_ENDSTART_SHIFT   (12U)
#define	FLEXSPI_HADDREND_ENDSTART(x)
HADDROFFSET - HADDR REMAP OFFSET
#define	FLEXSPI_HADDROFFSET_ADDROFFSET_MASK   (0xFFFFF000U)
#define	FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT   (12U)
#define	FLEXSPI_HADDROFFSET_ADDROFFSET(x)
IPSNSZSTART0 - IPS nonsecure region Start address of region 0
#define	FLEXSPI_IPSNSZSTART0_start_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_IPSNSZSTART0_start_address_SHIFT   (12U)
#define	FLEXSPI_IPSNSZSTART0_start_address(x)
IPSNSZEND0 - IPS nonsecure region End address of region 0
#define	FLEXSPI_IPSNSZEND0_end_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_IPSNSZEND0_end_address_SHIFT   (12U)
#define	FLEXSPI_IPSNSZEND0_end_address(x)
IPSNSZSTART1 - IPS nonsecure region Start address of region 1
#define	FLEXSPI_IPSNSZSTART1_start_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_IPSNSZSTART1_start_address_SHIFT   (12U)
#define	FLEXSPI_IPSNSZSTART1_start_address(x)
IPSNSZEND1 - IPS nonsecure region End address of region 1
#define	FLEXSPI_IPSNSZEND1_end_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_IPSNSZEND1_end_address_SHIFT   (12U)
#define	FLEXSPI_IPSNSZEND1_end_address(x)
AHBBUFREGIONSTART0 - RX BUF Start address of region 0
#define	FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONSTART0_start_address(x)
AHBBUFREGIONEND0 - RX BUF region End address of region 0
#define	FLEXSPI_AHBBUFREGIONEND0_end_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONEND0_end_address(x)
AHBBUFREGIONSTART1 - RX BUF Start address of region 1
#define	FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONSTART1_start_address(x)
AHBBUFREGIONEND1 - RX BUF region End address of region 1
#define	FLEXSPI_AHBBUFREGIONEND1_end_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONEND1_end_address(x)
AHBBUFREGIONSTART2 - RX BUF Start address of region 2
#define	FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONSTART2_start_address(x)
AHBBUFREGIONEND2 - RX BUF region End address of region 2
#define	FLEXSPI_AHBBUFREGIONEND2_end_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONEND2_end_address(x)
AHBBUFREGIONSTART3 - RX BUF Start address of region 3
#define	FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONSTART3_start_address(x)
AHBBUFREGIONEND3 - RX BUF region End address of region 3
#define	FLEXSPI_AHBBUFREGIONEND3_end_address_MASK   (0xFFFFF000U)
#define	FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT   (12U)
#define	FLEXSPI_AHBBUFREGIONEND3_end_address(x)
CM_AUTHEN_CTRL - CM Authentication Control
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK   (0x2U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK   (0x10U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT   (4U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK   (0xF00U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT   (8U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK   (0x1000U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT   (12U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x)
CM_INT_CTRL - CM Interrupt Control
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK   (0x2U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK   (0x4U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT   (2U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK   (0x10000U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT   (16U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK   (0x20000U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT   (17U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK   (0x40000U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT   (18U)
#define	GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x)
CM_MISC - Miscellaneous
#define	GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x)
#define	GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK   (0x2U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK   (0x4U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT   (2U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x)
#define	GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK   (0x10U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT   (4U)
#define	GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x)
CM_MODE_CTRL - CPU mode control
#define	GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK   (0x3U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x)
#define	GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK   (0x10U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT   (4U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x)
CM_MODE_STAT - CM CPU mode Status
#define	GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK   (0x3U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x)
#define	GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK   (0xCU)
#define	GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT   (2U)
#define	GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x)
CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x)
CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK   (0x2U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x)
CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK   (0xFFFFFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x)
CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK   (0x2U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x)
CM_SLEEP_SSAR_CTRL - CM sleep SSAR control
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x)
CM_SLEEP_LPCG_CTRL - CM sleep LPCG control
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x)
CM_SLEEP_PLL_CTRL - CM sleep PLL control
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x)
CM_SLEEP_ISO_CTRL - CM sleep isolation control
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x)
CM_SLEEP_RESET_CTRL - CM sleep reset control
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x)
CM_SLEEP_POWER_CTRL - CM sleep power control
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x)
CM_WAKEUP_POWER_CTRL - CM wakeup power control
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x)
CM_WAKEUP_RESET_CTRL - CM wakeup reset control
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x)
CM_WAKEUP_ISO_CTRL - CM wakeup isolation control
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x)
CM_WAKEUP_PLL_CTRL - CM wakeup PLL control
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x)
CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x)
CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x)
CM_SP_CTRL - CM Setpoint Control
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK   (0x1EU)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK   (0x20U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT   (5U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK   (0x3C0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT   (6U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK   (0x400U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT   (10U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK   (0x7800U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT   (11U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK   (0x8000U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT   (15U)
#define	GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x)
CM_SP_STAT - CM Setpoint Status
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK   (0xFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK   (0xF0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT   (4U)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK   (0xF00U)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT   (8U)
#define	GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x)
CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed
#define	GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x)
CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed
#define	GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x)
CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed
#define	GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x)
CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed
#define	GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x)
CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK   (0xFFFFU)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x)
CM_STBY_CTRL - CM standby control
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK   (0x1U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT   (0U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK   (0x2U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT   (1U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK   (0x4U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT   (2U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK   (0x10000U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT   (16U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK   (0x20000U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT   (17U)
#define	GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x)
SP_AUTHEN_CTRL - SP Authentication Control
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK   (0x1U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK   (0x2U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT   (1U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK   (0x10U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT   (4U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK   (0xF00U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT   (8U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK   (0x1000U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT   (12U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x)
SP_INT_CTRL - SP Interrupt Control
#define	GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK   (0x1U)
#define	GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x)
#define	GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK   (0x2U)
#define	GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT   (1U)
#define	GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x)
SP_CPU_REQ - CPU SP Request
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK   (0xFU)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK   (0xF0U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT   (4U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK   (0xF00U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT   (8U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK   (0xF000U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT   (12U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK   (0xF0000U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT   (16U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK   (0xF00000U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT   (20U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK   (0xF000000U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT   (24U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK   (0xF0000000U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x)
SP_SYS_STAT - SP System Status
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK   (0xF0000U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT   (16U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK   (0xF00000U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT   (20U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK   (0xF000000U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT   (24U)
#define	GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x)
SP_ROSC_CTRL - SP ROSC Control
#define	GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x)
SP_PRIORITY_0_7 - SP0~7 Priority
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK   (0xFU)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK   (0xF0U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT   (4U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK   (0xF00U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT   (8U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK   (0xF000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT   (12U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK   (0xF0000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT   (16U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK   (0xF00000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT   (20U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK   (0xF000000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT   (24U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK   (0xF0000000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x)
SP_PRIORITY_8_15 - SP8~15 Priority
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK   (0xFU)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK   (0xF0U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT   (4U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK   (0xF00U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT   (8U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK   (0xF000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT   (12U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK   (0xF0000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT   (16U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK   (0xF00000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT   (20U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK   (0xF000000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT   (24U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK   (0xF0000000U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x)
SP_SSAR_SAVE_CTRL - SP SSAR save control
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x)
SP_LPCG_OFF_CTRL - SP LPCG off control
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x)
SP_GROUP_DOWN_CTRL - SP group down control
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x)
SP_ROOT_DOWN_CTRL - SP root down control
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x)
SP_PLL_OFF_CTRL - SP PLL off control
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x)
SP_ISO_ON_CTRL - SP ISO on control
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x)
SP_RESET_EARLY_CTRL - SP reset early control
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x)
SP_POWER_OFF_CTRL - SP power off control
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x)
SP_BIAS_OFF_CTRL - SP bias off control
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x)
SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x)
SP_LDO_PRE_CTRL - SP LDO pre control
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x)
SP_DCDC_DOWN_CTRL - SP DCDC down control
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x)
SP_DCDC_UP_CTRL - SP DCDC up control
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x)
SP_LDO_POST_CTRL - SP LDO post control
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x)
SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x)
SP_BIAS_ON_CTRL - SP bias on control
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x)
SP_POWER_ON_CTRL - SP power on control
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x)
SP_RESET_LATE_CTRL - SP reset late control
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x)
SP_ISO_OFF_CTRL - SP ISO off control
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x)
SP_PLL_ON_CTRL - SP PLL on control
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x)
SP_ROOT_UP_CTRL - SP root up control
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x)
SP_GROUP_UP_CTRL - SP group up control
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x)
SP_LPCG_ON_CTRL - SP LPCG on control
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x)
SP_SSAR_RESTORE_CTRL - SP SSAR restore control
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x)
STBY_AUTHEN_CTRL - Standby Authentication Control
#define	GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x)
STBY_MISC - STBY Misc
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK   (0x1U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK   (0x2U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT   (1U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK   (0x4U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT   (2U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK   (0x8U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT   (3U)
#define	GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x)
STBY_LPCG_IN_CTRL - STBY lpcg_in control
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x)
STBY_PLL_IN_CTRL - STBY pll_in control
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x)
STBY_BIAS_IN_CTRL - STBY bias_in control
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x)
STBY_PLDO_IN_CTRL - STBY pldo_in control
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x)
STBY_BANDGAP_IN_CTRL - STBY bandgap_in control
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x)
STBY_LDO_IN_CTRL - STBY ldo_in control
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x)
STBY_DCDC_IN_CTRL - STBY dcdc_in control
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x)
STBY_PMIC_IN_CTRL - STBY PMIC in control
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x)
STBY_PMIC_OUT_CTRL - STBY PMIC out control
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x)
STBY_DCDC_OUT_CTRL - STBY DCDC out control
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x)
STBY_LDO_OUT_CTRL - STBY LDO out control
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x)
STBY_BANDGAP_OUT_CTRL - STBY bandgap out control
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x)
STBY_PLDO_OUT_CTRL - STBY pldo out control
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x)
STBY_BIAS_OUT_CTRL - STBY bias out control
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x)
STBY_PLL_OUT_CTRL - STBY PLL out control
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x)
STBY_LPCG_OUT_CTRL - STBY LPCG out control
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK   (0xFFFFU)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT   (0U)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK   (0x30000000U)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT   (28U)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK   (0x80000000U)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT   (31U)
#define	GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x)
DR - GPIO data register
#define	GPIO_DR_DR_MASK   (0xFFFFFFFFU)
#define	GPIO_DR_DR_SHIFT   (0U)
#define	GPIO_DR_DR(x)
GDIR - GPIO direction register
#define	GPIO_GDIR_GDIR_MASK   (0xFFFFFFFFU)
#define	GPIO_GDIR_GDIR_SHIFT   (0U)
#define	GPIO_GDIR_GDIR(x)
PSR - GPIO pad status register
#define	GPIO_PSR_PSR_MASK   (0xFFFFFFFFU)
#define	GPIO_PSR_PSR_SHIFT   (0U)
#define	GPIO_PSR_PSR(x)
ICR1 - GPIO interrupt configuration register1
#define	GPIO_ICR1_ICR0_MASK   (0x3U)
#define	GPIO_ICR1_ICR0_SHIFT   (0U)
#define	GPIO_ICR1_ICR0(x)
#define	GPIO_ICR1_ICR1_MASK   (0xCU)
#define	GPIO_ICR1_ICR1_SHIFT   (2U)
#define	GPIO_ICR1_ICR1(x)
#define	GPIO_ICR1_ICR2_MASK   (0x30U)
#define	GPIO_ICR1_ICR2_SHIFT   (4U)
#define	GPIO_ICR1_ICR2(x)
#define	GPIO_ICR1_ICR3_MASK   (0xC0U)
#define	GPIO_ICR1_ICR3_SHIFT   (6U)
#define	GPIO_ICR1_ICR3(x)
#define	GPIO_ICR1_ICR4_MASK   (0x300U)
#define	GPIO_ICR1_ICR4_SHIFT   (8U)
#define	GPIO_ICR1_ICR4(x)
#define	GPIO_ICR1_ICR5_MASK   (0xC00U)
#define	GPIO_ICR1_ICR5_SHIFT   (10U)
#define	GPIO_ICR1_ICR5(x)
#define	GPIO_ICR1_ICR6_MASK   (0x3000U)
#define	GPIO_ICR1_ICR6_SHIFT   (12U)
#define	GPIO_ICR1_ICR6(x)
#define	GPIO_ICR1_ICR7_MASK   (0xC000U)
#define	GPIO_ICR1_ICR7_SHIFT   (14U)
#define	GPIO_ICR1_ICR7(x)
#define	GPIO_ICR1_ICR8_MASK   (0x30000U)
#define	GPIO_ICR1_ICR8_SHIFT   (16U)
#define	GPIO_ICR1_ICR8(x)
#define	GPIO_ICR1_ICR9_MASK   (0xC0000U)
#define	GPIO_ICR1_ICR9_SHIFT   (18U)
#define	GPIO_ICR1_ICR9(x)
#define	GPIO_ICR1_ICR10_MASK   (0x300000U)
#define	GPIO_ICR1_ICR10_SHIFT   (20U)
#define	GPIO_ICR1_ICR10(x)
#define	GPIO_ICR1_ICR11_MASK   (0xC00000U)
#define	GPIO_ICR1_ICR11_SHIFT   (22U)
#define	GPIO_ICR1_ICR11(x)
#define	GPIO_ICR1_ICR12_MASK   (0x3000000U)
#define	GPIO_ICR1_ICR12_SHIFT   (24U)
#define	GPIO_ICR1_ICR12(x)
#define	GPIO_ICR1_ICR13_MASK   (0xC000000U)
#define	GPIO_ICR1_ICR13_SHIFT   (26U)
#define	GPIO_ICR1_ICR13(x)
#define	GPIO_ICR1_ICR14_MASK   (0x30000000U)
#define	GPIO_ICR1_ICR14_SHIFT   (28U)
#define	GPIO_ICR1_ICR14(x)
#define	GPIO_ICR1_ICR15_MASK   (0xC0000000U)
#define	GPIO_ICR1_ICR15_SHIFT   (30U)
#define	GPIO_ICR1_ICR15(x)
ICR2 - GPIO interrupt configuration register2
#define	GPIO_ICR2_ICR16_MASK   (0x3U)
#define	GPIO_ICR2_ICR16_SHIFT   (0U)
#define	GPIO_ICR2_ICR16(x)
#define	GPIO_ICR2_ICR17_MASK   (0xCU)
#define	GPIO_ICR2_ICR17_SHIFT   (2U)
#define	GPIO_ICR2_ICR17(x)
#define	GPIO_ICR2_ICR18_MASK   (0x30U)
#define	GPIO_ICR2_ICR18_SHIFT   (4U)
#define	GPIO_ICR2_ICR18(x)
#define	GPIO_ICR2_ICR19_MASK   (0xC0U)
#define	GPIO_ICR2_ICR19_SHIFT   (6U)
#define	GPIO_ICR2_ICR19(x)
#define	GPIO_ICR2_ICR20_MASK   (0x300U)
#define	GPIO_ICR2_ICR20_SHIFT   (8U)
#define	GPIO_ICR2_ICR20(x)
#define	GPIO_ICR2_ICR21_MASK   (0xC00U)
#define	GPIO_ICR2_ICR21_SHIFT   (10U)
#define	GPIO_ICR2_ICR21(x)
#define	GPIO_ICR2_ICR22_MASK   (0x3000U)
#define	GPIO_ICR2_ICR22_SHIFT   (12U)
#define	GPIO_ICR2_ICR22(x)
#define	GPIO_ICR2_ICR23_MASK   (0xC000U)
#define	GPIO_ICR2_ICR23_SHIFT   (14U)
#define	GPIO_ICR2_ICR23(x)
#define	GPIO_ICR2_ICR24_MASK   (0x30000U)
#define	GPIO_ICR2_ICR24_SHIFT   (16U)
#define	GPIO_ICR2_ICR24(x)
#define	GPIO_ICR2_ICR25_MASK   (0xC0000U)
#define	GPIO_ICR2_ICR25_SHIFT   (18U)
#define	GPIO_ICR2_ICR25(x)
#define	GPIO_ICR2_ICR26_MASK   (0x300000U)
#define	GPIO_ICR2_ICR26_SHIFT   (20U)
#define	GPIO_ICR2_ICR26(x)
#define	GPIO_ICR2_ICR27_MASK   (0xC00000U)
#define	GPIO_ICR2_ICR27_SHIFT   (22U)
#define	GPIO_ICR2_ICR27(x)
#define	GPIO_ICR2_ICR28_MASK   (0x3000000U)
#define	GPIO_ICR2_ICR28_SHIFT   (24U)
#define	GPIO_ICR2_ICR28(x)
#define	GPIO_ICR2_ICR29_MASK   (0xC000000U)
#define	GPIO_ICR2_ICR29_SHIFT   (26U)
#define	GPIO_ICR2_ICR29(x)
#define	GPIO_ICR2_ICR30_MASK   (0x30000000U)
#define	GPIO_ICR2_ICR30_SHIFT   (28U)
#define	GPIO_ICR2_ICR30(x)
#define	GPIO_ICR2_ICR31_MASK   (0xC0000000U)
#define	GPIO_ICR2_ICR31_SHIFT   (30U)
#define	GPIO_ICR2_ICR31(x)
IMR - GPIO interrupt mask register
#define	GPIO_IMR_IMR_MASK   (0xFFFFFFFFU)
#define	GPIO_IMR_IMR_SHIFT   (0U)
#define	GPIO_IMR_IMR(x)
ISR - GPIO interrupt status register
#define	GPIO_ISR_ISR_MASK   (0xFFFFFFFFU)
#define	GPIO_ISR_ISR_SHIFT   (0U)
#define	GPIO_ISR_ISR(x)
EDGE_SEL - GPIO edge select register
#define	GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK   (0xFFFFFFFFU)
#define	GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT   (0U)
#define	GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)
DR_SET - GPIO data register SET
#define	GPIO_DR_SET_DR_SET_MASK   (0xFFFFFFFFU)
#define	GPIO_DR_SET_DR_SET_SHIFT   (0U)
#define	GPIO_DR_SET_DR_SET(x)
DR_CLEAR - GPIO data register CLEAR
#define	GPIO_DR_CLEAR_DR_CLEAR_MASK   (0xFFFFFFFFU)
#define	GPIO_DR_CLEAR_DR_CLEAR_SHIFT   (0U)
#define	GPIO_DR_CLEAR_DR_CLEAR(x)
DR_TOGGLE - GPIO data register TOGGLE
#define	GPIO_DR_TOGGLE_DR_TOGGLE_MASK   (0xFFFFFFFFU)
#define	GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT   (0U)
#define	GPIO_DR_TOGGLE_DR_TOGGLE(x)
CR - GPT Control Register
#define	GPT_CR_EN_MASK   (0x1U)
#define	GPT_CR_EN_SHIFT   (0U)
#define	GPT_CR_EN(x)
#define	GPT_CR_ENMOD_MASK   (0x2U)
#define	GPT_CR_ENMOD_SHIFT   (1U)
#define	GPT_CR_ENMOD(x)
#define	GPT_CR_DBGEN_MASK   (0x4U)
#define	GPT_CR_DBGEN_SHIFT   (2U)
#define	GPT_CR_DBGEN(x)
#define	GPT_CR_WAITEN_MASK   (0x8U)
#define	GPT_CR_WAITEN_SHIFT   (3U)
#define	GPT_CR_WAITEN(x)
#define	GPT_CR_DOZEEN_MASK   (0x10U)
#define	GPT_CR_DOZEEN_SHIFT   (4U)
#define	GPT_CR_DOZEEN(x)
#define	GPT_CR_STOPEN_MASK   (0x20U)
#define	GPT_CR_STOPEN_SHIFT   (5U)
#define	GPT_CR_STOPEN(x)
#define	GPT_CR_CLKSRC_MASK   (0x1C0U)
#define	GPT_CR_CLKSRC_SHIFT   (6U)
#define	GPT_CR_CLKSRC(x)
#define	GPT_CR_FRR_MASK   (0x200U)
#define	GPT_CR_FRR_SHIFT   (9U)
#define	GPT_CR_FRR(x)
#define	GPT_CR_EN_24M_MASK   (0x400U)
#define	GPT_CR_EN_24M_SHIFT   (10U)
#define	GPT_CR_EN_24M(x)
#define	GPT_CR_SWR_MASK   (0x8000U)
#define	GPT_CR_SWR_SHIFT   (15U)
#define	GPT_CR_SWR(x)
#define	GPT_CR_IM1_MASK   (0x30000U)
#define	GPT_CR_IM1_SHIFT   (16U)
#define	GPT_CR_IM1(x)
#define	GPT_CR_IM2_MASK   (0xC0000U)
#define	GPT_CR_IM2_SHIFT   (18U)
#define	GPT_CR_IM2(x)
#define	GPT_CR_OM1_MASK   (0x700000U)
#define	GPT_CR_OM1_SHIFT   (20U)
#define	GPT_CR_OM1(x)
#define	GPT_CR_OM2_MASK   (0x3800000U)
#define	GPT_CR_OM2_SHIFT   (23U)
#define	GPT_CR_OM2(x)
#define	GPT_CR_OM3_MASK   (0x1C000000U)
#define	GPT_CR_OM3_SHIFT   (26U)
#define	GPT_CR_OM3(x)
#define	GPT_CR_FO1_MASK   (0x20000000U)
#define	GPT_CR_FO1_SHIFT   (29U)
#define	GPT_CR_FO1(x)
#define	GPT_CR_FO2_MASK   (0x40000000U)
#define	GPT_CR_FO2_SHIFT   (30U)
#define	GPT_CR_FO2(x)
#define	GPT_CR_FO3_MASK   (0x80000000U)
#define	GPT_CR_FO3_SHIFT   (31U)
#define	GPT_CR_FO3(x)
PR - GPT Prescaler Register
#define	GPT_PR_PRESCALER_MASK   (0xFFFU)
#define	GPT_PR_PRESCALER_SHIFT   (0U)
#define	GPT_PR_PRESCALER(x)
#define	GPT_PR_PRESCALER24M_MASK   (0xF000U)
#define	GPT_PR_PRESCALER24M_SHIFT   (12U)
#define	GPT_PR_PRESCALER24M(x)
SR - GPT Status Register
#define	GPT_SR_OF1_MASK   (0x1U)
#define	GPT_SR_OF1_SHIFT   (0U)
#define	GPT_SR_OF1(x)
#define	GPT_SR_OF2_MASK   (0x2U)
#define	GPT_SR_OF2_SHIFT   (1U)
#define	GPT_SR_OF2(x)
#define	GPT_SR_OF3_MASK   (0x4U)
#define	GPT_SR_OF3_SHIFT   (2U)
#define	GPT_SR_OF3(x)
#define	GPT_SR_IF1_MASK   (0x8U)
#define	GPT_SR_IF1_SHIFT   (3U)
#define	GPT_SR_IF1(x)
#define	GPT_SR_IF2_MASK   (0x10U)
#define	GPT_SR_IF2_SHIFT   (4U)
#define	GPT_SR_IF2(x)
#define	GPT_SR_ROV_MASK   (0x20U)
#define	GPT_SR_ROV_SHIFT   (5U)
#define	GPT_SR_ROV(x)
IR - GPT Interrupt Register
#define	GPT_IR_OF1IE_MASK   (0x1U)
#define	GPT_IR_OF1IE_SHIFT   (0U)
#define	GPT_IR_OF1IE(x)
#define	GPT_IR_OF2IE_MASK   (0x2U)
#define	GPT_IR_OF2IE_SHIFT   (1U)
#define	GPT_IR_OF2IE(x)
#define	GPT_IR_OF3IE_MASK   (0x4U)
#define	GPT_IR_OF3IE_SHIFT   (2U)
#define	GPT_IR_OF3IE(x)
#define	GPT_IR_IF1IE_MASK   (0x8U)
#define	GPT_IR_IF1IE_SHIFT   (3U)
#define	GPT_IR_IF1IE(x)
#define	GPT_IR_IF2IE_MASK   (0x10U)
#define	GPT_IR_IF2IE_SHIFT   (4U)
#define	GPT_IR_IF2IE(x)
#define	GPT_IR_ROVIE_MASK   (0x20U)
#define	GPT_IR_ROVIE_SHIFT   (5U)
#define	GPT_IR_ROVIE(x)
OCR - GPT Output Compare Register
#define	GPT_OCR_COMP_MASK   (0xFFFFFFFFU)
#define	GPT_OCR_COMP_SHIFT   (0U)
#define	GPT_OCR_COMP(x)
ICR - GPT Input Capture Register
#define	GPT_ICR_CAPT_MASK   (0xFFFFFFFFU)
#define	GPT_ICR_CAPT_SHIFT   (0U)
#define	GPT_ICR_CAPT(x)
CNT - GPT Counter Register
#define	GPT_CNT_COUNT_MASK   (0xFFFFFFFFU)
#define	GPT_CNT_COUNT_SHIFT   (0U)
#define	GPT_CNT_COUNT(x)
VERID - Version ID
#define	I2S_VERID_FEATURE_MASK   (0xFFFFU)
#define	I2S_VERID_FEATURE_SHIFT   (0U)
#define	I2S_VERID_FEATURE(x)
#define	I2S_VERID_MINOR_MASK   (0xFF0000U)
#define	I2S_VERID_MINOR_SHIFT   (16U)
#define	I2S_VERID_MINOR(x)
#define	I2S_VERID_MAJOR_MASK   (0xFF000000U)
#define	I2S_VERID_MAJOR_SHIFT   (24U)
#define	I2S_VERID_MAJOR(x)
#define	LPI2C_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPI2C_VERID_FEATURE_SHIFT   (0U)
#define	LPI2C_VERID_FEATURE(x)
#define	LPI2C_VERID_MINOR_MASK   (0xFF0000U)
#define	LPI2C_VERID_MINOR_SHIFT   (16U)
#define	LPI2C_VERID_MINOR(x)
#define	LPI2C_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPI2C_VERID_MAJOR_SHIFT   (24U)
#define	LPI2C_VERID_MAJOR(x)
#define	LPSPI_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPSPI_VERID_FEATURE_SHIFT   (0U)
#define	LPSPI_VERID_FEATURE(x)
#define	LPSPI_VERID_MINOR_MASK   (0xFF0000U)
#define	LPSPI_VERID_MINOR_SHIFT   (16U)
#define	LPSPI_VERID_MINOR(x)
#define	LPSPI_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPSPI_VERID_MAJOR_SHIFT   (24U)
#define	LPSPI_VERID_MAJOR(x)
PARAM - Parameter
#define	I2S_PARAM_DATALINE_MASK   (0xFU)
#define	I2S_PARAM_DATALINE_SHIFT   (0U)
#define	I2S_PARAM_DATALINE(x)
#define	I2S_PARAM_FIFO_MASK   (0xF00U)
#define	I2S_PARAM_FIFO_SHIFT   (8U)
#define	I2S_PARAM_FIFO(x)
#define	I2S_PARAM_FRAME_MASK   (0xF0000U)
#define	I2S_PARAM_FRAME_SHIFT   (16U)
#define	I2S_PARAM_FRAME(x)
#define	LPI2C_PARAM_MTXFIFO_MASK   (0xFU)
#define	LPI2C_PARAM_MTXFIFO_SHIFT   (0U)
#define	LPI2C_PARAM_MTXFIFO(x)
#define	LPI2C_PARAM_MRXFIFO_MASK   (0xF00U)
#define	LPI2C_PARAM_MRXFIFO_SHIFT   (8U)
#define	LPI2C_PARAM_MRXFIFO(x)
#define	LPSPI_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPSPI_PARAM_TXFIFO_SHIFT   (0U)
#define	LPSPI_PARAM_TXFIFO(x)
#define	LPSPI_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPSPI_PARAM_RXFIFO_SHIFT   (8U)
#define	LPSPI_PARAM_RXFIFO(x)
#define	LPSPI_PARAM_PCSNUM_MASK   (0xFF0000U)
#define	LPSPI_PARAM_PCSNUM_SHIFT   (16U)
#define	LPSPI_PARAM_PCSNUM(x)
TCSR - Transmit Control
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)
TCR1 - Transmit Configuration 1
#define	I2S_TCR1_TFW_MASK   (0x1FU)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)
TCR2 - Transmit Configuration 2
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)
#define	I2S_TCR2_BYP_MASK   (0x800000U)
#define	I2S_TCR2_BYP_SHIFT   (23U)
#define	I2S_TCR2_BYP(x)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)
#define	I2S_TCR2_SYNC_MASK   (0x40000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)
TCR3 - Transmit Configuration 3
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)
#define	I2S_TCR3_TCE_MASK   (0xF0000U)
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)
#define	I2S_TCR3_CFR_MASK   (0xF000000U)
#define	I2S_TCR3_CFR_SHIFT   (24U)
#define	I2S_TCR3_CFR(x)
TCR4 - Transmit Configuration 4
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)
#define	I2S_TCR4_ONDEM_MASK   (0x4U)
#define	I2S_TCR4_ONDEM_SHIFT   (2U)
#define	I2S_TCR4_ONDEM(x)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)
#define	I2S_TCR4_CHMOD_MASK   (0x20U)
#define	I2S_TCR4_CHMOD_SHIFT   (5U)
#define	I2S_TCR4_CHMOD(x)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)
#define	I2S_TCR4_FPACK_MASK   (0x3000000U)
#define	I2S_TCR4_FPACK_SHIFT   (24U)
#define	I2S_TCR4_FPACK(x)
#define	I2S_TCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_TCR4_FCOMB_SHIFT   (26U)
#define	I2S_TCR4_FCOMB(x)
#define	I2S_TCR4_FCONT_MASK   (0x10000000U)
#define	I2S_TCR4_FCONT_SHIFT   (28U)
#define	I2S_TCR4_FCONT(x)
TCR5 - Transmit Configuration 5
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)
TDR - Transmit Data
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)
#define	LPSPI_TDR_DATA_MASK   (0xFFFFFFFFU)
#define	LPSPI_TDR_DATA_SHIFT   (0U)
#define	LPSPI_TDR_DATA(x)
TFR - Transmit FIFO
#define	I2S_TFR_RFP_MASK   (0x3FU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)
#define	I2S_TFR_WFP_MASK   (0x3F0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)
#define	I2S_TFR_WCP_MASK   (0x80000000U)
#define	I2S_TFR_WCP_SHIFT   (31U)
#define	I2S_TFR_WCP(x)
TMR - Transmit Mask
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)
RCSR - Receive Control
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)
RCR1 - Receive Configuration 1
#define	I2S_RCR1_RFW_MASK   (0x1FU)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)
RCR2 - Receive Configuration 2
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)
#define	I2S_RCR2_BYP_MASK   (0x800000U)
#define	I2S_RCR2_BYP_SHIFT   (23U)
#define	I2S_RCR2_BYP(x)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)
#define	I2S_RCR2_SYNC_MASK   (0x40000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)
RCR3 - Receive Configuration 3
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)
#define	I2S_RCR3_RCE_MASK   (0xF0000U)
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)
#define	I2S_RCR3_CFR_MASK   (0xF000000U)
#define	I2S_RCR3_CFR_SHIFT   (24U)
#define	I2S_RCR3_CFR(x)
RCR4 - Receive Configuration 4
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)
#define	I2S_RCR4_ONDEM_MASK   (0x4U)
#define	I2S_RCR4_ONDEM_SHIFT   (2U)
#define	I2S_RCR4_ONDEM(x)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)
#define	I2S_RCR4_FPACK_MASK   (0x3000000U)
#define	I2S_RCR4_FPACK_SHIFT   (24U)
#define	I2S_RCR4_FPACK(x)
#define	I2S_RCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_RCR4_FCOMB_SHIFT   (26U)
#define	I2S_RCR4_FCOMB(x)
#define	I2S_RCR4_FCONT_MASK   (0x10000000U)
#define	I2S_RCR4_FCONT_SHIFT   (28U)
#define	I2S_RCR4_FCONT(x)
RCR5 - Receive Configuration 5
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)
RDR - Receive Data
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)
#define	LPSPI_RDR_DATA_MASK   (0xFFFFFFFFU)
#define	LPSPI_RDR_DATA_SHIFT   (0U)
#define	LPSPI_RDR_DATA(x)
RFR - Receive FIFO
#define	I2S_RFR_RFP_MASK   (0x3FU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)
#define	I2S_RFR_RCP_MASK   (0x8000U)
#define	I2S_RFR_RCP_SHIFT   (15U)
#define	I2S_RFR_RCP(x)
#define	I2S_RFR_WFP_MASK   (0x3F0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)
RMR - Receive Mask
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)
GCFG - IEE Global Configuration
#define	IEE_GCFG_RL0_MASK   (0x1U)
#define	IEE_GCFG_RL0_SHIFT   (0U)
#define	IEE_GCFG_RL0(x)
#define	IEE_GCFG_RL1_MASK   (0x2U)
#define	IEE_GCFG_RL1_SHIFT   (1U)
#define	IEE_GCFG_RL1(x)
#define	IEE_GCFG_RL2_MASK   (0x4U)
#define	IEE_GCFG_RL2_SHIFT   (2U)
#define	IEE_GCFG_RL2(x)
#define	IEE_GCFG_RL3_MASK   (0x8U)
#define	IEE_GCFG_RL3_SHIFT   (3U)
#define	IEE_GCFG_RL3(x)
#define	IEE_GCFG_RL4_MASK   (0x10U)
#define	IEE_GCFG_RL4_SHIFT   (4U)
#define	IEE_GCFG_RL4(x)
#define	IEE_GCFG_RL5_MASK   (0x20U)
#define	IEE_GCFG_RL5_SHIFT   (5U)
#define	IEE_GCFG_RL5(x)
#define	IEE_GCFG_RL6_MASK   (0x40U)
#define	IEE_GCFG_RL6_SHIFT   (6U)
#define	IEE_GCFG_RL6(x)
#define	IEE_GCFG_RL7_MASK   (0x80U)
#define	IEE_GCFG_RL7_SHIFT   (7U)
#define	IEE_GCFG_RL7(x)
#define	IEE_GCFG_TME_MASK   (0x10000U)
#define	IEE_GCFG_TME_SHIFT   (16U)
#define	IEE_GCFG_TME(x)
#define	IEE_GCFG_TMD_MASK   (0x20000U)
#define	IEE_GCFG_TMD_SHIFT   (17U)
#define	IEE_GCFG_TMD(x)
#define	IEE_GCFG_KEY_RD_DIS_MASK   (0x2000000U)
#define	IEE_GCFG_KEY_RD_DIS_SHIFT   (25U)
#define	IEE_GCFG_KEY_RD_DIS(x)
#define	IEE_GCFG_MON_EN_MASK   (0x10000000U)
#define	IEE_GCFG_MON_EN_SHIFT   (28U)
#define	IEE_GCFG_MON_EN(x)
#define	IEE_GCFG_CLR_MON_MASK   (0x20000000U)
#define	IEE_GCFG_CLR_MON_SHIFT   (29U)
#define	IEE_GCFG_CLR_MON(x)
#define	IEE_GCFG_RST_MASK   (0x80000000U)
#define	IEE_GCFG_RST_SHIFT   (31U)
#define	IEE_GCFG_RST(x)
STA - IEE Status
#define	IEE_STA_DSR_MASK   (0x1U)
#define	IEE_STA_DSR_SHIFT   (0U)
#define	IEE_STA_DSR(x)
#define	IEE_STA_AFD_MASK   (0x10U)
#define	IEE_STA_AFD_SHIFT   (4U)
#define	IEE_STA_AFD(x)
TSTMD - IEE Test Mode Register
#define	IEE_TSTMD_TMRDY_MASK   (0x1U)
#define	IEE_TSTMD_TMRDY_SHIFT   (0U)
#define	IEE_TSTMD_TMRDY(x)
#define	IEE_TSTMD_TMR_MASK   (0x2U)
#define	IEE_TSTMD_TMR_SHIFT   (1U)
#define	IEE_TSTMD_TMR(x)
#define	IEE_TSTMD_TMENCR_MASK   (0x4U)
#define	IEE_TSTMD_TMENCR_SHIFT   (2U)
#define	IEE_TSTMD_TMENCR(x)
#define	IEE_TSTMD_TMCONT_MASK   (0x8U)
#define	IEE_TSTMD_TMCONT_SHIFT   (3U)
#define	IEE_TSTMD_TMCONT(x)
#define	IEE_TSTMD_TMDONE_MASK   (0x10U)
#define	IEE_TSTMD_TMDONE_SHIFT   (4U)
#define	IEE_TSTMD_TMDONE(x)
#define	IEE_TSTMD_TMLEN_MASK   (0xF00U)
#define	IEE_TSTMD_TMLEN_SHIFT   (8U)
#define	IEE_TSTMD_TMLEN(x)
DPAMS - AES Mask Generation Seed
#define	IEE_DPAMS_DPAMS_MASK   (0xFFFFFFFFU)
#define	IEE_DPAMS_DPAMS_SHIFT   (0U)
#define	IEE_DPAMS_DPAMS(x)
PC_S_LT - Performance Counter, AES Slave Latency Threshold Value
#define	IEE_PC_S_LT_SW_LT_MASK   (0xFFFFU)
#define	IEE_PC_S_LT_SW_LT_SHIFT   (0U)
#define	IEE_PC_S_LT_SW_LT(x)
#define	IEE_PC_S_LT_SR_LT_MASK   (0xFFFF0000U)
#define	IEE_PC_S_LT_SR_LT_SHIFT   (16U)
#define	IEE_PC_S_LT_SR_LT(x)
PC_M_LT - Performance Counter, AES Master Latency Threshold
#define	IEE_PC_M_LT_MW_LT_MASK   (0xFFFU)
#define	IEE_PC_M_LT_MW_LT_SHIFT   (0U)
#define	IEE_PC_M_LT_MW_LT(x)
#define	IEE_PC_M_LT_MR_LT_MASK   (0xFFF0000U)
#define	IEE_PC_M_LT_MR_LT_SHIFT   (16U)
#define	IEE_PC_M_LT_MR_LT(x)
PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions
#define	IEE_PC_BLK_ENC_BLK_ENC_MASK   (0xFFFFFFFFU)
#define	IEE_PC_BLK_ENC_BLK_ENC_SHIFT   (0U)
#define	IEE_PC_BLK_ENC_BLK_ENC(x)
PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions
#define	IEE_PC_BLK_DEC_BLK_DEC_MASK   (0xFFFFFFFFU)
#define	IEE_PC_BLK_DEC_BLK_DEC_SHIFT   (0U)
#define	IEE_PC_BLK_DEC_BLK_DEC(x)
PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions
#define	IEE_PC_SR_TRANS_SR_TRANS_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SR_TRANS_SR_TRANS_SHIFT   (0U)
#define	IEE_PC_SR_TRANS_SR_TRANS(x)
PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions
#define	IEE_PC_SW_TRANS_SW_TRANS_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SW_TRANS_SW_TRANS_SHIFT   (0U)
#define	IEE_PC_SW_TRANS_SW_TRANS(x)
PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions
#define	IEE_PC_MR_TRANS_MR_TRANS_MASK   (0xFFFFFFFFU)
#define	IEE_PC_MR_TRANS_MR_TRANS_SHIFT   (0U)
#define	IEE_PC_MR_TRANS_MR_TRANS(x)
PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions
#define	IEE_PC_MW_TRANS_MW_TRANS_MASK   (0xFFFFFFFFU)
#define	IEE_PC_MW_TRANS_MW_TRANS_SHIFT   (0U)
#define	IEE_PC_MW_TRANS_MW_TRANS(x)
PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions
#define	IEE_PC_M_MBR_M_MBR_MASK   (0xFFFFFFFFU)
#define	IEE_PC_M_MBR_M_MBR_SHIFT   (0U)
#define	IEE_PC_M_MBR_M_MBR(x)
PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count
#define	IEE_PC_SR_TBC_U_SR_TBC_MASK   (0xFFFFU)
#define	IEE_PC_SR_TBC_U_SR_TBC_SHIFT   (0U)
#define	IEE_PC_SR_TBC_U_SR_TBC(x)
PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count
#define	IEE_PC_SR_TBC_L_SR_TBC_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SR_TBC_L_SR_TBC_SHIFT   (0U)
#define	IEE_PC_SR_TBC_L_SR_TBC(x)
PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count
#define	IEE_PC_SW_TBC_U_SW_TBC_MASK   (0xFFFFU)
#define	IEE_PC_SW_TBC_U_SW_TBC_SHIFT   (0U)
#define	IEE_PC_SW_TBC_U_SW_TBC(x)
PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count
#define	IEE_PC_SW_TBC_L_SW_TBC_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SW_TBC_L_SW_TBC_SHIFT   (0U)
#define	IEE_PC_SW_TBC_L_SW_TBC(x)
PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count
#define	IEE_PC_MR_TBC_U_MR_TBC_MASK   (0xFFFFU)
#define	IEE_PC_MR_TBC_U_MR_TBC_SHIFT   (0U)
#define	IEE_PC_MR_TBC_U_MR_TBC(x)
PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count
#define	IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK   (0xFU)
#define	IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT   (0U)
#define	IEE_PC_MR_TBC_L_MR_TBC_LSB(x)
#define	IEE_PC_MR_TBC_L_MR_TBC_MASK   (0xFFFFFFF0U)
#define	IEE_PC_MR_TBC_L_MR_TBC_SHIFT   (4U)
#define	IEE_PC_MR_TBC_L_MR_TBC(x)
PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count
#define	IEE_PC_MW_TBC_U_MW_TBC_MASK   (0xFFFFU)
#define	IEE_PC_MW_TBC_U_MW_TBC_SHIFT   (0U)
#define	IEE_PC_MW_TBC_U_MW_TBC(x)
PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count
#define	IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK   (0xFU)
#define	IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT   (0U)
#define	IEE_PC_MW_TBC_L_MW_TBC_LSB(x)
#define	IEE_PC_MW_TBC_L_MW_TBC_MASK   (0xFFFFFFF0U)
#define	IEE_PC_MW_TBC_L_MW_TBC_SHIFT   (4U)
#define	IEE_PC_MW_TBC_L_MW_TBC(x)
PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold
#define	IEE_PC_SR_TLGTT_SR_TLGTT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT   (0U)
#define	IEE_PC_SR_TLGTT_SR_TLGTT(x)
PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold
#define	IEE_PC_SW_TLGTT_SW_TLGTT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT   (0U)
#define	IEE_PC_SW_TLGTT_SW_TLGTT(x)
PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold
#define	IEE_PC_MR_TLGTT_MR_TLGTT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT   (0U)
#define	IEE_PC_MR_TLGTT_MR_TLGTT(x)
PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold
#define	IEE_PC_MW_TLGTT_MW_TGTT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_MW_TLGTT_MW_TGTT_SHIFT   (0U)
#define	IEE_PC_MW_TLGTT_MW_TGTT(x)
PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count
#define	IEE_PC_SR_TLAT_U_SR_TLAT_MASK   (0xFFFFU)
#define	IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT   (0U)
#define	IEE_PC_SR_TLAT_U_SR_TLAT(x)
PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count
#define	IEE_PC_SR_TLAT_L_SR_TLAT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT   (0U)
#define	IEE_PC_SR_TLAT_L_SR_TLAT(x)
PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count
#define	IEE_PC_SW_TLAT_U_SW_TLAT_MASK   (0xFFFFU)
#define	IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT   (0U)
#define	IEE_PC_SW_TLAT_U_SW_TLAT(x)
PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count
#define	IEE_PC_SW_TLAT_L_SW_TLAT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT   (0U)
#define	IEE_PC_SW_TLAT_L_SW_TLAT(x)
PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count
#define	IEE_PC_MR_TLAT_U_MR_TLAT_MASK   (0xFFFFU)
#define	IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT   (0U)
#define	IEE_PC_MR_TLAT_U_MR_TLAT(x)
PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count
#define	IEE_PC_MR_TLAT_L_MR_TLAT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT   (0U)
#define	IEE_PC_MR_TLAT_L_MR_TLAT(x)
PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count
#define	IEE_PC_MW_TLAT_U_MW_TLAT_MASK   (0xFFFFU)
#define	IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT   (0U)
#define	IEE_PC_MW_TLAT_U_MW_TLAT(x)
PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count
#define	IEE_PC_MW_TLAT_L_MW_TLAT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT   (0U)
#define	IEE_PC_MW_TLAT_L_MW_TLAT(x)
PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time
#define	IEE_PC_SR_TNRT_U_SR_TNRT_MASK   (0xFFFFU)
#define	IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT   (0U)
#define	IEE_PC_SR_TNRT_U_SR_TNRT(x)
PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time
#define	IEE_PC_SR_TNRT_L_SR_TNRT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT   (0U)
#define	IEE_PC_SR_TNRT_L_SR_TNRT(x)
PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time
#define	IEE_PC_SW_TNRT_U_SW_TNRT_MASK   (0xFFFFU)
#define	IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT   (0U)
#define	IEE_PC_SW_TNRT_U_SW_TNRT(x)
PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time
#define	IEE_PC_SW_TNRT_L_SW_TNRT_MASK   (0xFFFFFFFFU)
#define	IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT   (0U)
#define	IEE_PC_SW_TNRT_L_SW_TNRT(x)
VIDR1 - IEE Version ID Register 1
#define	IEE_VIDR1_MIN_REV_MASK   (0xFFU)
#define	IEE_VIDR1_MIN_REV_SHIFT   (0U)
#define	IEE_VIDR1_MIN_REV(x)
#define	IEE_VIDR1_MAJ_REV_MASK   (0xFF00U)
#define	IEE_VIDR1_MAJ_REV_SHIFT   (8U)
#define	IEE_VIDR1_MAJ_REV(x)
#define	IEE_VIDR1_IP_ID_MASK   (0xFFFF0000U)
#define	IEE_VIDR1_IP_ID_SHIFT   (16U)
#define	IEE_VIDR1_IP_ID(x)
AESVID - IEE AES Version ID Register
#define	IEE_AESVID_AESRN_MASK   (0xFU)
#define	IEE_AESVID_AESRN_SHIFT   (0U)
#define	IEE_AESVID_AESRN(x)
#define	IEE_AESVID_AESVID_MASK   (0xF0U)
#define	IEE_AESVID_AESVID_SHIFT   (4U)
#define	IEE_AESVID_AESVID(x)
REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register.
#define	IEE_REGATTR_KS_MASK   (0x1U)
#define	IEE_REGATTR_KS_SHIFT   (0U)
#define	IEE_REGATTR_KS(x)
#define	IEE_REGATTR_MD_MASK   (0x70U)
#define	IEE_REGATTR_MD_SHIFT   (4U)
#define	IEE_REGATTR_MD(x)
#define	IEE_REGATTR_BYP_MASK   (0x80U)
#define	IEE_REGATTR_BYP_SHIFT   (7U)
#define	IEE_REGATTR_BYP(x)
REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register
#define	IEE_REGPO_PGOFF_MASK   (0xFFFFFFU)
#define	IEE_REGPO_PGOFF_SHIFT   (0U)
#define	IEE_REGPO_PGOFF(x)
REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register
#define	IEE_REGKEY1_KEY1_MASK   (0xFFFFFFFFU)
#define	IEE_REGKEY1_KEY1_SHIFT   (0U)
#define	IEE_REGKEY1_KEY1(x)
REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register
#define	IEE_REGKEY2_KEY2_MASK   (0xFFFFFFFFU)
#define	IEE_REGKEY2_KEY2_SHIFT   (0U)
#define	IEE_REGKEY2_KEY2(x)
AES_TST_DB - IEE AES Test Mode Data Buffer
#define	IEE_AES_TST_DB_AES_TST_DB0_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB0_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB0(x)
#define	IEE_AES_TST_DB_AES_TST_DB1_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB1_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB1(x)
#define	IEE_AES_TST_DB_AES_TST_DB2_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB2_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB2(x)
#define	IEE_AES_TST_DB_AES_TST_DB3_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB3_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB3(x)
#define	IEE_AES_TST_DB_AES_TST_DB4_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB4_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB4(x)
#define	IEE_AES_TST_DB_AES_TST_DB5_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB5_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB5(x)
#define	IEE_AES_TST_DB_AES_TST_DB6_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB6_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB6(x)
#define	IEE_AES_TST_DB_AES_TST_DB7_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB7_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB7(x)
#define	IEE_AES_TST_DB_AES_TST_DB8_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB8_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB8(x)
#define	IEE_AES_TST_DB_AES_TST_DB9_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB9_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB9(x)
#define	IEE_AES_TST_DB_AES_TST_DB10_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB10_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB10(x)
#define	IEE_AES_TST_DB_AES_TST_DB11_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB11_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB11(x)
#define	IEE_AES_TST_DB_AES_TST_DB12_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB12_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB12(x)
#define	IEE_AES_TST_DB_AES_TST_DB13_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB13_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB13(x)
#define	IEE_AES_TST_DB_AES_TST_DB14_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB14_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB14(x)
#define	IEE_AES_TST_DB_AES_TST_DB15_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB15_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB15(x)
#define	IEE_AES_TST_DB_AES_TST_DB16_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB16_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB16(x)
#define	IEE_AES_TST_DB_AES_TST_DB17_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB17_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB17(x)
#define	IEE_AES_TST_DB_AES_TST_DB18_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB18_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB18(x)
#define	IEE_AES_TST_DB_AES_TST_DB19_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB19_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB19(x)
#define	IEE_AES_TST_DB_AES_TST_DB20_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB20_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB20(x)
#define	IEE_AES_TST_DB_AES_TST_DB21_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB21_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB21(x)
#define	IEE_AES_TST_DB_AES_TST_DB22_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB22_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB22(x)
#define	IEE_AES_TST_DB_AES_TST_DB23_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB23_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB23(x)
#define	IEE_AES_TST_DB_AES_TST_DB24_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB24_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB24(x)
#define	IEE_AES_TST_DB_AES_TST_DB25_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB25_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB25(x)
#define	IEE_AES_TST_DB_AES_TST_DB26_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB26_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB26(x)
#define	IEE_AES_TST_DB_AES_TST_DB27_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB27_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB27(x)
#define	IEE_AES_TST_DB_AES_TST_DB28_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB28_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB28(x)
#define	IEE_AES_TST_DB_AES_TST_DB29_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB29_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB29(x)
#define	IEE_AES_TST_DB_AES_TST_DB30_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB30_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB30(x)
#define	IEE_AES_TST_DB_AES_TST_DB31_MASK   (0xFFFFFFFFU)
#define	IEE_AES_TST_DB_AES_TST_DB31_SHIFT   (0U)
#define	IEE_AES_TST_DB_AES_TST_DB31(x)
REGION0_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x)
REGION0_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x)
REGION0_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x)
REGION0_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x)
REGION1_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x)
REGION1_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x)
REGION1_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x)
REGION1_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x)
REGION2_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x)
REGION2_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x)
REGION2_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x)
REGION2_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x)
REGION3_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x)
REGION3_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x)
REGION3_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x)
REGION3_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x)
REGION4_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x)
REGION4_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x)
REGION4_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x)
REGION4_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x)
REGION5_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x)
REGION5_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x)
REGION5_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x)
REGION5_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x)
REGION6_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x)
REGION6_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x)
REGION6_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x)
REGION6_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x)
REGION7_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x)
REGION7_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT   (0U)
#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x)
REGION7_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x)
REGION7_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK   (0x1U)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT   (0U)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK   (0x2U)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT   (1U)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x)
SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK   (0xFU)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_MASK   (0x10U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT   (4U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION(x)
SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_MASK   (0x1U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT   (0U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE(x)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_MASK   (0x2U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT   (1U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE(x)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK   (0x2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT   (1U)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV(x)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_MASK   (0x4U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT   (2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE(x)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL_MASK   (0xCU)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT   (2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL(x)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_MASK   (0x8U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT   (3U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS(x)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_MASK   (0x10U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT   (4U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE(x)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_MASK   (0x30000000U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT   (28U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP(x)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)
SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register
#define	IOMUXC_SELECT_INPUT_DAISY_MASK   (0x3U)
#define	IOMUXC_SELECT_INPUT_DAISY_SHIFT   (0U)
#define	IOMUXC_SELECT_INPUT_DAISY(x)
GPR0 - GPR0 General Purpose Register
#define	IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK   (0x7U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK   (0x38U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT   (3U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK   (0xC0U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT   (6U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK   (0x100U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT   (8U)
#define	IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x)
#define	IOMUXC_GPR_GPR0_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR0_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR0_DWP(x)
#define	IOMUXC_GPR_GPR0_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR0_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK   (0xFFF8U)
#define	IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x)
#define	IOMUXC_LPSR_GPR_GPR0_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR0_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x)
GPR1 - GPR1 General Purpose Register
#define	IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK   (0x3U)
#define	IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)
#define	IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK   (0x100U)
#define	IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT   (8U)
#define	IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)
#define	IOMUXC_GPR_GPR1_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR1_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR1_DWP(x)
#define	IOMUXC_GPR_GPR1_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR1_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK   (0xFFFFU)
#define	IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x)
#define	IOMUXC_LPSR_GPR_GPR1_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR1_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x)
GPR2 - GPR2 General Purpose Register
#define	IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK   (0x3U)
#define	IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x)
#define	IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK   (0x100U)
#define	IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT   (8U)
#define	IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x)
#define	IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK   (0x200U)
#define	IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT   (9U)
#define	IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x)
#define	IOMUXC_GPR_GPR2_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR2_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR2_DWP(x)
#define	IOMUXC_GPR_GPR2_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR2_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR2_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR2_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x)
GPR3 - GPR3 General Purpose Register
#define	IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK   (0xFFU)
#define	IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT   (0U)
#define	IOMUXC_GPR_GPR3_MQS_CLK_DIV(x)
#define	IOMUXC_GPR_GPR3_MQS_SW_RST_MASK   (0x100U)
#define	IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT   (8U)
#define	IOMUXC_GPR_GPR3_MQS_SW_RST(x)
#define	IOMUXC_GPR_GPR3_MQS_EN_MASK   (0x200U)
#define	IOMUXC_GPR_GPR3_MQS_EN_SHIFT   (9U)
#define	IOMUXC_GPR_GPR3_MQS_EN(x)
#define	IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK   (0x400U)
#define	IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT   (10U)
#define	IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x)
#define	IOMUXC_GPR_GPR3_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR3_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR3_DWP(x)
#define	IOMUXC_GPR_GPR3_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR3_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR3_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR3_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x)
GPR4 - GPR4 General Purpose Register
#define	IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x)
#define	IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK   (0x2U)
#define	IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT   (1U)
#define	IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x)
#define	IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK   (0x4U)
#define	IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT   (2U)
#define	IOMUXC_GPR_GPR4_ENET_TIME_SEL(x)
#define	IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK   (0x8U)
#define	IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT   (3U)
#define	IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x)
#define	IOMUXC_GPR_GPR4_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR4_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR4_DWP(x)
#define	IOMUXC_GPR_GPR4_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR4_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR4_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR4_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x)
GPR5 - GPR5 General Purpose Register
#define	IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x)
#define	IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK   (0x2U)
#define	IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT   (1U)
#define	IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x)
#define	IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK   (0x4U)
#define	IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT   (2U)
#define	IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x)
#define	IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK   (0x8U)
#define	IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT   (3U)
#define	IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x)
#define	IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK   (0x10U)
#define	IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT   (4U)
#define	IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x)
#define	IOMUXC_GPR_GPR5_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR5_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR5_DWP(x)
#define	IOMUXC_GPR_GPR5_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR5_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR5_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR5_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x)
GPR7 - GPR7 General Purpose Register
#define	IOMUXC_GPR_GPR7_GINT_MASK   (0x1U)
#define	IOMUXC_GPR_GPR7_GINT_SHIFT   (0U)
#define	IOMUXC_GPR_GPR7_GINT(x)
#define	IOMUXC_GPR_GPR7_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR7_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR7_DWP(x)
#define	IOMUXC_GPR_GPR7_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR7_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR7_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR7_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x)
GPR8 - GPR8 General Purpose Register
#define	IOMUXC_GPR_GPR8_WDOG1_MASK_MASK   (0x1U)
#define	IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT   (0U)
#define	IOMUXC_GPR_GPR8_WDOG1_MASK(x)
#define	IOMUXC_GPR_GPR8_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR8_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR8_DWP(x)
#define	IOMUXC_GPR_GPR8_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR8_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR8_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR8_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x)
GPR9 - GPR9 General Purpose Register
#define	IOMUXC_GPR_GPR9_WDOG2_MASK_MASK   (0x1U)
#define	IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT   (0U)
#define	IOMUXC_GPR_GPR9_WDOG2_MASK(x)
#define	IOMUXC_GPR_GPR9_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR9_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR9_DWP(x)
#define	IOMUXC_GPR_GPR9_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR9_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR9_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR9_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x)
GPR10 - GPR10 General Purpose Register
#define	IOMUXC_GPR_GPR10_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR10_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR10_DWP(x)
#define	IOMUXC_GPR_GPR10_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR10_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR10_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR10_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x)
GPR11 - GPR11 General Purpose Register
#define	IOMUXC_GPR_GPR11_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR11_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR11_DWP(x)
#define	IOMUXC_GPR_GPR11_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR11_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR11_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR11_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x)
GPR12 - GPR12 General Purpose Register
#define	IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK   (0x100U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT   (8U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK   (0x200U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT   (9U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK   (0x400U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT   (10U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK   (0x800U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT   (11U)
#define	IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR12_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR12_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR12_DWP(x)
#define	IOMUXC_GPR_GPR12_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR12_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR12_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR12_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x)
GPR13 - GPR13 General Purpose Register
#define	IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK   (0x100U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT   (8U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK   (0x200U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT   (9U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK   (0x400U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT   (10U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK   (0x800U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT   (11U)
#define	IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR13_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR13_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR13_DWP(x)
#define	IOMUXC_GPR_GPR13_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR13_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR13_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR13_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x)
GPR14 - GPR14 General Purpose Register
#define	IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK   (0x100U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT   (8U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK   (0x200U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT   (9U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK   (0x400U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT   (10U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK   (0x800U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT   (11U)
#define	IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR14_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR14_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR14_DWP(x)
#define	IOMUXC_GPR_GPR14_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR14_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR14_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR14_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x)
GPR15 - GPR15 General Purpose Register
#define	IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK   (0x100U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT   (8U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK   (0x200U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT   (9U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK   (0x400U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT   (10U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK   (0x800U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT   (11U)
#define	IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x)
#define	IOMUXC_GPR_GPR15_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR15_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR15_DWP(x)
#define	IOMUXC_GPR_GPR15_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR15_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR15_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR15_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x)
GPR16 - GPR16 General Purpose Register
#define	IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK   (0x4U)
#define	IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT   (2U)
#define	IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x)
#define	IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x)
#define	IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK   (0x20U)
#define	IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT   (5U)
#define	IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x)
#define	IOMUXC_GPR_GPR16_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR16_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR16_DWP(x)
#define	IOMUXC_GPR_GPR16_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR16_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR16_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR16_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x)
GPR17 - GPR17 General Purpose Register
#define	IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK   (0xFFFFU)
#define	IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT   (0U)
#define	IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x)
#define	IOMUXC_GPR_GPR17_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR17_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR17_DWP(x)
#define	IOMUXC_GPR_GPR17_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR17_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR17_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR17_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x)
GPR18 - GPR18 General Purpose Register
#define	IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK   (0xFFFFU)
#define	IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT   (0U)
#define	IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x)
#define	IOMUXC_GPR_GPR18_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR18_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR18_DWP(x)
#define	IOMUXC_GPR_GPR18_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR18_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR18_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR18_LOCK(x)
GPR20 - GPR20 General Purpose Register
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK   (0x1U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT   (0U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK   (0x2U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT   (1U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK   (0x4U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT   (2U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK   (0x8U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT   (3U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK   (0x10U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT   (4U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK   (0x20U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT   (5U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK   (0x40U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT   (6U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK   (0x80U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT   (7U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK   (0x100U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT   (8U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK   (0x200U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT   (9U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK   (0x400U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT   (10U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK   (0x800U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT   (11U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT   (12U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT   (13U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT   (14U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT   (15U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT   (16U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT   (17U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT   (18U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT   (19U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT   (20U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK   (0x200000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT   (21U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK   (0x400000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT   (22U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK   (0x800000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT   (23U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK   (0x1000000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT   (24U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK   (0x2000000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT   (25U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK   (0x4000000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT   (26U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK   (0x8000000U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT   (27U)
#define	IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x)
#define	IOMUXC_GPR_GPR20_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR20_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR20_DWP(x)
#define	IOMUXC_GPR_GPR20_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR20_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR20_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR20_LOCK(x)
GPR21 - GPR21 General Purpose Register
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK   (0x1U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT   (0U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK   (0x2U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT   (1U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK   (0x4U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT   (2U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK   (0x8U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT   (3U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK   (0x10U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT   (4U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK   (0x20U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT   (5U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK   (0x40U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT   (6U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK   (0x80U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT   (7U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK   (0x100U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT   (8U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK   (0x200U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT   (9U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK   (0x400U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT   (10U)
#define	IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x)
#define	IOMUXC_GPR_GPR21_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR21_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR21_DWP(x)
#define	IOMUXC_GPR_GPR21_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR21_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR21_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR21_LOCK(x)
GPR22 - GPR22 General Purpose Register
#define	IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK   (0x1U)
#define	IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT   (0U)
#define	IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x)
#define	IOMUXC_GPR_GPR22_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR22_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR22_DWP(x)
#define	IOMUXC_GPR_GPR22_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR22_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR22_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR22_LOCK(x)
GPR23 - GPR23 General Purpose Register
#define	IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK   (0x1U)
#define	IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT   (0U)
#define	IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x)
#define	IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK   (0x2U)
#define	IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT   (1U)
#define	IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x)
#define	IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK   (0x4U)
#define	IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT   (2U)
#define	IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x)
#define	IOMUXC_GPR_GPR23_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR23_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR23_DWP(x)
#define	IOMUXC_GPR_GPR23_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR23_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR23_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR23_LOCK(x)
GPR24 - GPR24 General Purpose Register
#define	IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK   (0x1U)
#define	IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT   (0U)
#define	IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x)
#define	IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK   (0x2U)
#define	IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT   (1U)
#define	IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x)
#define	IOMUXC_GPR_GPR24_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR24_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR24_DWP(x)
#define	IOMUXC_GPR_GPR24_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR24_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR24_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR24_LOCK(x)
GPR25 - GPR25 General Purpose Register
#define	IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK   (0x1U)
#define	IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT   (0U)
#define	IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x)
#define	IOMUXC_GPR_GPR25_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR25_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR25_DWP(x)
#define	IOMUXC_GPR_GPR25_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR25_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR25_APC_VALID(x)
#define	IOMUXC_LPSR_GPR_GPR25_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR25_LOCK(x)
GPR26 - GPR26 General Purpose Register
#define	IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK   (0x1U)
#define	IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT   (0U)
#define	IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x)
#define	IOMUXC_GPR_GPR26_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR26_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR26_DWP(x)
#define	IOMUXC_GPR_GPR26_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR26_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK   (0x1FFFFFFU)
#define	IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x)
#define	IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK   (0xE000000U)
#define	IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT   (25U)
#define	IOMUXC_LPSR_GPR_GPR26_FIELD_0(x)
#define	IOMUXC_LPSR_GPR_GPR26_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR26_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x)
GPR27 - GPR27 General Purpose Register
#define	IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK   (0x1U)
#define	IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT   (0U)
#define	IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x)
#define	IOMUXC_GPR_GPR27_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR27_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR27_DWP(x)
#define	IOMUXC_GPR_GPR27_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR27_DWP_LOCK(x)
GPR28 - GPR28 General Purpose Register
#define	IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK   (0x1U)
#define	IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT   (0U)
#define	IOMUXC_GPR_GPR28_ARCACHE_USDHC(x)
#define	IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK   (0x2U)
#define	IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT   (1U)
#define	IOMUXC_GPR_GPR28_AWCACHE_USDHC(x)
#define	IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK   (0x20U)
#define	IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT   (5U)
#define	IOMUXC_GPR_GPR28_CACHE_ENET1G(x)
#define	IOMUXC_GPR_GPR28_CACHE_ENET_MASK   (0x80U)
#define	IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT   (7U)
#define	IOMUXC_GPR_GPR28_CACHE_ENET(x)
#define	IOMUXC_GPR_GPR28_CACHE_USB_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR28_CACHE_USB_SHIFT   (13U)
#define	IOMUXC_GPR_GPR28_CACHE_USB(x)
#define	IOMUXC_GPR_GPR28_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR28_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR28_DWP(x)
#define	IOMUXC_GPR_GPR28_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR28_DWP_LOCK(x)
GPR29 - GPR29 General Purpose Register
#define	IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x)
#define	IOMUXC_GPR_GPR29_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR29_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR29_DWP(x)
#define	IOMUXC_GPR_GPR29_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR29_DWP_LOCK(x)
GPR30 - GPR30 General Purpose Register
#define	IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x)
#define	IOMUXC_GPR_GPR30_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR30_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR30_DWP(x)
#define	IOMUXC_GPR_GPR30_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR30_DWP_LOCK(x)
GPR31 - GPR31 General Purpose Register
#define	IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x)
#define	IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK   (0x4U)
#define	IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT   (2U)
#define	IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x)
#define	IOMUXC_GPR_GPR31_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR31_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR31_DWP(x)
#define	IOMUXC_GPR_GPR31_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR31_DWP_LOCK(x)
GPR32 - GPR32 General Purpose Register
#define	IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x)
#define	IOMUXC_GPR_GPR32_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR32_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR32_DWP(x)
#define	IOMUXC_GPR_GPR32_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR32_DWP_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR32_GPR_MASK   (0xFFFEU)
#define	IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT   (1U)
#define	IOMUXC_SNVS_GPR_GPR32_GPR(x)
#define	IOMUXC_SNVS_GPR_GPR32_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT   (16U)
#define	IOMUXC_SNVS_GPR_GPR32_LOCK(x)
GPR33 - GPR33 General Purpose Register
#define	IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x)
#define	IOMUXC_GPR_GPR33_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR33_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR33_DWP(x)
#define	IOMUXC_GPR_GPR33_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR33_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x)
#define	IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x)
#define	IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x)
#define	IOMUXC_LPSR_GPR_GPR33_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR33_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK   (0x2U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT   (1U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x)
#define	IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK   (0x4U)
#define	IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT   (2U)
#define	IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK   (0x10000U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT   (16U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK   (0x20000U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT   (17U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK   (0x40000U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT   (18U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK   (0x80000U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT   (19U)
#define	IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x)
#define	IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK   (0x100000U)
#define	IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT   (20U)
#define	IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x)
GPR34 - GPR34 General Purpose Register
#define	IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x)
#define	IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK   (0x2U)
#define	IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT   (1U)
#define	IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x)
#define	IOMUXC_GPR_GPR34_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR34_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR34_DWP(x)
#define	IOMUXC_GPR_GPR34_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR34_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x)
#define	IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x)
#define	IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x)
#define	IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x)
#define	IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x)
#define	IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x)
#define	IOMUXC_LPSR_GPR_GPR34_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR34_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR34_LOCK_MASK   (0x1U)
#define	IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT   (0U)
#define	IOMUXC_SNVS_GPR_GPR34_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK   (0x2U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT   (1U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK   (0xCU)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT   (2U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK   (0x80U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT   (7U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK   (0xFF00U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT   (8U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK   (0x30000U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT   (16U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK   (0xC0000U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT   (18U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK   (0x800000U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT   (23U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK   (0xF000000U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT   (24U)
#define	IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x)
GPR35 - GPR35 General Purpose Register
#define	IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x)
#define	IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK   (0x2U)
#define	IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT   (1U)
#define	IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x)
#define	IOMUXC_GPR_GPR35_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR35_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR35_DWP(x)
#define	IOMUXC_GPR_GPR35_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR35_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK   (0x20000U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT   (17U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK   (0x40000U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT   (18U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK   (0x80000U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT   (19U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK   (0x100000U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT   (20U)
#define	IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT   (22U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK   (0x800000U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT   (23U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK   (0x1000000U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT   (24U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK   (0x2000000U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT   (25U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK   (0x4000000U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT   (26U)
#define	IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR35_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR35_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR35_LOCK_MASK   (0x1U)
#define	IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT   (0U)
#define	IOMUXC_SNVS_GPR_GPR35_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK   (0x8U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT   (3U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK   (0xFF0U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT   (4U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK   (0x8000U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT   (15U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK   (0xFFF0000U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT   (16U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK   (0x30000000U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT   (28U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT   (30U)
#define	IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x)
GPR36 - GPR36 General Purpose Register
#define	IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK   (0x1U)
#define	IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT   (0U)
#define	IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x)
#define	IOMUXC_GPR_GPR36_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR36_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR36_DWP(x)
#define	IOMUXC_GPR_GPR36_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR36_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK   (0x4000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT   (14U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK   (0x20000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT   (17U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK   (0x40000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT   (18U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK   (0x80000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT   (19U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK   (0x100000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT   (20U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK   (0x400000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT   (22U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK   (0x800000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT   (23U)
#define	IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK   (0x1000000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT   (24U)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK   (0x2000000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT   (25U)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK   (0x4000000U)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT   (26U)
#define	IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR36_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR36_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK   (0x800000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT   (23U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK   (0x4000000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT   (26U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK   (0x8000000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT   (27U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK   (0x10000000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT   (28U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK   (0x20000000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT   (29U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK   (0x40000000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT   (30U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK   (0x80000000U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT   (31U)
#define	IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x)
GPR37 - GPR37 General Purpose Register
#define	IOMUXC_GPR_GPR37_NIDEN_MASK   (0x1U)
#define	IOMUXC_GPR_GPR37_NIDEN_SHIFT   (0U)
#define	IOMUXC_GPR_GPR37_NIDEN(x)
#define	IOMUXC_GPR_GPR37_DBG_EN_MASK   (0x2U)
#define	IOMUXC_GPR_GPR37_DBG_EN_SHIFT   (1U)
#define	IOMUXC_GPR_GPR37_DBG_EN(x)
#define	IOMUXC_GPR_GPR37_EXC_MON_MASK   (0x8U)
#define	IOMUXC_GPR_GPR37_EXC_MON_SHIFT   (3U)
#define	IOMUXC_GPR_GPR37_EXC_MON(x)
#define	IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK   (0x20U)
#define	IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT   (5U)
#define	IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x)
#define	IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK   (0x40U)
#define	IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT   (6U)
#define	IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x)
#define	IOMUXC_GPR_GPR37_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR37_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR37_DWP(x)
#define	IOMUXC_GPR_GPR37_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR37_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK   (0x4000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT   (14U)
#define	IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK   (0x20000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT   (17U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK   (0x40000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT   (18U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK   (0x80000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT   (19U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK   (0x100000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT   (20U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK   (0x400000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT   (22U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK   (0x800000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT   (23U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK   (0x1000000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT   (24U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK   (0x2000000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT   (25U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK   (0x4000000U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT   (26U)
#define	IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR37_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR37_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR37_LOCK_MASK   (0x1U)
#define	IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT   (0U)
#define	IOMUXC_SNVS_GPR_GPR37_LOCK(x)
#define	IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK   (0x7FEU)
#define	IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT   (1U)
#define	IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x)
#define	IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK   (0x1FF800U)
#define	IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT   (11U)
#define	IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x)
GPR38 - GPR38 General Purpose Register
#define	IOMUXC_GPR_GPR38_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR38_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR38_DWP(x)
#define	IOMUXC_GPR_GPR38_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR38_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK   (0x4000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT   (14U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK   (0x20000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT   (17U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK   (0x40000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT   (18U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK   (0x80000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT   (19U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK   (0x100000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT   (20U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK   (0x400000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT   (22U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK   (0x800000U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT   (23U)
#define	IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK   (0x1000000U)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT   (24U)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK   (0x2000000U)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT   (25U)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK   (0x4000000U)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT   (26U)
#define	IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x)
#define	IOMUXC_LPSR_GPR_GPR38_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR38_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x)
GPR39 - GPR39 General Purpose Register
#define	IOMUXC_GPR_GPR39_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR39_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR39_DWP(x)
#define	IOMUXC_GPR_GPR39_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR39_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x)
#define	IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK   (0x4000U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT   (14U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK   (0x20000U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT   (17U)
#define	IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x)
#define	IOMUXC_LPSR_GPR_GPR39_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR39_DWP(x)
#define	IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x)
GPR40 - GPR40 General Purpose Register
#define	IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK   (0xFFFFU)
#define	IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT   (0U)
#define	IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x)
#define	IOMUXC_GPR_GPR40_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR40_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR40_DWP(x)
#define	IOMUXC_GPR_GPR40_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR40_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK   (0x4000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT   (14U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK   (0x20000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT   (17U)
#define	IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK   (0x40000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT   (18U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK   (0x80000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT   (19U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK   (0x100000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT   (20U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK   (0x200000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT   (21U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK   (0x400000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT   (22U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK   (0x800000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT   (23U)
#define	IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK   (0x1000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT   (24U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK   (0x2000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT   (25U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK   (0x4000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT   (26U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK   (0x8000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT   (27U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK   (0x10000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT   (28U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK   (0x20000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT   (29U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK   (0x40000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT   (30U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK   (0x80000000U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT   (31U)
#define	IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x)
GPR41 - GPR41 General Purpose Register
#define	IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK   (0xFFFFU)
#define	IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT   (0U)
#define	IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x)
#define	IOMUXC_GPR_GPR41_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR41_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR41_DWP(x)
#define	IOMUXC_GPR_GPR41_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR41_DWP_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK   (0x2U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT   (1U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK   (0x4U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT   (2U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK   (0x8U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK   (0x20U)
#define	IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT   (5U)
#define	IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK   (0x40U)
#define	IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT   (6U)
#define	IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK   (0x80U)
#define	IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT   (7U)
#define	IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK   (0x100U)
#define	IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT   (8U)
#define	IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK   (0x200U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT   (9U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK   (0x400U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT   (10U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK   (0x800U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT   (11U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK   (0x1000U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT   (12U)
#define	IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK   (0x2000U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT   (13U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK   (0x4000U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT   (14U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK   (0x8000U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT   (15U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK   (0x10000U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x)
#define	IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK   (0x1000000U)
#define	IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT   (24U)
#define	IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x)
GPR42 - GPR42 General Purpose Register
#define	IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK   (0xFFFFU)
#define	IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT   (0U)
#define	IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x)
#define	IOMUXC_GPR_GPR42_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR42_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR42_DWP(x)
#define	IOMUXC_GPR_GPR42_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR42_DWP_LOCK(x)
GPR43 - GPR43 General Purpose Register
#define	IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK   (0xFFFFU)
#define	IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT   (0U)
#define	IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x)
#define	IOMUXC_GPR_GPR43_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR43_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR43_DWP(x)
#define	IOMUXC_GPR_GPR43_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR43_DWP_LOCK(x)
GPR44 - GPR44 General Purpose Register
#define	IOMUXC_GPR_GPR44_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR44_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR44_DWP(x)
#define	IOMUXC_GPR_GPR44_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR44_DWP_LOCK(x)
GPR45 - GPR45 General Purpose Register
#define	IOMUXC_GPR_GPR45_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR45_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR45_DWP(x)
#define	IOMUXC_GPR_GPR45_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR45_DWP_LOCK(x)
GPR46 - GPR46 General Purpose Register
#define	IOMUXC_GPR_GPR46_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR46_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR46_DWP(x)
#define	IOMUXC_GPR_GPR46_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR46_DWP_LOCK(x)
GPR47 - GPR47 General Purpose Register
#define	IOMUXC_GPR_GPR47_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR47_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR47_DWP(x)
#define	IOMUXC_GPR_GPR47_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR47_DWP_LOCK(x)
GPR48 - GPR48 General Purpose Register
#define	IOMUXC_GPR_GPR48_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR48_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR48_DWP(x)
#define	IOMUXC_GPR_GPR48_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR48_DWP_LOCK(x)
GPR49 - GPR49 General Purpose Register
#define	IOMUXC_GPR_GPR49_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR49_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR49_DWP(x)
#define	IOMUXC_GPR_GPR49_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR49_DWP_LOCK(x)
GPR50 - GPR50 General Purpose Register
#define	IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK   (0x1FU)
#define	IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT   (0U)
#define	IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x)
#define	IOMUXC_GPR_GPR50_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR50_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR50_DWP(x)
#define	IOMUXC_GPR_GPR50_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR50_DWP_LOCK(x)
GPR51 - GPR51 General Purpose Register
#define	IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK   (0x1U)
#define	IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT   (0U)
#define	IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x)
#define	IOMUXC_GPR_GPR51_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR51_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR51_DWP(x)
#define	IOMUXC_GPR_GPR51_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR51_DWP_LOCK(x)
GPR52 - GPR52 General Purpose Register
#define	IOMUXC_GPR_GPR52_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR52_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR52_DWP(x)
#define	IOMUXC_GPR_GPR52_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR52_DWP_LOCK(x)
GPR53 - GPR53 General Purpose Register
#define	IOMUXC_GPR_GPR53_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR53_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR53_DWP(x)
#define	IOMUXC_GPR_GPR53_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR53_DWP_LOCK(x)
GPR54 - GPR54 General Purpose Register
#define	IOMUXC_GPR_GPR54_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR54_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR54_DWP(x)
#define	IOMUXC_GPR_GPR54_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR54_DWP_LOCK(x)
GPR55 - GPR55 General Purpose Register
#define	IOMUXC_GPR_GPR55_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR55_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR55_DWP(x)
#define	IOMUXC_GPR_GPR55_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR55_DWP_LOCK(x)
GPR59 - GPR59 General Purpose Register
#define	IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK   (0x1U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT   (0U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK   (0x2U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT   (1U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK   (0x4U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT   (2U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK   (0x10U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT   (4U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK   (0xC0U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT   (6U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK   (0x300U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT   (8U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK   (0xC00U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT   (10U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK   (0x3F000U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT   (12U)
#define	IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x)
#define	IOMUXC_GPR_GPR59_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR59_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR59_DWP(x)
#define	IOMUXC_GPR_GPR59_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR59_DWP_LOCK(x)
GPR62 - GPR62 General Purpose Register
#define	IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK   (0x7U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT   (0U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK   (0x38U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT   (3U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK   (0x1C0U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT   (6U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK   (0x600U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT   (9U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK   (0x3800U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT   (11U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT   (16U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT   (17U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT   (18U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT   (19U)
#define	IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x)
#define	IOMUXC_GPR_GPR62_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR62_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR62_DWP(x)
#define	IOMUXC_GPR_GPR62_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR62_DWP_LOCK(x)
GPR63 - GPR63 General Purpose Register
#define	IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK   (0x7U)
#define	IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x)
GPR64 - GPR64 General Purpose Register
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK   (0x4U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT   (2U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK   (0xF0U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT   (4U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK   (0xF00U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT   (8U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT   (12U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT   (13U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT   (14U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT   (20U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK   (0x1E00000U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT   (21U)
#define	IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x)
#define	IOMUXC_GPR_GPR64_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR64_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR64_DWP(x)
#define	IOMUXC_GPR_GPR64_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR64_DWP_LOCK(x)
GPR65 - GPR65 General Purpose Register
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK   (0x4U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT   (2U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK   (0xF0U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT   (4U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK   (0xF00U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT   (8U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT   (12U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT   (13U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT   (14U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT   (20U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK   (0x1E00000U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT   (21U)
#define	IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x)
#define	IOMUXC_GPR_GPR65_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR65_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR65_DWP(x)
#define	IOMUXC_GPR_GPR65_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR65_DWP_LOCK(x)
GPR66 - GPR66 General Purpose Register
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK   (0x4U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT   (2U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK   (0xF0U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT   (4U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK   (0xF00U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT   (8U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT   (12U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT   (13U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT   (14U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT   (20U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK   (0x1E00000U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT   (21U)
#define	IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x)
#define	IOMUXC_GPR_GPR66_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR66_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR66_DWP(x)
#define	IOMUXC_GPR_GPR66_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR66_DWP_LOCK(x)
GPR67 - GPR67 General Purpose Register
#define	IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK   (0x4U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT   (2U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK   (0xF0U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT   (4U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK   (0xF00U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT   (8U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT   (12U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT   (13U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT   (14U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT   (20U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK   (0x1E00000U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT   (21U)
#define	IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x)
#define	IOMUXC_GPR_GPR67_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR67_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR67_DWP(x)
#define	IOMUXC_GPR_GPR67_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR67_DWP_LOCK(x)
GPR68 - GPR68 General Purpose Register
#define	IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK   (0x4U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT   (2U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK   (0x8U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT   (3U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK   (0xF0U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT   (4U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK   (0xF00U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT   (8U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT   (12U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT   (13U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT   (14U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT   (20U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK   (0x1E00000U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT   (21U)
#define	IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x)
#define	IOMUXC_GPR_GPR68_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR68_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR68_DWP(x)
#define	IOMUXC_GPR_GPR68_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR68_DWP_LOCK(x)
GPR69 - GPR69 General Purpose Register
#define	IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK   (0x2U)
#define	IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT   (1U)
#define	IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x)
#define	IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK   (0x4U)
#define	IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT   (2U)
#define	IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x)
#define	IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK   (0x10U)
#define	IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT   (4U)
#define	IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x)
#define	IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x)
#define	IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK   (0x80U)
#define	IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT   (7U)
#define	IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x)
#define	IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK   (0x100U)
#define	IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT   (8U)
#define	IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x)
#define	IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK   (0x200U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT   (9U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x)
#define	IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK   (0x400U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT   (10U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x)
#define	IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK   (0x800U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT   (11U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x)
#define	IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT   (12U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x)
#define	IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT   (13U)
#define	IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x)
#define	IOMUXC_GPR_GPR69_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR69_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR69_DWP(x)
#define	IOMUXC_GPR_GPR69_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR69_DWP_LOCK(x)
GPR70 - GPR70 General Purpose Register
#define	IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK   (0x4U)
#define	IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT   (2U)
#define	IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK   (0x10U)
#define	IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT   (4U)
#define	IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK   (0x100U)
#define	IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT   (8U)
#define	IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK   (0x200U)
#define	IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT   (9U)
#define	IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK   (0x400U)
#define	IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT   (10U)
#define	IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK   (0x800U)
#define	IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT   (11U)
#define	IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT   (15U)
#define	IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT   (17U)
#define	IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT   (18U)
#define	IOMUXC_GPR_GPR70_ENET_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT   (19U)
#define	IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT   (20U)
#define	IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
#define	IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT   (22U)
#define	IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK   (0x800000U)
#define	IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT   (23U)
#define	IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK   (0x1000000U)
#define	IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT   (24U)
#define	IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK   (0x2000000U)
#define	IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT   (25U)
#define	IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK   (0x4000000U)
#define	IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT   (26U)
#define	IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR70_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR70_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR70_DWP(x)
#define	IOMUXC_GPR_GPR70_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR70_DWP_LOCK(x)
GPR71 - GPR71 General Purpose Register
#define	IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK   (0x2U)
#define	IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT   (1U)
#define	IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK   (0x4U)
#define	IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT   (2U)
#define	IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK   (0x10U)
#define	IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT   (4U)
#define	IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK   (0x100U)
#define	IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT   (8U)
#define	IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK   (0x800U)
#define	IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT   (11U)
#define	IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT   (14U)
#define	IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT   (15U)
#define	IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT   (17U)
#define	IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT   (18U)
#define	IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT   (19U)
#define	IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT   (20U)
#define	IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK   (0x400000U)
#define	IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT   (22U)
#define	IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK   (0x800000U)
#define	IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT   (23U)
#define	IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK   (0x1000000U)
#define	IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT   (24U)
#define	IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK   (0x2000000U)
#define	IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT   (25U)
#define	IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK   (0x4000000U)
#define	IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT   (26U)
#define	IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR71_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR71_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR71_DWP(x)
#define	IOMUXC_GPR_GPR71_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR71_DWP_LOCK(x)
GPR72 - GPR72 General Purpose Register
#define	IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK   (0x4U)
#define	IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT   (2U)
#define	IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK   (0x10U)
#define	IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT   (4U)
#define	IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK   (0x100U)
#define	IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT   (8U)
#define	IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK   (0x800U)
#define	IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT   (11U)
#define	IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT   (14U)
#define	IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT   (15U)
#define	IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT   (17U)
#define	IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT   (18U)
#define	IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT   (19U)
#define	IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT   (20U)
#define	IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK   (0x400000U)
#define	IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT   (22U)
#define	IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK   (0x800000U)
#define	IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT   (23U)
#define	IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK   (0x1000000U)
#define	IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT   (24U)
#define	IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK   (0x2000000U)
#define	IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT   (25U)
#define	IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x)
#define	IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK   (0x4000000U)
#define	IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT   (26U)
#define	IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR72_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR72_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR72_DWP(x)
#define	IOMUXC_GPR_GPR72_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR72_DWP_LOCK(x)
GPR73 - GPR73 General Purpose Register
#define	IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK   (0x1U)
#define	IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT   (0U)
#define	IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK   (0x4U)
#define	IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT   (2U)
#define	IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK   (0x8U)
#define	IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT   (3U)
#define	IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK   (0x10U)
#define	IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT   (4U)
#define	IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK   (0x100U)
#define	IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT   (8U)
#define	IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK   (0x800U)
#define	IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT   (11U)
#define	IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT   (12U)
#define	IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT   (14U)
#define	IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT   (15U)
#define	IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT   (16U)
#define	IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT   (17U)
#define	IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT   (18U)
#define	IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT   (19U)
#define	IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT   (20U)
#define	IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK   (0x200000U)
#define	IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT   (21U)
#define	IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK   (0x400000U)
#define	IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT   (22U)
#define	IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK   (0x800000U)
#define	IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT   (23U)
#define	IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK   (0x1000000U)
#define	IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT   (24U)
#define	IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK   (0x2000000U)
#define	IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT   (25U)
#define	IOMUXC_GPR_GPR73_MIC_STOP_REQ(x)
#define	IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK   (0x4000000U)
#define	IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT   (26U)
#define	IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x)
#define	IOMUXC_GPR_GPR73_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR73_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR73_DWP(x)
#define	IOMUXC_GPR_GPR73_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR73_DWP_LOCK(x)
GPR74 - GPR74 General Purpose Register
#define	IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK   (0x2U)
#define	IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT   (1U)
#define	IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK   (0x4U)
#define	IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT   (2U)
#define	IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK   (0x8U)
#define	IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT   (3U)
#define	IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK   (0x10U)
#define	IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT   (4U)
#define	IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK   (0x20U)
#define	IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT   (5U)
#define	IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK   (0x40U)
#define	IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT   (6U)
#define	IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK   (0x80U)
#define	IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT   (7U)
#define	IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK   (0x100U)
#define	IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT   (8U)
#define	IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK   (0x200U)
#define	IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT   (9U)
#define	IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x)
#define	IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK   (0x400U)
#define	IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT   (10U)
#define	IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK   (0x800U)
#define	IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT   (11U)
#define	IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT   (12U)
#define	IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT   (13U)
#define	IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x)
#define	IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT   (14U)
#define	IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x)
#define	IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT   (15U)
#define	IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x)
#define	IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT   (16U)
#define	IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x)
#define	IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT   (17U)
#define	IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x)
#define	IOMUXC_GPR_GPR74_DWP_MASK   (0x30000000U)
#define	IOMUXC_GPR_GPR74_DWP_SHIFT   (28U)
#define	IOMUXC_GPR_GPR74_DWP(x)
#define	IOMUXC_GPR_GPR74_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR74_DWP_LOCK(x)
GPR75 - GPR75 General Purpose Register
#define	IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK   (0x1U)
#define	IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT   (0U)
#define	IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK   (0x2U)
#define	IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT   (1U)
#define	IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK   (0x4U)
#define	IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT   (2U)
#define	IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK   (0x8U)
#define	IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT   (3U)
#define	IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK   (0x10U)
#define	IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT   (4U)
#define	IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK   (0x20U)
#define	IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT   (5U)
#define	IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK   (0x40U)
#define	IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT   (6U)
#define	IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK   (0x80U)
#define	IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT   (7U)
#define	IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK   (0x100U)
#define	IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT   (8U)
#define	IOMUXC_GPR_GPR75_ENET_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK   (0x200U)
#define	IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT   (9U)
#define	IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK   (0x400U)
#define	IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT   (10U)
#define	IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK   (0x800U)
#define	IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT   (11U)
#define	IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT   (12U)
#define	IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT   (13U)
#define	IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT   (14U)
#define	IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT   (15U)
#define	IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT   (16U)
#define	IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK   (0x20000U)
#define	IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT   (17U)
#define	IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK   (0x40000U)
#define	IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT   (18U)
#define	IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK   (0x80000U)
#define	IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT   (19U)
#define	IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK   (0x100000U)
#define	IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT   (20U)
#define	IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK   (0x200000U)
#define	IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT   (21U)
#define	IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK   (0x400000U)
#define	IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT   (22U)
#define	IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK   (0x800000U)
#define	IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT   (23U)
#define	IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK   (0x1000000U)
#define	IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT   (24U)
#define	IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK   (0x2000000U)
#define	IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT   (25U)
#define	IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK   (0x4000000U)
#define	IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT   (26U)
#define	IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK   (0x8000000U)
#define	IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT   (27U)
#define	IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK   (0x10000000U)
#define	IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT   (28U)
#define	IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK   (0x20000000U)
#define	IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT   (29U)
#define	IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK   (0x40000000U)
#define	IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT   (30U)
#define	IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x)
#define	IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK   (0x80000000U)
#define	IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT   (31U)
#define	IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x)
GPR76 - GPR76 General Purpose Register
#define	IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK   (0x1U)
#define	IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT   (0U)
#define	IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK   (0x2U)
#define	IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT   (1U)
#define	IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK   (0x4U)
#define	IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT   (2U)
#define	IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK   (0x8U)
#define	IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT   (3U)
#define	IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK   (0x10U)
#define	IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT   (4U)
#define	IOMUXC_GPR_GPR76_MIC_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK   (0x20U)
#define	IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT   (5U)
#define	IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK   (0x40U)
#define	IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT   (6U)
#define	IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK   (0x80U)
#define	IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT   (7U)
#define	IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK   (0x100U)
#define	IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT   (8U)
#define	IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK   (0x200U)
#define	IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT   (9U)
#define	IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK   (0x400U)
#define	IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT   (10U)
#define	IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK   (0x800U)
#define	IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT   (11U)
#define	IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK   (0x1000U)
#define	IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT   (12U)
#define	IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x)
#define	IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK   (0x2000U)
#define	IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT   (13U)
#define	IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x)
#define	IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK   (0x4000U)
#define	IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT   (14U)
#define	IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x)
#define	IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK   (0x8000U)
#define	IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT   (15U)
#define	IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x)
#define	IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK   (0x10000U)
#define	IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT   (16U)
#define	IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x)
SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK   (0xFU)
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x)
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK   (0x10U)
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT   (4U)
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x)
SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK   (0x1U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT   (0U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK   (0x2U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT   (1U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK   (0x4U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT   (2U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK   (0x8U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT   (3U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK   (0x20U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT   (5U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK   (0x30000000U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT   (28U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x)
SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register
#define	IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK   (0x3U)
#define	IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT   (0U)
#define	IOMUXC_LPSR_SELECT_INPUT_DAISY(x)
GPR6 - GPR6 General Purpose Register
#define	IOMUXC_LPSR_GPR_GPR6_LOCK_MASK   (0x1U)
#define	IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT   (0U)
#define	IOMUXC_LPSR_GPR_GPR6_LOCK(x)
#define	IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)
#define	IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT   (3U)
#define	IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x)
GPR19 - GPR19 General Purpose Register
#define	IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK   (0x10U)
#define	IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT   (4U)
#define	IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x)
#define	IOMUXC_LPSR_GPR_GPR19_LOCK_MASK   (0xFFFF0000U)
#define	IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT   (16U)
#define	IOMUXC_LPSR_GPR_GPR19_LOCK(x)
SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x)
SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x)
SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x)
SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK   (0x10U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT   (4U)
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x)
SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x)
SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK   (0x1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT   (0U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK   (0x2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT   (1U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK   (0x4U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT   (2U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK   (0x8U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT   (3U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK   (0x40U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT   (6U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK   (0x30000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT   (28U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x)
GPR - GPR0 General Purpose Register
#define	IOMUXC_SNVS_GPR_GPR_GPR_MASK   (0xFFFFFFFFU)
#define	IOMUXC_SNVS_GPR_GPR_GPR_SHIFT   (0U)
#define	IOMUXC_SNVS_GPR_GPR_GPR(x)
SLOT_CTRL - Slot Control Register
#define	IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK   (0xFU)
#define	IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT   (0U)
#define	IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x)
#define	IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK   (0x8000U)
#define	IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT   (15U)
#define	IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x)
#define	IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK   (0x10000U)
#define	IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT   (16U)
#define	IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x)
#define	IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK   (0x20000U)
#define	IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT   (17U)
#define	IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x)
#define	IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
#define	IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT   (31U)
#define	IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x)
MASTER_KEY_CTRL - CSR Master Key Control Register
#define	KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK   (0x1U)
#define	KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT   (0U)
#define	KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x)
#define	KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK   (0x10000U)
#define	KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT   (16U)
#define	KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x)
OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control
#define	KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK   (0x1U)
#define	KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT   (0U)
#define	KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x)
#define	KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK   (0x10000U)
#define	KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT   (16U)
#define	KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x)
OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control
#define	KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK   (0x1U)
#define	KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT   (0U)
#define	KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x)
#define	KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK   (0x10000U)
#define	KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT   (16U)
#define	KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x)
IEE_KEY_CTRL - CSR IEE Key Control
#define	KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK   (0x1U)
#define	KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT   (0U)
#define	KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x)
PUF_KEY_CTRL - CSR PUF Key Control
#define	KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK   (0x1U)
#define	KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT   (0U)
#define	KEY_MANAGER_PUF_KEY_CTRL_LOCK(x)
SLOT0_CTRL - Slot 0 Control
#define	KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK   (0xFU)
#define	KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT   (0U)
#define	KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x)
#define	KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK   (0x8000U)
#define	KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT   (15U)
#define	KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x)
#define	KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK   (0x10000U)
#define	KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT   (16U)
#define	KEY_MANAGER_SLOT0_CTRL_TZ_NS(x)
#define	KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK   (0x20000U)
#define	KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT   (17U)
#define	KEY_MANAGER_SLOT0_CTRL_TZ_USER(x)
#define	KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
#define	KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT   (31U)
#define	KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x)
SLOT1_CTRL - Slot1 Control
#define	KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK   (0xFU)
#define	KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT   (0U)
#define	KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x)
#define	KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK   (0x8000U)
#define	KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT   (15U)
#define	KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x)
#define	KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK   (0x10000U)
#define	KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT   (16U)
#define	KEY_MANAGER_SLOT1_CTRL_TZ_NS(x)
#define	KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK   (0x20000U)
#define	KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT   (17U)
#define	KEY_MANAGER_SLOT1_CTRL_TZ_USER(x)
#define	KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
#define	KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT   (31U)
#define	KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x)
SLOT2_CTRL - Slot2 Control
#define	KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK   (0xFU)
#define	KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT   (0U)
#define	KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x)
#define	KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK   (0x8000U)
#define	KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT   (15U)
#define	KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x)
#define	KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK   (0x10000U)
#define	KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT   (16U)
#define	KEY_MANAGER_SLOT2_CTRL_TZ_NS(x)
#define	KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK   (0x20000U)
#define	KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT   (17U)
#define	KEY_MANAGER_SLOT2_CTRL_TZ_USER(x)
#define	KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
#define	KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT   (31U)
#define	KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x)
SLOT3_CTRL - Slot3 Control
#define	KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK   (0xFU)
#define	KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT   (0U)
#define	KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x)
#define	KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK   (0x8000U)
#define	KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT   (15U)
#define	KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x)
#define	KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK   (0x10000U)
#define	KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT   (16U)
#define	KEY_MANAGER_SLOT3_CTRL_TZ_NS(x)
#define	KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK   (0x20000U)
#define	KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT   (17U)
#define	KEY_MANAGER_SLOT3_CTRL_TZ_USER(x)
#define	KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
#define	KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT   (31U)
#define	KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x)
SLOT4_CTRL - Slot 4 Control
#define	KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK   (0xFU)
#define	KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT   (0U)
#define	KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x)
#define	KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK   (0x8000U)
#define	KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT   (15U)
#define	KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x)
#define	KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK   (0x10000U)
#define	KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT   (16U)
#define	KEY_MANAGER_SLOT4_CTRL_TZ_NS(x)
#define	KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK   (0x20000U)
#define	KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT   (17U)
#define	KEY_MANAGER_SLOT4_CTRL_TZ_USER(x)
#define	KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
#define	KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT   (31U)
#define	KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x)
KPCR - Keypad Control Register
#define	KPP_KPCR_KRE_MASK   (0xFFU)
#define	KPP_KPCR_KRE_SHIFT   (0U)
#define	KPP_KPCR_KRE(x)
#define	KPP_KPCR_KCO_MASK   (0xFF00U)
#define	KPP_KPCR_KCO_SHIFT   (8U)
#define	KPP_KPCR_KCO(x)
KPSR - Keypad Status Register
#define	KPP_KPSR_KPKD_MASK   (0x1U)
#define	KPP_KPSR_KPKD_SHIFT   (0U)
#define	KPP_KPSR_KPKD(x)
#define	KPP_KPSR_KPKR_MASK   (0x2U)
#define	KPP_KPSR_KPKR_SHIFT   (1U)
#define	KPP_KPSR_KPKR(x)
#define	KPP_KPSR_KDSC_MASK   (0x4U)
#define	KPP_KPSR_KDSC_SHIFT   (2U)
#define	KPP_KPSR_KDSC(x)
#define	KPP_KPSR_KRSS_MASK   (0x8U)
#define	KPP_KPSR_KRSS_SHIFT   (3U)
#define	KPP_KPSR_KRSS(x)
#define	KPP_KPSR_KDIE_MASK   (0x100U)
#define	KPP_KPSR_KDIE_SHIFT   (8U)
#define	KPP_KPSR_KDIE(x)
#define	KPP_KPSR_KRIE_MASK   (0x200U)
#define	KPP_KPSR_KRIE_SHIFT   (9U)
#define	KPP_KPSR_KRIE(x)
KDDR - Keypad Data Direction Register
#define	KPP_KDDR_KRDD_MASK   (0xFFU)
#define	KPP_KDDR_KRDD_SHIFT   (0U)
#define	KPP_KDDR_KRDD(x)
#define	KPP_KDDR_KCDD_MASK   (0xFF00U)
#define	KPP_KDDR_KCDD_SHIFT   (8U)
#define	KPP_KDDR_KCDD(x)
KPDR - Keypad Data Register
#define	KPP_KPDR_KRD_MASK   (0xFFU)
#define	KPP_KPDR_KRD_SHIFT   (0U)
#define	KPP_KPDR_KRD(x)
#define	KPP_KPDR_KCD_MASK   (0xFF00U)
#define	KPP_KPDR_KCD_SHIFT   (8U)
#define	KPP_KPDR_KCD(x)
CTRL - LCDIF General Control Register
#define	LCDIF_CTRL_RUN_MASK   (0x1U)
#define	LCDIF_CTRL_RUN_SHIFT   (0U)
#define	LCDIF_CTRL_RUN(x)
#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK   (0x2U)
#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT   (1U)
#define	LCDIF_CTRL_DATA_FORMAT_24_BIT(x)
#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK   (0x4U)
#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT   (2U)
#define	LCDIF_CTRL_DATA_FORMAT_18_BIT(x)
#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK   (0x8U)
#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT   (3U)
#define	LCDIF_CTRL_DATA_FORMAT_16_BIT(x)
#define	LCDIF_CTRL_RSRVD0_MASK   (0x10U)
#define	LCDIF_CTRL_RSRVD0_SHIFT   (4U)
#define	LCDIF_CTRL_RSRVD0(x)
#define	LCDIF_CTRL_MASTER_MASK   (0x20U)
#define	LCDIF_CTRL_MASTER_SHIFT   (5U)
#define	LCDIF_CTRL_MASTER(x)
#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK   (0x40U)
#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT   (6U)
#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x)
#define	LCDIF_CTRL_WORD_LENGTH_MASK   (0x300U)
#define	LCDIF_CTRL_WORD_LENGTH_SHIFT   (8U)
#define	LCDIF_CTRL_WORD_LENGTH(x)
#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK   (0xC00U)
#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT   (10U)
#define	LCDIF_CTRL_LCD_DATABUS_WIDTH(x)
#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK   (0x3000U)
#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT   (12U)
#define	LCDIF_CTRL_CSC_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT   (14U)
#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_DOTCLK_MODE_MASK   (0x20000U)
#define	LCDIF_CTRL_DOTCLK_MODE_SHIFT   (17U)
#define	LCDIF_CTRL_DOTCLK_MODE(x)
#define	LCDIF_CTRL_BYPASS_COUNT_MASK   (0x80000U)
#define	LCDIF_CTRL_BYPASS_COUNT_SHIFT   (19U)
#define	LCDIF_CTRL_BYPASS_COUNT(x)
#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK   (0x3E00000U)
#define	LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT   (21U)
#define	LCDIF_CTRL_SHIFT_NUM_BITS(x)
#define	LCDIF_CTRL_DATA_SHIFT_DIR_MASK   (0x4000000U)
#define	LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT   (26U)
#define	LCDIF_CTRL_DATA_SHIFT_DIR(x)
#define	LCDIF_CTRL_CLKGATE_MASK   (0x40000000U)
#define	LCDIF_CTRL_CLKGATE_SHIFT   (30U)
#define	LCDIF_CTRL_CLKGATE(x)
#define	LCDIF_CTRL_SFTRST_MASK   (0x80000000U)
#define	LCDIF_CTRL_SFTRST_SHIFT   (31U)
#define	LCDIF_CTRL_SFTRST(x)
CTRL_SET - LCDIF General Control Register
#define	LCDIF_CTRL_SET_RUN_MASK   (0x1U)
#define	LCDIF_CTRL_SET_RUN_SHIFT   (0U)
#define	LCDIF_CTRL_SET_RUN(x)
#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT   (1U)
#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)
#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT   (2U)
#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)
#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT   (3U)
#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x)
#define	LCDIF_CTRL_SET_RSRVD0_MASK   (0x10U)
#define	LCDIF_CTRL_SET_RSRVD0_SHIFT   (4U)
#define	LCDIF_CTRL_SET_RSRVD0(x)
#define	LCDIF_CTRL_SET_MASTER_MASK   (0x20U)
#define	LCDIF_CTRL_SET_MASTER_SHIFT   (5U)
#define	LCDIF_CTRL_SET_MASTER(x)
#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK   (0x40U)
#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT   (6U)
#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x)
#define	LCDIF_CTRL_SET_WORD_LENGTH_MASK   (0x300U)
#define	LCDIF_CTRL_SET_WORD_LENGTH_SHIFT   (8U)
#define	LCDIF_CTRL_SET_WORD_LENGTH(x)
#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK   (0xC00U)
#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)
#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK   (0x3000U)
#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT   (12U)
#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT   (14U)
#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_SET_DOTCLK_MODE_MASK   (0x20000U)
#define	LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT   (17U)
#define	LCDIF_CTRL_SET_DOTCLK_MODE(x)
#define	LCDIF_CTRL_SET_BYPASS_COUNT_MASK   (0x80000U)
#define	LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT   (19U)
#define	LCDIF_CTRL_SET_BYPASS_COUNT(x)
#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK   (0x3E00000U)
#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT   (21U)
#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)
#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK   (0x4000000U)
#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT   (26U)
#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)
#define	LCDIF_CTRL_SET_CLKGATE_MASK   (0x40000000U)
#define	LCDIF_CTRL_SET_CLKGATE_SHIFT   (30U)
#define	LCDIF_CTRL_SET_CLKGATE(x)
#define	LCDIF_CTRL_SET_SFTRST_MASK   (0x80000000U)
#define	LCDIF_CTRL_SET_SFTRST_SHIFT   (31U)
#define	LCDIF_CTRL_SET_SFTRST(x)
CTRL_CLR - LCDIF General Control Register
#define	LCDIF_CTRL_CLR_RUN_MASK   (0x1U)
#define	LCDIF_CTRL_CLR_RUN_SHIFT   (0U)
#define	LCDIF_CTRL_CLR_RUN(x)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT   (1U)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT   (2U)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT   (3U)
#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x)
#define	LCDIF_CTRL_CLR_RSRVD0_MASK   (0x10U)
#define	LCDIF_CTRL_CLR_RSRVD0_SHIFT   (4U)
#define	LCDIF_CTRL_CLR_RSRVD0(x)
#define	LCDIF_CTRL_CLR_MASTER_MASK   (0x20U)
#define	LCDIF_CTRL_CLR_MASTER_SHIFT   (5U)
#define	LCDIF_CTRL_CLR_MASTER(x)
#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK   (0x40U)
#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT   (6U)
#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x)
#define	LCDIF_CTRL_CLR_WORD_LENGTH_MASK   (0x300U)
#define	LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT   (8U)
#define	LCDIF_CTRL_CLR_WORD_LENGTH(x)
#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK   (0xC00U)
#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)
#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK   (0x3000U)
#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT   (12U)
#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT   (14U)
#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_CLR_DOTCLK_MODE_MASK   (0x20000U)
#define	LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT   (17U)
#define	LCDIF_CTRL_CLR_DOTCLK_MODE(x)
#define	LCDIF_CTRL_CLR_BYPASS_COUNT_MASK   (0x80000U)
#define	LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT   (19U)
#define	LCDIF_CTRL_CLR_BYPASS_COUNT(x)
#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK   (0x3E00000U)
#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT   (21U)
#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)
#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK   (0x4000000U)
#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT   (26U)
#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)
#define	LCDIF_CTRL_CLR_CLKGATE_MASK   (0x40000000U)
#define	LCDIF_CTRL_CLR_CLKGATE_SHIFT   (30U)
#define	LCDIF_CTRL_CLR_CLKGATE(x)
#define	LCDIF_CTRL_CLR_SFTRST_MASK   (0x80000000U)
#define	LCDIF_CTRL_CLR_SFTRST_SHIFT   (31U)
#define	LCDIF_CTRL_CLR_SFTRST(x)
CTRL_TOG - LCDIF General Control Register
#define	LCDIF_CTRL_TOG_RUN_MASK   (0x1U)
#define	LCDIF_CTRL_TOG_RUN_SHIFT   (0U)
#define	LCDIF_CTRL_TOG_RUN(x)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT   (1U)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT   (2U)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT   (3U)
#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x)
#define	LCDIF_CTRL_TOG_RSRVD0_MASK   (0x10U)
#define	LCDIF_CTRL_TOG_RSRVD0_SHIFT   (4U)
#define	LCDIF_CTRL_TOG_RSRVD0(x)
#define	LCDIF_CTRL_TOG_MASTER_MASK   (0x20U)
#define	LCDIF_CTRL_TOG_MASTER_SHIFT   (5U)
#define	LCDIF_CTRL_TOG_MASTER(x)
#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK   (0x40U)
#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT   (6U)
#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x)
#define	LCDIF_CTRL_TOG_WORD_LENGTH_MASK   (0x300U)
#define	LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT   (8U)
#define	LCDIF_CTRL_TOG_WORD_LENGTH(x)
#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK   (0xC00U)
#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)
#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK   (0x3000U)
#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT   (12U)
#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT   (14U)
#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)
#define	LCDIF_CTRL_TOG_DOTCLK_MODE_MASK   (0x20000U)
#define	LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT   (17U)
#define	LCDIF_CTRL_TOG_DOTCLK_MODE(x)
#define	LCDIF_CTRL_TOG_BYPASS_COUNT_MASK   (0x80000U)
#define	LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT   (19U)
#define	LCDIF_CTRL_TOG_BYPASS_COUNT(x)
#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK   (0x3E00000U)
#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT   (21U)
#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)
#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK   (0x4000000U)
#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT   (26U)
#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)
#define	LCDIF_CTRL_TOG_CLKGATE_MASK   (0x40000000U)
#define	LCDIF_CTRL_TOG_CLKGATE_SHIFT   (30U)
#define	LCDIF_CTRL_TOG_CLKGATE(x)
#define	LCDIF_CTRL_TOG_SFTRST_MASK   (0x80000000U)
#define	LCDIF_CTRL_TOG_SFTRST_SHIFT   (31U)
#define	LCDIF_CTRL_TOG_SFTRST(x)
CTRL1 - LCDIF General Control1 Register
#define	LCDIF_CTRL1_RSRVD0_MASK   (0xF8U)
#define	LCDIF_CTRL1_RSRVD0_SHIFT   (3U)
#define	LCDIF_CTRL1_RSRVD0(x)
#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK   (0x100U)
#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT   (8U)
#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)
#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK   (0x200U)
#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT   (9U)
#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)
#define	LCDIF_CTRL1_UNDERFLOW_IRQ_MASK   (0x400U)
#define	LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT   (10U)
#define	LCDIF_CTRL1_UNDERFLOW_IRQ(x)
#define	LCDIF_CTRL1_OVERFLOW_IRQ_MASK   (0x800U)
#define	LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT   (11U)
#define	LCDIF_CTRL1_OVERFLOW_IRQ(x)
#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT   (12U)
#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x)
#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT   (13U)
#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x)
#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK   (0x4000U)
#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT   (14U)
#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK   (0x8000U)
#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT   (15U)
#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK   (0xF0000U)
#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT   (16U)
#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)
#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK   (0x100000U)
#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT   (20U)
#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x)
#define	LCDIF_CTRL1_FIFO_CLEAR_MASK   (0x200000U)
#define	LCDIF_CTRL1_FIFO_CLEAR_SHIFT   (21U)
#define	LCDIF_CTRL1_FIFO_CLEAR(x)
#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK   (0x400000U)
#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT   (22U)
#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x)
#define	LCDIF_CTRL1_INTERLACE_FIELDS_MASK   (0x800000U)
#define	LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT   (23U)
#define	LCDIF_CTRL1_INTERLACE_FIELDS(x)
#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK   (0x1000000U)
#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)
#define	LCDIF_CTRL1_BM_ERROR_IRQ_MASK   (0x2000000U)
#define	LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT   (25U)
#define	LCDIF_CTRL1_BM_ERROR_IRQ(x)
#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK   (0x4000000U)
#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT   (26U)
#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN(x)
#define	LCDIF_CTRL1_CS_OUT_SELECT_MASK   (0x40000000U)
#define	LCDIF_CTRL1_CS_OUT_SELECT_SHIFT   (30U)
#define	LCDIF_CTRL1_CS_OUT_SELECT(x)
#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK   (0x80000000U)
#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT   (31U)
#define	LCDIF_CTRL1_IMAGE_DATA_SELECT(x)
CTRL1_SET - LCDIF General Control1 Register
#define	LCDIF_CTRL1_SET_RSRVD0_MASK   (0xF8U)
#define	LCDIF_CTRL1_SET_RSRVD0_SHIFT   (3U)
#define	LCDIF_CTRL1_SET_RSRVD0(x)
#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK   (0x100U)
#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT   (8U)
#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)
#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK   (0x200U)
#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT   (9U)
#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)
#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK   (0x400U)
#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT   (10U)
#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)
#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK   (0x800U)
#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT   (11U)
#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)
#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT   (12U)
#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x)
#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT   (13U)
#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x)
#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK   (0x4000U)
#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   (14U)
#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK   (0x8000U)
#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT   (15U)
#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK   (0xF0000U)
#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT   (16U)
#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)
#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK   (0x100000U)
#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT   (20U)
#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x)
#define	LCDIF_CTRL1_SET_FIFO_CLEAR_MASK   (0x200000U)
#define	LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT   (21U)
#define	LCDIF_CTRL1_SET_FIFO_CLEAR(x)
#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK   (0x400000U)
#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT   (22U)
#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x)
#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK   (0x800000U)
#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   (23U)
#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS(x)
#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK   (0x1000000U)
#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)
#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK   (0x2000000U)
#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT   (25U)
#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)
#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK   (0x4000000U)
#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT   (26U)
#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x)
#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK   (0x40000000U)
#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT   (30U)
#define	LCDIF_CTRL1_SET_CS_OUT_SELECT(x)
#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK   (0x80000000U)
#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT   (31U)
#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x)
CTRL1_CLR - LCDIF General Control1 Register
#define	LCDIF_CTRL1_CLR_RSRVD0_MASK   (0xF8U)
#define	LCDIF_CTRL1_CLR_RSRVD0_SHIFT   (3U)
#define	LCDIF_CTRL1_CLR_RSRVD0(x)
#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK   (0x100U)
#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT   (8U)
#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)
#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK   (0x200U)
#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT   (9U)
#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)
#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK   (0x400U)
#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT   (10U)
#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)
#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK   (0x800U)
#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT   (11U)
#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)
#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT   (12U)
#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x)
#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT   (13U)
#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x)
#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK   (0x4000U)
#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   (14U)
#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK   (0x8000U)
#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT   (15U)
#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK   (0xF0000U)
#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT   (16U)
#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)
#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK   (0x100000U)
#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT   (20U)
#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x)
#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK   (0x200000U)
#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT   (21U)
#define	LCDIF_CTRL1_CLR_FIFO_CLEAR(x)
#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK   (0x400000U)
#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT   (22U)
#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x)
#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK   (0x800000U)
#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   (23U)
#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x)
#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK   (0x1000000U)
#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)
#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK   (0x2000000U)
#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT   (25U)
#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)
#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK   (0x4000000U)
#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT   (26U)
#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x)
#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK   (0x40000000U)
#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT   (30U)
#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT(x)
#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK   (0x80000000U)
#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT   (31U)
#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x)
CTRL1_TOG - LCDIF General Control1 Register
#define	LCDIF_CTRL1_TOG_RSRVD0_MASK   (0xF8U)
#define	LCDIF_CTRL1_TOG_RSRVD0_SHIFT   (3U)
#define	LCDIF_CTRL1_TOG_RSRVD0(x)
#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK   (0x100U)
#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT   (8U)
#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)
#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK   (0x200U)
#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT   (9U)
#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)
#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK   (0x400U)
#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT   (10U)
#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)
#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK   (0x800U)
#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT   (11U)
#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)
#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT   (12U)
#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x)
#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT   (13U)
#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x)
#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK   (0x4000U)
#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   (14U)
#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK   (0x8000U)
#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT   (15U)
#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x)
#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK   (0xF0000U)
#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT   (16U)
#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)
#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK   (0x100000U)
#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT   (20U)
#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x)
#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK   (0x200000U)
#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT   (21U)
#define	LCDIF_CTRL1_TOG_FIFO_CLEAR(x)
#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK   (0x400000U)
#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT   (22U)
#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x)
#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK   (0x800000U)
#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   (23U)
#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x)
#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK   (0x1000000U)
#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)
#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK   (0x2000000U)
#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT   (25U)
#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)
#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK   (0x4000000U)
#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT   (26U)
#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x)
#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK   (0x40000000U)
#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT   (30U)
#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT(x)
#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK   (0x80000000U)
#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT   (31U)
#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x)
CTRL2 - LCDIF General Control2 Register
#define	LCDIF_CTRL2_RSRVD0_MASK   (0xFFFU)
#define	LCDIF_CTRL2_RSRVD0_SHIFT   (0U)
#define	LCDIF_CTRL2_RSRVD0(x)
#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK   (0x7000U)
#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT   (12U)
#define	LCDIF_CTRL2_EVEN_LINE_PATTERN(x)
#define	LCDIF_CTRL2_RSRVD3_MASK   (0x8000U)
#define	LCDIF_CTRL2_RSRVD3_SHIFT   (15U)
#define	LCDIF_CTRL2_RSRVD3(x)
#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK   (0x70000U)
#define	LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT   (16U)
#define	LCDIF_CTRL2_ODD_LINE_PATTERN(x)
#define	LCDIF_CTRL2_RSRVD4_MASK   (0x80000U)
#define	LCDIF_CTRL2_RSRVD4_SHIFT   (19U)
#define	LCDIF_CTRL2_RSRVD4(x)
#define	LCDIF_CTRL2_BURST_LEN_8_MASK   (0x100000U)
#define	LCDIF_CTRL2_BURST_LEN_8_SHIFT   (20U)
#define	LCDIF_CTRL2_BURST_LEN_8(x)
#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK   (0xE00000U)
#define	LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT   (21U)
#define	LCDIF_CTRL2_OUTSTANDING_REQS(x)
#define	LCDIF_CTRL2_RSRVD5_MASK   (0xFF000000U)
#define	LCDIF_CTRL2_RSRVD5_SHIFT   (24U)
#define	LCDIF_CTRL2_RSRVD5(x)
CTRL2_SET - LCDIF General Control2 Register
#define	LCDIF_CTRL2_SET_RSRVD0_MASK   (0xFFFU)
#define	LCDIF_CTRL2_SET_RSRVD0_SHIFT   (0U)
#define	LCDIF_CTRL2_SET_RSRVD0(x)
#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT   (12U)
#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)
#define	LCDIF_CTRL2_SET_RSRVD3_MASK   (0x8000U)
#define	LCDIF_CTRL2_SET_RSRVD3_SHIFT   (15U)
#define	LCDIF_CTRL2_SET_RSRVD3(x)
#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK   (0x70000U)
#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)
#define	LCDIF_CTRL2_SET_RSRVD4_MASK   (0x80000U)
#define	LCDIF_CTRL2_SET_RSRVD4_SHIFT   (19U)
#define	LCDIF_CTRL2_SET_RSRVD4(x)
#define	LCDIF_CTRL2_SET_BURST_LEN_8_MASK   (0x100000U)
#define	LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT   (20U)
#define	LCDIF_CTRL2_SET_BURST_LEN_8(x)
#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK   (0xE00000U)
#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)
#define	LCDIF_CTRL2_SET_RSRVD5_MASK   (0xFF000000U)
#define	LCDIF_CTRL2_SET_RSRVD5_SHIFT   (24U)
#define	LCDIF_CTRL2_SET_RSRVD5(x)
CTRL2_CLR - LCDIF General Control2 Register
#define	LCDIF_CTRL2_CLR_RSRVD0_MASK   (0xFFFU)
#define	LCDIF_CTRL2_CLR_RSRVD0_SHIFT   (0U)
#define	LCDIF_CTRL2_CLR_RSRVD0(x)
#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT   (12U)
#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)
#define	LCDIF_CTRL2_CLR_RSRVD3_MASK   (0x8000U)
#define	LCDIF_CTRL2_CLR_RSRVD3_SHIFT   (15U)
#define	LCDIF_CTRL2_CLR_RSRVD3(x)
#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK   (0x70000U)
#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)
#define	LCDIF_CTRL2_CLR_RSRVD4_MASK   (0x80000U)
#define	LCDIF_CTRL2_CLR_RSRVD4_SHIFT   (19U)
#define	LCDIF_CTRL2_CLR_RSRVD4(x)
#define	LCDIF_CTRL2_CLR_BURST_LEN_8_MASK   (0x100000U)
#define	LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT   (20U)
#define	LCDIF_CTRL2_CLR_BURST_LEN_8(x)
#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK   (0xE00000U)
#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)
#define	LCDIF_CTRL2_CLR_RSRVD5_MASK   (0xFF000000U)
#define	LCDIF_CTRL2_CLR_RSRVD5_SHIFT   (24U)
#define	LCDIF_CTRL2_CLR_RSRVD5(x)
CTRL2_TOG - LCDIF General Control2 Register
#define	LCDIF_CTRL2_TOG_RSRVD0_MASK   (0xFFFU)
#define	LCDIF_CTRL2_TOG_RSRVD0_SHIFT   (0U)
#define	LCDIF_CTRL2_TOG_RSRVD0(x)
#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT   (12U)
#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)
#define	LCDIF_CTRL2_TOG_RSRVD3_MASK   (0x8000U)
#define	LCDIF_CTRL2_TOG_RSRVD3_SHIFT   (15U)
#define	LCDIF_CTRL2_TOG_RSRVD3(x)
#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK   (0x70000U)
#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)
#define	LCDIF_CTRL2_TOG_RSRVD4_MASK   (0x80000U)
#define	LCDIF_CTRL2_TOG_RSRVD4_SHIFT   (19U)
#define	LCDIF_CTRL2_TOG_RSRVD4(x)
#define	LCDIF_CTRL2_TOG_BURST_LEN_8_MASK   (0x100000U)
#define	LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT   (20U)
#define	LCDIF_CTRL2_TOG_BURST_LEN_8(x)
#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK   (0xE00000U)
#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)
#define	LCDIF_CTRL2_TOG_RSRVD5_MASK   (0xFF000000U)
#define	LCDIF_CTRL2_TOG_RSRVD5_SHIFT   (24U)
#define	LCDIF_CTRL2_TOG_RSRVD5(x)
TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register
#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK   (0xFFFFU)
#define	LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT   (0U)
#define	LCDIF_TRANSFER_COUNT_H_COUNT(x)
#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK   (0xFFFF0000U)
#define	LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT   (16U)
#define	LCDIF_TRANSFER_COUNT_V_COUNT(x)
CUR_BUF - LCD Interface Current Buffer Address Register
#define	LCDIF_CUR_BUF_ADDR_MASK   (0xFFFFFFFFU)
#define	LCDIF_CUR_BUF_ADDR_SHIFT   (0U)
#define	LCDIF_CUR_BUF_ADDR(x)
NEXT_BUF - LCD Interface Next Buffer Address Register
#define	LCDIF_NEXT_BUF_ADDR_MASK   (0xFFFFFFFFU)
#define	LCDIF_NEXT_BUF_ADDR_SHIFT   (0U)
#define	LCDIF_NEXT_BUF_ADDR(x)
VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK   (0x3FFFFU)
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT   (0U)
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)
#define	LCDIF_VDCTRL0_HALF_LINE_MODE_MASK   (0x40000U)
#define	LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT   (18U)
#define	LCDIF_VDCTRL0_HALF_LINE_MODE(x)
#define	LCDIF_VDCTRL0_HALF_LINE_MASK   (0x80000U)
#define	LCDIF_VDCTRL0_HALF_LINE_SHIFT   (19U)
#define	LCDIF_VDCTRL0_HALF_LINE(x)
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK   (0x100000U)
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT   (20U)
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x)
#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK   (0x200000U)
#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT   (21U)
#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x)
#define	LCDIF_VDCTRL0_RSRVD1_MASK   (0xC00000U)
#define	LCDIF_VDCTRL0_RSRVD1_SHIFT   (22U)
#define	LCDIF_VDCTRL0_RSRVD1(x)
#define	LCDIF_VDCTRL0_ENABLE_POL_MASK   (0x1000000U)
#define	LCDIF_VDCTRL0_ENABLE_POL_SHIFT   (24U)
#define	LCDIF_VDCTRL0_ENABLE_POL(x)
#define	LCDIF_VDCTRL0_DOTCLK_POL_MASK   (0x2000000U)
#define	LCDIF_VDCTRL0_DOTCLK_POL_SHIFT   (25U)
#define	LCDIF_VDCTRL0_DOTCLK_POL(x)
#define	LCDIF_VDCTRL0_HSYNC_POL_MASK   (0x4000000U)
#define	LCDIF_VDCTRL0_HSYNC_POL_SHIFT   (26U)
#define	LCDIF_VDCTRL0_HSYNC_POL(x)
#define	LCDIF_VDCTRL0_VSYNC_POL_MASK   (0x8000000U)
#define	LCDIF_VDCTRL0_VSYNC_POL_SHIFT   (27U)
#define	LCDIF_VDCTRL0_VSYNC_POL(x)
#define	LCDIF_VDCTRL0_ENABLE_PRESENT_MASK   (0x10000000U)
#define	LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT   (28U)
#define	LCDIF_VDCTRL0_ENABLE_PRESENT(x)
#define	LCDIF_VDCTRL0_VSYNC_OEB_MASK   (0x20000000U)
#define	LCDIF_VDCTRL0_VSYNC_OEB_SHIFT   (29U)
#define	LCDIF_VDCTRL0_VSYNC_OEB(x)
#define	LCDIF_VDCTRL0_RSRVD2_MASK   (0xC0000000U)
#define	LCDIF_VDCTRL0_RSRVD2_SHIFT   (30U)
#define	LCDIF_VDCTRL0_RSRVD2(x)
VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK   (0x3FFFFU)
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT   (0U)
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)
#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK   (0x40000U)
#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   (18U)
#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x)
#define	LCDIF_VDCTRL0_SET_HALF_LINE_MASK   (0x80000U)
#define	LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT   (19U)
#define	LCDIF_VDCTRL0_SET_HALF_LINE(x)
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK   (0x100000U)
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT   (20U)
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x)
#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK   (0x200000U)
#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT   (21U)
#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x)
#define	LCDIF_VDCTRL0_SET_RSRVD1_MASK   (0xC00000U)
#define	LCDIF_VDCTRL0_SET_RSRVD1_SHIFT   (22U)
#define	LCDIF_VDCTRL0_SET_RSRVD1(x)
#define	LCDIF_VDCTRL0_SET_ENABLE_POL_MASK   (0x1000000U)
#define	LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT   (24U)
#define	LCDIF_VDCTRL0_SET_ENABLE_POL(x)
#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK   (0x2000000U)
#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT   (25U)
#define	LCDIF_VDCTRL0_SET_DOTCLK_POL(x)
#define	LCDIF_VDCTRL0_SET_HSYNC_POL_MASK   (0x4000000U)
#define	LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT   (26U)
#define	LCDIF_VDCTRL0_SET_HSYNC_POL(x)
#define	LCDIF_VDCTRL0_SET_VSYNC_POL_MASK   (0x8000000U)
#define	LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT   (27U)
#define	LCDIF_VDCTRL0_SET_VSYNC_POL(x)
#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK   (0x10000000U)
#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   (28U)
#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x)
#define	LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK   (0x20000000U)
#define	LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT   (29U)
#define	LCDIF_VDCTRL0_SET_VSYNC_OEB(x)
#define	LCDIF_VDCTRL0_SET_RSRVD2_MASK   (0xC0000000U)
#define	LCDIF_VDCTRL0_SET_RSRVD2_SHIFT   (30U)
#define	LCDIF_VDCTRL0_SET_RSRVD2(x)
VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK   (0x3FFFFU)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT   (0U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)
#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK   (0x40000U)
#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   (18U)
#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x)
#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MASK   (0x80000U)
#define	LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT   (19U)
#define	LCDIF_VDCTRL0_CLR_HALF_LINE(x)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK   (0x100000U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT   (20U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK   (0x200000U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT   (21U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x)
#define	LCDIF_VDCTRL0_CLR_RSRVD1_MASK   (0xC00000U)
#define	LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT   (22U)
#define	LCDIF_VDCTRL0_CLR_RSRVD1(x)
#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK   (0x1000000U)
#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT   (24U)
#define	LCDIF_VDCTRL0_CLR_ENABLE_POL(x)
#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK   (0x2000000U)
#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT   (25U)
#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL(x)
#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK   (0x4000000U)
#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT   (26U)
#define	LCDIF_VDCTRL0_CLR_HSYNC_POL(x)
#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK   (0x8000000U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT   (27U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_POL(x)
#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK   (0x10000000U)
#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   (28U)
#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x)
#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK   (0x20000000U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT   (29U)
#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB(x)
#define	LCDIF_VDCTRL0_CLR_RSRVD2_MASK   (0xC0000000U)
#define	LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT   (30U)
#define	LCDIF_VDCTRL0_CLR_RSRVD2(x)
VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK   (0x3FFFFU)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT   (0U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)
#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK   (0x40000U)
#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   (18U)
#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x)
#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MASK   (0x80000U)
#define	LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT   (19U)
#define	LCDIF_VDCTRL0_TOG_HALF_LINE(x)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK   (0x100000U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT   (20U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK   (0x200000U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT   (21U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x)
#define	LCDIF_VDCTRL0_TOG_RSRVD1_MASK   (0xC00000U)
#define	LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT   (22U)
#define	LCDIF_VDCTRL0_TOG_RSRVD1(x)
#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK   (0x1000000U)
#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT   (24U)
#define	LCDIF_VDCTRL0_TOG_ENABLE_POL(x)
#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK   (0x2000000U)
#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT   (25U)
#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL(x)
#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK   (0x4000000U)
#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT   (26U)
#define	LCDIF_VDCTRL0_TOG_HSYNC_POL(x)
#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK   (0x8000000U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT   (27U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_POL(x)
#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK   (0x10000000U)
#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   (28U)
#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x)
#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK   (0x20000000U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT   (29U)
#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB(x)
#define	LCDIF_VDCTRL0_TOG_RSRVD2_MASK   (0xC0000000U)
#define	LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT   (30U)
#define	LCDIF_VDCTRL0_TOG_RSRVD2(x)
VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1
#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK   (0xFFFFFFFFU)
#define	LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT   (0U)
#define	LCDIF_VDCTRL1_VSYNC_PERIOD(x)
VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2
#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK   (0x3FFFFU)
#define	LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT   (0U)
#define	LCDIF_VDCTRL2_HSYNC_PERIOD(x)
#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK   (0xFFFC0000U)
#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT   (18U)
#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)
VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3
#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK   (0xFFFFU)
#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT   (0U)
#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)
#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   (0xFFF0000U)
#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT   (16U)
#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)
#define	LCDIF_VDCTRL3_VSYNC_ONLY_MASK   (0x10000000U)
#define	LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT   (28U)
#define	LCDIF_VDCTRL3_VSYNC_ONLY(x)
#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK   (0x20000000U)
#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT   (29U)
#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x)
#define	LCDIF_VDCTRL3_RSRVD0_MASK   (0xC0000000U)
#define	LCDIF_VDCTRL3_RSRVD0_SHIFT   (30U)
#define	LCDIF_VDCTRL3_RSRVD0(x)
VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4
#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK   (0x3FFFFU)
#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT   (0U)
#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x)
#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK   (0x40000U)
#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT   (18U)
#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x)
#define	LCDIF_VDCTRL4_RSRVD0_MASK   (0x1FF80000U)
#define	LCDIF_VDCTRL4_RSRVD0_SHIFT   (19U)
#define	LCDIF_VDCTRL4_RSRVD0(x)
#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK   (0xE0000000U)
#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT   (29U)
#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)
BM_ERROR_STAT - Bus Master Error Status Register
#define	LCDIF_BM_ERROR_STAT_ADDR_MASK   (0xFFFFFFFFU)
#define	LCDIF_BM_ERROR_STAT_ADDR_SHIFT   (0U)
#define	LCDIF_BM_ERROR_STAT_ADDR(x)
CRC_STAT - CRC Status Register
#define	LCDIF_CRC_STAT_CRC_VALUE_MASK   (0xFFFFFFFFU)
#define	LCDIF_CRC_STAT_CRC_VALUE_SHIFT   (0U)
#define	LCDIF_CRC_STAT_CRC_VALUE(x)
STAT - LCD Interface Status Register
#define	LCDIF_STAT_LFIFO_COUNT_MASK   (0x1FFU)
#define	LCDIF_STAT_LFIFO_COUNT_SHIFT   (0U)
#define	LCDIF_STAT_LFIFO_COUNT(x)
#define	LCDIF_STAT_RSRVD0_MASK   (0x1FFFE00U)
#define	LCDIF_STAT_RSRVD0_SHIFT   (9U)
#define	LCDIF_STAT_RSRVD0(x)
#define	LCDIF_STAT_TXFIFO_EMPTY_MASK   (0x4000000U)
#define	LCDIF_STAT_TXFIFO_EMPTY_SHIFT   (26U)
#define	LCDIF_STAT_TXFIFO_EMPTY(x)
#define	LCDIF_STAT_TXFIFO_FULL_MASK   (0x8000000U)
#define	LCDIF_STAT_TXFIFO_FULL_SHIFT   (27U)
#define	LCDIF_STAT_TXFIFO_FULL(x)
#define	LCDIF_STAT_LFIFO_EMPTY_MASK   (0x10000000U)
#define	LCDIF_STAT_LFIFO_EMPTY_SHIFT   (28U)
#define	LCDIF_STAT_LFIFO_EMPTY(x)
#define	LCDIF_STAT_LFIFO_FULL_MASK   (0x20000000U)
#define	LCDIF_STAT_LFIFO_FULL_SHIFT   (29U)
#define	LCDIF_STAT_LFIFO_FULL(x)
#define	LCDIF_STAT_DMA_REQ_MASK   (0x40000000U)
#define	LCDIF_STAT_DMA_REQ_SHIFT   (30U)
#define	LCDIF_STAT_DMA_REQ(x)
#define	LCDIF_STAT_PRESENT_MASK   (0x80000000U)
#define	LCDIF_STAT_PRESENT_SHIFT   (31U)
#define	LCDIF_STAT_PRESENT(x)
THRES - LCDIF Threshold Register
#define	LCDIF_THRES_RSRVD_MASK   (0x1FFU)
#define	LCDIF_THRES_RSRVD_SHIFT   (0U)
#define	LCDIF_THRES_RSRVD(x)
#define	LCDIF_THRES_RSRVD1_MASK   (0xFE00U)
#define	LCDIF_THRES_RSRVD1_SHIFT   (9U)
#define	LCDIF_THRES_RSRVD1(x)
#define	LCDIF_THRES_FASTCLOCK_MASK   (0x1FF0000U)
#define	LCDIF_THRES_FASTCLOCK_SHIFT   (16U)
#define	LCDIF_THRES_FASTCLOCK(x)
#define	LCDIF_THRES_RSRVD2_MASK   (0xFE000000U)
#define	LCDIF_THRES_RSRVD2_SHIFT   (25U)
#define	LCDIF_THRES_RSRVD2(x)
PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_FD_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL0_FD_PERIOD(x)
#define	LCDIF_PIGEONCTRL0_LD_PERIOD_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL0_LD_PERIOD(x)
PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x)
#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x)
PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x)
#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x)
PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x)
#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x)
PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x)
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x)
PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x)
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x)
PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x)
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x)
PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK   (0xFFFU)
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x)
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK   (0xFFF0000U)
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT   (16U)
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x)
PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK   (0x1U)
#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x)
#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK   (0x2U)
#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT   (1U)
#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x)
PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK   (0x1U)
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x)
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK   (0x2U)
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT   (1U)
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x)
PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK   (0x1U)
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x)
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK   (0x2U)
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT   (1U)
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x)
PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK   (0x1U)
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT   (0U)
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x)
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK   (0x2U)
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT   (1U)
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x)
PIGEON_0 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_0_EN_MASK   (0x1U)
#define	LCDIF_PIGEON_0_EN_SHIFT   (0U)
#define	LCDIF_PIGEON_0_EN(x)
#define	LCDIF_PIGEON_0_POL_MASK   (0x2U)
#define	LCDIF_PIGEON_0_POL_SHIFT   (1U)
#define	LCDIF_PIGEON_0_POL(x)
#define	LCDIF_PIGEON_0_INC_SEL_MASK   (0xCU)
#define	LCDIF_PIGEON_0_INC_SEL_SHIFT   (2U)
#define	LCDIF_PIGEON_0_INC_SEL(x)
#define	LCDIF_PIGEON_0_OFFSET_MASK   (0xF0U)
#define	LCDIF_PIGEON_0_OFFSET_SHIFT   (4U)
#define	LCDIF_PIGEON_0_OFFSET(x)
#define	LCDIF_PIGEON_0_MASK_CNT_SEL_MASK   (0xF00U)
#define	LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT   (8U)
#define	LCDIF_PIGEON_0_MASK_CNT_SEL(x)
#define	LCDIF_PIGEON_0_MASK_CNT_MASK   (0xFFF000U)
#define	LCDIF_PIGEON_0_MASK_CNT_SHIFT   (12U)
#define	LCDIF_PIGEON_0_MASK_CNT(x)
#define	LCDIF_PIGEON_0_STATE_MASK_MASK   (0xFF000000U)
#define	LCDIF_PIGEON_0_STATE_MASK_SHIFT   (24U)
#define	LCDIF_PIGEON_0_STATE_MASK(x)
PIGEON_1 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_1_SET_CNT_MASK   (0xFFFFU)
#define	LCDIF_PIGEON_1_SET_CNT_SHIFT   (0U)
#define	LCDIF_PIGEON_1_SET_CNT(x)
#define	LCDIF_PIGEON_1_CLR_CNT_MASK   (0xFFFF0000U)
#define	LCDIF_PIGEON_1_CLR_CNT_SHIFT   (16U)
#define	LCDIF_PIGEON_1_CLR_CNT(x)
PIGEON_2 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_2_SIG_LOGIC_MASK   (0xFU)
#define	LCDIF_PIGEON_2_SIG_LOGIC_SHIFT   (0U)
#define	LCDIF_PIGEON_2_SIG_LOGIC(x)
#define	LCDIF_PIGEON_2_SIG_ANOTHER_MASK   (0x1F0U)
#define	LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT   (4U)
#define	LCDIF_PIGEON_2_SIG_ANOTHER(x)
#define	LCDIF_PIGEON_2_RSVD_MASK   (0xFFFFFE00U)
#define	LCDIF_PIGEON_2_RSVD_SHIFT   (9U)
#define	LCDIF_PIGEON_2_RSVD(x)
LUT_CTRL - Look Up Table Control Register
#define	LCDIF_LUT_CTRL_LUT_BYPASS_MASK   (0x1U)
#define	LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT   (0U)
#define	LCDIF_LUT_CTRL_LUT_BYPASS(x)
LUT0_ADDR - Lookup Table 0 Index Register
#define	LCDIF_LUT0_ADDR_ADDR_MASK   (0xFFU)
#define	LCDIF_LUT0_ADDR_ADDR_SHIFT   (0U)
#define	LCDIF_LUT0_ADDR_ADDR(x)
LUT0_DATA - Lookup Table 0 Data Register
#define	LCDIF_LUT0_DATA_DATA_MASK   (0xFFFFFFFFU)
#define	LCDIF_LUT0_DATA_DATA_SHIFT   (0U)
#define	LCDIF_LUT0_DATA_DATA(x)
LUT1_ADDR - Lookup Table 1 Index Register
#define	LCDIF_LUT1_ADDR_ADDR_MASK   (0xFFU)
#define	LCDIF_LUT1_ADDR_ADDR_SHIFT   (0U)
#define	LCDIF_LUT1_ADDR_ADDR(x)
LUT1_DATA - Lookup Table 1 Data Register
#define	LCDIF_LUT1_DATA_DATA_MASK   (0xFFFFFFFFU)
#define	LCDIF_LUT1_DATA_DATA_SHIFT   (0U)
#define	LCDIF_LUT1_DATA_DATA(x)
CTRL - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_INV_HS(x)
#define	LCDIFV2_CTRL_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_INV_VS(x)
#define	LCDIFV2_CTRL_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_INV_DE(x)
#define	LCDIFV2_CTRL_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_INV_PXCK(x)
#define	LCDIFV2_CTRL_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_NEG(x)
#define	LCDIFV2_CTRL_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_SW_RESET(x)
CTRL_SET - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_SET_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_SET_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_SET_INV_HS(x)
#define	LCDIFV2_CTRL_SET_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_SET_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_SET_INV_VS(x)
#define	LCDIFV2_CTRL_SET_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_SET_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_SET_INV_DE(x)
#define	LCDIFV2_CTRL_SET_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_SET_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_SET_INV_PXCK(x)
#define	LCDIFV2_CTRL_SET_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_SET_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_SET_NEG(x)
#define	LCDIFV2_CTRL_SET_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_SET_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_SET_SW_RESET(x)
CTRL_CLR - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_CLR_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_CLR_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_CLR_INV_HS(x)
#define	LCDIFV2_CTRL_CLR_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_CLR_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_CLR_INV_VS(x)
#define	LCDIFV2_CTRL_CLR_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_CLR_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_CLR_INV_DE(x)
#define	LCDIFV2_CTRL_CLR_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_CLR_INV_PXCK(x)
#define	LCDIFV2_CTRL_CLR_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_CLR_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_CLR_NEG(x)
#define	LCDIFV2_CTRL_CLR_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_CLR_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_CLR_SW_RESET(x)
CTRL_TOG - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_TOG_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_TOG_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_TOG_INV_HS(x)
#define	LCDIFV2_CTRL_TOG_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_TOG_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_TOG_INV_VS(x)
#define	LCDIFV2_CTRL_TOG_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_TOG_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_TOG_INV_DE(x)
#define	LCDIFV2_CTRL_TOG_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_TOG_INV_PXCK(x)
#define	LCDIFV2_CTRL_TOG_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_TOG_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_TOG_NEG(x)
#define	LCDIFV2_CTRL_TOG_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_TOG_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_TOG_SW_RESET(x)
DISP_PARA - Display Parameter Register
#define	LCDIFV2_DISP_PARA_BGND_B_MASK   (0xFFU)
#define	LCDIFV2_DISP_PARA_BGND_B_SHIFT   (0U)
#define	LCDIFV2_DISP_PARA_BGND_B(x)
#define	LCDIFV2_DISP_PARA_BGND_G_MASK   (0xFF00U)
#define	LCDIFV2_DISP_PARA_BGND_G_SHIFT   (8U)
#define	LCDIFV2_DISP_PARA_BGND_G(x)
#define	LCDIFV2_DISP_PARA_BGND_R_MASK   (0xFF0000U)
#define	LCDIFV2_DISP_PARA_BGND_R_SHIFT   (16U)
#define	LCDIFV2_DISP_PARA_BGND_R(x)
#define	LCDIFV2_DISP_PARA_DISP_MODE_MASK   (0x3000000U)
#define	LCDIFV2_DISP_PARA_DISP_MODE_SHIFT   (24U)
#define	LCDIFV2_DISP_PARA_DISP_MODE(x)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN_MASK   (0x1C000000U)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT   (26U)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN(x)
#define	LCDIFV2_DISP_PARA_DISP_ON_MASK   (0x80000000U)
#define	LCDIFV2_DISP_PARA_DISP_ON_SHIFT   (31U)
#define	LCDIFV2_DISP_PARA_DISP_ON(x)
DISP_SIZE - Display Size Register
#define	LCDIFV2_DISP_SIZE_DELTA_X_MASK   (0xFFFU)
#define	LCDIFV2_DISP_SIZE_DELTA_X_SHIFT   (0U)
#define	LCDIFV2_DISP_SIZE_DELTA_X(x)
#define	LCDIFV2_DISP_SIZE_DELTA_Y_MASK   (0xFFF0000U)
#define	LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT   (16U)
#define	LCDIFV2_DISP_SIZE_DELTA_Y(x)
HSYN_PARA - Horizontal Sync Parameter Register
#define	LCDIFV2_HSYN_PARA_FP_H_MASK   (0x1FFU)
#define	LCDIFV2_HSYN_PARA_FP_H_SHIFT   (0U)
#define	LCDIFV2_HSYN_PARA_FP_H(x)
#define	LCDIFV2_HSYN_PARA_PW_H_MASK   (0xFF800U)
#define	LCDIFV2_HSYN_PARA_PW_H_SHIFT   (11U)
#define	LCDIFV2_HSYN_PARA_PW_H(x)
#define	LCDIFV2_HSYN_PARA_BP_H_MASK   (0x7FC00000U)
#define	LCDIFV2_HSYN_PARA_BP_H_SHIFT   (22U)
#define	LCDIFV2_HSYN_PARA_BP_H(x)
VSYN_PARA - Vertical Sync Parameter Register
#define	LCDIFV2_VSYN_PARA_FP_V_MASK   (0x1FFU)
#define	LCDIFV2_VSYN_PARA_FP_V_SHIFT   (0U)
#define	LCDIFV2_VSYN_PARA_FP_V(x)
#define	LCDIFV2_VSYN_PARA_PW_V_MASK   (0xFF800U)
#define	LCDIFV2_VSYN_PARA_PW_V_SHIFT   (11U)
#define	LCDIFV2_VSYN_PARA_PW_V(x)
#define	LCDIFV2_VSYN_PARA_BP_V_MASK   (0x7FC00000U)
#define	LCDIFV2_VSYN_PARA_BP_V_SHIFT   (22U)
#define	LCDIFV2_VSYN_PARA_BP_V(x)
INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1
#define	LCDIFV2_INT_STATUS_VSYNC_MASK   (0x1U)
#define	LCDIFV2_INT_STATUS_VSYNC_SHIFT   (0U)
#define	LCDIFV2_INT_STATUS_VSYNC(x)
#define	LCDIFV2_INT_STATUS_UNDERRUN_MASK   (0x2U)
#define	LCDIFV2_INT_STATUS_UNDERRUN_SHIFT   (1U)
#define	LCDIFV2_INT_STATUS_UNDERRUN(x)
#define	LCDIFV2_INT_STATUS_VS_BLANK_MASK   (0x4U)
#define	LCDIFV2_INT_STATUS_VS_BLANK_SHIFT   (2U)
#define	LCDIFV2_INT_STATUS_VS_BLANK(x)
#define	LCDIFV2_INT_STATUS_DMA_ERR_MASK   (0xFF00U)
#define	LCDIFV2_INT_STATUS_DMA_ERR_SHIFT   (8U)
#define	LCDIFV2_INT_STATUS_DMA_ERR(x)
#define	LCDIFV2_INT_STATUS_DMA_DONE_MASK   (0xFF0000U)
#define	LCDIFV2_INT_STATUS_DMA_DONE_SHIFT   (16U)
#define	LCDIFV2_INT_STATUS_DMA_DONE(x)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK   (0xFF000000U)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT   (24U)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY(x)
INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1
#define	LCDIFV2_INT_ENABLE_VSYNC_EN_MASK   (0x1U)
#define	LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT   (0U)
#define	LCDIFV2_INT_ENABLE_VSYNC_EN(x)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK   (0x2U)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT   (1U)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN(x)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK   (0x4U)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT   (2U)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN(x)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK   (0xFF00U)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT   (8U)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN(x)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK   (0xFF0000U)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT   (16U)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN(x)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK   (0xFF000000U)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT   (24U)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x)
PDI_PARA - Parallel Data Interface Parameter Register
#define	LCDIFV2_PDI_PARA_INV_PDI_HS_MASK   (0x1U)
#define	LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT   (0U)
#define	LCDIFV2_PDI_PARA_INV_PDI_HS(x)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS_MASK   (0x2U)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT   (1U)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS(x)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE_MASK   (0x4U)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT   (2U)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE(x)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK   (0x8U)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT   (3U)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK(x)
#define	LCDIFV2_PDI_PARA_MODE_MASK   (0xF0U)
#define	LCDIFV2_PDI_PARA_MODE_SHIFT   (4U)
#define	LCDIFV2_PDI_PARA_MODE(x)
#define	LCDIFV2_PDI_PARA_PDI_SEL_MASK   (0x40000000U)
#define	LCDIFV2_PDI_PARA_PDI_SEL_SHIFT   (30U)
#define	LCDIFV2_PDI_PARA_PDI_SEL(x)
#define	LCDIFV2_PDI_PARA_PDI_EN_MASK   (0x80000000U)
#define	LCDIFV2_PDI_PARA_PDI_EN_SHIFT   (31U)
#define	LCDIFV2_PDI_PARA_PDI_EN(x)
CTRLDESCL1 - Control Descriptor Layer 1 Register
#define	LCDIFV2_CTRLDESCL1_WIDTH_MASK   (0xFFFU)
#define	LCDIFV2_CTRLDESCL1_WIDTH_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL1_WIDTH(x)
#define	LCDIFV2_CTRLDESCL1_HEIGHT_MASK   (0xFFF0000U)
#define	LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL1_HEIGHT(x)
CTRLDESCL2 - Control Descriptor Layer 2 Register
#define	LCDIFV2_CTRLDESCL2_POSX_MASK   (0xFFFU)
#define	LCDIFV2_CTRLDESCL2_POSX_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL2_POSX(x)
#define	LCDIFV2_CTRLDESCL2_POSY_MASK   (0xFFF0000U)
#define	LCDIFV2_CTRLDESCL2_POSY_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL2_POSY(x)
CTRLDESCL3 - Control Descriptor Layer 3 Register
#define	LCDIFV2_CTRLDESCL3_PITCH_MASK   (0xFFFFU)
#define	LCDIFV2_CTRLDESCL3_PITCH_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL3_PITCH(x)
CTRLDESCL4 - Control Descriptor Layer 4 Register
#define	LCDIFV2_CTRLDESCL4_ADDR_MASK   (0xFFFFFFFFU)
#define	LCDIFV2_CTRLDESCL4_ADDR_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL4_ADDR(x)
CTRLDESCL5 - Control Descriptor Layer 5 Register
#define	LCDIFV2_CTRLDESCL5_AB_MODE_MASK   (0x3U)
#define	LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL5_AB_MODE(x)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK   (0x30U)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT   (4U)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK   (0xC0U)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT   (6U)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK   (0x100U)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT   (8U)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK   (0x200U)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT   (9U)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK   (0xC000U)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT   (14U)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT(x)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK   (0xFF0000U)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x)
#define	LCDIFV2_CTRLDESCL5_BPP_MASK   (0xF000000U)
#define	LCDIFV2_CTRLDESCL5_BPP_SHIFT   (24U)
#define	LCDIFV2_CTRLDESCL5_BPP(x)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK   (0x10000000U)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT   (28U)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN(x)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK   (0x40000000U)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT   (30U)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x)
#define	LCDIFV2_CTRLDESCL5_EN_MASK   (0x80000000U)
#define	LCDIFV2_CTRLDESCL5_EN_SHIFT   (31U)
#define	LCDIFV2_CTRLDESCL5_EN(x)
CTRLDESCL6 - Control Descriptor Layer 6 Register
#define	LCDIFV2_CTRLDESCL6_BCLR_B_MASK   (0xFFU)
#define	LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL6_BCLR_B(x)
#define	LCDIFV2_CTRLDESCL6_BCLR_G_MASK   (0xFF00U)
#define	LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT   (8U)
#define	LCDIFV2_CTRLDESCL6_BCLR_G(x)
#define	LCDIFV2_CTRLDESCL6_BCLR_R_MASK   (0xFF0000U)
#define	LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL6_BCLR_R(x)
CSC_COEF0 - Color Space Conversion Coefficient Register 0
#define	LCDIFV2_CSC_COEF0_Y_OFFSET_MASK   (0x1FFU)
#define	LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF0_Y_OFFSET(x)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET_MASK   (0x3FE00U)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT   (9U)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET(x)
#define	LCDIFV2_CSC_COEF0_C0_MASK   (0x1FFC0000U)
#define	LCDIFV2_CSC_COEF0_C0_SHIFT   (18U)
#define	LCDIFV2_CSC_COEF0_C0(x)
#define	LCDIFV2_CSC_COEF0_ENABLE_MASK   (0x40000000U)
#define	LCDIFV2_CSC_COEF0_ENABLE_SHIFT   (30U)
#define	LCDIFV2_CSC_COEF0_ENABLE(x)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK   (0x80000000U)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT   (31U)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE(x)
CSC_COEF1 - Color Space Conversion Coefficient Register 1
#define	LCDIFV2_CSC_COEF1_C4_MASK   (0x7FFU)
#define	LCDIFV2_CSC_COEF1_C4_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF1_C4(x)
#define	LCDIFV2_CSC_COEF1_C1_MASK   (0x7FF0000U)
#define	LCDIFV2_CSC_COEF1_C1_SHIFT   (16U)
#define	LCDIFV2_CSC_COEF1_C1(x)
CSC_COEF2 - Color Space Conversion Coefficient Register 2
#define	LCDIFV2_CSC_COEF2_C3_MASK   (0x7FFU)
#define	LCDIFV2_CSC_COEF2_C3_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF2_C3(x)
#define	LCDIFV2_CSC_COEF2_C2_MASK   (0x7FF0000U)
#define	LCDIFV2_CSC_COEF2_C2_SHIFT   (16U)
#define	LCDIFV2_CSC_COEF2_C2(x)
CLUT_LOAD - LCDIFv2 CLUT load Register
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK   (0x1U)
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT   (0U)
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK   (0x70U)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT   (4U)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x)
PCCCR - PC bus Cache control register
#define	LMEM_PCCCR_ENCACHE_MASK   (0x1U)
#define	LMEM_PCCCR_ENCACHE_SHIFT   (0U)
#define	LMEM_PCCCR_ENCACHE(x)
#define	LMEM_PCCCR_ENWRBUF_MASK   (0x2U)
#define	LMEM_PCCCR_ENWRBUF_SHIFT   (1U)
#define	LMEM_PCCCR_ENWRBUF(x)
#define	LMEM_PCCCR_PCCR2_MASK   (0x4U)
#define	LMEM_PCCCR_PCCR2_SHIFT   (2U)
#define	LMEM_PCCCR_PCCR2(x)
#define	LMEM_PCCCR_PCCR3_MASK   (0x8U)
#define	LMEM_PCCCR_PCCR3_SHIFT   (3U)
#define	LMEM_PCCCR_PCCR3(x)
#define	LMEM_PCCCR_INVW0_MASK   (0x1000000U)
#define	LMEM_PCCCR_INVW0_SHIFT   (24U)
#define	LMEM_PCCCR_INVW0(x)
#define	LMEM_PCCCR_PUSHW0_MASK   (0x2000000U)
#define	LMEM_PCCCR_PUSHW0_SHIFT   (25U)
#define	LMEM_PCCCR_PUSHW0(x)
#define	LMEM_PCCCR_INVW1_MASK   (0x4000000U)
#define	LMEM_PCCCR_INVW1_SHIFT   (26U)
#define	LMEM_PCCCR_INVW1(x)
#define	LMEM_PCCCR_PUSHW1_MASK   (0x8000000U)
#define	LMEM_PCCCR_PUSHW1_SHIFT   (27U)
#define	LMEM_PCCCR_PUSHW1(x)
#define	LMEM_PCCCR_GO_MASK   (0x80000000U)
#define	LMEM_PCCCR_GO_SHIFT   (31U)
#define	LMEM_PCCCR_GO(x)
PCCLCR - PC bus Cache line control register
#define	LMEM_PCCLCR_LGO_MASK   (0x1U)
#define	LMEM_PCCLCR_LGO_SHIFT   (0U)
#define	LMEM_PCCLCR_LGO(x)
#define	LMEM_PCCLCR_CACHEADDR_MASK   (0x3FFCU)
#define	LMEM_PCCLCR_CACHEADDR_SHIFT   (2U)
#define	LMEM_PCCLCR_CACHEADDR(x)
#define	LMEM_PCCLCR_WSEL_MASK   (0x4000U)
#define	LMEM_PCCLCR_WSEL_SHIFT   (14U)
#define	LMEM_PCCLCR_WSEL(x)
#define	LMEM_PCCLCR_TDSEL_MASK   (0x10000U)
#define	LMEM_PCCLCR_TDSEL_SHIFT   (16U)
#define	LMEM_PCCLCR_TDSEL(x)
#define	LMEM_PCCLCR_LCIVB_MASK   (0x100000U)
#define	LMEM_PCCLCR_LCIVB_SHIFT   (20U)
#define	LMEM_PCCLCR_LCIVB(x)
#define	LMEM_PCCLCR_LCIMB_MASK   (0x200000U)
#define	LMEM_PCCLCR_LCIMB_SHIFT   (21U)
#define	LMEM_PCCLCR_LCIMB(x)
#define	LMEM_PCCLCR_LCWAY_MASK   (0x400000U)
#define	LMEM_PCCLCR_LCWAY_SHIFT   (22U)
#define	LMEM_PCCLCR_LCWAY(x)
#define	LMEM_PCCLCR_LCMD_MASK   (0x3000000U)
#define	LMEM_PCCLCR_LCMD_SHIFT   (24U)
#define	LMEM_PCCLCR_LCMD(x)
#define	LMEM_PCCLCR_LADSEL_MASK   (0x4000000U)
#define	LMEM_PCCLCR_LADSEL_SHIFT   (26U)
#define	LMEM_PCCLCR_LADSEL(x)
#define	LMEM_PCCLCR_LACC_MASK   (0x8000000U)
#define	LMEM_PCCLCR_LACC_SHIFT   (27U)
#define	LMEM_PCCLCR_LACC(x)
PCCSAR - PC bus Cache search address register
#define	LMEM_PCCSAR_LGO_MASK   (0x1U)
#define	LMEM_PCCSAR_LGO_SHIFT   (0U)
#define	LMEM_PCCSAR_LGO(x)
#define	LMEM_PCCSAR_PHYADDR_MASK   (0xFFFFFFFEU)
#define	LMEM_PCCSAR_PHYADDR_SHIFT   (1U)
#define	LMEM_PCCSAR_PHYADDR(x)
PCCCVR - PC bus Cache read/write value register
#define	LMEM_PCCCVR_DATA_MASK   (0xFFFFFFFFU)
#define	LMEM_PCCCVR_DATA_SHIFT   (0U)
#define	LMEM_PCCCVR_DATA(x)
PSCCR - PS bus Cache control register
#define	LMEM_PSCCR_ENCACHE_MASK   (0x1U)
#define	LMEM_PSCCR_ENCACHE_SHIFT   (0U)
#define	LMEM_PSCCR_ENCACHE(x)
#define	LMEM_PSCCR_ENWRBUF_MASK   (0x2U)
#define	LMEM_PSCCR_ENWRBUF_SHIFT   (1U)
#define	LMEM_PSCCR_ENWRBUF(x)
#define	LMEM_PSCCR_PSCR2_MASK   (0x4U)
#define	LMEM_PSCCR_PSCR2_SHIFT   (2U)
#define	LMEM_PSCCR_PSCR2(x)
#define	LMEM_PSCCR_PSCR3_MASK   (0x8U)
#define	LMEM_PSCCR_PSCR3_SHIFT   (3U)
#define	LMEM_PSCCR_PSCR3(x)
#define	LMEM_PSCCR_INVW0_MASK   (0x1000000U)
#define	LMEM_PSCCR_INVW0_SHIFT   (24U)
#define	LMEM_PSCCR_INVW0(x)
#define	LMEM_PSCCR_PUSHW0_MASK   (0x2000000U)
#define	LMEM_PSCCR_PUSHW0_SHIFT   (25U)
#define	LMEM_PSCCR_PUSHW0(x)
#define	LMEM_PSCCR_INVW1_MASK   (0x4000000U)
#define	LMEM_PSCCR_INVW1_SHIFT   (26U)
#define	LMEM_PSCCR_INVW1(x)
#define	LMEM_PSCCR_PUSHW1_MASK   (0x8000000U)
#define	LMEM_PSCCR_PUSHW1_SHIFT   (27U)
#define	LMEM_PSCCR_PUSHW1(x)
#define	LMEM_PSCCR_GO_MASK   (0x80000000U)
#define	LMEM_PSCCR_GO_SHIFT   (31U)
#define	LMEM_PSCCR_GO(x)
PSCLCR - PS bus Cache line control register
#define	LMEM_PSCLCR_LGO_MASK   (0x1U)
#define	LMEM_PSCLCR_LGO_SHIFT   (0U)
#define	LMEM_PSCLCR_LGO(x)
#define	LMEM_PSCLCR_CACHEADDR_MASK   (0x3FFCU)
#define	LMEM_PSCLCR_CACHEADDR_SHIFT   (2U)
#define	LMEM_PSCLCR_CACHEADDR(x)
#define	LMEM_PSCLCR_WSEL_MASK   (0x4000U)
#define	LMEM_PSCLCR_WSEL_SHIFT   (14U)
#define	LMEM_PSCLCR_WSEL(x)
#define	LMEM_PSCLCR_TDSEL_MASK   (0x10000U)
#define	LMEM_PSCLCR_TDSEL_SHIFT   (16U)
#define	LMEM_PSCLCR_TDSEL(x)
#define	LMEM_PSCLCR_LCIVB_MASK   (0x100000U)
#define	LMEM_PSCLCR_LCIVB_SHIFT   (20U)
#define	LMEM_PSCLCR_LCIVB(x)
#define	LMEM_PSCLCR_LCIMB_MASK   (0x200000U)
#define	LMEM_PSCLCR_LCIMB_SHIFT   (21U)
#define	LMEM_PSCLCR_LCIMB(x)
#define	LMEM_PSCLCR_LCWAY_MASK   (0x400000U)
#define	LMEM_PSCLCR_LCWAY_SHIFT   (22U)
#define	LMEM_PSCLCR_LCWAY(x)
#define	LMEM_PSCLCR_LCMD_MASK   (0x3000000U)
#define	LMEM_PSCLCR_LCMD_SHIFT   (24U)
#define	LMEM_PSCLCR_LCMD(x)
#define	LMEM_PSCLCR_LADSEL_MASK   (0x4000000U)
#define	LMEM_PSCLCR_LADSEL_SHIFT   (26U)
#define	LMEM_PSCLCR_LADSEL(x)
#define	LMEM_PSCLCR_LACC_MASK   (0x8000000U)
#define	LMEM_PSCLCR_LACC_SHIFT   (27U)
#define	LMEM_PSCLCR_LACC(x)
PSCSAR - PS bus Cache search address register
#define	LMEM_PSCSAR_LGO_MASK   (0x1U)
#define	LMEM_PSCSAR_LGO_SHIFT   (0U)
#define	LMEM_PSCSAR_LGO(x)
#define	LMEM_PSCSAR_PHYADDR_MASK   (0xFFFFFFFEU)
#define	LMEM_PSCSAR_PHYADDR_SHIFT   (1U)
#define	LMEM_PSCSAR_PHYADDR(x)
PSCCVR - PS bus Cache read/write value register
#define	LMEM_PSCCVR_DATA_MASK   (0xFFFFFFFFU)
#define	LMEM_PSCCVR_DATA_SHIFT   (0U)
#define	LMEM_PSCCVR_DATA(x)
MCR - Master Control
#define	LPI2C_MCR_MEN_MASK   (0x1U)
#define	LPI2C_MCR_MEN_SHIFT   (0U)
#define	LPI2C_MCR_MEN(x)
#define	LPI2C_MCR_RST_MASK   (0x2U)
#define	LPI2C_MCR_RST_SHIFT   (1U)
#define	LPI2C_MCR_RST(x)
#define	LPI2C_MCR_DOZEN_MASK   (0x4U)
#define	LPI2C_MCR_DOZEN_SHIFT   (2U)
#define	LPI2C_MCR_DOZEN(x)
#define	LPI2C_MCR_DBGEN_MASK   (0x8U)
#define	LPI2C_MCR_DBGEN_SHIFT   (3U)
#define	LPI2C_MCR_DBGEN(x)
#define	LPI2C_MCR_RTF_MASK   (0x100U)
#define	LPI2C_MCR_RTF_SHIFT   (8U)
#define	LPI2C_MCR_RTF(x)
#define	LPI2C_MCR_RRF_MASK   (0x200U)
#define	LPI2C_MCR_RRF_SHIFT   (9U)
#define	LPI2C_MCR_RRF(x)
MSR - Master Status
#define	LPI2C_MSR_TDF_MASK   (0x1U)
#define	LPI2C_MSR_TDF_SHIFT   (0U)
#define	LPI2C_MSR_TDF(x)
#define	LPI2C_MSR_RDF_MASK   (0x2U)
#define	LPI2C_MSR_RDF_SHIFT   (1U)
#define	LPI2C_MSR_RDF(x)
#define	LPI2C_MSR_EPF_MASK   (0x100U)
#define	LPI2C_MSR_EPF_SHIFT   (8U)
#define	LPI2C_MSR_EPF(x)
#define	LPI2C_MSR_SDF_MASK   (0x200U)
#define	LPI2C_MSR_SDF_SHIFT   (9U)
#define	LPI2C_MSR_SDF(x)
#define	LPI2C_MSR_NDF_MASK   (0x400U)
#define	LPI2C_MSR_NDF_SHIFT   (10U)
#define	LPI2C_MSR_NDF(x)
#define	LPI2C_MSR_ALF_MASK   (0x800U)
#define	LPI2C_MSR_ALF_SHIFT   (11U)
#define	LPI2C_MSR_ALF(x)
#define	LPI2C_MSR_FEF_MASK   (0x1000U)
#define	LPI2C_MSR_FEF_SHIFT   (12U)
#define	LPI2C_MSR_FEF(x)
#define	LPI2C_MSR_PLTF_MASK   (0x2000U)
#define	LPI2C_MSR_PLTF_SHIFT   (13U)
#define	LPI2C_MSR_PLTF(x)
#define	LPI2C_MSR_DMF_MASK   (0x4000U)
#define	LPI2C_MSR_DMF_SHIFT   (14U)
#define	LPI2C_MSR_DMF(x)
#define	LPI2C_MSR_MBF_MASK   (0x1000000U)
#define	LPI2C_MSR_MBF_SHIFT   (24U)
#define	LPI2C_MSR_MBF(x)
#define	LPI2C_MSR_BBF_MASK   (0x2000000U)
#define	LPI2C_MSR_BBF_SHIFT   (25U)
#define	LPI2C_MSR_BBF(x)
MIER - Master Interrupt Enable
#define	LPI2C_MIER_TDIE_MASK   (0x1U)
#define	LPI2C_MIER_TDIE_SHIFT   (0U)
#define	LPI2C_MIER_TDIE(x)
#define	LPI2C_MIER_RDIE_MASK   (0x2U)
#define	LPI2C_MIER_RDIE_SHIFT   (1U)
#define	LPI2C_MIER_RDIE(x)
#define	LPI2C_MIER_EPIE_MASK   (0x100U)
#define	LPI2C_MIER_EPIE_SHIFT   (8U)
#define	LPI2C_MIER_EPIE(x)
#define	LPI2C_MIER_SDIE_MASK   (0x200U)
#define	LPI2C_MIER_SDIE_SHIFT   (9U)
#define	LPI2C_MIER_SDIE(x)
#define	LPI2C_MIER_NDIE_MASK   (0x400U)
#define	LPI2C_MIER_NDIE_SHIFT   (10U)
#define	LPI2C_MIER_NDIE(x)
#define	LPI2C_MIER_ALIE_MASK   (0x800U)
#define	LPI2C_MIER_ALIE_SHIFT   (11U)
#define	LPI2C_MIER_ALIE(x)
#define	LPI2C_MIER_FEIE_MASK   (0x1000U)
#define	LPI2C_MIER_FEIE_SHIFT   (12U)
#define	LPI2C_MIER_FEIE(x)
#define	LPI2C_MIER_PLTIE_MASK   (0x2000U)
#define	LPI2C_MIER_PLTIE_SHIFT   (13U)
#define	LPI2C_MIER_PLTIE(x)
#define	LPI2C_MIER_DMIE_MASK   (0x4000U)
#define	LPI2C_MIER_DMIE_SHIFT   (14U)
#define	LPI2C_MIER_DMIE(x)
MDER - Master DMA Enable
#define	LPI2C_MDER_TDDE_MASK   (0x1U)
#define	LPI2C_MDER_TDDE_SHIFT   (0U)
#define	LPI2C_MDER_TDDE(x)
#define	LPI2C_MDER_RDDE_MASK   (0x2U)
#define	LPI2C_MDER_RDDE_SHIFT   (1U)
#define	LPI2C_MDER_RDDE(x)
MCFGR0 - Master Configuration 0
#define	LPI2C_MCFGR0_HREN_MASK   (0x1U)
#define	LPI2C_MCFGR0_HREN_SHIFT   (0U)
#define	LPI2C_MCFGR0_HREN(x)
#define	LPI2C_MCFGR0_HRPOL_MASK   (0x2U)
#define	LPI2C_MCFGR0_HRPOL_SHIFT   (1U)
#define	LPI2C_MCFGR0_HRPOL(x)
#define	LPI2C_MCFGR0_HRSEL_MASK   (0x4U)
#define	LPI2C_MCFGR0_HRSEL_SHIFT   (2U)
#define	LPI2C_MCFGR0_HRSEL(x)
#define	LPI2C_MCFGR0_CIRFIFO_MASK   (0x100U)
#define	LPI2C_MCFGR0_CIRFIFO_SHIFT   (8U)
#define	LPI2C_MCFGR0_CIRFIFO(x)
#define	LPI2C_MCFGR0_RDMO_MASK   (0x200U)
#define	LPI2C_MCFGR0_RDMO_SHIFT   (9U)
#define	LPI2C_MCFGR0_RDMO(x)
MCFGR1 - Master Configuration 1
#define	LPI2C_MCFGR1_PRESCALE_MASK   (0x7U)
#define	LPI2C_MCFGR1_PRESCALE_SHIFT   (0U)
#define	LPI2C_MCFGR1_PRESCALE(x)
#define	LPI2C_MCFGR1_AUTOSTOP_MASK   (0x100U)
#define	LPI2C_MCFGR1_AUTOSTOP_SHIFT   (8U)
#define	LPI2C_MCFGR1_AUTOSTOP(x)
#define	LPI2C_MCFGR1_IGNACK_MASK   (0x200U)
#define	LPI2C_MCFGR1_IGNACK_SHIFT   (9U)
#define	LPI2C_MCFGR1_IGNACK(x)
#define	LPI2C_MCFGR1_TIMECFG_MASK   (0x400U)
#define	LPI2C_MCFGR1_TIMECFG_SHIFT   (10U)
#define	LPI2C_MCFGR1_TIMECFG(x)
#define	LPI2C_MCFGR1_MATCFG_MASK   (0x70000U)
#define	LPI2C_MCFGR1_MATCFG_SHIFT   (16U)
#define	LPI2C_MCFGR1_MATCFG(x)
#define	LPI2C_MCFGR1_PINCFG_MASK   (0x7000000U)
#define	LPI2C_MCFGR1_PINCFG_SHIFT   (24U)
#define	LPI2C_MCFGR1_PINCFG(x)
MCFGR2 - Master Configuration 2
#define	LPI2C_MCFGR2_BUSIDLE_MASK   (0xFFFU)
#define	LPI2C_MCFGR2_BUSIDLE_SHIFT   (0U)
#define	LPI2C_MCFGR2_BUSIDLE(x)
#define	LPI2C_MCFGR2_FILTSCL_MASK   (0xF0000U)
#define	LPI2C_MCFGR2_FILTSCL_SHIFT   (16U)
#define	LPI2C_MCFGR2_FILTSCL(x)
#define	LPI2C_MCFGR2_FILTSDA_MASK   (0xF000000U)
#define	LPI2C_MCFGR2_FILTSDA_SHIFT   (24U)
#define	LPI2C_MCFGR2_FILTSDA(x)
MCFGR3 - Master Configuration 3
#define	LPI2C_MCFGR3_PINLOW_MASK   (0xFFF00U)
#define	LPI2C_MCFGR3_PINLOW_SHIFT   (8U)
#define	LPI2C_MCFGR3_PINLOW(x)
MDMR - Master Data Match
#define	LPI2C_MDMR_MATCH0_MASK   (0xFFU)
#define	LPI2C_MDMR_MATCH0_SHIFT   (0U)
#define	LPI2C_MDMR_MATCH0(x)
#define	LPI2C_MDMR_MATCH1_MASK   (0xFF0000U)
#define	LPI2C_MDMR_MATCH1_SHIFT   (16U)
#define	LPI2C_MDMR_MATCH1(x)
MCCR0 - Master Clock Configuration 0
#define	LPI2C_MCCR0_CLKLO_MASK   (0x3FU)
#define	LPI2C_MCCR0_CLKLO_SHIFT   (0U)
#define	LPI2C_MCCR0_CLKLO(x)
#define	LPI2C_MCCR0_CLKHI_MASK   (0x3F00U)
#define	LPI2C_MCCR0_CLKHI_SHIFT   (8U)
#define	LPI2C_MCCR0_CLKHI(x)
#define	LPI2C_MCCR0_SETHOLD_MASK   (0x3F0000U)
#define	LPI2C_MCCR0_SETHOLD_SHIFT   (16U)
#define	LPI2C_MCCR0_SETHOLD(x)
#define	LPI2C_MCCR0_DATAVD_MASK   (0x3F000000U)
#define	LPI2C_MCCR0_DATAVD_SHIFT   (24U)
#define	LPI2C_MCCR0_DATAVD(x)
MCCR1 - Master Clock Configuration 1
#define	LPI2C_MCCR1_CLKLO_MASK   (0x3FU)
#define	LPI2C_MCCR1_CLKLO_SHIFT   (0U)
#define	LPI2C_MCCR1_CLKLO(x)
#define	LPI2C_MCCR1_CLKHI_MASK   (0x3F00U)
#define	LPI2C_MCCR1_CLKHI_SHIFT   (8U)
#define	LPI2C_MCCR1_CLKHI(x)
#define	LPI2C_MCCR1_SETHOLD_MASK   (0x3F0000U)
#define	LPI2C_MCCR1_SETHOLD_SHIFT   (16U)
#define	LPI2C_MCCR1_SETHOLD(x)
#define	LPI2C_MCCR1_DATAVD_MASK   (0x3F000000U)
#define	LPI2C_MCCR1_DATAVD_SHIFT   (24U)
#define	LPI2C_MCCR1_DATAVD(x)
MFCR - Master FIFO Control
#define	LPI2C_MFCR_TXWATER_MASK   (0x3U)
#define	LPI2C_MFCR_TXWATER_SHIFT   (0U)
#define	LPI2C_MFCR_TXWATER(x)
#define	LPI2C_MFCR_RXWATER_MASK   (0x30000U)
#define	LPI2C_MFCR_RXWATER_SHIFT   (16U)
#define	LPI2C_MFCR_RXWATER(x)
MFSR - Master FIFO Status
#define	LPI2C_MFSR_TXCOUNT_MASK   (0x7U)
#define	LPI2C_MFSR_TXCOUNT_SHIFT   (0U)
#define	LPI2C_MFSR_TXCOUNT(x)
#define	LPI2C_MFSR_RXCOUNT_MASK   (0x70000U)
#define	LPI2C_MFSR_RXCOUNT_SHIFT   (16U)
#define	LPI2C_MFSR_RXCOUNT(x)
MTDR - Master Transmit Data
#define	LPI2C_MTDR_DATA_MASK   (0xFFU)
#define	LPI2C_MTDR_DATA_SHIFT   (0U)
#define	LPI2C_MTDR_DATA(x)
#define	LPI2C_MTDR_CMD_MASK   (0x700U)
#define	LPI2C_MTDR_CMD_SHIFT   (8U)
#define	LPI2C_MTDR_CMD(x)
MRDR - Master Receive Data
#define	LPI2C_MRDR_DATA_MASK   (0xFFU)
#define	LPI2C_MRDR_DATA_SHIFT   (0U)
#define	LPI2C_MRDR_DATA(x)
#define	LPI2C_MRDR_RXEMPTY_MASK   (0x4000U)
#define	LPI2C_MRDR_RXEMPTY_SHIFT   (14U)
#define	LPI2C_MRDR_RXEMPTY(x)
SCR - Slave Control
#define	LPI2C_SCR_SEN_MASK   (0x1U)
#define	LPI2C_SCR_SEN_SHIFT   (0U)
#define	LPI2C_SCR_SEN(x)
#define	LPI2C_SCR_RST_MASK   (0x2U)
#define	LPI2C_SCR_RST_SHIFT   (1U)
#define	LPI2C_SCR_RST(x)
#define	LPI2C_SCR_FILTEN_MASK   (0x10U)
#define	LPI2C_SCR_FILTEN_SHIFT   (4U)
#define	LPI2C_SCR_FILTEN(x)
#define	LPI2C_SCR_FILTDZ_MASK   (0x20U)
#define	LPI2C_SCR_FILTDZ_SHIFT   (5U)
#define	LPI2C_SCR_FILTDZ(x)
#define	LPI2C_SCR_RTF_MASK   (0x100U)
#define	LPI2C_SCR_RTF_SHIFT   (8U)
#define	LPI2C_SCR_RTF(x)
#define	LPI2C_SCR_RRF_MASK   (0x200U)
#define	LPI2C_SCR_RRF_SHIFT   (9U)
#define	LPI2C_SCR_RRF(x)
SSR - Slave Status
#define	LPI2C_SSR_TDF_MASK   (0x1U)
#define	LPI2C_SSR_TDF_SHIFT   (0U)
#define	LPI2C_SSR_TDF(x)
#define	LPI2C_SSR_RDF_MASK   (0x2U)
#define	LPI2C_SSR_RDF_SHIFT   (1U)
#define	LPI2C_SSR_RDF(x)
#define	LPI2C_SSR_AVF_MASK   (0x4U)
#define	LPI2C_SSR_AVF_SHIFT   (2U)
#define	LPI2C_SSR_AVF(x)
#define	LPI2C_SSR_TAF_MASK   (0x8U)
#define	LPI2C_SSR_TAF_SHIFT   (3U)
#define	LPI2C_SSR_TAF(x)
#define	LPI2C_SSR_RSF_MASK   (0x100U)
#define	LPI2C_SSR_RSF_SHIFT   (8U)
#define	LPI2C_SSR_RSF(x)
#define	LPI2C_SSR_SDF_MASK   (0x200U)
#define	LPI2C_SSR_SDF_SHIFT   (9U)
#define	LPI2C_SSR_SDF(x)
#define	LPI2C_SSR_BEF_MASK   (0x400U)
#define	LPI2C_SSR_BEF_SHIFT   (10U)
#define	LPI2C_SSR_BEF(x)
#define	LPI2C_SSR_FEF_MASK   (0x800U)
#define	LPI2C_SSR_FEF_SHIFT   (11U)
#define	LPI2C_SSR_FEF(x)
#define	LPI2C_SSR_AM0F_MASK   (0x1000U)
#define	LPI2C_SSR_AM0F_SHIFT   (12U)
#define	LPI2C_SSR_AM0F(x)
#define	LPI2C_SSR_AM1F_MASK   (0x2000U)
#define	LPI2C_SSR_AM1F_SHIFT   (13U)
#define	LPI2C_SSR_AM1F(x)
#define	LPI2C_SSR_GCF_MASK   (0x4000U)
#define	LPI2C_SSR_GCF_SHIFT   (14U)
#define	LPI2C_SSR_GCF(x)
#define	LPI2C_SSR_SARF_MASK   (0x8000U)
#define	LPI2C_SSR_SARF_SHIFT   (15U)
#define	LPI2C_SSR_SARF(x)
#define	LPI2C_SSR_SBF_MASK   (0x1000000U)
#define	LPI2C_SSR_SBF_SHIFT   (24U)
#define	LPI2C_SSR_SBF(x)
#define	LPI2C_SSR_BBF_MASK   (0x2000000U)
#define	LPI2C_SSR_BBF_SHIFT   (25U)
#define	LPI2C_SSR_BBF(x)
SIER - Slave Interrupt Enable
#define	LPI2C_SIER_TDIE_MASK   (0x1U)
#define	LPI2C_SIER_TDIE_SHIFT   (0U)
#define	LPI2C_SIER_TDIE(x)
#define	LPI2C_SIER_RDIE_MASK   (0x2U)
#define	LPI2C_SIER_RDIE_SHIFT   (1U)
#define	LPI2C_SIER_RDIE(x)
#define	LPI2C_SIER_AVIE_MASK   (0x4U)
#define	LPI2C_SIER_AVIE_SHIFT   (2U)
#define	LPI2C_SIER_AVIE(x)
#define	LPI2C_SIER_TAIE_MASK   (0x8U)
#define	LPI2C_SIER_TAIE_SHIFT   (3U)
#define	LPI2C_SIER_TAIE(x)
#define	LPI2C_SIER_RSIE_MASK   (0x100U)
#define	LPI2C_SIER_RSIE_SHIFT   (8U)
#define	LPI2C_SIER_RSIE(x)
#define	LPI2C_SIER_SDIE_MASK   (0x200U)
#define	LPI2C_SIER_SDIE_SHIFT   (9U)
#define	LPI2C_SIER_SDIE(x)
#define	LPI2C_SIER_BEIE_MASK   (0x400U)
#define	LPI2C_SIER_BEIE_SHIFT   (10U)
#define	LPI2C_SIER_BEIE(x)
#define	LPI2C_SIER_FEIE_MASK   (0x800U)
#define	LPI2C_SIER_FEIE_SHIFT   (11U)
#define	LPI2C_SIER_FEIE(x)
#define	LPI2C_SIER_AM0IE_MASK   (0x1000U)
#define	LPI2C_SIER_AM0IE_SHIFT   (12U)
#define	LPI2C_SIER_AM0IE(x)
#define	LPI2C_SIER_AM1IE_MASK   (0x2000U)
#define	LPI2C_SIER_AM1IE_SHIFT   (13U)
#define	LPI2C_SIER_AM1IE(x)
#define	LPI2C_SIER_GCIE_MASK   (0x4000U)
#define	LPI2C_SIER_GCIE_SHIFT   (14U)
#define	LPI2C_SIER_GCIE(x)
#define	LPI2C_SIER_SARIE_MASK   (0x8000U)
#define	LPI2C_SIER_SARIE_SHIFT   (15U)
#define	LPI2C_SIER_SARIE(x)
SDER - Slave DMA Enable
#define	LPI2C_SDER_TDDE_MASK   (0x1U)
#define	LPI2C_SDER_TDDE_SHIFT   (0U)
#define	LPI2C_SDER_TDDE(x)
#define	LPI2C_SDER_RDDE_MASK   (0x2U)
#define	LPI2C_SDER_RDDE_SHIFT   (1U)
#define	LPI2C_SDER_RDDE(x)
#define	LPI2C_SDER_AVDE_MASK   (0x4U)
#define	LPI2C_SDER_AVDE_SHIFT   (2U)
#define	LPI2C_SDER_AVDE(x)
SCFGR1 - Slave Configuration 1
#define	LPI2C_SCFGR1_ADRSTALL_MASK   (0x1U)
#define	LPI2C_SCFGR1_ADRSTALL_SHIFT   (0U)
#define	LPI2C_SCFGR1_ADRSTALL(x)
#define	LPI2C_SCFGR1_RXSTALL_MASK   (0x2U)
#define	LPI2C_SCFGR1_RXSTALL_SHIFT   (1U)
#define	LPI2C_SCFGR1_RXSTALL(x)
#define	LPI2C_SCFGR1_TXDSTALL_MASK   (0x4U)
#define	LPI2C_SCFGR1_TXDSTALL_SHIFT   (2U)
#define	LPI2C_SCFGR1_TXDSTALL(x)
#define	LPI2C_SCFGR1_ACKSTALL_MASK   (0x8U)
#define	LPI2C_SCFGR1_ACKSTALL_SHIFT   (3U)
#define	LPI2C_SCFGR1_ACKSTALL(x)
#define	LPI2C_SCFGR1_GCEN_MASK   (0x100U)
#define	LPI2C_SCFGR1_GCEN_SHIFT   (8U)
#define	LPI2C_SCFGR1_GCEN(x)
#define	LPI2C_SCFGR1_SAEN_MASK   (0x200U)
#define	LPI2C_SCFGR1_SAEN_SHIFT   (9U)
#define	LPI2C_SCFGR1_SAEN(x)
#define	LPI2C_SCFGR1_TXCFG_MASK   (0x400U)
#define	LPI2C_SCFGR1_TXCFG_SHIFT   (10U)
#define	LPI2C_SCFGR1_TXCFG(x)
#define	LPI2C_SCFGR1_RXCFG_MASK   (0x800U)
#define	LPI2C_SCFGR1_RXCFG_SHIFT   (11U)
#define	LPI2C_SCFGR1_RXCFG(x)
#define	LPI2C_SCFGR1_IGNACK_MASK   (0x1000U)
#define	LPI2C_SCFGR1_IGNACK_SHIFT   (12U)
#define	LPI2C_SCFGR1_IGNACK(x)
#define	LPI2C_SCFGR1_HSMEN_MASK   (0x2000U)
#define	LPI2C_SCFGR1_HSMEN_SHIFT   (13U)
#define	LPI2C_SCFGR1_HSMEN(x)
#define	LPI2C_SCFGR1_ADDRCFG_MASK   (0x70000U)
#define	LPI2C_SCFGR1_ADDRCFG_SHIFT   (16U)
#define	LPI2C_SCFGR1_ADDRCFG(x)
SCFGR2 - Slave Configuration 2
#define	LPI2C_SCFGR2_CLKHOLD_MASK   (0xFU)
#define	LPI2C_SCFGR2_CLKHOLD_SHIFT   (0U)
#define	LPI2C_SCFGR2_CLKHOLD(x)
#define	LPI2C_SCFGR2_DATAVD_MASK   (0x3F00U)
#define	LPI2C_SCFGR2_DATAVD_SHIFT   (8U)
#define	LPI2C_SCFGR2_DATAVD(x)
#define	LPI2C_SCFGR2_FILTSCL_MASK   (0xF0000U)
#define	LPI2C_SCFGR2_FILTSCL_SHIFT   (16U)
#define	LPI2C_SCFGR2_FILTSCL(x)
#define	LPI2C_SCFGR2_FILTSDA_MASK   (0xF000000U)
#define	LPI2C_SCFGR2_FILTSDA_SHIFT   (24U)
#define	LPI2C_SCFGR2_FILTSDA(x)
SAMR - Slave Address Match
#define	LPI2C_SAMR_ADDR0_MASK   (0x7FEU)
#define	LPI2C_SAMR_ADDR0_SHIFT   (1U)
#define	LPI2C_SAMR_ADDR0(x)
#define	LPI2C_SAMR_ADDR1_MASK   (0x7FE0000U)
#define	LPI2C_SAMR_ADDR1_SHIFT   (17U)
#define	LPI2C_SAMR_ADDR1(x)
SASR - Slave Address Status
#define	LPI2C_SASR_RADDR_MASK   (0x7FFU)
#define	LPI2C_SASR_RADDR_SHIFT   (0U)
#define	LPI2C_SASR_RADDR(x)
#define	LPI2C_SASR_ANV_MASK   (0x4000U)
#define	LPI2C_SASR_ANV_SHIFT   (14U)
#define	LPI2C_SASR_ANV(x)
STAR - Slave Transmit ACK
#define	LPI2C_STAR_TXNACK_MASK   (0x1U)
#define	LPI2C_STAR_TXNACK_SHIFT   (0U)
#define	LPI2C_STAR_TXNACK(x)
STDR - Slave Transmit Data
#define	LPI2C_STDR_DATA_MASK   (0xFFU)
#define	LPI2C_STDR_DATA_SHIFT   (0U)
#define	LPI2C_STDR_DATA(x)
SRDR - Slave Receive Data
#define	LPI2C_SRDR_DATA_MASK   (0xFFU)
#define	LPI2C_SRDR_DATA_SHIFT   (0U)
#define	LPI2C_SRDR_DATA(x)
#define	LPI2C_SRDR_RXEMPTY_MASK   (0x4000U)
#define	LPI2C_SRDR_RXEMPTY_SHIFT   (14U)
#define	LPI2C_SRDR_RXEMPTY(x)
#define	LPI2C_SRDR_SOF_MASK   (0x8000U)
#define	LPI2C_SRDR_SOF_SHIFT   (15U)
#define	LPI2C_SRDR_SOF(x)
SR - Status
#define	LPSPI_SR_TDF_MASK   (0x1U)
#define	LPSPI_SR_TDF_SHIFT   (0U)
#define	LPSPI_SR_TDF(x)
#define	LPSPI_SR_RDF_MASK   (0x2U)
#define	LPSPI_SR_RDF_SHIFT   (1U)
#define	LPSPI_SR_RDF(x)
#define	LPSPI_SR_WCF_MASK   (0x100U)
#define	LPSPI_SR_WCF_SHIFT   (8U)
#define	LPSPI_SR_WCF(x)
#define	LPSPI_SR_FCF_MASK   (0x200U)
#define	LPSPI_SR_FCF_SHIFT   (9U)
#define	LPSPI_SR_FCF(x)
#define	LPSPI_SR_TCF_MASK   (0x400U)
#define	LPSPI_SR_TCF_SHIFT   (10U)
#define	LPSPI_SR_TCF(x)
#define	LPSPI_SR_TEF_MASK   (0x800U)
#define	LPSPI_SR_TEF_SHIFT   (11U)
#define	LPSPI_SR_TEF(x)
#define	LPSPI_SR_REF_MASK   (0x1000U)
#define	LPSPI_SR_REF_SHIFT   (12U)
#define	LPSPI_SR_REF(x)
#define	LPSPI_SR_DMF_MASK   (0x2000U)
#define	LPSPI_SR_DMF_SHIFT   (13U)
#define	LPSPI_SR_DMF(x)
#define	LPSPI_SR_MBF_MASK   (0x1000000U)
#define	LPSPI_SR_MBF_SHIFT   (24U)
#define	LPSPI_SR_MBF(x)
IER - Interrupt Enable
#define	LPSPI_IER_TDIE_MASK   (0x1U)
#define	LPSPI_IER_TDIE_SHIFT   (0U)
#define	LPSPI_IER_TDIE(x)
#define	LPSPI_IER_RDIE_MASK   (0x2U)
#define	LPSPI_IER_RDIE_SHIFT   (1U)
#define	LPSPI_IER_RDIE(x)
#define	LPSPI_IER_WCIE_MASK   (0x100U)
#define	LPSPI_IER_WCIE_SHIFT   (8U)
#define	LPSPI_IER_WCIE(x)
#define	LPSPI_IER_FCIE_MASK   (0x200U)
#define	LPSPI_IER_FCIE_SHIFT   (9U)
#define	LPSPI_IER_FCIE(x)
#define	LPSPI_IER_TCIE_MASK   (0x400U)
#define	LPSPI_IER_TCIE_SHIFT   (10U)
#define	LPSPI_IER_TCIE(x)
#define	LPSPI_IER_TEIE_MASK   (0x800U)
#define	LPSPI_IER_TEIE_SHIFT   (11U)
#define	LPSPI_IER_TEIE(x)
#define	LPSPI_IER_REIE_MASK   (0x1000U)
#define	LPSPI_IER_REIE_SHIFT   (12U)
#define	LPSPI_IER_REIE(x)
#define	LPSPI_IER_DMIE_MASK   (0x2000U)
#define	LPSPI_IER_DMIE_SHIFT   (13U)
#define	LPSPI_IER_DMIE(x)
DER - DMA Enable
#define	LPSPI_DER_TDDE_MASK   (0x1U)
#define	LPSPI_DER_TDDE_SHIFT   (0U)
#define	LPSPI_DER_TDDE(x)
#define	LPSPI_DER_RDDE_MASK   (0x2U)
#define	LPSPI_DER_RDDE_SHIFT   (1U)
#define	LPSPI_DER_RDDE(x)
CFGR0 - Configuration 0
#define	LPSPI_CFGR0_CIRFIFO_MASK   (0x100U)
#define	LPSPI_CFGR0_CIRFIFO_SHIFT   (8U)
#define	LPSPI_CFGR0_CIRFIFO(x)
#define	LPSPI_CFGR0_RDMO_MASK   (0x200U)
#define	LPSPI_CFGR0_RDMO_SHIFT   (9U)
#define	LPSPI_CFGR0_RDMO(x)
CFGR1 - Configuration 1
#define	LPSPI_CFGR1_MASTER_MASK   (0x1U)
#define	LPSPI_CFGR1_MASTER_SHIFT   (0U)
#define	LPSPI_CFGR1_MASTER(x)
#define	LPSPI_CFGR1_SAMPLE_MASK   (0x2U)
#define	LPSPI_CFGR1_SAMPLE_SHIFT   (1U)
#define	LPSPI_CFGR1_SAMPLE(x)
#define	LPSPI_CFGR1_AUTOPCS_MASK   (0x4U)
#define	LPSPI_CFGR1_AUTOPCS_SHIFT   (2U)
#define	LPSPI_CFGR1_AUTOPCS(x)
#define	LPSPI_CFGR1_NOSTALL_MASK   (0x8U)
#define	LPSPI_CFGR1_NOSTALL_SHIFT   (3U)
#define	LPSPI_CFGR1_NOSTALL(x)
#define	LPSPI_CFGR1_PCSPOL_MASK   (0xF00U)
#define	LPSPI_CFGR1_PCSPOL_SHIFT   (8U)
#define	LPSPI_CFGR1_PCSPOL(x)
#define	LPSPI_CFGR1_MATCFG_MASK   (0x70000U)
#define	LPSPI_CFGR1_MATCFG_SHIFT   (16U)
#define	LPSPI_CFGR1_MATCFG(x)
#define	LPSPI_CFGR1_PINCFG_MASK   (0x3000000U)
#define	LPSPI_CFGR1_PINCFG_SHIFT   (24U)
#define	LPSPI_CFGR1_PINCFG(x)
#define	LPSPI_CFGR1_OUTCFG_MASK   (0x4000000U)
#define	LPSPI_CFGR1_OUTCFG_SHIFT   (26U)
#define	LPSPI_CFGR1_OUTCFG(x)
#define	LPSPI_CFGR1_PCSCFG_MASK   (0x8000000U)
#define	LPSPI_CFGR1_PCSCFG_SHIFT   (27U)
#define	LPSPI_CFGR1_PCSCFG(x)
DMR0 - Data Match 0
#define	LPSPI_DMR0_MATCH0_MASK   (0xFFFFFFFFU)
#define	LPSPI_DMR0_MATCH0_SHIFT   (0U)
#define	LPSPI_DMR0_MATCH0(x)
DMR1 - Data Match 1
#define	LPSPI_DMR1_MATCH1_MASK   (0xFFFFFFFFU)
#define	LPSPI_DMR1_MATCH1_SHIFT   (0U)
#define	LPSPI_DMR1_MATCH1(x)
CCR - Clock Configuration
#define	LPSPI_CCR_SCKDIV_MASK   (0xFFU)
#define	LPSPI_CCR_SCKDIV_SHIFT   (0U)
#define	LPSPI_CCR_SCKDIV(x)
#define	LPSPI_CCR_DBT_MASK   (0xFF00U)
#define	LPSPI_CCR_DBT_SHIFT   (8U)
#define	LPSPI_CCR_DBT(x)
#define	LPSPI_CCR_PCSSCK_MASK   (0xFF0000U)
#define	LPSPI_CCR_PCSSCK_SHIFT   (16U)
#define	LPSPI_CCR_PCSSCK(x)
#define	LPSPI_CCR_SCKPCS_MASK   (0xFF000000U)
#define	LPSPI_CCR_SCKPCS_SHIFT   (24U)
#define	LPSPI_CCR_SCKPCS(x)
FCR - FIFO Control
#define	LPSPI_FCR_TXWATER_MASK   (0xFU)
#define	LPSPI_FCR_TXWATER_SHIFT   (0U)
#define	LPSPI_FCR_TXWATER(x)
#define	LPSPI_FCR_RXWATER_MASK   (0xF0000U)
#define	LPSPI_FCR_RXWATER_SHIFT   (16U)
#define	LPSPI_FCR_RXWATER(x)
FSR - FIFO Status
#define	LPSPI_FSR_TXCOUNT_MASK   (0x1FU)
#define	LPSPI_FSR_TXCOUNT_SHIFT   (0U)
#define	LPSPI_FSR_TXCOUNT(x)
#define	LPSPI_FSR_RXCOUNT_MASK   (0x1F0000U)
#define	LPSPI_FSR_RXCOUNT_SHIFT   (16U)
#define	LPSPI_FSR_RXCOUNT(x)
TCR - Transmit Command
#define	LPSPI_TCR_FRAMESZ_MASK   (0xFFFU)
#define	LPSPI_TCR_FRAMESZ_SHIFT   (0U)
#define	LPSPI_TCR_FRAMESZ(x)
#define	LPSPI_TCR_WIDTH_MASK   (0x30000U)
#define	LPSPI_TCR_WIDTH_SHIFT   (16U)
#define	LPSPI_TCR_WIDTH(x)
#define	LPSPI_TCR_TXMSK_MASK   (0x40000U)
#define	LPSPI_TCR_TXMSK_SHIFT   (18U)
#define	LPSPI_TCR_TXMSK(x)
#define	LPSPI_TCR_RXMSK_MASK   (0x80000U)
#define	LPSPI_TCR_RXMSK_SHIFT   (19U)
#define	LPSPI_TCR_RXMSK(x)
#define	LPSPI_TCR_CONTC_MASK   (0x100000U)
#define	LPSPI_TCR_CONTC_SHIFT   (20U)
#define	LPSPI_TCR_CONTC(x)
#define	LPSPI_TCR_CONT_MASK   (0x200000U)
#define	LPSPI_TCR_CONT_SHIFT   (21U)
#define	LPSPI_TCR_CONT(x)
#define	LPSPI_TCR_BYSW_MASK   (0x400000U)
#define	LPSPI_TCR_BYSW_SHIFT   (22U)
#define	LPSPI_TCR_BYSW(x)
#define	LPSPI_TCR_LSBF_MASK   (0x800000U)
#define	LPSPI_TCR_LSBF_SHIFT   (23U)
#define	LPSPI_TCR_LSBF(x)
#define	LPSPI_TCR_PCS_MASK   (0x3000000U)
#define	LPSPI_TCR_PCS_SHIFT   (24U)
#define	LPSPI_TCR_PCS(x)
#define	LPSPI_TCR_PRESCALE_MASK   (0x38000000U)
#define	LPSPI_TCR_PRESCALE_SHIFT   (27U)
#define	LPSPI_TCR_PRESCALE(x)
#define	LPSPI_TCR_CPHA_MASK   (0x40000000U)
#define	LPSPI_TCR_CPHA_SHIFT   (30U)
#define	LPSPI_TCR_CPHA(x)
#define	LPSPI_TCR_CPOL_MASK   (0x80000000U)
#define	LPSPI_TCR_CPOL_SHIFT   (31U)
#define	LPSPI_TCR_CPOL(x)
RSR - Receive Status
#define	LPSPI_RSR_SOF_MASK   (0x1U)
#define	LPSPI_RSR_SOF_SHIFT   (0U)
#define	LPSPI_RSR_SOF(x)
#define	LPSPI_RSR_RXEMPTY_MASK   (0x2U)
#define	LPSPI_RSR_RXEMPTY_SHIFT   (1U)
#define	LPSPI_RSR_RXEMPTY(x)
GLOBAL - LPUART Global Register
#define	LPUART_GLOBAL_RST_MASK   (0x2U)
#define	LPUART_GLOBAL_RST_SHIFT   (1U)
#define	LPUART_GLOBAL_RST(x)
PINCFG - LPUART Pin Configuration Register
#define	LPUART_PINCFG_TRGSEL_MASK   (0x3U)
#define	LPUART_PINCFG_TRGSEL_SHIFT   (0U)
#define	LPUART_PINCFG_TRGSEL(x)
BAUD - LPUART Baud Rate Register
#define	LPUART_BAUD_SBR_MASK   (0x1FFFU)
#define	LPUART_BAUD_SBR_SHIFT   (0U)
#define	LPUART_BAUD_SBR(x)
#define	LPUART_BAUD_SBNS_MASK   (0x2000U)
#define	LPUART_BAUD_SBNS_SHIFT   (13U)
#define	LPUART_BAUD_SBNS(x)
#define	LPUART_BAUD_RXEDGIE_MASK   (0x4000U)
#define	LPUART_BAUD_RXEDGIE_SHIFT   (14U)
#define	LPUART_BAUD_RXEDGIE(x)
#define	LPUART_BAUD_LBKDIE_MASK   (0x8000U)
#define	LPUART_BAUD_LBKDIE_SHIFT   (15U)
#define	LPUART_BAUD_LBKDIE(x)
#define	LPUART_BAUD_RESYNCDIS_MASK   (0x10000U)
#define	LPUART_BAUD_RESYNCDIS_SHIFT   (16U)
#define	LPUART_BAUD_RESYNCDIS(x)
#define	LPUART_BAUD_BOTHEDGE_MASK   (0x20000U)
#define	LPUART_BAUD_BOTHEDGE_SHIFT   (17U)
#define	LPUART_BAUD_BOTHEDGE(x)
#define	LPUART_BAUD_MATCFG_MASK   (0xC0000U)
#define	LPUART_BAUD_MATCFG_SHIFT   (18U)
#define	LPUART_BAUD_MATCFG(x)
#define	LPUART_BAUD_RDMAE_MASK   (0x200000U)
#define	LPUART_BAUD_RDMAE_SHIFT   (21U)
#define	LPUART_BAUD_RDMAE(x)
#define	LPUART_BAUD_TDMAE_MASK   (0x800000U)
#define	LPUART_BAUD_TDMAE_SHIFT   (23U)
#define	LPUART_BAUD_TDMAE(x)
#define	LPUART_BAUD_OSR_MASK   (0x1F000000U)
#define	LPUART_BAUD_OSR_SHIFT   (24U)
#define	LPUART_BAUD_OSR(x)
#define	LPUART_BAUD_M10_MASK   (0x20000000U)
#define	LPUART_BAUD_M10_SHIFT   (29U)
#define	LPUART_BAUD_M10(x)
#define	LPUART_BAUD_MAEN2_MASK   (0x40000000U)
#define	LPUART_BAUD_MAEN2_SHIFT   (30U)
#define	LPUART_BAUD_MAEN2(x)
#define	LPUART_BAUD_MAEN1_MASK   (0x80000000U)
#define	LPUART_BAUD_MAEN1_SHIFT   (31U)
#define	LPUART_BAUD_MAEN1(x)
STAT - LPUART Status Register
#define	LPUART_STAT_MA2F_MASK   (0x4000U)
#define	LPUART_STAT_MA2F_SHIFT   (14U)
#define	LPUART_STAT_MA2F(x)
#define	LPUART_STAT_MA1F_MASK   (0x8000U)
#define	LPUART_STAT_MA1F_SHIFT   (15U)
#define	LPUART_STAT_MA1F(x)
#define	LPUART_STAT_PF_MASK   (0x10000U)
#define	LPUART_STAT_PF_SHIFT   (16U)
#define	LPUART_STAT_PF(x)
#define	LPUART_STAT_FE_MASK   (0x20000U)
#define	LPUART_STAT_FE_SHIFT   (17U)
#define	LPUART_STAT_FE(x)
#define	LPUART_STAT_NF_MASK   (0x40000U)
#define	LPUART_STAT_NF_SHIFT   (18U)
#define	LPUART_STAT_NF(x)
#define	LPUART_STAT_OR_MASK   (0x80000U)
#define	LPUART_STAT_OR_SHIFT   (19U)
#define	LPUART_STAT_OR(x)
#define	LPUART_STAT_IDLE_MASK   (0x100000U)
#define	LPUART_STAT_IDLE_SHIFT   (20U)
#define	LPUART_STAT_IDLE(x)
#define	LPUART_STAT_RDRF_MASK   (0x200000U)
#define	LPUART_STAT_RDRF_SHIFT   (21U)
#define	LPUART_STAT_RDRF(x)
#define	LPUART_STAT_TC_MASK   (0x400000U)
#define	LPUART_STAT_TC_SHIFT   (22U)
#define	LPUART_STAT_TC(x)
#define	LPUART_STAT_TDRE_MASK   (0x800000U)
#define	LPUART_STAT_TDRE_SHIFT   (23U)
#define	LPUART_STAT_TDRE(x)
#define	LPUART_STAT_RAF_MASK   (0x1000000U)
#define	LPUART_STAT_RAF_SHIFT   (24U)
#define	LPUART_STAT_RAF(x)
#define	LPUART_STAT_LBKDE_MASK   (0x2000000U)
#define	LPUART_STAT_LBKDE_SHIFT   (25U)
#define	LPUART_STAT_LBKDE(x)
#define	LPUART_STAT_BRK13_MASK   (0x4000000U)
#define	LPUART_STAT_BRK13_SHIFT   (26U)
#define	LPUART_STAT_BRK13(x)
#define	LPUART_STAT_RWUID_MASK   (0x8000000U)
#define	LPUART_STAT_RWUID_SHIFT   (27U)
#define	LPUART_STAT_RWUID(x)
#define	LPUART_STAT_RXINV_MASK   (0x10000000U)
#define	LPUART_STAT_RXINV_SHIFT   (28U)
#define	LPUART_STAT_RXINV(x)
#define	LPUART_STAT_MSBF_MASK   (0x20000000U)
#define	LPUART_STAT_MSBF_SHIFT   (29U)
#define	LPUART_STAT_MSBF(x)
#define	LPUART_STAT_RXEDGIF_MASK   (0x40000000U)
#define	LPUART_STAT_RXEDGIF_SHIFT   (30U)
#define	LPUART_STAT_RXEDGIF(x)
#define	LPUART_STAT_LBKDIF_MASK   (0x80000000U)
#define	LPUART_STAT_LBKDIF_SHIFT   (31U)
#define	LPUART_STAT_LBKDIF(x)
CTRL - LPUART Control Register
#define	LPUART_CTRL_PT_MASK   (0x1U)
#define	LPUART_CTRL_PT_SHIFT   (0U)
#define	LPUART_CTRL_PT(x)
#define	LPUART_CTRL_PE_MASK   (0x2U)
#define	LPUART_CTRL_PE_SHIFT   (1U)
#define	LPUART_CTRL_PE(x)
#define	LPUART_CTRL_ILT_MASK   (0x4U)
#define	LPUART_CTRL_ILT_SHIFT   (2U)
#define	LPUART_CTRL_ILT(x)
#define	LPUART_CTRL_WAKE_MASK   (0x8U)
#define	LPUART_CTRL_WAKE_SHIFT   (3U)
#define	LPUART_CTRL_WAKE(x)
#define	LPUART_CTRL_M_MASK   (0x10U)
#define	LPUART_CTRL_M_SHIFT   (4U)
#define	LPUART_CTRL_M(x)
#define	LPUART_CTRL_RSRC_MASK   (0x20U)
#define	LPUART_CTRL_RSRC_SHIFT   (5U)
#define	LPUART_CTRL_RSRC(x)
#define	LPUART_CTRL_DOZEEN_MASK   (0x40U)
#define	LPUART_CTRL_DOZEEN_SHIFT   (6U)
#define	LPUART_CTRL_DOZEEN(x)
#define	LPUART_CTRL_LOOPS_MASK   (0x80U)
#define	LPUART_CTRL_LOOPS_SHIFT   (7U)
#define	LPUART_CTRL_LOOPS(x)
#define	LPUART_CTRL_IDLECFG_MASK   (0x700U)
#define	LPUART_CTRL_IDLECFG_SHIFT   (8U)
#define	LPUART_CTRL_IDLECFG(x)
#define	LPUART_CTRL_M7_MASK   (0x800U)
#define	LPUART_CTRL_M7_SHIFT   (11U)
#define	LPUART_CTRL_M7(x)
#define	LPUART_CTRL_MA2IE_MASK   (0x4000U)
#define	LPUART_CTRL_MA2IE_SHIFT   (14U)
#define	LPUART_CTRL_MA2IE(x)
#define	LPUART_CTRL_MA1IE_MASK   (0x8000U)
#define	LPUART_CTRL_MA1IE_SHIFT   (15U)
#define	LPUART_CTRL_MA1IE(x)
#define	LPUART_CTRL_SBK_MASK   (0x10000U)
#define	LPUART_CTRL_SBK_SHIFT   (16U)
#define	LPUART_CTRL_SBK(x)
#define	LPUART_CTRL_RWU_MASK   (0x20000U)
#define	LPUART_CTRL_RWU_SHIFT   (17U)
#define	LPUART_CTRL_RWU(x)
#define	LPUART_CTRL_RE_MASK   (0x40000U)
#define	LPUART_CTRL_RE_SHIFT   (18U)
#define	LPUART_CTRL_RE(x)
#define	LPUART_CTRL_TE_MASK   (0x80000U)
#define	LPUART_CTRL_TE_SHIFT   (19U)
#define	LPUART_CTRL_TE(x)
#define	LPUART_CTRL_ILIE_MASK   (0x100000U)
#define	LPUART_CTRL_ILIE_SHIFT   (20U)
#define	LPUART_CTRL_ILIE(x)
#define	LPUART_CTRL_RIE_MASK   (0x200000U)
#define	LPUART_CTRL_RIE_SHIFT   (21U)
#define	LPUART_CTRL_RIE(x)
#define	LPUART_CTRL_TCIE_MASK   (0x400000U)
#define	LPUART_CTRL_TCIE_SHIFT   (22U)
#define	LPUART_CTRL_TCIE(x)
#define	LPUART_CTRL_TIE_MASK   (0x800000U)
#define	LPUART_CTRL_TIE_SHIFT   (23U)
#define	LPUART_CTRL_TIE(x)
#define	LPUART_CTRL_PEIE_MASK   (0x1000000U)
#define	LPUART_CTRL_PEIE_SHIFT   (24U)
#define	LPUART_CTRL_PEIE(x)
#define	LPUART_CTRL_FEIE_MASK   (0x2000000U)
#define	LPUART_CTRL_FEIE_SHIFT   (25U)
#define	LPUART_CTRL_FEIE(x)
#define	LPUART_CTRL_NEIE_MASK   (0x4000000U)
#define	LPUART_CTRL_NEIE_SHIFT   (26U)
#define	LPUART_CTRL_NEIE(x)
#define	LPUART_CTRL_ORIE_MASK   (0x8000000U)
#define	LPUART_CTRL_ORIE_SHIFT   (27U)
#define	LPUART_CTRL_ORIE(x)
#define	LPUART_CTRL_TXINV_MASK   (0x10000000U)
#define	LPUART_CTRL_TXINV_SHIFT   (28U)
#define	LPUART_CTRL_TXINV(x)
#define	LPUART_CTRL_TXDIR_MASK   (0x20000000U)
#define	LPUART_CTRL_TXDIR_SHIFT   (29U)
#define	LPUART_CTRL_TXDIR(x)
#define	LPUART_CTRL_R9T8_MASK   (0x40000000U)
#define	LPUART_CTRL_R9T8_SHIFT   (30U)
#define	LPUART_CTRL_R9T8(x)
#define	LPUART_CTRL_R8T9_MASK   (0x80000000U)
#define	LPUART_CTRL_R8T9_SHIFT   (31U)
#define	LPUART_CTRL_R8T9(x)
DATA - LPUART Data Register
#define	LPUART_DATA_R0T0_MASK   (0x1U)
#define	LPUART_DATA_R0T0_SHIFT   (0U)
#define	LPUART_DATA_R0T0(x)
#define	LPUART_DATA_R1T1_MASK   (0x2U)
#define	LPUART_DATA_R1T1_SHIFT   (1U)
#define	LPUART_DATA_R1T1(x)
#define	LPUART_DATA_R2T2_MASK   (0x4U)
#define	LPUART_DATA_R2T2_SHIFT   (2U)
#define	LPUART_DATA_R2T2(x)
#define	LPUART_DATA_R3T3_MASK   (0x8U)
#define	LPUART_DATA_R3T3_SHIFT   (3U)
#define	LPUART_DATA_R3T3(x)
#define	LPUART_DATA_R4T4_MASK   (0x10U)
#define	LPUART_DATA_R4T4_SHIFT   (4U)
#define	LPUART_DATA_R4T4(x)
#define	LPUART_DATA_R5T5_MASK   (0x20U)
#define	LPUART_DATA_R5T5_SHIFT   (5U)
#define	LPUART_DATA_R5T5(x)
#define	LPUART_DATA_R6T6_MASK   (0x40U)
#define	LPUART_DATA_R6T6_SHIFT   (6U)
#define	LPUART_DATA_R6T6(x)
#define	LPUART_DATA_R7T7_MASK   (0x80U)
#define	LPUART_DATA_R7T7_SHIFT   (7U)
#define	LPUART_DATA_R7T7(x)
#define	LPUART_DATA_R8T8_MASK   (0x100U)
#define	LPUART_DATA_R8T8_SHIFT   (8U)
#define	LPUART_DATA_R8T8(x)
#define	LPUART_DATA_R9T9_MASK   (0x200U)
#define	LPUART_DATA_R9T9_SHIFT   (9U)
#define	LPUART_DATA_R9T9(x)
#define	LPUART_DATA_IDLINE_MASK   (0x800U)
#define	LPUART_DATA_IDLINE_SHIFT   (11U)
#define	LPUART_DATA_IDLINE(x)
#define	LPUART_DATA_RXEMPT_MASK   (0x1000U)
#define	LPUART_DATA_RXEMPT_SHIFT   (12U)
#define	LPUART_DATA_RXEMPT(x)
#define	LPUART_DATA_FRETSC_MASK   (0x2000U)
#define	LPUART_DATA_FRETSC_SHIFT   (13U)
#define	LPUART_DATA_FRETSC(x)
#define	LPUART_DATA_PARITYE_MASK   (0x4000U)
#define	LPUART_DATA_PARITYE_SHIFT   (14U)
#define	LPUART_DATA_PARITYE(x)
#define	LPUART_DATA_NOISY_MASK   (0x8000U)
#define	LPUART_DATA_NOISY_SHIFT   (15U)
#define	LPUART_DATA_NOISY(x)
MATCH - LPUART Match Address Register
#define	LPUART_MATCH_MA1_MASK   (0x3FFU)
#define	LPUART_MATCH_MA1_SHIFT   (0U)
#define	LPUART_MATCH_MA1(x)
#define	LPUART_MATCH_MA2_MASK   (0x3FF0000U)
#define	LPUART_MATCH_MA2_SHIFT   (16U)
#define	LPUART_MATCH_MA2(x)
MODIR - LPUART Modem IrDA Register
#define	LPUART_MODIR_TXCTSE_MASK   (0x1U)
#define	LPUART_MODIR_TXCTSE_SHIFT   (0U)
#define	LPUART_MODIR_TXCTSE(x)
#define	LPUART_MODIR_TXRTSE_MASK   (0x2U)
#define	LPUART_MODIR_TXRTSE_SHIFT   (1U)
#define	LPUART_MODIR_TXRTSE(x)
#define	LPUART_MODIR_TXRTSPOL_MASK   (0x4U)
#define	LPUART_MODIR_TXRTSPOL_SHIFT   (2U)
#define	LPUART_MODIR_TXRTSPOL(x)
#define	LPUART_MODIR_RXRTSE_MASK   (0x8U)
#define	LPUART_MODIR_RXRTSE_SHIFT   (3U)
#define	LPUART_MODIR_RXRTSE(x)
#define	LPUART_MODIR_TXCTSC_MASK   (0x10U)
#define	LPUART_MODIR_TXCTSC_SHIFT   (4U)
#define	LPUART_MODIR_TXCTSC(x)
#define	LPUART_MODIR_TXCTSSRC_MASK   (0x20U)
#define	LPUART_MODIR_TXCTSSRC_SHIFT   (5U)
#define	LPUART_MODIR_TXCTSSRC(x)
#define	LPUART_MODIR_RTSWATER_MASK   (0x300U)
#define	LPUART_MODIR_RTSWATER_SHIFT   (8U)
#define	LPUART_MODIR_RTSWATER(x)
#define	LPUART_MODIR_TNP_MASK   (0x30000U)
#define	LPUART_MODIR_TNP_SHIFT   (16U)
#define	LPUART_MODIR_TNP(x)
#define	LPUART_MODIR_IREN_MASK   (0x40000U)
#define	LPUART_MODIR_IREN_SHIFT   (18U)
#define	LPUART_MODIR_IREN(x)
FIFO - LPUART FIFO Register
#define	LPUART_FIFO_RXFIFOSIZE_MASK   (0x7U)
#define	LPUART_FIFO_RXFIFOSIZE_SHIFT   (0U)
#define	LPUART_FIFO_RXFIFOSIZE(x)
#define	LPUART_FIFO_RXFE_MASK   (0x8U)
#define	LPUART_FIFO_RXFE_SHIFT   (3U)
#define	LPUART_FIFO_RXFE(x)
#define	LPUART_FIFO_TXFIFOSIZE_MASK   (0x70U)
#define	LPUART_FIFO_TXFIFOSIZE_SHIFT   (4U)
#define	LPUART_FIFO_TXFIFOSIZE(x)
#define	LPUART_FIFO_TXFE_MASK   (0x80U)
#define	LPUART_FIFO_TXFE_SHIFT   (7U)
#define	LPUART_FIFO_TXFE(x)
#define	LPUART_FIFO_RXUFE_MASK   (0x100U)
#define	LPUART_FIFO_RXUFE_SHIFT   (8U)
#define	LPUART_FIFO_RXUFE(x)
#define	LPUART_FIFO_TXOFE_MASK   (0x200U)
#define	LPUART_FIFO_TXOFE_SHIFT   (9U)
#define	LPUART_FIFO_TXOFE(x)
#define	LPUART_FIFO_RXIDEN_MASK   (0x1C00U)
#define	LPUART_FIFO_RXIDEN_SHIFT   (10U)
#define	LPUART_FIFO_RXIDEN(x)
#define	LPUART_FIFO_RXFLUSH_MASK   (0x4000U)
#define	LPUART_FIFO_RXFLUSH_SHIFT   (14U)
#define	LPUART_FIFO_RXFLUSH(x)
#define	LPUART_FIFO_TXFLUSH_MASK   (0x8000U)
#define	LPUART_FIFO_TXFLUSH_SHIFT   (15U)
#define	LPUART_FIFO_TXFLUSH(x)
#define	LPUART_FIFO_RXUF_MASK   (0x10000U)
#define	LPUART_FIFO_RXUF_SHIFT   (16U)
#define	LPUART_FIFO_RXUF(x)
#define	LPUART_FIFO_TXOF_MASK   (0x20000U)
#define	LPUART_FIFO_TXOF_SHIFT   (17U)
#define	LPUART_FIFO_TXOF(x)
#define	LPUART_FIFO_RXEMPT_MASK   (0x400000U)
#define	LPUART_FIFO_RXEMPT_SHIFT   (22U)
#define	LPUART_FIFO_RXEMPT(x)
#define	LPUART_FIFO_TXEMPT_MASK   (0x800000U)
#define	LPUART_FIFO_TXEMPT_SHIFT   (23U)
#define	LPUART_FIFO_TXEMPT(x)
WATER - LPUART Watermark Register
#define	LPUART_WATER_TXWATER_MASK   (0x3U)
#define	LPUART_WATER_TXWATER_SHIFT   (0U)
#define	LPUART_WATER_TXWATER(x)
#define	LPUART_WATER_TXCOUNT_MASK   (0x700U)
#define	LPUART_WATER_TXCOUNT_SHIFT   (8U)
#define	LPUART_WATER_TXCOUNT(x)
#define	LPUART_WATER_RXWATER_MASK   (0x30000U)
#define	LPUART_WATER_RXWATER_SHIFT   (16U)
#define	LPUART_WATER_RXWATER(x)
#define	LPUART_WATER_RXCOUNT_MASK   (0x7000000U)
#define	LPUART_WATER_RXCOUNT_SHIFT   (24U)
#define	LPUART_WATER_RXCOUNT(x)
PLREV - SoC-defined platform revision
#define	MCM_PLREV_PLREV_MASK   (0xFFFFU)
#define	MCM_PLREV_PLREV_SHIFT   (0U)
#define	MCM_PLREV_PLREV(x)
PCT - Processor core type
#define	MCM_PCT_PCT_MASK   (0xFFFFU)
#define	MCM_PCT_PCT_SHIFT   (0U)
#define	MCM_PCT_PCT(x)
MEMCFG - Memory configuration
#define	MCM_MEMCFG_TCRAMUSZ_MASK   (0x3CU)
#define	MCM_MEMCFG_TCRAMUSZ_SHIFT   (2U)
#define	MCM_MEMCFG_TCRAMUSZ(x)
#define	MCM_MEMCFG_TCRAMLSZ_MASK   (0xF00U)
#define	MCM_MEMCFG_TCRAMLSZ_SHIFT   (8U)
#define	MCM_MEMCFG_TCRAMLSZ(x)
PLASC - Crossbar Switch (AXBS) Slave Configuration
#define	MCM_PLASC_ASC_MASK   (0xFFU)
#define	MCM_PLASC_ASC_SHIFT   (0U)
#define	MCM_PLASC_ASC(x)
PLAMC - Crossbar Switch (AXBS) Master Configuration
#define	MCM_PLAMC_AMC_MASK   (0xFFU)
#define	MCM_PLAMC_AMC_SHIFT   (0U)
#define	MCM_PLAMC_AMC(x)
CR - Control Register
#define	MCM_CR_STATUS_MASK   (0x1FFU)
#define	MCM_CR_STATUS_SHIFT   (0U)
#define	MCM_CR_STATUS(x)
#define	MCM_CR_CBRR_MASK   (0x200U)
#define	MCM_CR_CBRR_SHIFT   (9U)
#define	MCM_CR_CBRR(x)
#define	MCM_CR_STCMAP_MASK   (0x3000000U)
#define	MCM_CR_STCMAP_SHIFT   (24U)
#define	MCM_CR_STCMAP(x)
#define	MCM_CR_STCMWP_MASK   (0x4000000U)
#define	MCM_CR_STCMWP_SHIFT   (26U)
#define	MCM_CR_STCMWP(x)
#define	MCM_CR_CTCMAP_MASK   (0x30000000U)
#define	MCM_CR_CTCMAP_SHIFT   (28U)
#define	MCM_CR_CTCMAP(x)
#define	MCM_CR_CTCMWP_MASK   (0x40000000U)
#define	MCM_CR_CTCMWP_SHIFT   (30U)
#define	MCM_CR_CTCMWP(x)
ISCR - Interrupt Status and Control Register
#define	MCM_ISCR_CWBER_MASK   (0x10U)
#define	MCM_ISCR_CWBER_SHIFT   (4U)
#define	MCM_ISCR_CWBER(x)
#define	MCM_ISCR_CWBEE_MASK   (0x100000U)
#define	MCM_ISCR_CWBEE_SHIFT   (20U)
#define	MCM_ISCR_CWBEE(x)
ISCR - Interrupt Status and Control Register
#define	MCM_ISCR_FIOC_MASK   (0x100U)
#define	MCM_ISCR_FIOC_SHIFT   (8U)
#define	MCM_ISCR_FIOC(x)
#define	MCM_ISCR_FDZC_MASK   (0x200U)
#define	MCM_ISCR_FDZC_SHIFT   (9U)
#define	MCM_ISCR_FDZC(x)
#define	MCM_ISCR_FOFC_MASK   (0x400U)
#define	MCM_ISCR_FOFC_SHIFT   (10U)
#define	MCM_ISCR_FOFC(x)
#define	MCM_ISCR_FUFC_MASK   (0x800U)
#define	MCM_ISCR_FUFC_SHIFT   (11U)
#define	MCM_ISCR_FUFC(x)
#define	MCM_ISCR_FIXC_MASK   (0x1000U)
#define	MCM_ISCR_FIXC_SHIFT   (12U)
#define	MCM_ISCR_FIXC(x)
#define	MCM_ISCR_FIDC_MASK   (0x8000U)
#define	MCM_ISCR_FIDC_SHIFT   (15U)
#define	MCM_ISCR_FIDC(x)
#define	MCM_ISCR_FIOCE_MASK   (0x1000000U)
#define	MCM_ISCR_FIOCE_SHIFT   (24U)
#define	MCM_ISCR_FIOCE(x)
#define	MCM_ISCR_FDZCE_MASK   (0x2000000U)
#define	MCM_ISCR_FDZCE_SHIFT   (25U)
#define	MCM_ISCR_FDZCE(x)
#define	MCM_ISCR_FOFCE_MASK   (0x4000000U)
#define	MCM_ISCR_FOFCE_SHIFT   (26U)
#define	MCM_ISCR_FOFCE(x)
#define	MCM_ISCR_FUFCE_MASK   (0x8000000U)
#define	MCM_ISCR_FUFCE_SHIFT   (27U)
#define	MCM_ISCR_FUFCE(x)
#define	MCM_ISCR_FIXCE_MASK   (0x10000000U)
#define	MCM_ISCR_FIXCE_SHIFT   (28U)
#define	MCM_ISCR_FIXCE(x)
#define	MCM_ISCR_FIDCE_MASK   (0x80000000U)
#define	MCM_ISCR_FIDCE_SHIFT   (31U)
#define	MCM_ISCR_FIDCE(x)
FADR - Fault address register
#define	MCM_FADR_ADDRESS_MASK   (0xFFFFFFFFU)
#define	MCM_FADR_ADDRESS_SHIFT   (0U)
#define	MCM_FADR_ADDRESS(x)
FATR - Fault attributes register
#define	MCM_FATR_BEDA_MASK   (0x1U)
#define	MCM_FATR_BEDA_SHIFT   (0U)
#define	MCM_FATR_BEDA(x)
#define	MCM_FATR_BEMD_MASK   (0x2U)
#define	MCM_FATR_BEMD_SHIFT   (1U)
#define	MCM_FATR_BEMD(x)
#define	MCM_FATR_BESZ_MASK   (0x30U)
#define	MCM_FATR_BESZ_SHIFT   (4U)
#define	MCM_FATR_BESZ(x)
#define	MCM_FATR_BEWT_MASK   (0x80U)
#define	MCM_FATR_BEWT_SHIFT   (7U)
#define	MCM_FATR_BEWT(x)
#define	MCM_FATR_BEMN_MASK   (0xF00U)
#define	MCM_FATR_BEMN_SHIFT   (8U)
#define	MCM_FATR_BEMN(x)
#define	MCM_FATR_BEOVR_MASK   (0x80000000U)
#define	MCM_FATR_BEOVR_SHIFT   (31U)
#define	MCM_FATR_BEOVR(x)
FDR - Fault data register
#define	MCM_FDR_DATA_MASK   (0xFFFFFFFFU)
#define	MCM_FDR_DATA_SHIFT   (0U)
#define	MCM_FDR_DATA(x)
LMDR - Local Memory Descriptor Register
#define	MCM_LMDR_CF0_MASK   (0xFU)
#define	MCM_LMDR_CF0_SHIFT   (0U)
#define	MCM_LMDR_CF0(x)
#define	MCM_LMDR_CF1_MASK   (0xF0U)
#define	MCM_LMDR_CF1_SHIFT   (4U)
#define	MCM_LMDR_CF1(x)
#define	MCM_LMDR_MT_MASK   (0xE000U)
#define	MCM_LMDR_MT_SHIFT   (13U)
#define	MCM_LMDR_MT(x)
#define	MCM_LMDR_RO_MASK   (0x10000U)
#define	MCM_LMDR_RO_SHIFT   (16U)
#define	MCM_LMDR_RO(x)
#define	MCM_LMDR_DPW_MASK   (0xE0000U)
#define	MCM_LMDR_DPW_SHIFT   (17U)
#define	MCM_LMDR_DPW(x)
#define	MCM_LMDR_WY_MASK   (0xF00000U)
#define	MCM_LMDR_WY_SHIFT   (20U)
#define	MCM_LMDR_WY(x)
#define	MCM_LMDR_LMSZ_MASK   (0xF000000U)
#define	MCM_LMDR_LMSZ_SHIFT   (24U)
#define	MCM_LMDR_LMSZ(x)
#define	MCM_LMDR_LMSZH_MASK   (0x10000000U)
#define	MCM_LMDR_LMSZH_SHIFT   (28U)
#define	MCM_LMDR_LMSZH(x)
#define	MCM_LMDR_V_MASK   (0x80000000U)
#define	MCM_LMDR_V_SHIFT   (31U)
#define	MCM_LMDR_V(x)
LMPECR - LMEM Parity & ECC Control Register
#define	MCM_LMPECR_ERNCR_MASK   (0x1U)
#define	MCM_LMPECR_ERNCR_SHIFT   (0U)
#define	MCM_LMPECR_ERNCR(x)
#define	MCM_LMPECR_ERNCI_MASK   (0x2U)
#define	MCM_LMPECR_ERNCI_SHIFT   (1U)
#define	MCM_LMPECR_ERNCI(x)
#define	MCM_LMPECR_ER1BR_MASK   (0x100U)
#define	MCM_LMPECR_ER1BR_SHIFT   (8U)
#define	MCM_LMPECR_ER1BR(x)
#define	MCM_LMPECR_ER1BI_MASK   (0x200U)
#define	MCM_LMPECR_ER1BI_SHIFT   (9U)
#define	MCM_LMPECR_ER1BI(x)
#define	MCM_LMPECR_ECPR_MASK   (0x100000U)
#define	MCM_LMPECR_ECPR_SHIFT   (20U)
#define	MCM_LMPECR_ECPR(x)
#define	MCM_LMPECR_ECPI_MASK   (0x200000U)
#define	MCM_LMPECR_ECPI_SHIFT   (21U)
#define	MCM_LMPECR_ECPI(x)
LMPEIR - LMEM Parity & ECC Interrupt Register
#define	MCM_LMPEIR_ENC_MASK   (0xFFU)
#define	MCM_LMPEIR_ENC_SHIFT   (0U)
#define	MCM_LMPEIR_ENC(x)
#define	MCM_LMPEIR_E1B_MASK   (0xFF00U)
#define	MCM_LMPEIR_E1B_SHIFT   (8U)
#define	MCM_LMPEIR_E1B(x)
#define	MCM_LMPEIR_PE_MASK   (0xFF0000U)
#define	MCM_LMPEIR_PE_SHIFT   (16U)
#define	MCM_LMPEIR_PE(x)
#define	MCM_LMPEIR_PEELOC_MASK   (0x1F000000U)
#define	MCM_LMPEIR_PEELOC_SHIFT   (24U)
#define	MCM_LMPEIR_PEELOC(x)
#define	MCM_LMPEIR_V_MASK   (0x80000000U)
#define	MCM_LMPEIR_V_SHIFT   (31U)
#define	MCM_LMPEIR_V(x)
LMFAR - LMEM Fault Address Register
#define	MCM_LMFAR_EFADD_MASK   (0xFFFFFFFFU)
#define	MCM_LMFAR_EFADD_SHIFT   (0U)
#define	MCM_LMFAR_EFADD(x)
LMFATR - LMEM Fault Attribute Register
#define	MCM_LMFATR_PEFPRT_MASK   (0xFU)
#define	MCM_LMFATR_PEFPRT_SHIFT   (0U)
#define	MCM_LMFATR_PEFPRT(x)
#define	MCM_LMFATR_PEFSIZE_MASK   (0x70U)
#define	MCM_LMFATR_PEFSIZE_SHIFT   (4U)
#define	MCM_LMFATR_PEFSIZE(x)
#define	MCM_LMFATR_PEFW_MASK   (0x80U)
#define	MCM_LMFATR_PEFW_SHIFT   (7U)
#define	MCM_LMFATR_PEFW(x)
#define	MCM_LMFATR_PEFMST_MASK   (0xFF00U)
#define	MCM_LMFATR_PEFMST_SHIFT   (8U)
#define	MCM_LMFATR_PEFMST(x)
#define	MCM_LMFATR_WORDID_MASK   (0x1000000U)
#define	MCM_LMFATR_WORDID_SHIFT   (24U)
#define	MCM_LMFATR_WORDID(x)
#define	MCM_LMFATR_OVR_MASK   (0x80000000U)
#define	MCM_LMFATR_OVR_SHIFT   (31U)
#define	MCM_LMFATR_OVR(x)
LMFDHR - LMEM Fault Data High Register
#define	MCM_LMFDHR_PEFDH_MASK   (0xFFFFFFFFU)
#define	MCM_LMFDHR_PEFDH_SHIFT   (0U)
#define	MCM_LMFDHR_PEFDH(x)
LMFDLR - LMEM Fault Data Low Register
#define	MCM_LMFDLR_PEFDL_MASK   (0xFFFFFFFFU)
#define	MCM_LMFDLR_PEFDL_SHIFT   (0U)
#define	MCM_LMFDLR_PEFDL(x)
ERR_STATUS - Error Interrupt Status Register
#define	MECC_ERR_STATUS_SINGLE_ERR0_MASK   (0x1U)
#define	MECC_ERR_STATUS_SINGLE_ERR0_SHIFT   (0U)
#define	MECC_ERR_STATUS_SINGLE_ERR0(x)
#define	MECC_ERR_STATUS_SINGLE_ERR1_MASK   (0x2U)
#define	MECC_ERR_STATUS_SINGLE_ERR1_SHIFT   (1U)
#define	MECC_ERR_STATUS_SINGLE_ERR1(x)
#define	MECC_ERR_STATUS_SINGLE_ERR2_MASK   (0x4U)
#define	MECC_ERR_STATUS_SINGLE_ERR2_SHIFT   (2U)
#define	MECC_ERR_STATUS_SINGLE_ERR2(x)
#define	MECC_ERR_STATUS_SINGLE_ERR3_MASK   (0x8U)
#define	MECC_ERR_STATUS_SINGLE_ERR3_SHIFT   (3U)
#define	MECC_ERR_STATUS_SINGLE_ERR3(x)
#define	MECC_ERR_STATUS_MULTI_ERR0_MASK   (0x10U)
#define	MECC_ERR_STATUS_MULTI_ERR0_SHIFT   (4U)
#define	MECC_ERR_STATUS_MULTI_ERR0(x)
#define	MECC_ERR_STATUS_MULTI_ERR1_MASK   (0x20U)
#define	MECC_ERR_STATUS_MULTI_ERR1_SHIFT   (5U)
#define	MECC_ERR_STATUS_MULTI_ERR1(x)
#define	MECC_ERR_STATUS_MULTI_ERR2_MASK   (0x40U)
#define	MECC_ERR_STATUS_MULTI_ERR2_SHIFT   (6U)
#define	MECC_ERR_STATUS_MULTI_ERR2(x)
#define	MECC_ERR_STATUS_MULTI_ERR3_MASK   (0x80U)
#define	MECC_ERR_STATUS_MULTI_ERR3_SHIFT   (7U)
#define	MECC_ERR_STATUS_MULTI_ERR3(x)
#define	MECC_ERR_STATUS_STRB_ERR0_MASK   (0x100U)
#define	MECC_ERR_STATUS_STRB_ERR0_SHIFT   (8U)
#define	MECC_ERR_STATUS_STRB_ERR0(x)
#define	MECC_ERR_STATUS_STRB_ERR1_MASK   (0x200U)
#define	MECC_ERR_STATUS_STRB_ERR1_SHIFT   (9U)
#define	MECC_ERR_STATUS_STRB_ERR1(x)
#define	MECC_ERR_STATUS_STRB_ERR2_MASK   (0x400U)
#define	MECC_ERR_STATUS_STRB_ERR2_SHIFT   (10U)
#define	MECC_ERR_STATUS_STRB_ERR2(x)
#define	MECC_ERR_STATUS_STRB_ERR3_MASK   (0x800U)
#define	MECC_ERR_STATUS_STRB_ERR3_SHIFT   (11U)
#define	MECC_ERR_STATUS_STRB_ERR3(x)
#define	MECC_ERR_STATUS_ADDR_ERR0_MASK   (0x1000U)
#define	MECC_ERR_STATUS_ADDR_ERR0_SHIFT   (12U)
#define	MECC_ERR_STATUS_ADDR_ERR0(x)
#define	MECC_ERR_STATUS_ADDR_ERR1_MASK   (0x2000U)
#define	MECC_ERR_STATUS_ADDR_ERR1_SHIFT   (13U)
#define	MECC_ERR_STATUS_ADDR_ERR1(x)
#define	MECC_ERR_STATUS_ADDR_ERR2_MASK   (0x4000U)
#define	MECC_ERR_STATUS_ADDR_ERR2_SHIFT   (14U)
#define	MECC_ERR_STATUS_ADDR_ERR2(x)
#define	MECC_ERR_STATUS_ADDR_ERR3_MASK   (0x8000U)
#define	MECC_ERR_STATUS_ADDR_ERR3_SHIFT   (15U)
#define	MECC_ERR_STATUS_ADDR_ERR3(x)
#define	XECC_ERR_STATUS_SINGLE_ERR_MASK   (0x1U)
#define	XECC_ERR_STATUS_SINGLE_ERR_SHIFT   (0U)
#define	XECC_ERR_STATUS_SINGLE_ERR(x)
#define	XECC_ERR_STATUS_MULTI_ERR_MASK   (0x2U)
#define	XECC_ERR_STATUS_MULTI_ERR_SHIFT   (1U)
#define	XECC_ERR_STATUS_MULTI_ERR(x)
#define	XECC_ERR_STATUS_Reserved1_MASK   (0xFFFFFFFCU)
#define	XECC_ERR_STATUS_Reserved1_SHIFT   (2U)
#define	XECC_ERR_STATUS_Reserved1(x)
ERR_STAT_EN - Error Interrupt Status Enable Register
#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK   (0x1U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT   (0U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x)
#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK   (0x2U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT   (1U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x)
#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK   (0x4U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT   (2U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x)
#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK   (0x8U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT   (3U)
#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x)
#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK   (0x10U)
#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT   (4U)
#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x)
#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK   (0x20U)
#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT   (5U)
#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x)
#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK   (0x40U)
#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT   (6U)
#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x)
#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK   (0x80U)
#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT   (7U)
#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x)
#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK   (0x100U)
#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT   (8U)
#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x)
#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK   (0x200U)
#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT   (9U)
#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x)
#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK   (0x400U)
#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT   (10U)
#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x)
#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK   (0x800U)
#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT   (11U)
#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x)
#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK   (0x1000U)
#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT   (12U)
#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x)
#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK   (0x2000U)
#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT   (13U)
#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x)
#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK   (0x4000U)
#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT   (14U)
#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x)
#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK   (0x8000U)
#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT   (15U)
#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x)
#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK   (0x1U)
#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT   (0U)
#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x)
#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK   (0x2U)
#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT   (1U)
#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x)
#define	XECC_ERR_STAT_EN_Reserved1_MASK   (0xFFFFFFFCU)
#define	XECC_ERR_STAT_EN_Reserved1_SHIFT   (2U)
#define	XECC_ERR_STAT_EN_Reserved1(x)
ERR_SIG_EN - Error Interrupt Enable Register
#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK   (0x1U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT   (0U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x)
#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK   (0x2U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT   (1U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x)
#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK   (0x4U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT   (2U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x)
#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK   (0x8U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT   (3U)
#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x)
#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK   (0x10U)
#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT   (4U)
#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x)
#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK   (0x20U)
#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT   (5U)
#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x)
#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK   (0x40U)
#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT   (6U)
#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x)
#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK   (0x80U)
#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT   (7U)
#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x)
#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK   (0x100U)
#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT   (8U)
#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x)
#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK   (0x200U)
#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT   (9U)
#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x)
#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK   (0x400U)
#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT   (10U)
#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x)
#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK   (0x800U)
#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT   (11U)
#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x)
#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK   (0x1000U)
#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT   (12U)
#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x)
#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK   (0x2000U)
#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT   (13U)
#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x)
#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK   (0x4000U)
#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT   (14U)
#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x)
#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK   (0x8000U)
#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT   (15U)
#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x)
#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK   (0x1U)
#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT   (0U)
#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x)
#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK   (0x2U)
#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT   (1U)
#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x)
#define	XECC_ERR_SIG_EN_Reserved1_MASK   (0xFFFFFFFCU)
#define	XECC_ERR_SIG_EN_Reserved1_SHIFT   (2U)
#define	XECC_ERR_SIG_EN_Reserved1(x)
ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data
#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x)
ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data
#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x)
ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data
#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK   (0xFFU)
#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT   (0U)
#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x)
ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data
#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x)
ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data
#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x)
ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data
#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK   (0xFFU)
#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT   (0U)
#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x)
ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data
#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x)
ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data
#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x)
ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data
#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK   (0xFFU)
#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT   (0U)
#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x)
ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data
#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x)
ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data
#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT   (0U)
#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x)
ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data
#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK   (0xFFU)
#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT   (0U)
#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x)
SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK   (0xFFU)
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT   (0U)
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x)
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT   (8U)
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x)
SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0
#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x)
SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0
#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x)
SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0
#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x)
SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0
#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x)
SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK   (0xFFU)
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT   (0U)
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x)
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT   (8U)
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x)
SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1
#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x)
SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1
#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x)
SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1
#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x)
SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1
#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x)
SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK   (0xFFU)
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT   (0U)
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x)
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT   (8U)
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x)
SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2
#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x)
SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2
#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x)
SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2
#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x)
SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2
#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x)
SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK   (0xFFU)
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT   (0U)
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x)
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT   (8U)
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x)
SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3
#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x)
SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3
#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT   (0U)
#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x)
SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3
#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x)
SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3
#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT   (0U)
#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x)
MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK   (0xFFU)
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT   (0U)
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x)
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT   (8U)
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x)
MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0
#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x)
MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0
#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x)
MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK   (0xFFU)
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT   (0U)
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x)
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT   (8U)
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x)
MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1
#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x)
MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1
#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x)
MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK   (0xFFU)
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT   (0U)
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x)
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT   (8U)
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x)
MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2
#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x)
MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2
#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x)
MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK   (0xFFU)
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT   (0U)
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x)
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK   (0x7FFFF00U)
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT   (8U)
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x)
MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3
#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x)
MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3
#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT   (0U)
#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x)
PIPE_ECC_EN - OCRAM Pipeline And ECC Enable
#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK   (0x1U)
#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT   (0U)
#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x)
#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK   (0x2U)
#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT   (1U)
#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x)
#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK   (0x4U)
#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT   (2U)
#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x)
#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK   (0x8U)
#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT   (3U)
#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x)
#define	MECC_PIPE_ECC_EN_ECC_EN_MASK   (0x10U)
#define	MECC_PIPE_ECC_EN_ECC_EN_SHIFT   (4U)
#define	MECC_PIPE_ECC_EN_ECC_EN(x)
PENDING_STAT - Pending Status
#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK   (0x1U)
#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT   (0U)
#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x)
#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK   (0x2U)
#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT   (1U)
#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x)
#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK   (0x4U)
#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT   (2U)
#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x)
#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK   (0x8U)
#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT   (3U)
#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x)
CFG_NUM_LANES - Lane Configuration Register
#define	MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK   (0x3U)
#define	MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x)
CFG_DISABLE_DATA_LANES - Disable Data Lane Register
#define	MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK   (0xFU)
#define	MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x)
BIT_ERR - ECC and CRC Error Status Register
#define	MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK   (0x3FFU)
#define	MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT   (0U)
#define	MIPI_CSI2RX_BIT_ERR_BIT_ERR(x)
IRQ_STATUS - IRQ Status Register
#define	MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK   (0x1FFU)
#define	MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x)
IRQ_MASK - IRQ Mask Setting Register
#define	MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK   (0x1FFU)
#define	MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT   (0U)
#define	MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x)
ULPS_STATUS - Ultra Low Power State (ULPS) Status Register
#define	MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK   (0x3FFU)
#define	MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_ULPS_STATUS_STATUS(x)
PPI_ERRSOT_HS - ERRSot HS Status Register
#define	MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK   (0xFU)
#define	MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x)
PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register
#define	MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK   (0xFU)
#define	MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x)
PPI_ERRESC - ErrEsc Status Register
#define	MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK   (0xFU)
#define	MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_PPI_ERRESC_STATUS(x)
PPI_ERRSYNCESC - ErrSyncEsc Status Register
#define	MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK   (0xFU)
#define	MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x)
PPI_ERRCONTROL - ErrControl Status Register
#define	MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK   (0xFU)
#define	MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT   (0U)
#define	MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x)
CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK   (0x1U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK   (0x2U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT   (1U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK   (0x4U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT   (2U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK   (0x400U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT   (10U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK   (0x4000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT   (14U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK   (0x10000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT   (16U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK   (0x20000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT   (17U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK   (0x40000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT   (18U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK   (0x80000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT   (19U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK   (0x100000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT   (20U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x)
CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK   (0x1U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK   (0x2U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT   (1U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK   (0x4U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT   (2U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK   (0x8U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT   (3U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK   (0x10U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT   (4U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK   (0x20U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT   (5U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK   (0x40U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT   (6U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK   (0x80U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT   (7U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK   (0x10000U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT   (16U)
#define	MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x)
CFG_IGNORE_VC - Ignore Virtual Channel Register
#define	MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK   (0x1U)
#define	MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x)
CFG_VID_VC - Virtual Channel value Register
#define	MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK   (0x3U)
#define	MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_VID_VC_VID_VC(x)
CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register
#define	MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK   (0xFFFFU)
#define	MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x)
CFG_VID_VSYNC - VSYNC Configuration Register
#define	MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK   (0xFFU)
#define	MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x)
CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register
#define	MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK   (0xFFU)
#define	MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x)
CFG_VID_HSYNC - HSYNC Configuration Register
#define	MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK   (0xFFU)
#define	MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x)
CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register
#define	MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK   (0xFFU)
#define	MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT   (0U)
#define	MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x)
CASR - Status Register
#define	MMCAU_CASR_IC_MASK   (0x1U)
#define	MMCAU_CASR_IC_SHIFT   (0U)
#define	MMCAU_CASR_IC(x)
#define	MMCAU_CASR_DPE_MASK   (0x2U)
#define	MMCAU_CASR_DPE_SHIFT   (1U)
#define	MMCAU_CASR_DPE(x)
#define	MMCAU_CASR_VER_MASK   (0xF0000000U)
#define	MMCAU_CASR_VER_SHIFT   (28U)
#define	MMCAU_CASR_VER(x)
CAA - Accumulator
#define	MMCAU_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	MMCAU_CAA_ACC_SHIFT   (0U)
#define	MMCAU_CAA_ACC(x)
CA - General Purpose Register
#define	MMCAU_CA_CAn_MASK   (0xFFFFFFFFU)
#define	MMCAU_CA_CAn_SHIFT   (0U)
#define	MMCAU_CA_CAn(x)
TR - Processor A Transmit Register 0..Processor A Transmit Register 3
#define	MU_TR_DATA_MASK   (0xFFFFFFFFU)
#define	MU_TR_DATA_SHIFT   (0U)
#define	MU_TR_DATA(x)
RR - Processor A Receive Register 0..Processor A Receive Register 3
#define	MU_RR_DATA_MASK   (0xFFFFFFFFU)
#define	MU_RR_DATA_SHIFT   (0U)
#define	MU_RR_DATA(x)
SR - Processor A Status Register
#define	MU_SR_Fn_MASK   (0x7U)
#define	MU_SR_Fn_SHIFT   (0U)
#define	MU_SR_Fn(x)
#define	MU_SR_EP_MASK   (0x10U)
#define	MU_SR_EP_SHIFT   (4U)
#define	MU_SR_EP(x)
#define	MU_SR_RS_MASK   (0x80U)
#define	MU_SR_RS_SHIFT   (7U)
#define	MU_SR_RS(x)
#define	MU_SR_FUP_MASK   (0x100U)
#define	MU_SR_FUP_SHIFT   (8U)
#define	MU_SR_FUP(x)
#define	MU_SR_TEn_MASK   (0xF00000U)
#define	MU_SR_TEn_SHIFT   (20U)
#define	MU_SR_TEn(x)
#define	MU_SR_RFn_MASK   (0xF000000U)
#define	MU_SR_RFn_SHIFT   (24U)
#define	MU_SR_RFn(x)
#define	MU_SR_GIPn_MASK   (0xF0000000U)
#define	MU_SR_GIPn_SHIFT   (28U)
#define	MU_SR_GIPn(x)
CR - Processor A Control Register
#define	MU_CR_Fn_MASK   (0x7U)
#define	MU_CR_Fn_SHIFT   (0U)
#define	MU_CR_Fn(x)
#define	MU_CR_GIRn_MASK   (0xF0000U)
#define	MU_CR_GIRn_SHIFT   (16U)
#define	MU_CR_GIRn(x)
#define	MU_CR_TIEn_MASK   (0xF00000U)
#define	MU_CR_TIEn_SHIFT   (20U)
#define	MU_CR_TIEn(x)
#define	MU_CR_RIEn_MASK   (0xF000000U)
#define	MU_CR_RIEn_SHIFT   (24U)
#define	MU_CR_RIEn(x)
#define	MU_CR_GIEn_MASK   (0xF0000000U)
#define	MU_CR_GIEn_SHIFT   (28U)
#define	MU_CR_GIEn(x)
CTRL - OTP Controller Control and Status Register
#define	OCOTP_CTRL_ADDR_MASK   (0x3FFU)
#define	OCOTP_CTRL_ADDR_SHIFT   (0U)
#define	OCOTP_CTRL_ADDR(x)
#define	OCOTP_CTRL_BUSY_MASK   (0x400U)
#define	OCOTP_CTRL_BUSY_SHIFT   (10U)
#define	OCOTP_CTRL_BUSY(x)
#define	OCOTP_CTRL_ERROR_MASK   (0x800U)
#define	OCOTP_CTRL_ERROR_SHIFT   (11U)
#define	OCOTP_CTRL_ERROR(x)
#define	OCOTP_CTRL_RELOAD_SHADOWS_MASK   (0x1000U)
#define	OCOTP_CTRL_RELOAD_SHADOWS_SHIFT   (12U)
#define	OCOTP_CTRL_RELOAD_SHADOWS(x)
#define	OCOTP_CTRL_WORDLOCK_MASK   (0x8000U)
#define	OCOTP_CTRL_WORDLOCK_SHIFT   (15U)
#define	OCOTP_CTRL_WORDLOCK(x)
#define	OCOTP_CTRL_WR_UNLOCK_MASK   (0xFFFF0000U)
#define	OCOTP_CTRL_WR_UNLOCK_SHIFT   (16U)
#define	OCOTP_CTRL_WR_UNLOCK(x)
CTRL_SET - OTP Controller Control and Status Register
#define	OCOTP_CTRL_SET_ADDR_MASK   (0x3FFU)
#define	OCOTP_CTRL_SET_ADDR_SHIFT   (0U)
#define	OCOTP_CTRL_SET_ADDR(x)
#define	OCOTP_CTRL_SET_BUSY_MASK   (0x400U)
#define	OCOTP_CTRL_SET_BUSY_SHIFT   (10U)
#define	OCOTP_CTRL_SET_BUSY(x)
#define	OCOTP_CTRL_SET_ERROR_MASK   (0x800U)
#define	OCOTP_CTRL_SET_ERROR_SHIFT   (11U)
#define	OCOTP_CTRL_SET_ERROR(x)
#define	OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK   (0x1000U)
#define	OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT   (12U)
#define	OCOTP_CTRL_SET_RELOAD_SHADOWS(x)
#define	OCOTP_CTRL_SET_WORDLOCK_MASK   (0x8000U)
#define	OCOTP_CTRL_SET_WORDLOCK_SHIFT   (15U)
#define	OCOTP_CTRL_SET_WORDLOCK(x)
#define	OCOTP_CTRL_SET_WR_UNLOCK_MASK   (0xFFFF0000U)
#define	OCOTP_CTRL_SET_WR_UNLOCK_SHIFT   (16U)
#define	OCOTP_CTRL_SET_WR_UNLOCK(x)
CTRL_CLR - OTP Controller Control and Status Register
#define	OCOTP_CTRL_CLR_ADDR_MASK   (0x3FFU)
#define	OCOTP_CTRL_CLR_ADDR_SHIFT   (0U)
#define	OCOTP_CTRL_CLR_ADDR(x)
#define	OCOTP_CTRL_CLR_BUSY_MASK   (0x400U)
#define	OCOTP_CTRL_CLR_BUSY_SHIFT   (10U)
#define	OCOTP_CTRL_CLR_BUSY(x)
#define	OCOTP_CTRL_CLR_ERROR_MASK   (0x800U)
#define	OCOTP_CTRL_CLR_ERROR_SHIFT   (11U)
#define	OCOTP_CTRL_CLR_ERROR(x)
#define	OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK   (0x1000U)
#define	OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT   (12U)
#define	OCOTP_CTRL_CLR_RELOAD_SHADOWS(x)
#define	OCOTP_CTRL_CLR_WORDLOCK_MASK   (0x8000U)
#define	OCOTP_CTRL_CLR_WORDLOCK_SHIFT   (15U)
#define	OCOTP_CTRL_CLR_WORDLOCK(x)
#define	OCOTP_CTRL_CLR_WR_UNLOCK_MASK   (0xFFFF0000U)
#define	OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT   (16U)
#define	OCOTP_CTRL_CLR_WR_UNLOCK(x)
CTRL_TOG - OTP Controller Control and Status Register
#define	OCOTP_CTRL_TOG_ADDR_MASK   (0x3FFU)
#define	OCOTP_CTRL_TOG_ADDR_SHIFT   (0U)
#define	OCOTP_CTRL_TOG_ADDR(x)
#define	OCOTP_CTRL_TOG_BUSY_MASK   (0x400U)
#define	OCOTP_CTRL_TOG_BUSY_SHIFT   (10U)
#define	OCOTP_CTRL_TOG_BUSY(x)
#define	OCOTP_CTRL_TOG_ERROR_MASK   (0x800U)
#define	OCOTP_CTRL_TOG_ERROR_SHIFT   (11U)
#define	OCOTP_CTRL_TOG_ERROR(x)
#define	OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK   (0x1000U)
#define	OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT   (12U)
#define	OCOTP_CTRL_TOG_RELOAD_SHADOWS(x)
#define	OCOTP_CTRL_TOG_WORDLOCK_MASK   (0x8000U)
#define	OCOTP_CTRL_TOG_WORDLOCK_SHIFT   (15U)
#define	OCOTP_CTRL_TOG_WORDLOCK(x)
#define	OCOTP_CTRL_TOG_WR_UNLOCK_MASK   (0xFFFF0000U)
#define	OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT   (16U)
#define	OCOTP_CTRL_TOG_WR_UNLOCK(x)
PDN - OTP Controller PDN Register
#define	OCOTP_PDN_PDN_MASK   (0x1U)
#define	OCOTP_PDN_PDN_SHIFT   (0U)
#define	OCOTP_PDN_PDN(x)
DATA - OTP Controller Write Data Register
#define	OCOTP_DATA_DATA_MASK   (0xFFFFFFFFU)
#define	OCOTP_DATA_DATA_SHIFT   (0U)
#define	OCOTP_DATA_DATA(x)
READ_CTRL - OTP Controller Read Control Register
#define	OCOTP_READ_CTRL_READ_FUSE_MASK   (0x1U)
#define	OCOTP_READ_CTRL_READ_FUSE_SHIFT   (0U)
#define	OCOTP_READ_CTRL_READ_FUSE(x)
#define	OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK   (0x6U)
#define	OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT   (1U)
#define	OCOTP_READ_CTRL_READ_FUSE_CNTR(x)
#define	OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK   (0x8U)
#define	OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT   (3U)
#define	OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x)
#define	OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK   (0x10U)
#define	OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT   (4U)
#define	OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x)
OUT_STATUS - 8K OTP Memory STATUS Register
#define	OCOTP_OUT_STATUS_SEC_MASK   (0x200U)
#define	OCOTP_OUT_STATUS_SEC_SHIFT   (9U)
#define	OCOTP_OUT_STATUS_SEC(x)
#define	OCOTP_OUT_STATUS_DED_MASK   (0x400U)
#define	OCOTP_OUT_STATUS_DED_SHIFT   (10U)
#define	OCOTP_OUT_STATUS_DED(x)
#define	OCOTP_OUT_STATUS_LOCKED_MASK   (0x800U)
#define	OCOTP_OUT_STATUS_LOCKED_SHIFT   (11U)
#define	OCOTP_OUT_STATUS_LOCKED(x)
#define	OCOTP_OUT_STATUS_PROGFAIL_MASK   (0x1000U)
#define	OCOTP_OUT_STATUS_PROGFAIL_SHIFT   (12U)
#define	OCOTP_OUT_STATUS_PROGFAIL(x)
#define	OCOTP_OUT_STATUS_ACK_MASK   (0x2000U)
#define	OCOTP_OUT_STATUS_ACK_SHIFT   (13U)
#define	OCOTP_OUT_STATUS_ACK(x)
#define	OCOTP_OUT_STATUS_PWOK_MASK   (0x4000U)
#define	OCOTP_OUT_STATUS_PWOK_SHIFT   (14U)
#define	OCOTP_OUT_STATUS_PWOK(x)
#define	OCOTP_OUT_STATUS_FLAGSTATE_MASK   (0x78000U)
#define	OCOTP_OUT_STATUS_FLAGSTATE_SHIFT   (15U)
#define	OCOTP_OUT_STATUS_FLAGSTATE(x)
#define	OCOTP_OUT_STATUS_SEC_RELOAD_MASK   (0x80000U)
#define	OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT   (19U)
#define	OCOTP_OUT_STATUS_SEC_RELOAD(x)
#define	OCOTP_OUT_STATUS_DED_RELOAD_MASK   (0x100000U)
#define	OCOTP_OUT_STATUS_DED_RELOAD_SHIFT   (20U)
#define	OCOTP_OUT_STATUS_DED_RELOAD(x)
#define	OCOTP_OUT_STATUS_CALIBRATED_MASK   (0x200000U)
#define	OCOTP_OUT_STATUS_CALIBRATED_SHIFT   (21U)
#define	OCOTP_OUT_STATUS_CALIBRATED(x)
#define	OCOTP_OUT_STATUS_READ_DONE_INTR_MASK   (0x400000U)
#define	OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT   (22U)
#define	OCOTP_OUT_STATUS_READ_DONE_INTR(x)
#define	OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK   (0x800000U)
#define	OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT   (23U)
#define	OCOTP_OUT_STATUS_READ_ERROR_INTR(x)
#define	OCOTP_OUT_STATUS_DED0_MASK   (0x1000000U)
#define	OCOTP_OUT_STATUS_DED0_SHIFT   (24U)
#define	OCOTP_OUT_STATUS_DED0(x)
#define	OCOTP_OUT_STATUS_DED1_MASK   (0x2000000U)
#define	OCOTP_OUT_STATUS_DED1_SHIFT   (25U)
#define	OCOTP_OUT_STATUS_DED1(x)
#define	OCOTP_OUT_STATUS_DED2_MASK   (0x4000000U)
#define	OCOTP_OUT_STATUS_DED2_SHIFT   (26U)
#define	OCOTP_OUT_STATUS_DED2(x)
#define	OCOTP_OUT_STATUS_DED3_MASK   (0x8000000U)
#define	OCOTP_OUT_STATUS_DED3_SHIFT   (27U)
#define	OCOTP_OUT_STATUS_DED3(x)
OUT_STATUS_SET - 8K OTP Memory STATUS Register
#define	OCOTP_OUT_STATUS_SET_SEC_MASK   (0x200U)
#define	OCOTP_OUT_STATUS_SET_SEC_SHIFT   (9U)
#define	OCOTP_OUT_STATUS_SET_SEC(x)
#define	OCOTP_OUT_STATUS_SET_DED_MASK   (0x400U)
#define	OCOTP_OUT_STATUS_SET_DED_SHIFT   (10U)
#define	OCOTP_OUT_STATUS_SET_DED(x)
#define	OCOTP_OUT_STATUS_SET_LOCKED_MASK   (0x800U)
#define	OCOTP_OUT_STATUS_SET_LOCKED_SHIFT   (11U)
#define	OCOTP_OUT_STATUS_SET_LOCKED(x)
#define	OCOTP_OUT_STATUS_SET_PROGFAIL_MASK   (0x1000U)
#define	OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT   (12U)
#define	OCOTP_OUT_STATUS_SET_PROGFAIL(x)
#define	OCOTP_OUT_STATUS_SET_ACK_MASK   (0x2000U)
#define	OCOTP_OUT_STATUS_SET_ACK_SHIFT   (13U)
#define	OCOTP_OUT_STATUS_SET_ACK(x)
#define	OCOTP_OUT_STATUS_SET_PWOK_MASK   (0x4000U)
#define	OCOTP_OUT_STATUS_SET_PWOK_SHIFT   (14U)
#define	OCOTP_OUT_STATUS_SET_PWOK(x)
#define	OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK   (0x78000U)
#define	OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT   (15U)
#define	OCOTP_OUT_STATUS_SET_FLAGSTATE(x)
#define	OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK   (0x80000U)
#define	OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT   (19U)
#define	OCOTP_OUT_STATUS_SET_SEC_RELOAD(x)
#define	OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK   (0x100000U)
#define	OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT   (20U)
#define	OCOTP_OUT_STATUS_SET_DED_RELOAD(x)
#define	OCOTP_OUT_STATUS_SET_CALIBRATED_MASK   (0x200000U)
#define	OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT   (21U)
#define	OCOTP_OUT_STATUS_SET_CALIBRATED(x)
#define	OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK   (0x400000U)
#define	OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT   (22U)
#define	OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x)
#define	OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK   (0x800000U)
#define	OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT   (23U)
#define	OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x)
#define	OCOTP_OUT_STATUS_SET_DED0_MASK   (0x1000000U)
#define	OCOTP_OUT_STATUS_SET_DED0_SHIFT   (24U)
#define	OCOTP_OUT_STATUS_SET_DED0(x)
#define	OCOTP_OUT_STATUS_SET_DED1_MASK   (0x2000000U)
#define	OCOTP_OUT_STATUS_SET_DED1_SHIFT   (25U)
#define	OCOTP_OUT_STATUS_SET_DED1(x)
#define	OCOTP_OUT_STATUS_SET_DED2_MASK   (0x4000000U)
#define	OCOTP_OUT_STATUS_SET_DED2_SHIFT   (26U)
#define	OCOTP_OUT_STATUS_SET_DED2(x)
#define	OCOTP_OUT_STATUS_SET_DED3_MASK   (0x8000000U)
#define	OCOTP_OUT_STATUS_SET_DED3_SHIFT   (27U)
#define	OCOTP_OUT_STATUS_SET_DED3(x)
OUT_STATUS_CLR - 8K OTP Memory STATUS Register
#define	OCOTP_OUT_STATUS_CLR_SEC_MASK   (0x200U)
#define	OCOTP_OUT_STATUS_CLR_SEC_SHIFT   (9U)
#define	OCOTP_OUT_STATUS_CLR_SEC(x)
#define	OCOTP_OUT_STATUS_CLR_DED_MASK   (0x400U)
#define	OCOTP_OUT_STATUS_CLR_DED_SHIFT   (10U)
#define	OCOTP_OUT_STATUS_CLR_DED(x)
#define	OCOTP_OUT_STATUS_CLR_LOCKED_MASK   (0x800U)
#define	OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT   (11U)
#define	OCOTP_OUT_STATUS_CLR_LOCKED(x)
#define	OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK   (0x1000U)
#define	OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT   (12U)
#define	OCOTP_OUT_STATUS_CLR_PROGFAIL(x)
#define	OCOTP_OUT_STATUS_CLR_ACK_MASK   (0x2000U)
#define	OCOTP_OUT_STATUS_CLR_ACK_SHIFT   (13U)
#define	OCOTP_OUT_STATUS_CLR_ACK(x)
#define	OCOTP_OUT_STATUS_CLR_PWOK_MASK   (0x4000U)
#define	OCOTP_OUT_STATUS_CLR_PWOK_SHIFT   (14U)
#define	OCOTP_OUT_STATUS_CLR_PWOK(x)
#define	OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK   (0x78000U)
#define	OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT   (15U)
#define	OCOTP_OUT_STATUS_CLR_FLAGSTATE(x)
#define	OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK   (0x80000U)
#define	OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT   (19U)
#define	OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x)
#define	OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK   (0x100000U)
#define	OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT   (20U)
#define	OCOTP_OUT_STATUS_CLR_DED_RELOAD(x)
#define	OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK   (0x200000U)
#define	OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT   (21U)
#define	OCOTP_OUT_STATUS_CLR_CALIBRATED(x)
#define	OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK   (0x400000U)
#define	OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT   (22U)
#define	OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x)
#define	OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK   (0x800000U)
#define	OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT   (23U)
#define	OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x)
#define	OCOTP_OUT_STATUS_CLR_DED0_MASK   (0x1000000U)
#define	OCOTP_OUT_STATUS_CLR_DED0_SHIFT   (24U)
#define	OCOTP_OUT_STATUS_CLR_DED0(x)
#define	OCOTP_OUT_STATUS_CLR_DED1_MASK   (0x2000000U)
#define	OCOTP_OUT_STATUS_CLR_DED1_SHIFT   (25U)
#define	OCOTP_OUT_STATUS_CLR_DED1(x)
#define	OCOTP_OUT_STATUS_CLR_DED2_MASK   (0x4000000U)
#define	OCOTP_OUT_STATUS_CLR_DED2_SHIFT   (26U)
#define	OCOTP_OUT_STATUS_CLR_DED2(x)
#define	OCOTP_OUT_STATUS_CLR_DED3_MASK   (0x8000000U)
#define	OCOTP_OUT_STATUS_CLR_DED3_SHIFT   (27U)
#define	OCOTP_OUT_STATUS_CLR_DED3(x)
OUT_STATUS_TOG - 8K OTP Memory STATUS Register
#define	OCOTP_OUT_STATUS_TOG_SEC_MASK   (0x200U)
#define	OCOTP_OUT_STATUS_TOG_SEC_SHIFT   (9U)
#define	OCOTP_OUT_STATUS_TOG_SEC(x)
#define	OCOTP_OUT_STATUS_TOG_DED_MASK   (0x400U)
#define	OCOTP_OUT_STATUS_TOG_DED_SHIFT   (10U)
#define	OCOTP_OUT_STATUS_TOG_DED(x)
#define	OCOTP_OUT_STATUS_TOG_LOCKED_MASK   (0x800U)
#define	OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT   (11U)
#define	OCOTP_OUT_STATUS_TOG_LOCKED(x)
#define	OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK   (0x1000U)
#define	OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT   (12U)
#define	OCOTP_OUT_STATUS_TOG_PROGFAIL(x)
#define	OCOTP_OUT_STATUS_TOG_ACK_MASK   (0x2000U)
#define	OCOTP_OUT_STATUS_TOG_ACK_SHIFT   (13U)
#define	OCOTP_OUT_STATUS_TOG_ACK(x)
#define	OCOTP_OUT_STATUS_TOG_PWOK_MASK   (0x4000U)
#define	OCOTP_OUT_STATUS_TOG_PWOK_SHIFT   (14U)
#define	OCOTP_OUT_STATUS_TOG_PWOK(x)
#define	OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK   (0x78000U)
#define	OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT   (15U)
#define	OCOTP_OUT_STATUS_TOG_FLAGSTATE(x)
#define	OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK   (0x80000U)
#define	OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT   (19U)
#define	OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x)
#define	OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK   (0x100000U)
#define	OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT   (20U)
#define	OCOTP_OUT_STATUS_TOG_DED_RELOAD(x)
#define	OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK   (0x200000U)
#define	OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT   (21U)
#define	OCOTP_OUT_STATUS_TOG_CALIBRATED(x)
#define	OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK   (0x400000U)
#define	OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT   (22U)
#define	OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x)
#define	OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK   (0x800000U)
#define	OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT   (23U)
#define	OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x)
#define	OCOTP_OUT_STATUS_TOG_DED0_MASK   (0x1000000U)
#define	OCOTP_OUT_STATUS_TOG_DED0_SHIFT   (24U)
#define	OCOTP_OUT_STATUS_TOG_DED0(x)
#define	OCOTP_OUT_STATUS_TOG_DED1_MASK   (0x2000000U)
#define	OCOTP_OUT_STATUS_TOG_DED1_SHIFT   (25U)
#define	OCOTP_OUT_STATUS_TOG_DED1(x)
#define	OCOTP_OUT_STATUS_TOG_DED2_MASK   (0x4000000U)
#define	OCOTP_OUT_STATUS_TOG_DED2_SHIFT   (26U)
#define	OCOTP_OUT_STATUS_TOG_DED2(x)
#define	OCOTP_OUT_STATUS_TOG_DED3_MASK   (0x8000000U)
#define	OCOTP_OUT_STATUS_TOG_DED3_SHIFT   (27U)
#define	OCOTP_OUT_STATUS_TOG_DED3(x)
VERSION - OTP Controller Version Register
#define	OCOTP_VERSION_STEP_MASK   (0xFFFFU)
#define	OCOTP_VERSION_STEP_SHIFT   (0U)
#define	OCOTP_VERSION_STEP(x)
#define	OCOTP_VERSION_MINOR_MASK   (0xFF0000U)
#define	OCOTP_VERSION_MINOR_SHIFT   (16U)
#define	OCOTP_VERSION_MINOR(x)
#define	OCOTP_VERSION_MAJOR_MASK   (0xFF000000U)
#define	OCOTP_VERSION_MAJOR_SHIFT   (24U)
#define	OCOTP_VERSION_MAJOR(x)
READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register
#define	OCOTP_READ_FUSE_DATA_DATA_MASK   (0xFFFFFFFFU)
#define	OCOTP_READ_FUSE_DATA_DATA_SHIFT   (0U)
#define	OCOTP_READ_FUSE_DATA_DATA(x)
SW_LOCK - SW_LOCK Register
#define	OCOTP_SW_LOCK_SW_LOCK_MASK   (0xFFFFFFFFU)
#define	OCOTP_SW_LOCK_SW_LOCK_SHIFT   (0U)
#define	OCOTP_SW_LOCK_SW_LOCK(x)
BIT_LOCK - BIT_LOCK Register
#define	OCOTP_BIT_LOCK_BIT_LOCK_MASK   (0xFFFFFFFFU)
#define	OCOTP_BIT_LOCK_BIT_LOCK_SHIFT   (0U)
#define	OCOTP_BIT_LOCK_BIT_LOCK(x)
LOCKED0 - OTP Controller Program Locked Status 0 Register
#define	OCOTP_LOCKED0_LOCKED_MASK   (0xFFFFU)
#define	OCOTP_LOCKED0_LOCKED_SHIFT   (0U)
#define	OCOTP_LOCKED0_LOCKED(x)
LOCKED1 - OTP Controller Program Locked Status 1 Register
#define	OCOTP_LOCKED1_LOCKED_MASK   (0xFFFFFFFFU)
#define	OCOTP_LOCKED1_LOCKED_SHIFT   (0U)
#define	OCOTP_LOCKED1_LOCKED(x)
LOCKED2 - OTP Controller Program Locked Status 2 Register
#define	OCOTP_LOCKED2_LOCKED_MASK   (0xFFFFFFFFU)
#define	OCOTP_LOCKED2_LOCKED_SHIFT   (0U)
#define	OCOTP_LOCKED2_LOCKED(x)
LOCKED3 - OTP Controller Program Locked Status 3 Register
#define	OCOTP_LOCKED3_LOCKED_MASK   (0xFFFFFFFFU)
#define	OCOTP_LOCKED3_LOCKED_SHIFT   (0U)
#define	OCOTP_LOCKED3_LOCKED(x)
LOCKED4 - OTP Controller Program Locked Status 4 Register
#define	OCOTP_LOCKED4_LOCKED_MASK   (0xFFFFFFFFU)
#define	OCOTP_LOCKED4_LOCKED_SHIFT   (0U)
#define	OCOTP_LOCKED4_LOCKED(x)
FUSE - Value of fuse word 0..Value of fuse word 143
#define	OCOTP_FUSE_BITS_MASK   (0xFFFFFFFFU)
#define	OCOTP_FUSE_BITS_SHIFT   (0U)
#define	OCOTP_FUSE_BITS(x)
CTRL0 - Control Register 0
#define	OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK   (0x3F000000U)
#define	OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT   (24U)
#define	OSC_RC_400M_CTRL0_REF_CLK_DIV(x)
CTRL1 - Control Register 1
#define	OSC_RC_400M_CTRL1_HYST_MINUS_MASK   (0xFU)
#define	OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT   (0U)
#define	OSC_RC_400M_CTRL1_HYST_MINUS(x)
#define	OSC_RC_400M_CTRL1_HYST_PLUS_MASK   (0xF00U)
#define	OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT   (8U)
#define	OSC_RC_400M_CTRL1_HYST_PLUS(x)
#define	OSC_RC_400M_CTRL1_TARGET_COUNT_MASK   (0xFFFF0000U)
#define	OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT   (16U)
#define	OSC_RC_400M_CTRL1_TARGET_COUNT(x)
CTRL2 - Control Register 2
#define	OSC_RC_400M_CTRL2_TUNE_BYP_MASK   (0x400U)
#define	OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT   (10U)
#define	OSC_RC_400M_CTRL2_TUNE_BYP(x)
#define	OSC_RC_400M_CTRL2_TUNE_EN_MASK   (0x1000U)
#define	OSC_RC_400M_CTRL2_TUNE_EN_SHIFT   (12U)
#define	OSC_RC_400M_CTRL2_TUNE_EN(x)
#define	OSC_RC_400M_CTRL2_TUNE_START_MASK   (0x4000U)
#define	OSC_RC_400M_CTRL2_TUNE_START_SHIFT   (14U)
#define	OSC_RC_400M_CTRL2_TUNE_START(x)
#define	OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define	OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT   (24U)
#define	OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)
CTRL3 - Control Register 3
#define	OSC_RC_400M_CTRL3_CLR_ERR_MASK   (0x1U)
#define	OSC_RC_400M_CTRL3_CLR_ERR_SHIFT   (0U)
#define	OSC_RC_400M_CTRL3_CLR_ERR(x)
#define	OSC_RC_400M_CTRL3_EN_1M_CLK_MASK   (0x100U)
#define	OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT   (8U)
#define	OSC_RC_400M_CTRL3_EN_1M_CLK(x)
#define	OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK   (0x400U)
#define	OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT   (10U)
#define	OSC_RC_400M_CTRL3_MUX_1M_CLK(x)
#define	OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK   (0xFFFF0000U)
#define	OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT   (16U)
#define	OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)
STAT0 - Status Register 0
#define	OSC_RC_400M_STAT0_CLK1M_ERR_MASK   (0x1U)
#define	OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT   (0U)
#define	OSC_RC_400M_STAT0_CLK1M_ERR(x)
STAT1 - Status Register 1
#define	OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK   (0xFFFF0000U)
#define	OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
#define	OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)
STAT2 - Status Register 2
#define	OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define	OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT   (24U)
#define	OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)
CR - Control Register
#define	OTFAD_CR_FERR_MASK   (0x2U)
#define	OTFAD_CR_FERR_SHIFT   (1U)
#define	OTFAD_CR_FERR(x)
#define	OTFAD_CR_FLDM_MASK   (0x8U)
#define	OTFAD_CR_FLDM_SHIFT   (3U)
#define	OTFAD_CR_FLDM(x)
#define	OTFAD_CR_KBSE_MASK   (0x10U)
#define	OTFAD_CR_KBSE_SHIFT   (4U)
#define	OTFAD_CR_KBSE(x)
#define	OTFAD_CR_KBPE_MASK   (0x20U)
#define	OTFAD_CR_KBPE_SHIFT   (5U)
#define	OTFAD_CR_KBPE(x)
#define	OTFAD_CR_RRAE_MASK   (0x80U)
#define	OTFAD_CR_RRAE_SHIFT   (7U)
#define	OTFAD_CR_RRAE(x)
#define	OTFAD_CR_SKBP_MASK   (0x40000000U)
#define	OTFAD_CR_SKBP_SHIFT   (30U)
#define	OTFAD_CR_SKBP(x)
#define	OTFAD_CR_GE_MASK   (0x80000000U)
#define	OTFAD_CR_GE_SHIFT   (31U)
#define	OTFAD_CR_GE(x)
SR - Status Register
#define	OTFAD_SR_KBERR_MASK   (0x1U)
#define	OTFAD_SR_KBERR_SHIFT   (0U)
#define	OTFAD_SR_KBERR(x)
#define	OTFAD_SR_MDPCP_MASK   (0x2U)
#define	OTFAD_SR_MDPCP_SHIFT   (1U)
#define	OTFAD_SR_MDPCP(x)
#define	OTFAD_SR_MODE_MASK   (0xCU)
#define	OTFAD_SR_MODE_SHIFT   (2U)
#define	OTFAD_SR_MODE(x)
#define	OTFAD_SR_NCTX_MASK   (0xF0U)
#define	OTFAD_SR_NCTX_SHIFT   (4U)
#define	OTFAD_SR_NCTX(x)
#define	OTFAD_SR_CTXER0_MASK   (0x100U)
#define	OTFAD_SR_CTXER0_SHIFT   (8U)
#define	OTFAD_SR_CTXER0(x)
#define	OTFAD_SR_CTXER1_MASK   (0x200U)
#define	OTFAD_SR_CTXER1_SHIFT   (9U)
#define	OTFAD_SR_CTXER1(x)
#define	OTFAD_SR_CTXER2_MASK   (0x400U)
#define	OTFAD_SR_CTXER2_SHIFT   (10U)
#define	OTFAD_SR_CTXER2(x)
#define	OTFAD_SR_CTXER3_MASK   (0x800U)
#define	OTFAD_SR_CTXER3_SHIFT   (11U)
#define	OTFAD_SR_CTXER3(x)
#define	OTFAD_SR_CTXIE0_MASK   (0x10000U)
#define	OTFAD_SR_CTXIE0_SHIFT   (16U)
#define	OTFAD_SR_CTXIE0(x)
#define	OTFAD_SR_CTXIE1_MASK   (0x20000U)
#define	OTFAD_SR_CTXIE1_SHIFT   (17U)
#define	OTFAD_SR_CTXIE1(x)
#define	OTFAD_SR_CTXIE2_MASK   (0x40000U)
#define	OTFAD_SR_CTXIE2_SHIFT   (18U)
#define	OTFAD_SR_CTXIE2(x)
#define	OTFAD_SR_CTXIE3_MASK   (0x80000U)
#define	OTFAD_SR_CTXIE3_SHIFT   (19U)
#define	OTFAD_SR_CTXIE3(x)
#define	OTFAD_SR_HRL_MASK   (0xF000000U)
#define	OTFAD_SR_HRL_SHIFT   (24U)
#define	OTFAD_SR_HRL(x)
#define	OTFAD_SR_RRAM_MASK   (0x10000000U)
#define	OTFAD_SR_RRAM_SHIFT   (28U)
#define	OTFAD_SR_RRAM(x)
#define	OTFAD_SR_GEM_MASK   (0x20000000U)
#define	OTFAD_SR_GEM_SHIFT   (29U)
#define	OTFAD_SR_GEM(x)
#define	OTFAD_SR_KBPE_MASK   (0x40000000U)
#define	OTFAD_SR_KBPE_SHIFT   (30U)
#define	OTFAD_SR_KBPE(x)
#define	OTFAD_SR_KBD_MASK   (0x80000000U)
#define	OTFAD_SR_KBD_SHIFT   (31U)
#define	OTFAD_SR_KBD(x)
#define	XRDC2_SR_DIN_MASK   (0xFU)
#define	XRDC2_SR_DIN_SHIFT   (0U)
#define	XRDC2_SR_DIN(x)
#define	XRDC2_SR_HRL_MASK   (0xF0U)
#define	XRDC2_SR_HRL_SHIFT   (4U)
#define	XRDC2_SR_HRL(x)
#define	XRDC2_SR_GCLO_MASK   (0xF00U)
#define	XRDC2_SR_GCLO_SHIFT   (8U)
#define	XRDC2_SR_GCLO(x)
KEY - AES Key Word
#define	OTFAD_KEY_KEY_MASK   (0xFFFFFFFFU)
#define	OTFAD_KEY_KEY_SHIFT   (0U)
#define	OTFAD_KEY_KEY(x)
CTR - AES Counter Word
#define	OTFAD_CTR_CTR_MASK   (0xFFFFFFFFU)
#define	OTFAD_CTR_CTR_SHIFT   (0U)
#define	OTFAD_CTR_CTR(x)
RGD_W0 - AES Region Descriptor Word0
#define	OTFAD_RGD_W0_SRTADDR_MASK   (0xFFFFFC00U)
#define	OTFAD_RGD_W0_SRTADDR_SHIFT   (10U)
#define	OTFAD_RGD_W0_SRTADDR(x)
RGD_W1 - AES Region Descriptor Word1
#define	OTFAD_RGD_W1_VLD_MASK   (0x1U)
#define	OTFAD_RGD_W1_VLD_SHIFT   (0U)
#define	OTFAD_RGD_W1_VLD(x)
#define	OTFAD_RGD_W1_ADE_MASK   (0x2U)
#define	OTFAD_RGD_W1_ADE_SHIFT   (1U)
#define	OTFAD_RGD_W1_ADE(x)
#define	OTFAD_RGD_W1_RO_MASK   (0x4U)
#define	OTFAD_RGD_W1_RO_SHIFT   (2U)
#define	OTFAD_RGD_W1_RO(x)
#define	OTFAD_RGD_W1_ENDADDR_MASK   (0xFFFFFC00U)
#define	OTFAD_RGD_W1_ENDADDR_SHIFT   (10U)
#define	OTFAD_RGD_W1_ENDADDR(x)
CTRL_1 - PDM Control register 1
#define	PDM_CTRL_1_CH0EN_MASK   (0x1U)
#define	PDM_CTRL_1_CH0EN_SHIFT   (0U)
#define	PDM_CTRL_1_CH0EN(x)
#define	PDM_CTRL_1_CH1EN_MASK   (0x2U)
#define	PDM_CTRL_1_CH1EN_SHIFT   (1U)
#define	PDM_CTRL_1_CH1EN(x)
#define	PDM_CTRL_1_CH2EN_MASK   (0x4U)
#define	PDM_CTRL_1_CH2EN_SHIFT   (2U)
#define	PDM_CTRL_1_CH2EN(x)
#define	PDM_CTRL_1_CH3EN_MASK   (0x8U)
#define	PDM_CTRL_1_CH3EN_SHIFT   (3U)
#define	PDM_CTRL_1_CH3EN(x)
#define	PDM_CTRL_1_CH4EN_MASK   (0x10U)
#define	PDM_CTRL_1_CH4EN_SHIFT   (4U)
#define	PDM_CTRL_1_CH4EN(x)
#define	PDM_CTRL_1_CH5EN_MASK   (0x20U)
#define	PDM_CTRL_1_CH5EN_SHIFT   (5U)
#define	PDM_CTRL_1_CH5EN(x)
#define	PDM_CTRL_1_CH6EN_MASK   (0x40U)
#define	PDM_CTRL_1_CH6EN_SHIFT   (6U)
#define	PDM_CTRL_1_CH6EN(x)
#define	PDM_CTRL_1_CH7EN_MASK   (0x80U)
#define	PDM_CTRL_1_CH7EN_SHIFT   (7U)
#define	PDM_CTRL_1_CH7EN(x)
#define	PDM_CTRL_1_ERREN_MASK   (0x800000U)
#define	PDM_CTRL_1_ERREN_SHIFT   (23U)
#define	PDM_CTRL_1_ERREN(x)
#define	PDM_CTRL_1_DISEL_MASK   (0x3000000U)
#define	PDM_CTRL_1_DISEL_SHIFT   (24U)
#define	PDM_CTRL_1_DISEL(x)
#define	PDM_CTRL_1_DBGE_MASK   (0x4000000U)
#define	PDM_CTRL_1_DBGE_SHIFT   (26U)
#define	PDM_CTRL_1_DBGE(x)
#define	PDM_CTRL_1_SRES_MASK   (0x8000000U)
#define	PDM_CTRL_1_SRES_SHIFT   (27U)
#define	PDM_CTRL_1_SRES(x)
#define	PDM_CTRL_1_DBG_MASK   (0x10000000U)
#define	PDM_CTRL_1_DBG_SHIFT   (28U)
#define	PDM_CTRL_1_DBG(x)
#define	PDM_CTRL_1_PDMIEN_MASK   (0x20000000U)
#define	PDM_CTRL_1_PDMIEN_SHIFT   (29U)
#define	PDM_CTRL_1_PDMIEN(x)
#define	PDM_CTRL_1_DOZEN_MASK   (0x40000000U)
#define	PDM_CTRL_1_DOZEN_SHIFT   (30U)
#define	PDM_CTRL_1_DOZEN(x)
#define	PDM_CTRL_1_MDIS_MASK   (0x80000000U)
#define	PDM_CTRL_1_MDIS_SHIFT   (31U)
#define	PDM_CTRL_1_MDIS(x)
CTRL_2 - PDM Control register 2
#define	PDM_CTRL_2_CLKDIV_MASK   (0xFFU)
#define	PDM_CTRL_2_CLKDIV_SHIFT   (0U)
#define	PDM_CTRL_2_CLKDIV(x)
#define	PDM_CTRL_2_CICOSR_MASK   (0xF0000U)
#define	PDM_CTRL_2_CICOSR_SHIFT   (16U)
#define	PDM_CTRL_2_CICOSR(x)
#define	PDM_CTRL_2_QSEL_MASK   (0xE000000U)
#define	PDM_CTRL_2_QSEL_SHIFT   (25U)
#define	PDM_CTRL_2_QSEL(x)
STAT - PDM Status register
#define	PDM_STAT_CH0F_MASK   (0x1U)
#define	PDM_STAT_CH0F_SHIFT   (0U)
#define	PDM_STAT_CH0F(x)
#define	PDM_STAT_CH1F_MASK   (0x2U)
#define	PDM_STAT_CH1F_SHIFT   (1U)
#define	PDM_STAT_CH1F(x)
#define	PDM_STAT_CH2F_MASK   (0x4U)
#define	PDM_STAT_CH2F_SHIFT   (2U)
#define	PDM_STAT_CH2F(x)
#define	PDM_STAT_CH3F_MASK   (0x8U)
#define	PDM_STAT_CH3F_SHIFT   (3U)
#define	PDM_STAT_CH3F(x)
#define	PDM_STAT_CH4F_MASK   (0x10U)
#define	PDM_STAT_CH4F_SHIFT   (4U)
#define	PDM_STAT_CH4F(x)
#define	PDM_STAT_CH5F_MASK   (0x20U)
#define	PDM_STAT_CH5F_SHIFT   (5U)
#define	PDM_STAT_CH5F(x)
#define	PDM_STAT_CH6F_MASK   (0x40U)
#define	PDM_STAT_CH6F_SHIFT   (6U)
#define	PDM_STAT_CH6F(x)
#define	PDM_STAT_CH7F_MASK   (0x80U)
#define	PDM_STAT_CH7F_SHIFT   (7U)
#define	PDM_STAT_CH7F(x)
#define	PDM_STAT_LOWFREQF_MASK   (0x20000000U)
#define	PDM_STAT_LOWFREQF_SHIFT   (29U)
#define	PDM_STAT_LOWFREQF(x)
#define	PDM_STAT_FIR_RDY_MASK   (0x40000000U)
#define	PDM_STAT_FIR_RDY_SHIFT   (30U)
#define	PDM_STAT_FIR_RDY(x)
#define	PDM_STAT_BSY_FIL_MASK   (0x80000000U)
#define	PDM_STAT_BSY_FIL_SHIFT   (31U)
#define	PDM_STAT_BSY_FIL(x)
FIFO_CTRL - PDM FIFO Control register
#define	PDM_FIFO_CTRL_FIFOWMK_MASK   (0x7U)
#define	PDM_FIFO_CTRL_FIFOWMK_SHIFT   (0U)
#define	PDM_FIFO_CTRL_FIFOWMK(x)
FIFO_STAT - PDM FIFO Status register
#define	PDM_FIFO_STAT_FIFOOVF0_MASK   (0x1U)
#define	PDM_FIFO_STAT_FIFOOVF0_SHIFT   (0U)
#define	PDM_FIFO_STAT_FIFOOVF0(x)
#define	PDM_FIFO_STAT_FIFOOVF1_MASK   (0x2U)
#define	PDM_FIFO_STAT_FIFOOVF1_SHIFT   (1U)
#define	PDM_FIFO_STAT_FIFOOVF1(x)
#define	PDM_FIFO_STAT_FIFOOVF2_MASK   (0x4U)
#define	PDM_FIFO_STAT_FIFOOVF2_SHIFT   (2U)
#define	PDM_FIFO_STAT_FIFOOVF2(x)
#define	PDM_FIFO_STAT_FIFOOVF3_MASK   (0x8U)
#define	PDM_FIFO_STAT_FIFOOVF3_SHIFT   (3U)
#define	PDM_FIFO_STAT_FIFOOVF3(x)
#define	PDM_FIFO_STAT_FIFOOVF4_MASK   (0x10U)
#define	PDM_FIFO_STAT_FIFOOVF4_SHIFT   (4U)
#define	PDM_FIFO_STAT_FIFOOVF4(x)
#define	PDM_FIFO_STAT_FIFOOVF5_MASK   (0x20U)
#define	PDM_FIFO_STAT_FIFOOVF5_SHIFT   (5U)
#define	PDM_FIFO_STAT_FIFOOVF5(x)
#define	PDM_FIFO_STAT_FIFOOVF6_MASK   (0x40U)
#define	PDM_FIFO_STAT_FIFOOVF6_SHIFT   (6U)
#define	PDM_FIFO_STAT_FIFOOVF6(x)
#define	PDM_FIFO_STAT_FIFOOVF7_MASK   (0x80U)
#define	PDM_FIFO_STAT_FIFOOVF7_SHIFT   (7U)
#define	PDM_FIFO_STAT_FIFOOVF7(x)
#define	PDM_FIFO_STAT_FIFOUND0_MASK   (0x100U)
#define	PDM_FIFO_STAT_FIFOUND0_SHIFT   (8U)
#define	PDM_FIFO_STAT_FIFOUND0(x)
#define	PDM_FIFO_STAT_FIFOUND1_MASK   (0x200U)
#define	PDM_FIFO_STAT_FIFOUND1_SHIFT   (9U)
#define	PDM_FIFO_STAT_FIFOUND1(x)
#define	PDM_FIFO_STAT_FIFOUND2_MASK   (0x400U)
#define	PDM_FIFO_STAT_FIFOUND2_SHIFT   (10U)
#define	PDM_FIFO_STAT_FIFOUND2(x)
#define	PDM_FIFO_STAT_FIFOUND3_MASK   (0x800U)
#define	PDM_FIFO_STAT_FIFOUND3_SHIFT   (11U)
#define	PDM_FIFO_STAT_FIFOUND3(x)
#define	PDM_FIFO_STAT_FIFOUND4_MASK   (0x1000U)
#define	PDM_FIFO_STAT_FIFOUND4_SHIFT   (12U)
#define	PDM_FIFO_STAT_FIFOUND4(x)
#define	PDM_FIFO_STAT_FIFOUND5_MASK   (0x2000U)
#define	PDM_FIFO_STAT_FIFOUND5_SHIFT   (13U)
#define	PDM_FIFO_STAT_FIFOUND5(x)
#define	PDM_FIFO_STAT_FIFOUND6_MASK   (0x4000U)
#define	PDM_FIFO_STAT_FIFOUND6_SHIFT   (14U)
#define	PDM_FIFO_STAT_FIFOUND6(x)
#define	PDM_FIFO_STAT_FIFOUND7_MASK   (0x8000U)
#define	PDM_FIFO_STAT_FIFOUND7_SHIFT   (15U)
#define	PDM_FIFO_STAT_FIFOUND7(x)
DATACH - PDM Output Result Register
#define	PDM_DATACH_DATA_MASK   (0xFFFFFFFFU)
#define	PDM_DATACH_DATA_SHIFT   (0U)
#define	PDM_DATACH_DATA(x)
DC_CTRL - PDM DC Remover Control register
#define	PDM_DC_CTRL_DCCONFIG0_MASK   (0x3U)
#define	PDM_DC_CTRL_DCCONFIG0_SHIFT   (0U)
#define	PDM_DC_CTRL_DCCONFIG0(x)
#define	PDM_DC_CTRL_DCCONFIG1_MASK   (0xCU)
#define	PDM_DC_CTRL_DCCONFIG1_SHIFT   (2U)
#define	PDM_DC_CTRL_DCCONFIG1(x)
#define	PDM_DC_CTRL_DCCONFIG2_MASK   (0x30U)
#define	PDM_DC_CTRL_DCCONFIG2_SHIFT   (4U)
#define	PDM_DC_CTRL_DCCONFIG2(x)
#define	PDM_DC_CTRL_DCCONFIG3_MASK   (0xC0U)
#define	PDM_DC_CTRL_DCCONFIG3_SHIFT   (6U)
#define	PDM_DC_CTRL_DCCONFIG3(x)
#define	PDM_DC_CTRL_DCCONFIG4_MASK   (0x300U)
#define	PDM_DC_CTRL_DCCONFIG4_SHIFT   (8U)
#define	PDM_DC_CTRL_DCCONFIG4(x)
#define	PDM_DC_CTRL_DCCONFIG5_MASK   (0xC00U)
#define	PDM_DC_CTRL_DCCONFIG5_SHIFT   (10U)
#define	PDM_DC_CTRL_DCCONFIG5(x)
#define	PDM_DC_CTRL_DCCONFIG6_MASK   (0x3000U)
#define	PDM_DC_CTRL_DCCONFIG6_SHIFT   (12U)
#define	PDM_DC_CTRL_DCCONFIG6(x)
#define	PDM_DC_CTRL_DCCONFIG7_MASK   (0xC000U)
#define	PDM_DC_CTRL_DCCONFIG7_SHIFT   (14U)
#define	PDM_DC_CTRL_DCCONFIG7(x)
RANGE_CTRL - PDM Range Control register
#define	PDM_RANGE_CTRL_RANGEADJ0_MASK   (0xFU)
#define	PDM_RANGE_CTRL_RANGEADJ0_SHIFT   (0U)
#define	PDM_RANGE_CTRL_RANGEADJ0(x)
#define	PDM_RANGE_CTRL_RANGEADJ1_MASK   (0xF0U)
#define	PDM_RANGE_CTRL_RANGEADJ1_SHIFT   (4U)
#define	PDM_RANGE_CTRL_RANGEADJ1(x)
#define	PDM_RANGE_CTRL_RANGEADJ2_MASK   (0xF00U)
#define	PDM_RANGE_CTRL_RANGEADJ2_SHIFT   (8U)
#define	PDM_RANGE_CTRL_RANGEADJ2(x)
#define	PDM_RANGE_CTRL_RANGEADJ3_MASK   (0xF000U)
#define	PDM_RANGE_CTRL_RANGEADJ3_SHIFT   (12U)
#define	PDM_RANGE_CTRL_RANGEADJ3(x)
#define	PDM_RANGE_CTRL_RANGEADJ4_MASK   (0xF0000U)
#define	PDM_RANGE_CTRL_RANGEADJ4_SHIFT   (16U)
#define	PDM_RANGE_CTRL_RANGEADJ4(x)
#define	PDM_RANGE_CTRL_RANGEADJ5_MASK   (0xF00000U)
#define	PDM_RANGE_CTRL_RANGEADJ5_SHIFT   (20U)
#define	PDM_RANGE_CTRL_RANGEADJ5(x)
#define	PDM_RANGE_CTRL_RANGEADJ6_MASK   (0xF000000U)
#define	PDM_RANGE_CTRL_RANGEADJ6_SHIFT   (24U)
#define	PDM_RANGE_CTRL_RANGEADJ6(x)
#define	PDM_RANGE_CTRL_RANGEADJ7_MASK   (0xF0000000U)
#define	PDM_RANGE_CTRL_RANGEADJ7_SHIFT   (28U)
#define	PDM_RANGE_CTRL_RANGEADJ7(x)
RANGE_STAT - PDM Range Status register
#define	PDM_RANGE_STAT_RANGEOVF0_MASK   (0x1U)
#define	PDM_RANGE_STAT_RANGEOVF0_SHIFT   (0U)
#define	PDM_RANGE_STAT_RANGEOVF0(x)
#define	PDM_RANGE_STAT_RANGEOVF1_MASK   (0x2U)
#define	PDM_RANGE_STAT_RANGEOVF1_SHIFT   (1U)
#define	PDM_RANGE_STAT_RANGEOVF1(x)
#define	PDM_RANGE_STAT_RANGEOVF2_MASK   (0x4U)
#define	PDM_RANGE_STAT_RANGEOVF2_SHIFT   (2U)
#define	PDM_RANGE_STAT_RANGEOVF2(x)
#define	PDM_RANGE_STAT_RANGEOVF3_MASK   (0x8U)
#define	PDM_RANGE_STAT_RANGEOVF3_SHIFT   (3U)
#define	PDM_RANGE_STAT_RANGEOVF3(x)
#define	PDM_RANGE_STAT_RANGEOVF4_MASK   (0x10U)
#define	PDM_RANGE_STAT_RANGEOVF4_SHIFT   (4U)
#define	PDM_RANGE_STAT_RANGEOVF4(x)
#define	PDM_RANGE_STAT_RANGEOVF5_MASK   (0x20U)
#define	PDM_RANGE_STAT_RANGEOVF5_SHIFT   (5U)
#define	PDM_RANGE_STAT_RANGEOVF5(x)
#define	PDM_RANGE_STAT_RANGEOVF6_MASK   (0x40U)
#define	PDM_RANGE_STAT_RANGEOVF6_SHIFT   (6U)
#define	PDM_RANGE_STAT_RANGEOVF6(x)
#define	PDM_RANGE_STAT_RANGEOVF7_MASK   (0x80U)
#define	PDM_RANGE_STAT_RANGEOVF7_SHIFT   (7U)
#define	PDM_RANGE_STAT_RANGEOVF7(x)
#define	PDM_RANGE_STAT_RANGEUNF0_MASK   (0x10000U)
#define	PDM_RANGE_STAT_RANGEUNF0_SHIFT   (16U)
#define	PDM_RANGE_STAT_RANGEUNF0(x)
#define	PDM_RANGE_STAT_RANGEUNF1_MASK   (0x20000U)
#define	PDM_RANGE_STAT_RANGEUNF1_SHIFT   (17U)
#define	PDM_RANGE_STAT_RANGEUNF1(x)
#define	PDM_RANGE_STAT_RANGEUNF2_MASK   (0x40000U)
#define	PDM_RANGE_STAT_RANGEUNF2_SHIFT   (18U)
#define	PDM_RANGE_STAT_RANGEUNF2(x)
#define	PDM_RANGE_STAT_RANGEUNF3_MASK   (0x80000U)
#define	PDM_RANGE_STAT_RANGEUNF3_SHIFT   (19U)
#define	PDM_RANGE_STAT_RANGEUNF3(x)
#define	PDM_RANGE_STAT_RANGEUNF4_MASK   (0x100000U)
#define	PDM_RANGE_STAT_RANGEUNF4_SHIFT   (20U)
#define	PDM_RANGE_STAT_RANGEUNF4(x)
#define	PDM_RANGE_STAT_RANGEUNF5_MASK   (0x200000U)
#define	PDM_RANGE_STAT_RANGEUNF5_SHIFT   (21U)
#define	PDM_RANGE_STAT_RANGEUNF5(x)
#define	PDM_RANGE_STAT_RANGEUNF6_MASK   (0x400000U)
#define	PDM_RANGE_STAT_RANGEUNF6_SHIFT   (22U)
#define	PDM_RANGE_STAT_RANGEUNF6(x)
#define	PDM_RANGE_STAT_RANGEUNF7_MASK   (0x800000U)
#define	PDM_RANGE_STAT_RANGEUNF7_SHIFT   (23U)
#define	PDM_RANGE_STAT_RANGEUNF7(x)
VAD0_CTRL_1 - Voice Activity Detector 0 Control register
#define	PDM_VAD0_CTRL_1_VADEN_MASK   (0x1U)
#define	PDM_VAD0_CTRL_1_VADEN_SHIFT   (0U)
#define	PDM_VAD0_CTRL_1_VADEN(x)
#define	PDM_VAD0_CTRL_1_VADRST_MASK   (0x2U)
#define	PDM_VAD0_CTRL_1_VADRST_SHIFT   (1U)
#define	PDM_VAD0_CTRL_1_VADRST(x)
#define	PDM_VAD0_CTRL_1_VADIE_MASK   (0x4U)
#define	PDM_VAD0_CTRL_1_VADIE_SHIFT   (2U)
#define	PDM_VAD0_CTRL_1_VADIE(x)
#define	PDM_VAD0_CTRL_1_VADERIE_MASK   (0x8U)
#define	PDM_VAD0_CTRL_1_VADERIE_SHIFT   (3U)
#define	PDM_VAD0_CTRL_1_VADERIE(x)
#define	PDM_VAD0_CTRL_1_VADST10_MASK   (0x10U)
#define	PDM_VAD0_CTRL_1_VADST10_SHIFT   (4U)
#define	PDM_VAD0_CTRL_1_VADST10(x)
#define	PDM_VAD0_CTRL_1_VADINITT_MASK   (0x1F00U)
#define	PDM_VAD0_CTRL_1_VADINITT_SHIFT   (8U)
#define	PDM_VAD0_CTRL_1_VADINITT(x)
#define	PDM_VAD0_CTRL_1_VADCICOSR_MASK   (0xF0000U)
#define	PDM_VAD0_CTRL_1_VADCICOSR_SHIFT   (16U)
#define	PDM_VAD0_CTRL_1_VADCICOSR(x)
#define	PDM_VAD0_CTRL_1_VADCHSEL_MASK   (0x7000000U)
#define	PDM_VAD0_CTRL_1_VADCHSEL_SHIFT   (24U)
#define	PDM_VAD0_CTRL_1_VADCHSEL(x)
VAD0_CTRL_2 - Voice Activity Detector 0 Control register
#define	PDM_VAD0_CTRL_2_VADHPF_MASK   (0x3U)
#define	PDM_VAD0_CTRL_2_VADHPF_SHIFT   (0U)
#define	PDM_VAD0_CTRL_2_VADHPF(x)
#define	PDM_VAD0_CTRL_2_VADINPGAIN_MASK   (0xF00U)
#define	PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT   (8U)
#define	PDM_VAD0_CTRL_2_VADINPGAIN(x)
#define	PDM_VAD0_CTRL_2_VADFRAMET_MASK   (0x3F0000U)
#define	PDM_VAD0_CTRL_2_VADFRAMET_SHIFT   (16U)
#define	PDM_VAD0_CTRL_2_VADFRAMET(x)
#define	PDM_VAD0_CTRL_2_VADFOUTDIS_MASK   (0x10000000U)
#define	PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT   (28U)
#define	PDM_VAD0_CTRL_2_VADFOUTDIS(x)
#define	PDM_VAD0_CTRL_2_VADPREFEN_MASK   (0x40000000U)
#define	PDM_VAD0_CTRL_2_VADPREFEN_SHIFT   (30U)
#define	PDM_VAD0_CTRL_2_VADPREFEN(x)
#define	PDM_VAD0_CTRL_2_VADFRENDIS_MASK   (0x80000000U)
#define	PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT   (31U)
#define	PDM_VAD0_CTRL_2_VADFRENDIS(x)
VAD0_STAT - Voice Activity Detector 0 Status register
#define	PDM_VAD0_STAT_VADIF_MASK   (0x1U)
#define	PDM_VAD0_STAT_VADIF_SHIFT   (0U)
#define	PDM_VAD0_STAT_VADIF(x)
#define	PDM_VAD0_STAT_VADEF_MASK   (0x8000U)
#define	PDM_VAD0_STAT_VADEF_SHIFT   (15U)
#define	PDM_VAD0_STAT_VADEF(x)
#define	PDM_VAD0_STAT_VADINSATF_MASK   (0x10000U)
#define	PDM_VAD0_STAT_VADINSATF_SHIFT   (16U)
#define	PDM_VAD0_STAT_VADINSATF(x)
#define	PDM_VAD0_STAT_VADINITF_MASK   (0x80000000U)
#define	PDM_VAD0_STAT_VADINITF_SHIFT   (31U)
#define	PDM_VAD0_STAT_VADINITF(x)
VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration
#define	PDM_VAD0_SCONFIG_VADSGAIN_MASK   (0xFU)
#define	PDM_VAD0_SCONFIG_VADSGAIN_SHIFT   (0U)
#define	PDM_VAD0_SCONFIG_VADSGAIN(x)
#define	PDM_VAD0_SCONFIG_VADSMAXEN_MASK   (0x40000000U)
#define	PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT   (30U)
#define	PDM_VAD0_SCONFIG_VADSMAXEN(x)
#define	PDM_VAD0_SCONFIG_VADSFILEN_MASK   (0x80000000U)
#define	PDM_VAD0_SCONFIG_VADSFILEN_SHIFT   (31U)
#define	PDM_VAD0_SCONFIG_VADSFILEN(x)
VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration
#define	PDM_VAD0_NCONFIG_VADNGAIN_MASK   (0xFU)
#define	PDM_VAD0_NCONFIG_VADNGAIN_SHIFT   (0U)
#define	PDM_VAD0_NCONFIG_VADNGAIN(x)
#define	PDM_VAD0_NCONFIG_VADNFILADJ_MASK   (0x1F00U)
#define	PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT   (8U)
#define	PDM_VAD0_NCONFIG_VADNFILADJ(x)
#define	PDM_VAD0_NCONFIG_VADNOREN_MASK   (0x10000000U)
#define	PDM_VAD0_NCONFIG_VADNOREN_SHIFT   (28U)
#define	PDM_VAD0_NCONFIG_VADNOREN(x)
#define	PDM_VAD0_NCONFIG_VADNDECEN_MASK   (0x20000000U)
#define	PDM_VAD0_NCONFIG_VADNDECEN_SHIFT   (29U)
#define	PDM_VAD0_NCONFIG_VADNDECEN(x)
#define	PDM_VAD0_NCONFIG_VADNMINEN_MASK   (0x40000000U)
#define	PDM_VAD0_NCONFIG_VADNMINEN_SHIFT   (30U)
#define	PDM_VAD0_NCONFIG_VADNMINEN(x)
#define	PDM_VAD0_NCONFIG_VADNFILAUTO_MASK   (0x80000000U)
#define	PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT   (31U)
#define	PDM_VAD0_NCONFIG_VADNFILAUTO(x)
VAD0_NDATA - Voice Activity Detector 0 Noise Data
#define	PDM_VAD0_NDATA_VADNDATA_MASK   (0xFFFFU)
#define	PDM_VAD0_NDATA_VADNDATA_SHIFT   (0U)
#define	PDM_VAD0_NDATA_VADNDATA(x)
VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector
#define	PDM_VAD0_ZCD_VADZCDEN_MASK   (0x1U)
#define	PDM_VAD0_ZCD_VADZCDEN_SHIFT   (0U)
#define	PDM_VAD0_ZCD_VADZCDEN(x)
#define	PDM_VAD0_ZCD_VADZCDAUTO_MASK   (0x4U)
#define	PDM_VAD0_ZCD_VADZCDAUTO_SHIFT   (2U)
#define	PDM_VAD0_ZCD_VADZCDAUTO(x)
#define	PDM_VAD0_ZCD_VADZCDAND_MASK   (0x10U)
#define	PDM_VAD0_ZCD_VADZCDAND_SHIFT   (4U)
#define	PDM_VAD0_ZCD_VADZCDAND(x)
#define	PDM_VAD0_ZCD_VADZCDADJ_MASK   (0xF00U)
#define	PDM_VAD0_ZCD_VADZCDADJ_SHIFT   (8U)
#define	PDM_VAD0_ZCD_VADZCDADJ(x)
#define	PDM_VAD0_ZCD_VADZCDTH_MASK   (0x3FF0000U)
#define	PDM_VAD0_ZCD_VADZCDTH_SHIFT   (16U)
#define	PDM_VAD0_ZCD_VADZCDTH(x)
BPC_AUTHEN_CTRL - BPC Authentication Control
#define	PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK   (0x1U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT   (0U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_USER(x)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK   (0x2U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT   (1U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK   (0x10U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT   (4U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK   (0xF00U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT   (8U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK   (0x1000U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT   (12U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x)
BPC_MODE - BPC Mode
#define	PGMC_BPC_BPC_MODE_CTRL_MODE_MASK   (0x3U)
#define	PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT   (0U)
#define	PGMC_BPC_BPC_MODE_CTRL_MODE(x)
#define	PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK   (0x30U)
#define	PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT   (4U)
#define	PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x)
BPC_POWER_CTRL - BPC power control
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK   (0x2U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT   (1U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK   (0x4U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT   (2U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK   (0x8U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT   (3U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x)
#define	PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK   (0x100U)
#define	PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT   (8U)
#define	PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x)
#define	PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK   (0x200U)
#define	PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT   (9U)
#define	PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x)
#define	PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK   (0x400U)
#define	PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT   (10U)
#define	PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x)
#define	PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK   (0x800U)
#define	PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT   (11U)
#define	PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK   (0xFFFF0000U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT   (16U)
#define	PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x)
BPC_FLAG - BPC flag
#define	PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK   (0x1U)
#define	PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT   (0U)
#define	PGMC_BPC_BPC_FLAG_PDN_FLAG(x)
BPC_SSAR_SAVE_CTRL - BPC SSAR save control
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK   (0x1U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT   (0U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK   (0x2U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT   (1U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK   (0x4U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT   (2U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK   (0x8U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT   (3U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK   (0xFFFF0000U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT   (16U)
#define	PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x)
BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control
#define	PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK   (0x1U)
#define	PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT   (0U)
#define	PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x)
#define	PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK   (0xFFFF0000U)
#define	PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT   (16U)
#define	PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x)
CPC_AUTHEN_CTRL - CPC Authentication Control
#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK   (0x1U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT   (0U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER(x)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK   (0x2U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT   (1U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK   (0x10U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT   (4U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK   (0xF00U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT   (8U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK   (0x1000U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT   (12U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x)
CPC_CORE_MODE - CPC Core Mode
#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK   (0x3U)
#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT   (0U)
#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x)
CPC_CORE_POWER_CTRL - CPC core power control
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK   (0x2U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT   (1U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK   (0x4U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT   (2U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK   (0x8U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT   (3U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK   (0x100U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT   (8U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK   (0x200U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT   (9U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK   (0x400U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT   (10U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK   (0x800U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT   (11U)
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x)
CPC_FLAG - CPC flag
#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK   (0x1U)
#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT   (0U)
#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x)
CPC_CACHE_MODE - CPC Cache Mode
#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK   (0x3U)
#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT   (0U)
#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x)
CPC_CACHE_CM_CTRL - CPC cache CPU mode control
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK   (0xFU)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT   (0U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK   (0xF0U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT   (4U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK   (0xF00U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT   (8U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK   (0xF000U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT   (12U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK   (0x10000U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT   (16U)
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x)
CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK   (0xFU)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT   (0U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK   (0xF0U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT   (4U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK   (0xF00U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT   (8U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK   (0xF000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT   (12U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK   (0xF0000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT   (16U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK   (0xF00000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT   (20U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK   (0xF000000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT   (24U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK   (0xF0000000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT   (28U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x)
CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK   (0xFU)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT   (0U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK   (0xF0U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT   (4U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK   (0xF00U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT   (8U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK   (0xF000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT   (12U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK   (0xF0000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT   (16U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK   (0xF00000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT   (20U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK   (0xF000000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT   (24U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK   (0xF0000000U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT   (28U)
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x)
CPC_LMEM_MODE - CPC local memory Mode
#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK   (0x3U)
#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT   (0U)
#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x)
CPC_LMEM_CM_CTRL - CPC local memory CPU mode control
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK   (0xFU)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT   (0U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK   (0xF0U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT   (4U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK   (0xF00U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT   (8U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK   (0xF000U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT   (12U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK   (0x10000U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT   (16U)
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x)
CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK   (0xFU)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT   (0U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK   (0xF0U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT   (4U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK   (0xF00U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT   (8U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK   (0xF000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT   (12U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK   (0xF0000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT   (16U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK   (0xF00000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT   (20U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK   (0xF000000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT   (24U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK   (0xF0000000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT   (28U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x)
CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK   (0xFU)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT   (0U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK   (0xF0U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT   (4U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK   (0xF00U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT   (8U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK   (0xF000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT   (12U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK   (0xF0000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT   (16U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK   (0xF00000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT   (20U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK   (0xF000000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT   (24U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK   (0xF0000000U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT   (28U)
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x)
MIF_AUTHEN_CTRL - MIF Authentication Control
#define	PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x)
MIF_MLPL_SLEEP - MIF MLPL control of SLEEP
#define	PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x)
MIF_MLPL_IG - MIF MLPL control of IG
#define	PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x)
MIF_MLPL_LS - MIF MLPL control of LS
#define	PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x)
MIF_MLPL_HS - MIF MLPL control of HS
#define	PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x)
MIF_MLPL_STDBY - MIF MLPL control of STDBY
#define	PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x)
MIF_MLPL_ARR_PDN - MIF MLPL control of array power down
#define	PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x)
MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down
#define	PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x)
MIF_MLPL_INITN - MIF MLPL control of INITN
#define	PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x)
#define	PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK   (0x80000000U)
#define	PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT   (31U)
#define	PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x)
MIF_MLPL_ISO - MIF MLPL control of isolation enable
#define	PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK   (0xFFFFU)
#define	PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT   (0U)
#define	PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x)
PPC_AUTHEN_CTRL - PPC Authentication Control
#define	PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK   (0x1U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT   (0U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_USER(x)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK   (0x2U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT   (1U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK   (0x10U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT   (4U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK   (0xF00U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT   (8U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK   (0x1000U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT   (12U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT   (20U)
#define	PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x)
PPC_MODE - PPC Mode
#define	PGMC_PPC_PPC_MODE_CTRL_MODE_MASK   (0x3U)
#define	PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT   (0U)
#define	PGMC_PPC_PPC_MODE_CTRL_MODE(x)
#define	PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK   (0x30U)
#define	PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT   (4U)
#define	PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x)
PPC_STBY_CM_CTRL - PPC standby CPU mode control
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK   (0x2U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT   (1U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK   (0x4U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT   (2U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK   (0x8U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT   (3U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK   (0x100U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT   (8U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK   (0x200U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT   (9U)
#define	PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x)
PPC_STBY_SP_CTRL - PPC standby Setpoint control
#define	PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK   (0xFFFFU)
#define	PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT   (0U)
#define	PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x)
#define	PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK   (0xFFFF0000U)
#define	PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT   (16U)
#define	PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x)
CTRL0 - Analog Control Register CTRL0
#define	PHY_LDO_CTRL0_LINREG_EN_MASK   (0x1U)
#define	PHY_LDO_CTRL0_LINREG_EN_SHIFT   (0U)
#define	PHY_LDO_CTRL0_LINREG_EN(x)
#define	PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK   (0x2U)
#define	PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT   (1U)
#define	PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x)
#define	PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK   (0x4U)
#define	PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT   (2U)
#define	PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x)
#define	PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK   (0x1F0U)
#define	PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT   (4U)
#define	PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x)
#define	PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK   (0x8000U)
#define	PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT   (15U)
#define	PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x)
#define	VMBANDGAP_CTRL0_REFTOP_PWD_MASK   (0x1U)
#define	VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT   (0U)
#define	VMBANDGAP_CTRL0_REFTOP_PWD(x)
#define	VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK   (0x2U)
#define	VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT   (1U)
#define	VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)
#define	VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK   (0x4U)
#define	VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT   (2U)
#define	VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x)
#define	VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK   (0x8U)
#define	VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT   (3U)
#define	VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x)
#define	VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK   (0x10U)
#define	VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT   (4U)
#define	VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)
STAT0 - Analog Status Register STAT0
#define	PHY_LDO_STAT0_LINREG_STAT_MASK   (0xFU)
#define	PHY_LDO_STAT0_LINREG_STAT_SHIFT   (0U)
#define	PHY_LDO_STAT0_LINREG_STAT(x)
#define	VMBANDGAP_STAT0_REFTOP_VBGUP_MASK   (0x1U)
#define	VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT   (0U)
#define	VMBANDGAP_STAT0_REFTOP_VBGUP(x)
#define	VMBANDGAP_STAT0_VDD1_PORB_MASK   (0x2U)
#define	VMBANDGAP_STAT0_VDD1_PORB_SHIFT   (1U)
#define	VMBANDGAP_STAT0_VDD1_PORB(x)
#define	VMBANDGAP_STAT0_VDD2_PORB_MASK   (0x4U)
#define	VMBANDGAP_STAT0_VDD2_PORB_SHIFT   (2U)
#define	VMBANDGAP_STAT0_VDD2_PORB(x)
#define	VMBANDGAP_STAT0_VDD3_PORB_MASK   (0x8U)
#define	VMBANDGAP_STAT0_VDD3_PORB_SHIFT   (3U)
#define	VMBANDGAP_STAT0_VDD3_PORB(x)
MCR - PIT Module Control Register
#define	PIT_MCR_FRZ_MASK   (0x1U)
#define	PIT_MCR_FRZ_SHIFT   (0U)
#define	PIT_MCR_FRZ(x)
#define	PIT_MCR_MDIS_MASK   (0x2U)
#define	PIT_MCR_MDIS_SHIFT   (1U)
#define	PIT_MCR_MDIS(x)
LTMR64H - PIT Upper Lifetime Timer Register
#define	PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64H_LTH_SHIFT   (0U)
#define	PIT_LTMR64H_LTH(x)
LTMR64L - PIT Lower Lifetime Timer Register
#define	PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64L_LTL_SHIFT   (0U)
#define	PIT_LTMR64L_LTL(x)
LDVAL - Timer Load Value Register
#define	PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
#define	PIT_LDVAL_TSV_SHIFT   (0U)
#define	PIT_LDVAL_TSV(x)
CVAL - Current Timer Value Register
#define	PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
#define	PIT_CVAL_TVL_SHIFT   (0U)
#define	PIT_CVAL_TVL(x)
TCTRL - Timer Control Register
#define	PIT_TCTRL_TEN_MASK   (0x1U)
#define	PIT_TCTRL_TEN_SHIFT   (0U)
#define	PIT_TCTRL_TEN(x)
#define	PIT_TCTRL_TIE_MASK   (0x2U)
#define	PIT_TCTRL_TIE_SHIFT   (1U)
#define	PIT_TCTRL_TIE(x)
#define	PIT_TCTRL_CHN_MASK   (0x4U)
#define	PIT_TCTRL_CHN_SHIFT   (2U)
#define	PIT_TCTRL_CHN(x)
TFLG - Timer Flag Register
#define	PIT_TFLG_TIF_MASK   (0x1U)
#define	PIT_TFLG_TIF_SHIFT   (0U)
#define	PIT_TFLG_TIF(x)
CTRL - PUF Control Register
#define	PUF_CTRL_ZEROIZE_MASK   (0x1U)
#define	PUF_CTRL_ZEROIZE_SHIFT   (0U)
#define	PUF_CTRL_ZEROIZE(x)
#define	PUF_CTRL_ENROLL_MASK   (0x2U)
#define	PUF_CTRL_ENROLL_SHIFT   (1U)
#define	PUF_CTRL_ENROLL(x)
#define	PUF_CTRL_START_MASK   (0x4U)
#define	PUF_CTRL_START_SHIFT   (2U)
#define	PUF_CTRL_START(x)
#define	PUF_CTRL_GENERATEKEY_MASK   (0x8U)
#define	PUF_CTRL_GENERATEKEY_SHIFT   (3U)
#define	PUF_CTRL_GENERATEKEY(x)
#define	PUF_CTRL_SETKEY_MASK   (0x10U)
#define	PUF_CTRL_SETKEY_SHIFT   (4U)
#define	PUF_CTRL_SETKEY(x)
#define	PUF_CTRL_GETKEY_MASK   (0x40U)
#define	PUF_CTRL_GETKEY_SHIFT   (6U)
#define	PUF_CTRL_GETKEY(x)
KEYINDEX - PUF Key Index Register
#define	PUF_KEYINDEX_KEYIDX_MASK   (0xFU)
#define	PUF_KEYINDEX_KEYIDX_SHIFT   (0U)
#define	PUF_KEYINDEX_KEYIDX(x)
KEYSIZE - PUF Key Size Register
#define	PUF_KEYSIZE_KEYSIZE_MASK   (0x3FU)
#define	PUF_KEYSIZE_KEYSIZE_SHIFT   (0U)
#define	PUF_KEYSIZE_KEYSIZE(x)
STAT - PUF Status Register
#define	PUF_STAT_BUSY_MASK   (0x1U)
#define	PUF_STAT_BUSY_SHIFT   (0U)
#define	PUF_STAT_BUSY(x)
#define	PUF_STAT_SUCCESS_MASK   (0x2U)
#define	PUF_STAT_SUCCESS_SHIFT   (1U)
#define	PUF_STAT_SUCCESS(x)
#define	PUF_STAT_ERROR_MASK   (0x4U)
#define	PUF_STAT_ERROR_SHIFT   (2U)
#define	PUF_STAT_ERROR(x)
#define	PUF_STAT_KEYINREQ_MASK   (0x10U)
#define	PUF_STAT_KEYINREQ_SHIFT   (4U)
#define	PUF_STAT_KEYINREQ(x)
#define	PUF_STAT_KEYOUTAVAIL_MASK   (0x20U)
#define	PUF_STAT_KEYOUTAVAIL_SHIFT   (5U)
#define	PUF_STAT_KEYOUTAVAIL(x)
#define	PUF_STAT_CODEINREQ_MASK   (0x40U)
#define	PUF_STAT_CODEINREQ_SHIFT   (6U)
#define	PUF_STAT_CODEINREQ(x)
#define	PUF_STAT_CODEOUTAVAIL_MASK   (0x80U)
#define	PUF_STAT_CODEOUTAVAIL_SHIFT   (7U)
#define	PUF_STAT_CODEOUTAVAIL(x)
ALLOW - PUF Allow Register
#define	PUF_ALLOW_ALLOWENROLL_MASK   (0x1U)
#define	PUF_ALLOW_ALLOWENROLL_SHIFT   (0U)
#define	PUF_ALLOW_ALLOWENROLL(x)
#define	PUF_ALLOW_ALLOWSTART_MASK   (0x2U)
#define	PUF_ALLOW_ALLOWSTART_SHIFT   (1U)
#define	PUF_ALLOW_ALLOWSTART(x)
#define	PUF_ALLOW_ALLOWSETKEY_MASK   (0x4U)
#define	PUF_ALLOW_ALLOWSETKEY_SHIFT   (2U)
#define	PUF_ALLOW_ALLOWSETKEY(x)
#define	PUF_ALLOW_ALLOWGETKEY_MASK   (0x8U)
#define	PUF_ALLOW_ALLOWGETKEY_SHIFT   (3U)
#define	PUF_ALLOW_ALLOWGETKEY(x)
KEYINPUT - PUF Key Input Register
#define	PUF_KEYINPUT_KEYIN_MASK   (0xFFFFFFFFU)
#define	PUF_KEYINPUT_KEYIN_SHIFT   (0U)
#define	PUF_KEYINPUT_KEYIN(x)
CODEINPUT - PUF Code Input Register
#define	PUF_CODEINPUT_CODEIN_MASK   (0xFFFFFFFFU)
#define	PUF_CODEINPUT_CODEIN_SHIFT   (0U)
#define	PUF_CODEINPUT_CODEIN(x)
CODEOUTPUT - PUF Code Output Register
#define	PUF_CODEOUTPUT_CODEOUT_MASK   (0xFFFFFFFFU)
#define	PUF_CODEOUTPUT_CODEOUT_SHIFT   (0U)
#define	PUF_CODEOUTPUT_CODEOUT(x)
KEYOUTINDEX - PUF Key Output Index Register
#define	PUF_KEYOUTINDEX_KEYOUTIDX_MASK   (0xFFFFFFFFU)
#define	PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT   (0U)
#define	PUF_KEYOUTINDEX_KEYOUTIDX(x)
KEYOUTPUT - PUF Key Output Register
#define	PUF_KEYOUTPUT_KEYOUT_MASK   (0xFFFFFFFFU)
#define	PUF_KEYOUTPUT_KEYOUT_SHIFT   (0U)
#define	PUF_KEYOUTPUT_KEYOUT(x)
IFSTAT - PUF Interface Status Register
#define	PUF_IFSTAT_ERROR_MASK   (0x1U)
#define	PUF_IFSTAT_ERROR_SHIFT   (0U)
#define	PUF_IFSTAT_ERROR(x)
VERSION - PUF Version Register
#define	PUF_VERSION_VERSION_MASK   (0xFFFFFFFFU)
#define	PUF_VERSION_VERSION_SHIFT   (0U)
#define	PUF_VERSION_VERSION(x)
INTEN - PUF Interrupt Enable
#define	PUF_INTEN_READYEN_MASK   (0x1U)
#define	PUF_INTEN_READYEN_SHIFT   (0U)
#define	PUF_INTEN_READYEN(x)
#define	PUF_INTEN_SUCCESSEN_MASK   (0x2U)
#define	PUF_INTEN_SUCCESSEN_SHIFT   (1U)
#define	PUF_INTEN_SUCCESSEN(x)
#define	PUF_INTEN_ERROREN_MASK   (0x4U)
#define	PUF_INTEN_ERROREN_SHIFT   (2U)
#define	PUF_INTEN_ERROREN(x)
#define	PUF_INTEN_KEYINREQEN_MASK   (0x10U)
#define	PUF_INTEN_KEYINREQEN_SHIFT   (4U)
#define	PUF_INTEN_KEYINREQEN(x)
#define	PUF_INTEN_KEYOUTAVAILEN_MASK   (0x20U)
#define	PUF_INTEN_KEYOUTAVAILEN_SHIFT   (5U)
#define	PUF_INTEN_KEYOUTAVAILEN(x)
#define	PUF_INTEN_CODEINREQEN_MASK   (0x40U)
#define	PUF_INTEN_CODEINREQEN_SHIFT   (6U)
#define	PUF_INTEN_CODEINREQEN(x)
#define	PUF_INTEN_CODEOUTAVAILEN_MASK   (0x80U)
#define	PUF_INTEN_CODEOUTAVAILEN_SHIFT   (7U)
#define	PUF_INTEN_CODEOUTAVAILEN(x)
INTSTAT - PUF Interrupt Status
#define	PUF_INTSTAT_READY_MASK   (0x1U)
#define	PUF_INTSTAT_READY_SHIFT   (0U)
#define	PUF_INTSTAT_READY(x)
#define	PUF_INTSTAT_SUCCESS_MASK   (0x2U)
#define	PUF_INTSTAT_SUCCESS_SHIFT   (1U)
#define	PUF_INTSTAT_SUCCESS(x)
#define	PUF_INTSTAT_ERROR_MASK   (0x4U)
#define	PUF_INTSTAT_ERROR_SHIFT   (2U)
#define	PUF_INTSTAT_ERROR(x)
#define	PUF_INTSTAT_KEYINREQ_MASK   (0x10U)
#define	PUF_INTSTAT_KEYINREQ_SHIFT   (4U)
#define	PUF_INTSTAT_KEYINREQ(x)
#define	PUF_INTSTAT_KEYOUTAVAIL_MASK   (0x20U)
#define	PUF_INTSTAT_KEYOUTAVAIL_SHIFT   (5U)
#define	PUF_INTSTAT_KEYOUTAVAIL(x)
#define	PUF_INTSTAT_CODEINREQ_MASK   (0x40U)
#define	PUF_INTSTAT_CODEINREQ_SHIFT   (6U)
#define	PUF_INTSTAT_CODEINREQ(x)
#define	PUF_INTSTAT_CODEOUTAVAIL_MASK   (0x80U)
#define	PUF_INTSTAT_CODEOUTAVAIL_SHIFT   (7U)
#define	PUF_INTSTAT_CODEOUTAVAIL(x)
PWRCTRL - PUF Power Control Of RAM
#define	PUF_PWRCTRL_RAM_ON_MASK   (0x1U)
#define	PUF_PWRCTRL_RAM_ON_SHIFT   (0U)
#define	PUF_PWRCTRL_RAM_ON(x)
#define	PUF_PWRCTRL_CK_DIS_MASK   (0x4U)
#define	PUF_PWRCTRL_CK_DIS_SHIFT   (2U)
#define	PUF_PWRCTRL_CK_DIS(x)
#define	PUF_PWRCTRL_RAM_INITN_MASK   (0x8U)
#define	PUF_PWRCTRL_RAM_INITN_SHIFT   (3U)
#define	PUF_PWRCTRL_RAM_INITN(x)
#define	PUF_PWRCTRL_RAM_PSW_MASK   (0xF0U)
#define	PUF_PWRCTRL_RAM_PSW_SHIFT   (4U)
#define	PUF_PWRCTRL_RAM_PSW(x)
CFG - PUF Configuration Register
#define	PUF_CFG_PUF_BLOCK_SET_KEY_MASK   (0x1U)
#define	PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT   (0U)
#define	PUF_CFG_PUF_BLOCK_SET_KEY(x)
#define	PUF_CFG_PUF_BLOCK_ENROLL_MASK   (0x2U)
#define	PUF_CFG_PUF_BLOCK_ENROLL_SHIFT   (1U)
#define	PUF_CFG_PUF_BLOCK_ENROLL(x)
KEYLOCK - PUF Key Manager Lock
#define	PUF_KEYLOCK_LOCK0_MASK   (0x3U)
#define	PUF_KEYLOCK_LOCK0_SHIFT   (0U)
#define	PUF_KEYLOCK_LOCK0(x)
#define	PUF_KEYLOCK_LOCK1_MASK   (0xCU)
#define	PUF_KEYLOCK_LOCK1_SHIFT   (2U)
#define	PUF_KEYLOCK_LOCK1(x)
KEYENABLE - PUF Key Manager Enable
#define	PUF_KEYENABLE_ENABLE0_MASK   (0x3U)
#define	PUF_KEYENABLE_ENABLE0_SHIFT   (0U)
#define	PUF_KEYENABLE_ENABLE0(x)
#define	PUF_KEYENABLE_ENABLE1_MASK   (0xCU)
#define	PUF_KEYENABLE_ENABLE1_SHIFT   (2U)
#define	PUF_KEYENABLE_ENABLE1(x)
KEYRESET - PUF Key Manager Reset
#define	PUF_KEYRESET_RESET0_MASK   (0x3U)
#define	PUF_KEYRESET_RESET0_SHIFT   (0U)
#define	PUF_KEYRESET_RESET0(x)
#define	PUF_KEYRESET_RESET1_MASK   (0xCU)
#define	PUF_KEYRESET_RESET1_SHIFT   (2U)
#define	PUF_KEYRESET_RESET1(x)
IDXBLK - PUF Index Block Key Output
#define	PUF_IDXBLK_IDXBLK0_MASK   (0x3U)
#define	PUF_IDXBLK_IDXBLK0_SHIFT   (0U)
#define	PUF_IDXBLK_IDXBLK0(x)
#define	PUF_IDXBLK_IDXBLK1_MASK   (0xCU)
#define	PUF_IDXBLK_IDXBLK1_SHIFT   (2U)
#define	PUF_IDXBLK_IDXBLK1(x)
#define	PUF_IDXBLK_IDXBLK2_MASK   (0x30U)
#define	PUF_IDXBLK_IDXBLK2_SHIFT   (4U)
#define	PUF_IDXBLK_IDXBLK2(x)
#define	PUF_IDXBLK_IDXBLK3_MASK   (0xC0U)
#define	PUF_IDXBLK_IDXBLK3_SHIFT   (6U)
#define	PUF_IDXBLK_IDXBLK3(x)
#define	PUF_IDXBLK_IDXBLK4_MASK   (0x300U)
#define	PUF_IDXBLK_IDXBLK4_SHIFT   (8U)
#define	PUF_IDXBLK_IDXBLK4(x)
#define	PUF_IDXBLK_IDXBLK5_MASK   (0xC00U)
#define	PUF_IDXBLK_IDXBLK5_SHIFT   (10U)
#define	PUF_IDXBLK_IDXBLK5(x)
#define	PUF_IDXBLK_IDXBLK6_MASK   (0x3000U)
#define	PUF_IDXBLK_IDXBLK6_SHIFT   (12U)
#define	PUF_IDXBLK_IDXBLK6(x)
#define	PUF_IDXBLK_IDXBLK7_MASK   (0xC000U)
#define	PUF_IDXBLK_IDXBLK7_SHIFT   (14U)
#define	PUF_IDXBLK_IDXBLK7(x)
#define	PUF_IDXBLK_IDXBLK8_MASK   (0x30000U)
#define	PUF_IDXBLK_IDXBLK8_SHIFT   (16U)
#define	PUF_IDXBLK_IDXBLK8(x)
#define	PUF_IDXBLK_IDXBLK9_MASK   (0xC0000U)
#define	PUF_IDXBLK_IDXBLK9_SHIFT   (18U)
#define	PUF_IDXBLK_IDXBLK9(x)
#define	PUF_IDXBLK_IDXBLK10_MASK   (0x300000U)
#define	PUF_IDXBLK_IDXBLK10_SHIFT   (20U)
#define	PUF_IDXBLK_IDXBLK10(x)
#define	PUF_IDXBLK_IDXBLK11_MASK   (0xC00000U)
#define	PUF_IDXBLK_IDXBLK11_SHIFT   (22U)
#define	PUF_IDXBLK_IDXBLK11(x)
#define	PUF_IDXBLK_IDXBLK12_MASK   (0x3000000U)
#define	PUF_IDXBLK_IDXBLK12_SHIFT   (24U)
#define	PUF_IDXBLK_IDXBLK12(x)
#define	PUF_IDXBLK_IDXBLK13_MASK   (0xC000000U)
#define	PUF_IDXBLK_IDXBLK13_SHIFT   (26U)
#define	PUF_IDXBLK_IDXBLK13(x)
#define	PUF_IDXBLK_IDXBLK14_MASK   (0x30000000U)
#define	PUF_IDXBLK_IDXBLK14_SHIFT   (28U)
#define	PUF_IDXBLK_IDXBLK14(x)
#define	PUF_IDXBLK_IDXBLK15_MASK   (0xC0000000U)
#define	PUF_IDXBLK_IDXBLK15_SHIFT   (30U)
#define	PUF_IDXBLK_IDXBLK15(x)
IDXBLK_DP - PUF Index Block Key Output
#define	PUF_IDXBLK_DP_IDXBLK_DP0_MASK   (0x3U)
#define	PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT   (0U)
#define	PUF_IDXBLK_DP_IDXBLK_DP0(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP1_MASK   (0xCU)
#define	PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT   (2U)
#define	PUF_IDXBLK_DP_IDXBLK_DP1(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP2_MASK   (0x30U)
#define	PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT   (4U)
#define	PUF_IDXBLK_DP_IDXBLK_DP2(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP3_MASK   (0xC0U)
#define	PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT   (6U)
#define	PUF_IDXBLK_DP_IDXBLK_DP3(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP4_MASK   (0x300U)
#define	PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT   (8U)
#define	PUF_IDXBLK_DP_IDXBLK_DP4(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP5_MASK   (0xC00U)
#define	PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT   (10U)
#define	PUF_IDXBLK_DP_IDXBLK_DP5(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP6_MASK   (0x3000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT   (12U)
#define	PUF_IDXBLK_DP_IDXBLK_DP6(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP7_MASK   (0xC000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT   (14U)
#define	PUF_IDXBLK_DP_IDXBLK_DP7(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP8_MASK   (0x30000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT   (16U)
#define	PUF_IDXBLK_DP_IDXBLK_DP8(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP9_MASK   (0xC0000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT   (18U)
#define	PUF_IDXBLK_DP_IDXBLK_DP9(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP10_MASK   (0x300000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT   (20U)
#define	PUF_IDXBLK_DP_IDXBLK_DP10(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP11_MASK   (0xC00000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT   (22U)
#define	PUF_IDXBLK_DP_IDXBLK_DP11(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP12_MASK   (0x3000000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT   (24U)
#define	PUF_IDXBLK_DP_IDXBLK_DP12(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP13_MASK   (0xC000000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT   (26U)
#define	PUF_IDXBLK_DP_IDXBLK_DP13(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP14_MASK   (0x30000000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT   (28U)
#define	PUF_IDXBLK_DP_IDXBLK_DP14(x)
#define	PUF_IDXBLK_DP_IDXBLK_DP15_MASK   (0xC0000000U)
#define	PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT   (30U)
#define	PUF_IDXBLK_DP_IDXBLK_DP15(x)
KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable
#define	PUF_KEYMASK_KEYMASK_MASK   (0xFFFFFFFFU)
#define	PUF_KEYMASK_KEYMASK_SHIFT   (0U)
#define	PUF_KEYMASK_KEYMASK(x)
IDXBLK_STATUS - PUF Index Block Setting Status Register
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK   (0x3U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT   (0U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK   (0xCU)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT   (2U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK   (0x30U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT   (4U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK   (0xC0U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT   (6U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK   (0x300U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT   (8U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK   (0xC00U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT   (10U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK   (0x3000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT   (12U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK   (0xC000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT   (14U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK   (0x30000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT   (16U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK   (0xC0000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT   (18U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK   (0x300000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT   (20U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK   (0xC00000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT   (22U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK   (0x3000000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT   (24U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK   (0xC000000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT   (26U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK   (0x30000000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT   (28U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK   (0xC0000000U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT   (30U)
#define	PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x)
IDXBLK_SHIFT - PUF Key Manager Shift Status
#define	PUF_IDXBLK_SHIFT_IND_KEY0_MASK   (0xFU)
#define	PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT   (0U)
#define	PUF_IDXBLK_SHIFT_IND_KEY0(x)
#define	PUF_IDXBLK_SHIFT_IND_KEY1_MASK   (0xF0U)
#define	PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT   (4U)
#define	PUF_IDXBLK_SHIFT_IND_KEY1(x)
CNT - Counter Register
#define	PWM_CNT_CNT_MASK   (0xFFFFU)
#define	PWM_CNT_CNT_SHIFT   (0U)
#define	PWM_CNT_CNT(x)
INIT - Initial Count Register
#define	PWM_INIT_INIT_MASK   (0xFFFFU)
#define	PWM_INIT_INIT_SHIFT   (0U)
#define	PWM_INIT_INIT(x)
VAL0 - Value Register 0
#define	PWM_VAL0_VAL0_MASK   (0xFFFFU)
#define	PWM_VAL0_VAL0_SHIFT   (0U)
#define	PWM_VAL0_VAL0(x)
FRACVAL1 - Fractional Value Register 1
#define	PWM_FRACVAL1_FRACVAL1_MASK   (0xF800U)
#define	PWM_FRACVAL1_FRACVAL1_SHIFT   (11U)
#define	PWM_FRACVAL1_FRACVAL1(x)
VAL1 - Value Register 1
#define	PWM_VAL1_VAL1_MASK   (0xFFFFU)
#define	PWM_VAL1_VAL1_SHIFT   (0U)
#define	PWM_VAL1_VAL1(x)
FRACVAL2 - Fractional Value Register 2
#define	PWM_FRACVAL2_FRACVAL2_MASK   (0xF800U)
#define	PWM_FRACVAL2_FRACVAL2_SHIFT   (11U)
#define	PWM_FRACVAL2_FRACVAL2(x)
VAL2 - Value Register 2
#define	PWM_VAL2_VAL2_MASK   (0xFFFFU)
#define	PWM_VAL2_VAL2_SHIFT   (0U)
#define	PWM_VAL2_VAL2(x)
FRACVAL3 - Fractional Value Register 3
#define	PWM_FRACVAL3_FRACVAL3_MASK   (0xF800U)
#define	PWM_FRACVAL3_FRACVAL3_SHIFT   (11U)
#define	PWM_FRACVAL3_FRACVAL3(x)
VAL3 - Value Register 3
#define	PWM_VAL3_VAL3_MASK   (0xFFFFU)
#define	PWM_VAL3_VAL3_SHIFT   (0U)
#define	PWM_VAL3_VAL3(x)
FRACVAL4 - Fractional Value Register 4
#define	PWM_FRACVAL4_FRACVAL4_MASK   (0xF800U)
#define	PWM_FRACVAL4_FRACVAL4_SHIFT   (11U)
#define	PWM_FRACVAL4_FRACVAL4(x)
VAL4 - Value Register 4
#define	PWM_VAL4_VAL4_MASK   (0xFFFFU)
#define	PWM_VAL4_VAL4_SHIFT   (0U)
#define	PWM_VAL4_VAL4(x)
FRACVAL5 - Fractional Value Register 5
#define	PWM_FRACVAL5_FRACVAL5_MASK   (0xF800U)
#define	PWM_FRACVAL5_FRACVAL5_SHIFT   (11U)
#define	PWM_FRACVAL5_FRACVAL5(x)
VAL5 - Value Register 5
#define	PWM_VAL5_VAL5_MASK   (0xFFFFU)
#define	PWM_VAL5_VAL5_SHIFT   (0U)
#define	PWM_VAL5_VAL5(x)
FRCTRL - Fractional Control Register
#define	PWM_FRCTRL_FRAC1_EN_MASK   (0x2U)
#define	PWM_FRCTRL_FRAC1_EN_SHIFT   (1U)
#define	PWM_FRCTRL_FRAC1_EN(x)
#define	PWM_FRCTRL_FRAC23_EN_MASK   (0x4U)
#define	PWM_FRCTRL_FRAC23_EN_SHIFT   (2U)
#define	PWM_FRCTRL_FRAC23_EN(x)
#define	PWM_FRCTRL_FRAC45_EN_MASK   (0x10U)
#define	PWM_FRCTRL_FRAC45_EN_SHIFT   (4U)
#define	PWM_FRCTRL_FRAC45_EN(x)
#define	PWM_FRCTRL_TEST_MASK   (0x8000U)
#define	PWM_FRCTRL_TEST_SHIFT   (15U)
#define	PWM_FRCTRL_TEST(x)
OCTRL - Output Control Register
#define	PWM_OCTRL_PWMXFS_MASK   (0x3U)
#define	PWM_OCTRL_PWMXFS_SHIFT   (0U)
#define	PWM_OCTRL_PWMXFS(x)
#define	PWM_OCTRL_PWMBFS_MASK   (0xCU)
#define	PWM_OCTRL_PWMBFS_SHIFT   (2U)
#define	PWM_OCTRL_PWMBFS(x)
#define	PWM_OCTRL_PWMAFS_MASK   (0x30U)
#define	PWM_OCTRL_PWMAFS_SHIFT   (4U)
#define	PWM_OCTRL_PWMAFS(x)
#define	PWM_OCTRL_POLX_MASK   (0x100U)
#define	PWM_OCTRL_POLX_SHIFT   (8U)
#define	PWM_OCTRL_POLX(x)
#define	PWM_OCTRL_POLB_MASK   (0x200U)
#define	PWM_OCTRL_POLB_SHIFT   (9U)
#define	PWM_OCTRL_POLB(x)
#define	PWM_OCTRL_POLA_MASK   (0x400U)
#define	PWM_OCTRL_POLA_SHIFT   (10U)
#define	PWM_OCTRL_POLA(x)
#define	PWM_OCTRL_PWMX_IN_MASK   (0x2000U)
#define	PWM_OCTRL_PWMX_IN_SHIFT   (13U)
#define	PWM_OCTRL_PWMX_IN(x)
#define	PWM_OCTRL_PWMB_IN_MASK   (0x4000U)
#define	PWM_OCTRL_PWMB_IN_SHIFT   (14U)
#define	PWM_OCTRL_PWMB_IN(x)
#define	PWM_OCTRL_PWMA_IN_MASK   (0x8000U)
#define	PWM_OCTRL_PWMA_IN_SHIFT   (15U)
#define	PWM_OCTRL_PWMA_IN(x)
STS - Status Register
#define	PWM_STS_CMPF_MASK   (0x3FU)
#define	PWM_STS_CMPF_SHIFT   (0U)
#define	PWM_STS_CMPF(x)
#define	PWM_STS_CFX0_MASK   (0x40U)
#define	PWM_STS_CFX0_SHIFT   (6U)
#define	PWM_STS_CFX0(x)
#define	PWM_STS_CFX1_MASK   (0x80U)
#define	PWM_STS_CFX1_SHIFT   (7U)
#define	PWM_STS_CFX1(x)
#define	PWM_STS_CFB0_MASK   (0x100U)
#define	PWM_STS_CFB0_SHIFT   (8U)
#define	PWM_STS_CFB0(x)
#define	PWM_STS_CFB1_MASK   (0x200U)
#define	PWM_STS_CFB1_SHIFT   (9U)
#define	PWM_STS_CFB1(x)
#define	PWM_STS_CFA0_MASK   (0x400U)
#define	PWM_STS_CFA0_SHIFT   (10U)
#define	PWM_STS_CFA0(x)
#define	PWM_STS_CFA1_MASK   (0x800U)
#define	PWM_STS_CFA1_SHIFT   (11U)
#define	PWM_STS_CFA1(x)
#define	PWM_STS_RF_MASK   (0x1000U)
#define	PWM_STS_RF_SHIFT   (12U)
#define	PWM_STS_RF(x)
#define	PWM_STS_REF_MASK   (0x2000U)
#define	PWM_STS_REF_SHIFT   (13U)
#define	PWM_STS_REF(x)
#define	PWM_STS_RUF_MASK   (0x4000U)
#define	PWM_STS_RUF_SHIFT   (14U)
#define	PWM_STS_RUF(x)
DMAEN - DMA Enable Register
#define	PWM_DMAEN_CX0DE_MASK   (0x1U)
#define	PWM_DMAEN_CX0DE_SHIFT   (0U)
#define	PWM_DMAEN_CX0DE(x)
#define	PWM_DMAEN_CX1DE_MASK   (0x2U)
#define	PWM_DMAEN_CX1DE_SHIFT   (1U)
#define	PWM_DMAEN_CX1DE(x)
#define	PWM_DMAEN_CB0DE_MASK   (0x4U)
#define	PWM_DMAEN_CB0DE_SHIFT   (2U)
#define	PWM_DMAEN_CB0DE(x)
#define	PWM_DMAEN_CB1DE_MASK   (0x8U)
#define	PWM_DMAEN_CB1DE_SHIFT   (3U)
#define	PWM_DMAEN_CB1DE(x)
#define	PWM_DMAEN_CA0DE_MASK   (0x10U)
#define	PWM_DMAEN_CA0DE_SHIFT   (4U)
#define	PWM_DMAEN_CA0DE(x)
#define	PWM_DMAEN_CA1DE_MASK   (0x20U)
#define	PWM_DMAEN_CA1DE_SHIFT   (5U)
#define	PWM_DMAEN_CA1DE(x)
#define	PWM_DMAEN_CAPTDE_MASK   (0xC0U)
#define	PWM_DMAEN_CAPTDE_SHIFT   (6U)
#define	PWM_DMAEN_CAPTDE(x)
#define	PWM_DMAEN_FAND_MASK   (0x100U)
#define	PWM_DMAEN_FAND_SHIFT   (8U)
#define	PWM_DMAEN_FAND(x)
#define	PWM_DMAEN_VALDE_MASK   (0x200U)
#define	PWM_DMAEN_VALDE_SHIFT   (9U)
#define	PWM_DMAEN_VALDE(x)
TCTRL - Output Trigger Control Register
#define	PWM_TCTRL_OUT_TRIG_EN_MASK   (0x3FU)
#define	PWM_TCTRL_OUT_TRIG_EN_SHIFT   (0U)
#define	PWM_TCTRL_OUT_TRIG_EN(x)
#define	PWM_TCTRL_TRGFRQ_MASK   (0x1000U)
#define	PWM_TCTRL_TRGFRQ_SHIFT   (12U)
#define	PWM_TCTRL_TRGFRQ(x)
#define	PWM_TCTRL_PWBOT1_MASK   (0x4000U)
#define	PWM_TCTRL_PWBOT1_SHIFT   (14U)
#define	PWM_TCTRL_PWBOT1(x)
#define	PWM_TCTRL_PWAOT0_MASK   (0x8000U)
#define	PWM_TCTRL_PWAOT0_SHIFT   (15U)
#define	PWM_TCTRL_PWAOT0(x)
DISMAP - Fault Disable Mapping Register 0
#define	PWM_DISMAP_DIS0A_MASK   (0xFU)
#define	PWM_DISMAP_DIS0A_SHIFT   (0U)
#define	PWM_DISMAP_DIS0A(x)
#define	PWM_DISMAP_DIS0B_MASK   (0xF0U)
#define	PWM_DISMAP_DIS0B_SHIFT   (4U)
#define	PWM_DISMAP_DIS0B(x)
#define	PWM_DISMAP_DIS0X_MASK   (0xF00U)
#define	PWM_DISMAP_DIS0X_SHIFT   (8U)
#define	PWM_DISMAP_DIS0X(x)
DTCNT0 - Deadtime Count Register 0
#define	PWM_DTCNT0_DTCNT0_MASK   (0xFFFFU)
#define	PWM_DTCNT0_DTCNT0_SHIFT   (0U)
#define	PWM_DTCNT0_DTCNT0(x)
DTCNT1 - Deadtime Count Register 1
#define	PWM_DTCNT1_DTCNT1_MASK   (0xFFFFU)
#define	PWM_DTCNT1_DTCNT1_SHIFT   (0U)
#define	PWM_DTCNT1_DTCNT1(x)
CAPTCTRLA - Capture Control A Register
#define	PWM_CAPTCTRLA_ARMA_MASK   (0x1U)
#define	PWM_CAPTCTRLA_ARMA_SHIFT   (0U)
#define	PWM_CAPTCTRLA_ARMA(x)
#define	PWM_CAPTCTRLA_ONESHOTA_MASK   (0x2U)
#define	PWM_CAPTCTRLA_ONESHOTA_SHIFT   (1U)
#define	PWM_CAPTCTRLA_ONESHOTA(x)
#define	PWM_CAPTCTRLA_EDGA0_MASK   (0xCU)
#define	PWM_CAPTCTRLA_EDGA0_SHIFT   (2U)
#define	PWM_CAPTCTRLA_EDGA0(x)
#define	PWM_CAPTCTRLA_EDGA1_MASK   (0x30U)
#define	PWM_CAPTCTRLA_EDGA1_SHIFT   (4U)
#define	PWM_CAPTCTRLA_EDGA1(x)
#define	PWM_CAPTCTRLA_INP_SELA_MASK   (0x40U)
#define	PWM_CAPTCTRLA_INP_SELA_SHIFT   (6U)
#define	PWM_CAPTCTRLA_INP_SELA(x)
#define	PWM_CAPTCTRLA_EDGCNTA_EN_MASK   (0x80U)
#define	PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT   (7U)
#define	PWM_CAPTCTRLA_EDGCNTA_EN(x)
#define	PWM_CAPTCTRLA_CFAWM_MASK   (0x300U)
#define	PWM_CAPTCTRLA_CFAWM_SHIFT   (8U)
#define	PWM_CAPTCTRLA_CFAWM(x)
#define	PWM_CAPTCTRLA_CA0CNT_MASK   (0x1C00U)
#define	PWM_CAPTCTRLA_CA0CNT_SHIFT   (10U)
#define	PWM_CAPTCTRLA_CA0CNT(x)
#define	PWM_CAPTCTRLA_CA1CNT_MASK   (0xE000U)
#define	PWM_CAPTCTRLA_CA1CNT_SHIFT   (13U)
#define	PWM_CAPTCTRLA_CA1CNT(x)
CAPTCOMPA - Capture Compare A Register
#define	PWM_CAPTCOMPA_EDGCMPA_MASK   (0xFFU)
#define	PWM_CAPTCOMPA_EDGCMPA_SHIFT   (0U)
#define	PWM_CAPTCOMPA_EDGCMPA(x)
#define	PWM_CAPTCOMPA_EDGCNTA_MASK   (0xFF00U)
#define	PWM_CAPTCOMPA_EDGCNTA_SHIFT   (8U)
#define	PWM_CAPTCOMPA_EDGCNTA(x)
CAPTCTRLB - Capture Control B Register
#define	PWM_CAPTCTRLB_ARMB_MASK   (0x1U)
#define	PWM_CAPTCTRLB_ARMB_SHIFT   (0U)
#define	PWM_CAPTCTRLB_ARMB(x)
#define	PWM_CAPTCTRLB_ONESHOTB_MASK   (0x2U)
#define	PWM_CAPTCTRLB_ONESHOTB_SHIFT   (1U)
#define	PWM_CAPTCTRLB_ONESHOTB(x)
#define	PWM_CAPTCTRLB_EDGB0_MASK   (0xCU)
#define	PWM_CAPTCTRLB_EDGB0_SHIFT   (2U)
#define	PWM_CAPTCTRLB_EDGB0(x)
#define	PWM_CAPTCTRLB_EDGB1_MASK   (0x30U)
#define	PWM_CAPTCTRLB_EDGB1_SHIFT   (4U)
#define	PWM_CAPTCTRLB_EDGB1(x)
#define	PWM_CAPTCTRLB_INP_SELB_MASK   (0x40U)
#define	PWM_CAPTCTRLB_INP_SELB_SHIFT   (6U)
#define	PWM_CAPTCTRLB_INP_SELB(x)
#define	PWM_CAPTCTRLB_EDGCNTB_EN_MASK   (0x80U)
#define	PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT   (7U)
#define	PWM_CAPTCTRLB_EDGCNTB_EN(x)
#define	PWM_CAPTCTRLB_CFBWM_MASK   (0x300U)
#define	PWM_CAPTCTRLB_CFBWM_SHIFT   (8U)
#define	PWM_CAPTCTRLB_CFBWM(x)
#define	PWM_CAPTCTRLB_CB0CNT_MASK   (0x1C00U)
#define	PWM_CAPTCTRLB_CB0CNT_SHIFT   (10U)
#define	PWM_CAPTCTRLB_CB0CNT(x)
#define	PWM_CAPTCTRLB_CB1CNT_MASK   (0xE000U)
#define	PWM_CAPTCTRLB_CB1CNT_SHIFT   (13U)
#define	PWM_CAPTCTRLB_CB1CNT(x)
CAPTCOMPB - Capture Compare B Register
#define	PWM_CAPTCOMPB_EDGCMPB_MASK   (0xFFU)
#define	PWM_CAPTCOMPB_EDGCMPB_SHIFT   (0U)
#define	PWM_CAPTCOMPB_EDGCMPB(x)
#define	PWM_CAPTCOMPB_EDGCNTB_MASK   (0xFF00U)
#define	PWM_CAPTCOMPB_EDGCNTB_SHIFT   (8U)
#define	PWM_CAPTCOMPB_EDGCNTB(x)
CAPTCTRLX - Capture Control X Register
#define	PWM_CAPTCTRLX_ARMX_MASK   (0x1U)
#define	PWM_CAPTCTRLX_ARMX_SHIFT   (0U)
#define	PWM_CAPTCTRLX_ARMX(x)
#define	PWM_CAPTCTRLX_ONESHOTX_MASK   (0x2U)
#define	PWM_CAPTCTRLX_ONESHOTX_SHIFT   (1U)
#define	PWM_CAPTCTRLX_ONESHOTX(x)
#define	PWM_CAPTCTRLX_EDGX0_MASK   (0xCU)
#define	PWM_CAPTCTRLX_EDGX0_SHIFT   (2U)
#define	PWM_CAPTCTRLX_EDGX0(x)
#define	PWM_CAPTCTRLX_EDGX1_MASK   (0x30U)
#define	PWM_CAPTCTRLX_EDGX1_SHIFT   (4U)
#define	PWM_CAPTCTRLX_EDGX1(x)
#define	PWM_CAPTCTRLX_INP_SELX_MASK   (0x40U)
#define	PWM_CAPTCTRLX_INP_SELX_SHIFT   (6U)
#define	PWM_CAPTCTRLX_INP_SELX(x)
#define	PWM_CAPTCTRLX_EDGCNTX_EN_MASK   (0x80U)
#define	PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT   (7U)
#define	PWM_CAPTCTRLX_EDGCNTX_EN(x)
#define	PWM_CAPTCTRLX_CFXWM_MASK   (0x300U)
#define	PWM_CAPTCTRLX_CFXWM_SHIFT   (8U)
#define	PWM_CAPTCTRLX_CFXWM(x)
#define	PWM_CAPTCTRLX_CX0CNT_MASK   (0x1C00U)
#define	PWM_CAPTCTRLX_CX0CNT_SHIFT   (10U)
#define	PWM_CAPTCTRLX_CX0CNT(x)
#define	PWM_CAPTCTRLX_CX1CNT_MASK   (0xE000U)
#define	PWM_CAPTCTRLX_CX1CNT_SHIFT   (13U)
#define	PWM_CAPTCTRLX_CX1CNT(x)
CAPTCOMPX - Capture Compare X Register
#define	PWM_CAPTCOMPX_EDGCMPX_MASK   (0xFFU)
#define	PWM_CAPTCOMPX_EDGCMPX_SHIFT   (0U)
#define	PWM_CAPTCOMPX_EDGCMPX(x)
#define	PWM_CAPTCOMPX_EDGCNTX_MASK   (0xFF00U)
#define	PWM_CAPTCOMPX_EDGCNTX_SHIFT   (8U)
#define	PWM_CAPTCOMPX_EDGCNTX(x)
CVAL0 - Capture Value 0 Register
#define	PWM_CVAL0_CAPTVAL0_MASK   (0xFFFFU)
#define	PWM_CVAL0_CAPTVAL0_SHIFT   (0U)
#define	PWM_CVAL0_CAPTVAL0(x)
CVAL0CYC - Capture Value 0 Cycle Register
#define	PWM_CVAL0CYC_CVAL0CYC_MASK   (0xFU)
#define	PWM_CVAL0CYC_CVAL0CYC_SHIFT   (0U)
#define	PWM_CVAL0CYC_CVAL0CYC(x)
CVAL1 - Capture Value 1 Register
#define	PWM_CVAL1_CAPTVAL1_MASK   (0xFFFFU)
#define	PWM_CVAL1_CAPTVAL1_SHIFT   (0U)
#define	PWM_CVAL1_CAPTVAL1(x)
CVAL1CYC - Capture Value 1 Cycle Register
#define	PWM_CVAL1CYC_CVAL1CYC_MASK   (0xFU)
#define	PWM_CVAL1CYC_CVAL1CYC_SHIFT   (0U)
#define	PWM_CVAL1CYC_CVAL1CYC(x)
CVAL2 - Capture Value 2 Register
#define	PWM_CVAL2_CAPTVAL2_MASK   (0xFFFFU)
#define	PWM_CVAL2_CAPTVAL2_SHIFT   (0U)
#define	PWM_CVAL2_CAPTVAL2(x)
CVAL2CYC - Capture Value 2 Cycle Register
#define	PWM_CVAL2CYC_CVAL2CYC_MASK   (0xFU)
#define	PWM_CVAL2CYC_CVAL2CYC_SHIFT   (0U)
#define	PWM_CVAL2CYC_CVAL2CYC(x)
CVAL3 - Capture Value 3 Register
#define	PWM_CVAL3_CAPTVAL3_MASK   (0xFFFFU)
#define	PWM_CVAL3_CAPTVAL3_SHIFT   (0U)
#define	PWM_CVAL3_CAPTVAL3(x)
CVAL3CYC - Capture Value 3 Cycle Register
#define	PWM_CVAL3CYC_CVAL3CYC_MASK   (0xFU)
#define	PWM_CVAL3CYC_CVAL3CYC_SHIFT   (0U)
#define	PWM_CVAL3CYC_CVAL3CYC(x)
CVAL4 - Capture Value 4 Register
#define	PWM_CVAL4_CAPTVAL4_MASK   (0xFFFFU)
#define	PWM_CVAL4_CAPTVAL4_SHIFT   (0U)
#define	PWM_CVAL4_CAPTVAL4(x)
CVAL4CYC - Capture Value 4 Cycle Register
#define	PWM_CVAL4CYC_CVAL4CYC_MASK   (0xFU)
#define	PWM_CVAL4CYC_CVAL4CYC_SHIFT   (0U)
#define	PWM_CVAL4CYC_CVAL4CYC(x)
CVAL5 - Capture Value 5 Register
#define	PWM_CVAL5_CAPTVAL5_MASK   (0xFFFFU)
#define	PWM_CVAL5_CAPTVAL5_SHIFT   (0U)
#define	PWM_CVAL5_CAPTVAL5(x)
CVAL5CYC - Capture Value 5 Cycle Register
#define	PWM_CVAL5CYC_CVAL5CYC_MASK   (0xFU)
#define	PWM_CVAL5CYC_CVAL5CYC_SHIFT   (0U)
#define	PWM_CVAL5CYC_CVAL5CYC(x)
OUTEN - Output Enable Register
#define	PWM_OUTEN_PWMX_EN_MASK   (0xFU)
#define	PWM_OUTEN_PWMX_EN_SHIFT   (0U)
#define	PWM_OUTEN_PWMX_EN(x)
#define	PWM_OUTEN_PWMB_EN_MASK   (0xF0U)
#define	PWM_OUTEN_PWMB_EN_SHIFT   (4U)
#define	PWM_OUTEN_PWMB_EN(x)
#define	PWM_OUTEN_PWMA_EN_MASK   (0xF00U)
#define	PWM_OUTEN_PWMA_EN_SHIFT   (8U)
#define	PWM_OUTEN_PWMA_EN(x)
MASK - Mask Register
#define	PWM_MASK_MASKX_MASK   (0xFU)
#define	PWM_MASK_MASKX_SHIFT   (0U)
#define	PWM_MASK_MASKX(x)
#define	PWM_MASK_MASKB_MASK   (0xF0U)
#define	PWM_MASK_MASKB_SHIFT   (4U)
#define	PWM_MASK_MASKB(x)
#define	PWM_MASK_MASKA_MASK   (0xF00U)
#define	PWM_MASK_MASKA_SHIFT   (8U)
#define	PWM_MASK_MASKA(x)
SWCOUT - Software Controlled Output Register
#define	PWM_SWCOUT_SM0OUT45_MASK   (0x1U)
#define	PWM_SWCOUT_SM0OUT45_SHIFT   (0U)
#define	PWM_SWCOUT_SM0OUT45(x)
#define	PWM_SWCOUT_SM0OUT23_MASK   (0x2U)
#define	PWM_SWCOUT_SM0OUT23_SHIFT   (1U)
#define	PWM_SWCOUT_SM0OUT23(x)
#define	PWM_SWCOUT_SM1OUT45_MASK   (0x4U)
#define	PWM_SWCOUT_SM1OUT45_SHIFT   (2U)
#define	PWM_SWCOUT_SM1OUT45(x)
#define	PWM_SWCOUT_SM1OUT23_MASK   (0x8U)
#define	PWM_SWCOUT_SM1OUT23_SHIFT   (3U)
#define	PWM_SWCOUT_SM1OUT23(x)
#define	PWM_SWCOUT_SM2OUT45_MASK   (0x10U)
#define	PWM_SWCOUT_SM2OUT45_SHIFT   (4U)
#define	PWM_SWCOUT_SM2OUT45(x)
#define	PWM_SWCOUT_SM2OUT23_MASK   (0x20U)
#define	PWM_SWCOUT_SM2OUT23_SHIFT   (5U)
#define	PWM_SWCOUT_SM2OUT23(x)
#define	PWM_SWCOUT_SM3OUT45_MASK   (0x40U)
#define	PWM_SWCOUT_SM3OUT45_SHIFT   (6U)
#define	PWM_SWCOUT_SM3OUT45(x)
#define	PWM_SWCOUT_SM3OUT23_MASK   (0x80U)
#define	PWM_SWCOUT_SM3OUT23_SHIFT   (7U)
#define	PWM_SWCOUT_SM3OUT23(x)
DTSRCSEL - PWM Source Select Register
#define	PWM_DTSRCSEL_SM0SEL45_MASK   (0x3U)
#define	PWM_DTSRCSEL_SM0SEL45_SHIFT   (0U)
#define	PWM_DTSRCSEL_SM0SEL45(x)
#define	PWM_DTSRCSEL_SM0SEL23_MASK   (0xCU)
#define	PWM_DTSRCSEL_SM0SEL23_SHIFT   (2U)
#define	PWM_DTSRCSEL_SM0SEL23(x)
#define	PWM_DTSRCSEL_SM1SEL45_MASK   (0x30U)
#define	PWM_DTSRCSEL_SM1SEL45_SHIFT   (4U)
#define	PWM_DTSRCSEL_SM1SEL45(x)
#define	PWM_DTSRCSEL_SM1SEL23_MASK   (0xC0U)
#define	PWM_DTSRCSEL_SM1SEL23_SHIFT   (6U)
#define	PWM_DTSRCSEL_SM1SEL23(x)
#define	PWM_DTSRCSEL_SM2SEL45_MASK   (0x300U)
#define	PWM_DTSRCSEL_SM2SEL45_SHIFT   (8U)
#define	PWM_DTSRCSEL_SM2SEL45(x)
#define	PWM_DTSRCSEL_SM2SEL23_MASK   (0xC00U)
#define	PWM_DTSRCSEL_SM2SEL23_SHIFT   (10U)
#define	PWM_DTSRCSEL_SM2SEL23(x)
#define	PWM_DTSRCSEL_SM3SEL45_MASK   (0x3000U)
#define	PWM_DTSRCSEL_SM3SEL45_SHIFT   (12U)
#define	PWM_DTSRCSEL_SM3SEL45(x)
#define	PWM_DTSRCSEL_SM3SEL23_MASK   (0xC000U)
#define	PWM_DTSRCSEL_SM3SEL23_SHIFT   (14U)
#define	PWM_DTSRCSEL_SM3SEL23(x)
MCTRL - Master Control Register
#define	PWM_MCTRL_LDOK_MASK   (0xFU)
#define	PWM_MCTRL_LDOK_SHIFT   (0U)
#define	PWM_MCTRL_LDOK(x)
#define	PWM_MCTRL_CLDOK_MASK   (0xF0U)
#define	PWM_MCTRL_CLDOK_SHIFT   (4U)
#define	PWM_MCTRL_CLDOK(x)
#define	PWM_MCTRL_RUN_MASK   (0xF00U)
#define	PWM_MCTRL_RUN_SHIFT   (8U)
#define	PWM_MCTRL_RUN(x)
#define	PWM_MCTRL_IPOL_MASK   (0xF000U)
#define	PWM_MCTRL_IPOL_SHIFT   (12U)
#define	PWM_MCTRL_IPOL(x)
MCTRL2 - Master Control 2 Register
#define	PWM_MCTRL2_MONPLL_MASK   (0x3U)
#define	PWM_MCTRL2_MONPLL_SHIFT   (0U)
#define	PWM_MCTRL2_MONPLL(x)
FCTRL - Fault Control Register
#define	PWM_FCTRL_FIE_MASK   (0xFU)
#define	PWM_FCTRL_FIE_SHIFT   (0U)
#define	PWM_FCTRL_FIE(x)
#define	PWM_FCTRL_FSAFE_MASK   (0xF0U)
#define	PWM_FCTRL_FSAFE_SHIFT   (4U)
#define	PWM_FCTRL_FSAFE(x)
#define	PWM_FCTRL_FAUTO_MASK   (0xF00U)
#define	PWM_FCTRL_FAUTO_SHIFT   (8U)
#define	PWM_FCTRL_FAUTO(x)
#define	PWM_FCTRL_FLVL_MASK   (0xF000U)
#define	PWM_FCTRL_FLVL_SHIFT   (12U)
#define	PWM_FCTRL_FLVL(x)
FSTS - Fault Status Register
#define	PWM_FSTS_FFLAG_MASK   (0xFU)
#define	PWM_FSTS_FFLAG_SHIFT   (0U)
#define	PWM_FSTS_FFLAG(x)
#define	PWM_FSTS_FFULL_MASK   (0xF0U)
#define	PWM_FSTS_FFULL_SHIFT   (4U)
#define	PWM_FSTS_FFULL(x)
#define	PWM_FSTS_FFPIN_MASK   (0xF00U)
#define	PWM_FSTS_FFPIN_SHIFT   (8U)
#define	PWM_FSTS_FFPIN(x)
#define	PWM_FSTS_FHALF_MASK   (0xF000U)
#define	PWM_FSTS_FHALF_SHIFT   (12U)
#define	PWM_FSTS_FHALF(x)
FFILT - Fault Filter Register
#define	PWM_FFILT_FILT_PER_MASK   (0xFFU)
#define	PWM_FFILT_FILT_PER_SHIFT   (0U)
#define	PWM_FFILT_FILT_PER(x)
#define	PWM_FFILT_FILT_CNT_MASK   (0x700U)
#define	PWM_FFILT_FILT_CNT_SHIFT   (8U)
#define	PWM_FFILT_FILT_CNT(x)
#define	PWM_FFILT_GSTR_MASK   (0x8000U)
#define	PWM_FFILT_GSTR_SHIFT   (15U)
#define	PWM_FFILT_GSTR(x)
FTST - Fault Test Register
#define	PWM_FTST_FTEST_MASK   (0x1U)
#define	PWM_FTST_FTEST_SHIFT   (0U)
#define	PWM_FTST_FTEST(x)
FCTRL2 - Fault Control 2 Register
#define	PWM_FCTRL2_NOCOMB_MASK   (0xFU)
#define	PWM_FCTRL2_NOCOMB_SHIFT   (0U)
#define	PWM_FCTRL2_NOCOMB(x)
CTRL - Control Register 0
#define	PXP_CTRL_ENABLE_MASK   (0x1U)
#define	PXP_CTRL_ENABLE_SHIFT   (0U)
#define	PXP_CTRL_ENABLE(x)
#define	PXP_CTRL_IRQ_ENABLE_MASK   (0x2U)
#define	PXP_CTRL_IRQ_ENABLE_SHIFT   (1U)
#define	PXP_CTRL_IRQ_ENABLE(x)
#define	PXP_CTRL_NEXT_IRQ_ENABLE_MASK   (0x4U)
#define	PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT   (2U)
#define	PXP_CTRL_NEXT_IRQ_ENABLE(x)
#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT   (4U)
#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE(x)
#define	PXP_CTRL_ROTATE_MASK   (0x300U)
#define	PXP_CTRL_ROTATE_SHIFT   (8U)
#define	PXP_CTRL_ROTATE(x)
#define	PXP_CTRL_HFLIP_MASK   (0x400U)
#define	PXP_CTRL_HFLIP_SHIFT   (10U)
#define	PXP_CTRL_HFLIP(x)
#define	PXP_CTRL_VFLIP_MASK   (0x800U)
#define	PXP_CTRL_VFLIP_SHIFT   (11U)
#define	PXP_CTRL_VFLIP(x)
#define	PXP_CTRL_ROT_POS_MASK   (0x400000U)
#define	PXP_CTRL_ROT_POS_SHIFT   (22U)
#define	PXP_CTRL_ROT_POS(x)
#define	PXP_CTRL_BLOCK_SIZE_MASK   (0x800000U)
#define	PXP_CTRL_BLOCK_SIZE_SHIFT   (23U)
#define	PXP_CTRL_BLOCK_SIZE(x)
#define	PXP_CTRL_EN_REPEAT_MASK   (0x10000000U)
#define	PXP_CTRL_EN_REPEAT_SHIFT   (28U)
#define	PXP_CTRL_EN_REPEAT(x)
#define	PXP_CTRL_CLKGATE_MASK   (0x40000000U)
#define	PXP_CTRL_CLKGATE_SHIFT   (30U)
#define	PXP_CTRL_CLKGATE(x)
#define	PXP_CTRL_SFTRST_MASK   (0x80000000U)
#define	PXP_CTRL_SFTRST_SHIFT   (31U)
#define	PXP_CTRL_SFTRST(x)
CTRL_SET - Control Register 0
#define	PXP_CTRL_SET_ENABLE_MASK   (0x1U)
#define	PXP_CTRL_SET_ENABLE_SHIFT   (0U)
#define	PXP_CTRL_SET_ENABLE(x)
#define	PXP_CTRL_SET_IRQ_ENABLE_MASK   (0x2U)
#define	PXP_CTRL_SET_IRQ_ENABLE_SHIFT   (1U)
#define	PXP_CTRL_SET_IRQ_ENABLE(x)
#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK   (0x4U)
#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT   (2U)
#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE(x)
#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT   (4U)
#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x)
#define	PXP_CTRL_SET_ROTATE_MASK   (0x300U)
#define	PXP_CTRL_SET_ROTATE_SHIFT   (8U)
#define	PXP_CTRL_SET_ROTATE(x)
#define	PXP_CTRL_SET_HFLIP_MASK   (0x400U)
#define	PXP_CTRL_SET_HFLIP_SHIFT   (10U)
#define	PXP_CTRL_SET_HFLIP(x)
#define	PXP_CTRL_SET_VFLIP_MASK   (0x800U)
#define	PXP_CTRL_SET_VFLIP_SHIFT   (11U)
#define	PXP_CTRL_SET_VFLIP(x)
#define	PXP_CTRL_SET_ROT_POS_MASK   (0x400000U)
#define	PXP_CTRL_SET_ROT_POS_SHIFT   (22U)
#define	PXP_CTRL_SET_ROT_POS(x)
#define	PXP_CTRL_SET_BLOCK_SIZE_MASK   (0x800000U)
#define	PXP_CTRL_SET_BLOCK_SIZE_SHIFT   (23U)
#define	PXP_CTRL_SET_BLOCK_SIZE(x)
#define	PXP_CTRL_SET_EN_REPEAT_MASK   (0x10000000U)
#define	PXP_CTRL_SET_EN_REPEAT_SHIFT   (28U)
#define	PXP_CTRL_SET_EN_REPEAT(x)
#define	PXP_CTRL_SET_CLKGATE_MASK   (0x40000000U)
#define	PXP_CTRL_SET_CLKGATE_SHIFT   (30U)
#define	PXP_CTRL_SET_CLKGATE(x)
#define	PXP_CTRL_SET_SFTRST_MASK   (0x80000000U)
#define	PXP_CTRL_SET_SFTRST_SHIFT   (31U)
#define	PXP_CTRL_SET_SFTRST(x)
CTRL_CLR - Control Register 0
#define	PXP_CTRL_CLR_ENABLE_MASK   (0x1U)
#define	PXP_CTRL_CLR_ENABLE_SHIFT   (0U)
#define	PXP_CTRL_CLR_ENABLE(x)
#define	PXP_CTRL_CLR_IRQ_ENABLE_MASK   (0x2U)
#define	PXP_CTRL_CLR_IRQ_ENABLE_SHIFT   (1U)
#define	PXP_CTRL_CLR_IRQ_ENABLE(x)
#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK   (0x4U)
#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT   (2U)
#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x)
#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT   (4U)
#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x)
#define	PXP_CTRL_CLR_ROTATE_MASK   (0x300U)
#define	PXP_CTRL_CLR_ROTATE_SHIFT   (8U)
#define	PXP_CTRL_CLR_ROTATE(x)
#define	PXP_CTRL_CLR_HFLIP_MASK   (0x400U)
#define	PXP_CTRL_CLR_HFLIP_SHIFT   (10U)
#define	PXP_CTRL_CLR_HFLIP(x)
#define	PXP_CTRL_CLR_VFLIP_MASK   (0x800U)
#define	PXP_CTRL_CLR_VFLIP_SHIFT   (11U)
#define	PXP_CTRL_CLR_VFLIP(x)
#define	PXP_CTRL_CLR_ROT_POS_MASK   (0x400000U)
#define	PXP_CTRL_CLR_ROT_POS_SHIFT   (22U)
#define	PXP_CTRL_CLR_ROT_POS(x)
#define	PXP_CTRL_CLR_BLOCK_SIZE_MASK   (0x800000U)
#define	PXP_CTRL_CLR_BLOCK_SIZE_SHIFT   (23U)
#define	PXP_CTRL_CLR_BLOCK_SIZE(x)
#define	PXP_CTRL_CLR_EN_REPEAT_MASK   (0x10000000U)
#define	PXP_CTRL_CLR_EN_REPEAT_SHIFT   (28U)
#define	PXP_CTRL_CLR_EN_REPEAT(x)
#define	PXP_CTRL_CLR_CLKGATE_MASK   (0x40000000U)
#define	PXP_CTRL_CLR_CLKGATE_SHIFT   (30U)
#define	PXP_CTRL_CLR_CLKGATE(x)
#define	PXP_CTRL_CLR_SFTRST_MASK   (0x80000000U)
#define	PXP_CTRL_CLR_SFTRST_SHIFT   (31U)
#define	PXP_CTRL_CLR_SFTRST(x)
CTRL_TOG - Control Register 0
#define	PXP_CTRL_TOG_ENABLE_MASK   (0x1U)
#define	PXP_CTRL_TOG_ENABLE_SHIFT   (0U)
#define	PXP_CTRL_TOG_ENABLE(x)
#define	PXP_CTRL_TOG_IRQ_ENABLE_MASK   (0x2U)
#define	PXP_CTRL_TOG_IRQ_ENABLE_SHIFT   (1U)
#define	PXP_CTRL_TOG_IRQ_ENABLE(x)
#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK   (0x4U)
#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT   (2U)
#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x)
#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT   (4U)
#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x)
#define	PXP_CTRL_TOG_ROTATE_MASK   (0x300U)
#define	PXP_CTRL_TOG_ROTATE_SHIFT   (8U)
#define	PXP_CTRL_TOG_ROTATE(x)
#define	PXP_CTRL_TOG_HFLIP_MASK   (0x400U)
#define	PXP_CTRL_TOG_HFLIP_SHIFT   (10U)
#define	PXP_CTRL_TOG_HFLIP(x)
#define	PXP_CTRL_TOG_VFLIP_MASK   (0x800U)
#define	PXP_CTRL_TOG_VFLIP_SHIFT   (11U)
#define	PXP_CTRL_TOG_VFLIP(x)
#define	PXP_CTRL_TOG_ROT_POS_MASK   (0x400000U)
#define	PXP_CTRL_TOG_ROT_POS_SHIFT   (22U)
#define	PXP_CTRL_TOG_ROT_POS(x)
#define	PXP_CTRL_TOG_BLOCK_SIZE_MASK   (0x800000U)
#define	PXP_CTRL_TOG_BLOCK_SIZE_SHIFT   (23U)
#define	PXP_CTRL_TOG_BLOCK_SIZE(x)
#define	PXP_CTRL_TOG_EN_REPEAT_MASK   (0x10000000U)
#define	PXP_CTRL_TOG_EN_REPEAT_SHIFT   (28U)
#define	PXP_CTRL_TOG_EN_REPEAT(x)
#define	PXP_CTRL_TOG_CLKGATE_MASK   (0x40000000U)
#define	PXP_CTRL_TOG_CLKGATE_SHIFT   (30U)
#define	PXP_CTRL_TOG_CLKGATE(x)
#define	PXP_CTRL_TOG_SFTRST_MASK   (0x80000000U)
#define	PXP_CTRL_TOG_SFTRST_SHIFT   (31U)
#define	PXP_CTRL_TOG_SFTRST(x)
STAT - Status Register
#define	PXP_STAT_IRQ_MASK   (0x1U)
#define	PXP_STAT_IRQ_SHIFT   (0U)
#define	PXP_STAT_IRQ(x)
#define	PXP_STAT_AXI_WRITE_ERROR_MASK   (0x2U)
#define	PXP_STAT_AXI_WRITE_ERROR_SHIFT   (1U)
#define	PXP_STAT_AXI_WRITE_ERROR(x)
#define	PXP_STAT_AXI_READ_ERROR_MASK   (0x4U)
#define	PXP_STAT_AXI_READ_ERROR_SHIFT   (2U)
#define	PXP_STAT_AXI_READ_ERROR(x)
#define	PXP_STAT_NEXT_IRQ_MASK   (0x8U)
#define	PXP_STAT_NEXT_IRQ_SHIFT   (3U)
#define	PXP_STAT_NEXT_IRQ(x)
#define	PXP_STAT_AXI_ERROR_ID_MASK   (0xF0U)
#define	PXP_STAT_AXI_ERROR_ID_SHIFT   (4U)
#define	PXP_STAT_AXI_ERROR_ID(x)
#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK   (0x100U)
#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT   (8U)
#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x)
#define	PXP_STAT_BLOCKY_MASK   (0xFF0000U)
#define	PXP_STAT_BLOCKY_SHIFT   (16U)
#define	PXP_STAT_BLOCKY(x)
#define	PXP_STAT_BLOCKX_MASK   (0xFF000000U)
#define	PXP_STAT_BLOCKX_SHIFT   (24U)
#define	PXP_STAT_BLOCKX(x)
STAT_SET - Status Register
#define	PXP_STAT_SET_IRQ_MASK   (0x1U)
#define	PXP_STAT_SET_IRQ_SHIFT   (0U)
#define	PXP_STAT_SET_IRQ(x)
#define	PXP_STAT_SET_AXI_WRITE_ERROR_MASK   (0x2U)
#define	PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT   (1U)
#define	PXP_STAT_SET_AXI_WRITE_ERROR(x)
#define	PXP_STAT_SET_AXI_READ_ERROR_MASK   (0x4U)
#define	PXP_STAT_SET_AXI_READ_ERROR_SHIFT   (2U)
#define	PXP_STAT_SET_AXI_READ_ERROR(x)
#define	PXP_STAT_SET_NEXT_IRQ_MASK   (0x8U)
#define	PXP_STAT_SET_NEXT_IRQ_SHIFT   (3U)
#define	PXP_STAT_SET_NEXT_IRQ(x)
#define	PXP_STAT_SET_AXI_ERROR_ID_MASK   (0xF0U)
#define	PXP_STAT_SET_AXI_ERROR_ID_SHIFT   (4U)
#define	PXP_STAT_SET_AXI_ERROR_ID(x)
#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK   (0x100U)
#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT   (8U)
#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x)
#define	PXP_STAT_SET_BLOCKY_MASK   (0xFF0000U)
#define	PXP_STAT_SET_BLOCKY_SHIFT   (16U)
#define	PXP_STAT_SET_BLOCKY(x)
#define	PXP_STAT_SET_BLOCKX_MASK   (0xFF000000U)
#define	PXP_STAT_SET_BLOCKX_SHIFT   (24U)
#define	PXP_STAT_SET_BLOCKX(x)
STAT_CLR - Status Register
#define	PXP_STAT_CLR_IRQ_MASK   (0x1U)
#define	PXP_STAT_CLR_IRQ_SHIFT   (0U)
#define	PXP_STAT_CLR_IRQ(x)
#define	PXP_STAT_CLR_AXI_WRITE_ERROR_MASK   (0x2U)
#define	PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT   (1U)
#define	PXP_STAT_CLR_AXI_WRITE_ERROR(x)
#define	PXP_STAT_CLR_AXI_READ_ERROR_MASK   (0x4U)
#define	PXP_STAT_CLR_AXI_READ_ERROR_SHIFT   (2U)
#define	PXP_STAT_CLR_AXI_READ_ERROR(x)
#define	PXP_STAT_CLR_NEXT_IRQ_MASK   (0x8U)
#define	PXP_STAT_CLR_NEXT_IRQ_SHIFT   (3U)
#define	PXP_STAT_CLR_NEXT_IRQ(x)
#define	PXP_STAT_CLR_AXI_ERROR_ID_MASK   (0xF0U)
#define	PXP_STAT_CLR_AXI_ERROR_ID_SHIFT   (4U)
#define	PXP_STAT_CLR_AXI_ERROR_ID(x)
#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK   (0x100U)
#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT   (8U)
#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x)
#define	PXP_STAT_CLR_BLOCKY_MASK   (0xFF0000U)
#define	PXP_STAT_CLR_BLOCKY_SHIFT   (16U)
#define	PXP_STAT_CLR_BLOCKY(x)
#define	PXP_STAT_CLR_BLOCKX_MASK   (0xFF000000U)
#define	PXP_STAT_CLR_BLOCKX_SHIFT   (24U)
#define	PXP_STAT_CLR_BLOCKX(x)
STAT_TOG - Status Register
#define	PXP_STAT_TOG_IRQ_MASK   (0x1U)
#define	PXP_STAT_TOG_IRQ_SHIFT   (0U)
#define	PXP_STAT_TOG_IRQ(x)
#define	PXP_STAT_TOG_AXI_WRITE_ERROR_MASK   (0x2U)
#define	PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT   (1U)
#define	PXP_STAT_TOG_AXI_WRITE_ERROR(x)
#define	PXP_STAT_TOG_AXI_READ_ERROR_MASK   (0x4U)
#define	PXP_STAT_TOG_AXI_READ_ERROR_SHIFT   (2U)
#define	PXP_STAT_TOG_AXI_READ_ERROR(x)
#define	PXP_STAT_TOG_NEXT_IRQ_MASK   (0x8U)
#define	PXP_STAT_TOG_NEXT_IRQ_SHIFT   (3U)
#define	PXP_STAT_TOG_NEXT_IRQ(x)
#define	PXP_STAT_TOG_AXI_ERROR_ID_MASK   (0xF0U)
#define	PXP_STAT_TOG_AXI_ERROR_ID_SHIFT   (4U)
#define	PXP_STAT_TOG_AXI_ERROR_ID(x)
#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK   (0x100U)
#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT   (8U)
#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x)
#define	PXP_STAT_TOG_BLOCKY_MASK   (0xFF0000U)
#define	PXP_STAT_TOG_BLOCKY_SHIFT   (16U)
#define	PXP_STAT_TOG_BLOCKY(x)
#define	PXP_STAT_TOG_BLOCKX_MASK   (0xFF000000U)
#define	PXP_STAT_TOG_BLOCKX_SHIFT   (24U)
#define	PXP_STAT_TOG_BLOCKX(x)
OUT_CTRL - Output Buffer Control Register
#define	PXP_OUT_CTRL_FORMAT_MASK   (0x1FU)
#define	PXP_OUT_CTRL_FORMAT_SHIFT   (0U)
#define	PXP_OUT_CTRL_FORMAT(x)
#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK   (0x300U)
#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT   (8U)
#define	PXP_OUT_CTRL_INTERLACED_OUTPUT(x)
#define	PXP_OUT_CTRL_ALPHA_OUTPUT_MASK   (0x800000U)
#define	PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT   (23U)
#define	PXP_OUT_CTRL_ALPHA_OUTPUT(x)
#define	PXP_OUT_CTRL_ALPHA_MASK   (0xFF000000U)
#define	PXP_OUT_CTRL_ALPHA_SHIFT   (24U)
#define	PXP_OUT_CTRL_ALPHA(x)
OUT_CTRL_SET - Output Buffer Control Register
#define	PXP_OUT_CTRL_SET_FORMAT_MASK   (0x1FU)
#define	PXP_OUT_CTRL_SET_FORMAT_SHIFT   (0U)
#define	PXP_OUT_CTRL_SET_FORMAT(x)
#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK   (0x300U)
#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT   (8U)
#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)
#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK   (0x800000U)
#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT   (23U)
#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x)
#define	PXP_OUT_CTRL_SET_ALPHA_MASK   (0xFF000000U)
#define	PXP_OUT_CTRL_SET_ALPHA_SHIFT   (24U)
#define	PXP_OUT_CTRL_SET_ALPHA(x)
OUT_CTRL_CLR - Output Buffer Control Register
#define	PXP_OUT_CTRL_CLR_FORMAT_MASK   (0x1FU)
#define	PXP_OUT_CTRL_CLR_FORMAT_SHIFT   (0U)
#define	PXP_OUT_CTRL_CLR_FORMAT(x)
#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK   (0x300U)
#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT   (8U)
#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)
#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK   (0x800000U)
#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT   (23U)
#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x)
#define	PXP_OUT_CTRL_CLR_ALPHA_MASK   (0xFF000000U)
#define	PXP_OUT_CTRL_CLR_ALPHA_SHIFT   (24U)
#define	PXP_OUT_CTRL_CLR_ALPHA(x)
OUT_CTRL_TOG - Output Buffer Control Register
#define	PXP_OUT_CTRL_TOG_FORMAT_MASK   (0x1FU)
#define	PXP_OUT_CTRL_TOG_FORMAT_SHIFT   (0U)
#define	PXP_OUT_CTRL_TOG_FORMAT(x)
#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK   (0x300U)
#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT   (8U)
#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)
#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK   (0x800000U)
#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT   (23U)
#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x)
#define	PXP_OUT_CTRL_TOG_ALPHA_MASK   (0xFF000000U)
#define	PXP_OUT_CTRL_TOG_ALPHA_SHIFT   (24U)
#define	PXP_OUT_CTRL_TOG_ALPHA(x)
OUT_BUF - Output Frame Buffer Pointer
#define	PXP_OUT_BUF_ADDR_MASK   (0xFFFFFFFFU)
#define	PXP_OUT_BUF_ADDR_SHIFT   (0U)
#define	PXP_OUT_BUF_ADDR(x)
OUT_BUF2 - Output Frame Buffer Pointer #2
#define	PXP_OUT_BUF2_ADDR_MASK   (0xFFFFFFFFU)
#define	PXP_OUT_BUF2_ADDR_SHIFT   (0U)
#define	PXP_OUT_BUF2_ADDR(x)
OUT_PITCH - Output Buffer Pitch
#define	PXP_OUT_PITCH_PITCH_MASK   (0xFFFFU)
#define	PXP_OUT_PITCH_PITCH_SHIFT   (0U)
#define	PXP_OUT_PITCH_PITCH(x)
OUT_LRC - Output Surface Lower Right Coordinate
#define	PXP_OUT_LRC_Y_MASK   (0x3FFFU)
#define	PXP_OUT_LRC_Y_SHIFT   (0U)
#define	PXP_OUT_LRC_Y(x)
#define	PXP_OUT_LRC_X_MASK   (0x3FFF0000U)
#define	PXP_OUT_LRC_X_SHIFT   (16U)
#define	PXP_OUT_LRC_X(x)
OUT_PS_ULC - Processed Surface Upper Left Coordinate
#define	PXP_OUT_PS_ULC_Y_MASK   (0x3FFFU)
#define	PXP_OUT_PS_ULC_Y_SHIFT   (0U)
#define	PXP_OUT_PS_ULC_Y(x)
#define	PXP_OUT_PS_ULC_X_MASK   (0x3FFF0000U)
#define	PXP_OUT_PS_ULC_X_SHIFT   (16U)
#define	PXP_OUT_PS_ULC_X(x)
OUT_PS_LRC - Processed Surface Lower Right Coordinate
#define	PXP_OUT_PS_LRC_Y_MASK   (0x3FFFU)
#define	PXP_OUT_PS_LRC_Y_SHIFT   (0U)
#define	PXP_OUT_PS_LRC_Y(x)
#define	PXP_OUT_PS_LRC_X_MASK   (0x3FFF0000U)
#define	PXP_OUT_PS_LRC_X_SHIFT   (16U)
#define	PXP_OUT_PS_LRC_X(x)
OUT_AS_ULC - Alpha Surface Upper Left Coordinate
#define	PXP_OUT_AS_ULC_Y_MASK   (0x3FFFU)
#define	PXP_OUT_AS_ULC_Y_SHIFT   (0U)
#define	PXP_OUT_AS_ULC_Y(x)
#define	PXP_OUT_AS_ULC_X_MASK   (0x3FFF0000U)
#define	PXP_OUT_AS_ULC_X_SHIFT   (16U)
#define	PXP_OUT_AS_ULC_X(x)
OUT_AS_LRC - Alpha Surface Lower Right Coordinate
#define	PXP_OUT_AS_LRC_Y_MASK   (0x3FFFU)
#define	PXP_OUT_AS_LRC_Y_SHIFT   (0U)
#define	PXP_OUT_AS_LRC_Y(x)
#define	PXP_OUT_AS_LRC_X_MASK   (0x3FFF0000U)
#define	PXP_OUT_AS_LRC_X_SHIFT   (16U)
#define	PXP_OUT_AS_LRC_X(x)
PS_CTRL - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_FORMAT_MASK   (0x3FU)
#define	PXP_PS_CTRL_FORMAT_SHIFT   (0U)
#define	PXP_PS_CTRL_FORMAT(x)
#define	PXP_PS_CTRL_WB_SWAP_MASK   (0x40U)
#define	PXP_PS_CTRL_WB_SWAP_SHIFT   (6U)
#define	PXP_PS_CTRL_WB_SWAP(x)
#define	PXP_PS_CTRL_DECY_MASK   (0x300U)
#define	PXP_PS_CTRL_DECY_SHIFT   (8U)
#define	PXP_PS_CTRL_DECY(x)
#define	PXP_PS_CTRL_DECX_MASK   (0xC00U)
#define	PXP_PS_CTRL_DECX_SHIFT   (10U)
#define	PXP_PS_CTRL_DECX(x)
PS_CTRL_SET - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_SET_FORMAT_MASK   (0x3FU)
#define	PXP_PS_CTRL_SET_FORMAT_SHIFT   (0U)
#define	PXP_PS_CTRL_SET_FORMAT(x)
#define	PXP_PS_CTRL_SET_WB_SWAP_MASK   (0x40U)
#define	PXP_PS_CTRL_SET_WB_SWAP_SHIFT   (6U)
#define	PXP_PS_CTRL_SET_WB_SWAP(x)
#define	PXP_PS_CTRL_SET_DECY_MASK   (0x300U)
#define	PXP_PS_CTRL_SET_DECY_SHIFT   (8U)
#define	PXP_PS_CTRL_SET_DECY(x)
#define	PXP_PS_CTRL_SET_DECX_MASK   (0xC00U)
#define	PXP_PS_CTRL_SET_DECX_SHIFT   (10U)
#define	PXP_PS_CTRL_SET_DECX(x)
PS_CTRL_CLR - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_CLR_FORMAT_MASK   (0x3FU)
#define	PXP_PS_CTRL_CLR_FORMAT_SHIFT   (0U)
#define	PXP_PS_CTRL_CLR_FORMAT(x)
#define	PXP_PS_CTRL_CLR_WB_SWAP_MASK   (0x40U)
#define	PXP_PS_CTRL_CLR_WB_SWAP_SHIFT   (6U)
#define	PXP_PS_CTRL_CLR_WB_SWAP(x)
#define	PXP_PS_CTRL_CLR_DECY_MASK   (0x300U)
#define	PXP_PS_CTRL_CLR_DECY_SHIFT   (8U)
#define	PXP_PS_CTRL_CLR_DECY(x)
#define	PXP_PS_CTRL_CLR_DECX_MASK   (0xC00U)
#define	PXP_PS_CTRL_CLR_DECX_SHIFT   (10U)
#define	PXP_PS_CTRL_CLR_DECX(x)
PS_CTRL_TOG - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_TOG_FORMAT_MASK   (0x3FU)
#define	PXP_PS_CTRL_TOG_FORMAT_SHIFT   (0U)
#define	PXP_PS_CTRL_TOG_FORMAT(x)
#define	PXP_PS_CTRL_TOG_WB_SWAP_MASK   (0x40U)
#define	PXP_PS_CTRL_TOG_WB_SWAP_SHIFT   (6U)
#define	PXP_PS_CTRL_TOG_WB_SWAP(x)
#define	PXP_PS_CTRL_TOG_DECY_MASK   (0x300U)
#define	PXP_PS_CTRL_TOG_DECY_SHIFT   (8U)
#define	PXP_PS_CTRL_TOG_DECY(x)
#define	PXP_PS_CTRL_TOG_DECX_MASK   (0xC00U)
#define	PXP_PS_CTRL_TOG_DECX_SHIFT   (10U)
#define	PXP_PS_CTRL_TOG_DECX(x)
PS_BUF - PS Input Buffer Address
#define	PXP_PS_BUF_ADDR_MASK   (0xFFFFFFFFU)
#define	PXP_PS_BUF_ADDR_SHIFT   (0U)
#define	PXP_PS_BUF_ADDR(x)
PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address
#define	PXP_PS_UBUF_ADDR_MASK   (0xFFFFFFFFU)
#define	PXP_PS_UBUF_ADDR_SHIFT   (0U)
#define	PXP_PS_UBUF_ADDR(x)
PS_VBUF - PS V/Cr Input Buffer Address
#define	PXP_PS_VBUF_ADDR_MASK   (0xFFFFFFFFU)
#define	PXP_PS_VBUF_ADDR_SHIFT   (0U)
#define	PXP_PS_VBUF_ADDR(x)
PS_PITCH - Processed Surface Pitch
#define	PXP_PS_PITCH_PITCH_MASK   (0xFFFFU)
#define	PXP_PS_PITCH_PITCH_SHIFT   (0U)
#define	PXP_PS_PITCH_PITCH(x)
PS_BACKGROUND - PS Background Color
#define	PXP_PS_BACKGROUND_COLOR_MASK   (0xFFFFFFU)
#define	PXP_PS_BACKGROUND_COLOR_SHIFT   (0U)
#define	PXP_PS_BACKGROUND_COLOR(x)
PS_SCALE - PS Scale Factor Register
#define	PXP_PS_SCALE_XSCALE_MASK   (0x7FFFU)
#define	PXP_PS_SCALE_XSCALE_SHIFT   (0U)
#define	PXP_PS_SCALE_XSCALE(x)
#define	PXP_PS_SCALE_YSCALE_MASK   (0x7FFF0000U)
#define	PXP_PS_SCALE_YSCALE_SHIFT   (16U)
#define	PXP_PS_SCALE_YSCALE(x)
PS_OFFSET - PS Scale Offset Register
#define	PXP_PS_OFFSET_XOFFSET_MASK   (0xFFFU)
#define	PXP_PS_OFFSET_XOFFSET_SHIFT   (0U)
#define	PXP_PS_OFFSET_XOFFSET(x)
#define	PXP_PS_OFFSET_YOFFSET_MASK   (0xFFF0000U)
#define	PXP_PS_OFFSET_YOFFSET_SHIFT   (16U)
#define	PXP_PS_OFFSET_YOFFSET(x)
PS_CLRKEYLOW - PS Color Key Low
#define	PXP_PS_CLRKEYLOW_PIXEL_MASK   (0xFFFFFFU)
#define	PXP_PS_CLRKEYLOW_PIXEL_SHIFT   (0U)
#define	PXP_PS_CLRKEYLOW_PIXEL(x)
PS_CLRKEYHIGH - PS Color Key High
#define	PXP_PS_CLRKEYHIGH_PIXEL_MASK   (0xFFFFFFU)
#define	PXP_PS_CLRKEYHIGH_PIXEL_SHIFT   (0U)
#define	PXP_PS_CLRKEYHIGH_PIXEL(x)
AS_CTRL - Alpha Surface Control
#define	PXP_AS_CTRL_ALPHA_CTRL_MASK   (0x6U)
#define	PXP_AS_CTRL_ALPHA_CTRL_SHIFT   (1U)
#define	PXP_AS_CTRL_ALPHA_CTRL(x)
#define	PXP_AS_CTRL_ENABLE_COLORKEY_MASK   (0x8U)
#define	PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT   (3U)
#define	PXP_AS_CTRL_ENABLE_COLORKEY(x)
#define	PXP_AS_CTRL_FORMAT_MASK   (0xF0U)
#define	PXP_AS_CTRL_FORMAT_SHIFT   (4U)
#define	PXP_AS_CTRL_FORMAT(x)
#define	PXP_AS_CTRL_ALPHA_MASK   (0xFF00U)
#define	PXP_AS_CTRL_ALPHA_SHIFT   (8U)
#define	PXP_AS_CTRL_ALPHA(x)
#define	PXP_AS_CTRL_ROP_MASK   (0xF0000U)
#define	PXP_AS_CTRL_ROP_SHIFT   (16U)
#define	PXP_AS_CTRL_ROP(x)
#define	PXP_AS_CTRL_ALPHA_INVERT_MASK   (0x100000U)
#define	PXP_AS_CTRL_ALPHA_INVERT_SHIFT   (20U)
#define	PXP_AS_CTRL_ALPHA_INVERT(x)
AS_BUF - Alpha Surface Buffer Pointer
#define	PXP_AS_BUF_ADDR_MASK   (0xFFFFFFFFU)
#define	PXP_AS_BUF_ADDR_SHIFT   (0U)
#define	PXP_AS_BUF_ADDR(x)
AS_PITCH - Alpha Surface Pitch
#define	PXP_AS_PITCH_PITCH_MASK   (0xFFFFU)
#define	PXP_AS_PITCH_PITCH_SHIFT   (0U)
#define	PXP_AS_PITCH_PITCH(x)
AS_CLRKEYLOW - Overlay Color Key Low
#define	PXP_AS_CLRKEYLOW_PIXEL_MASK   (0xFFFFFFU)
#define	PXP_AS_CLRKEYLOW_PIXEL_SHIFT   (0U)
#define	PXP_AS_CLRKEYLOW_PIXEL(x)
AS_CLRKEYHIGH - Overlay Color Key High
#define	PXP_AS_CLRKEYHIGH_PIXEL_MASK   (0xFFFFFFU)
#define	PXP_AS_CLRKEYHIGH_PIXEL_SHIFT   (0U)
#define	PXP_AS_CLRKEYHIGH_PIXEL(x)
CSC1_COEF0 - Color Space Conversion Coefficient Register 0
#define	PXP_CSC1_COEF0_Y_OFFSET_MASK   (0x1FFU)
#define	PXP_CSC1_COEF0_Y_OFFSET_SHIFT   (0U)
#define	PXP_CSC1_COEF0_Y_OFFSET(x)
#define	PXP_CSC1_COEF0_UV_OFFSET_MASK   (0x3FE00U)
#define	PXP_CSC1_COEF0_UV_OFFSET_SHIFT   (9U)
#define	PXP_CSC1_COEF0_UV_OFFSET(x)
#define	PXP_CSC1_COEF0_C0_MASK   (0x1FFC0000U)
#define	PXP_CSC1_COEF0_C0_SHIFT   (18U)
#define	PXP_CSC1_COEF0_C0(x)
#define	PXP_CSC1_COEF0_BYPASS_MASK   (0x40000000U)
#define	PXP_CSC1_COEF0_BYPASS_SHIFT   (30U)
#define	PXP_CSC1_COEF0_BYPASS(x)
#define	PXP_CSC1_COEF0_YCBCR_MODE_MASK   (0x80000000U)
#define	PXP_CSC1_COEF0_YCBCR_MODE_SHIFT   (31U)
#define	PXP_CSC1_COEF0_YCBCR_MODE(x)
CSC1_COEF1 - Color Space Conversion Coefficient Register 1
#define	PXP_CSC1_COEF1_C4_MASK   (0x7FFU)
#define	PXP_CSC1_COEF1_C4_SHIFT   (0U)
#define	PXP_CSC1_COEF1_C4(x)
#define	PXP_CSC1_COEF1_C1_MASK   (0x7FF0000U)
#define	PXP_CSC1_COEF1_C1_SHIFT   (16U)
#define	PXP_CSC1_COEF1_C1(x)
CSC1_COEF2 - Color Space Conversion Coefficient Register 2
#define	PXP_CSC1_COEF2_C3_MASK   (0x7FFU)
#define	PXP_CSC1_COEF2_C3_SHIFT   (0U)
#define	PXP_CSC1_COEF2_C3(x)
#define	PXP_CSC1_COEF2_C2_MASK   (0x7FF0000U)
#define	PXP_CSC1_COEF2_C2_SHIFT   (16U)
#define	PXP_CSC1_COEF2_C2(x)
POWER - PXP Power Control Register
#define	PXP_POWER_ROT_MEM_LP_STATE_MASK   (0xE00U)
#define	PXP_POWER_ROT_MEM_LP_STATE_SHIFT   (9U)
#define	PXP_POWER_ROT_MEM_LP_STATE(x)
NEXT - Next Frame Pointer
#define	PXP_NEXT_ENABLED_MASK   (0x1U)
#define	PXP_NEXT_ENABLED_SHIFT   (0U)
#define	PXP_NEXT_ENABLED(x)
#define	PXP_NEXT_POINTER_MASK   (0xFFFFFFFCU)
#define	PXP_NEXT_POINTER_SHIFT   (2U)
#define	PXP_NEXT_POINTER(x)
PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register.
#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK   (0x1U)
#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT   (0U)
#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x)
#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK   (0x6U)
#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT   (1U)
#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK   (0x18U)
#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT   (3U)
#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK   (0x20U)
#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT   (5U)
#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK   (0x40U)
#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT   (6U)
#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK   (0x300U)
#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT   (8U)
#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK   (0xC00U)
#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT   (10U)
#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK   (0x1000U)
#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT   (12U)
#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK   (0x2000U)
#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT   (13U)
#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x)
#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK   (0xFF0000U)
#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT   (16U)
#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x)
#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK   (0xFF000000U)
#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT   (24U)
#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x)
VIR - Version Information
#define	RDC_VIR_NDID_MASK   (0xFU)
#define	RDC_VIR_NDID_SHIFT   (0U)
#define	RDC_VIR_NDID(x)
#define	RDC_VIR_NMSTR_MASK   (0xFF0U)
#define	RDC_VIR_NMSTR_SHIFT   (4U)
#define	RDC_VIR_NMSTR(x)
#define	RDC_VIR_NPER_MASK   (0xFF000U)
#define	RDC_VIR_NPER_SHIFT   (12U)
#define	RDC_VIR_NPER(x)
#define	RDC_VIR_NRGN_MASK   (0xFF00000U)
#define	RDC_VIR_NRGN_SHIFT   (20U)
#define	RDC_VIR_NRGN(x)
STAT - Status
#define	RDC_STAT_DID_MASK   (0xFU)
#define	RDC_STAT_DID_SHIFT   (0U)
#define	RDC_STAT_DID(x)
#define	RDC_STAT_PDS_MASK   (0x100U)
#define	RDC_STAT_PDS_SHIFT   (8U)
#define	RDC_STAT_PDS(x)
INTCTRL - Interrupt and Control
#define	RDC_INTCTRL_RCI_EN_MASK   (0x1U)
#define	RDC_INTCTRL_RCI_EN_SHIFT   (0U)
#define	RDC_INTCTRL_RCI_EN(x)
INTSTAT - Interrupt Status
#define	RDC_INTSTAT_INT_MASK   (0x1U)
#define	RDC_INTSTAT_INT_SHIFT   (0U)
#define	RDC_INTSTAT_INT(x)
MDA - Master Domain Assignment
#define	RDC_MDA_DID_MASK   (0x3U)
#define	RDC_MDA_DID_SHIFT   (0U)
#define	RDC_MDA_DID(x)
#define	RDC_MDA_LCK_MASK   (0x80000000U)
#define	RDC_MDA_LCK_SHIFT   (31U)
#define	RDC_MDA_LCK(x)
PDAP - Peripheral Domain Access Permissions
#define	RDC_PDAP_D0W_MASK   (0x1U)
#define	RDC_PDAP_D0W_SHIFT   (0U)
#define	RDC_PDAP_D0W(x)
#define	RDC_PDAP_D0R_MASK   (0x2U)
#define	RDC_PDAP_D0R_SHIFT   (1U)
#define	RDC_PDAP_D0R(x)
#define	RDC_PDAP_D1W_MASK   (0x4U)
#define	RDC_PDAP_D1W_SHIFT   (2U)
#define	RDC_PDAP_D1W(x)
#define	RDC_PDAP_D1R_MASK   (0x8U)
#define	RDC_PDAP_D1R_SHIFT   (3U)
#define	RDC_PDAP_D1R(x)
#define	RDC_PDAP_SREQ_MASK   (0x40000000U)
#define	RDC_PDAP_SREQ_SHIFT   (30U)
#define	RDC_PDAP_SREQ(x)
#define	RDC_PDAP_LCK_MASK   (0x80000000U)
#define	RDC_PDAP_LCK_SHIFT   (31U)
#define	RDC_PDAP_LCK(x)
MRSA - Memory Region Start Address
#define	RDC_MRSA_SADR_MASK   (0xFFFFFF80U)
#define	RDC_MRSA_SADR_SHIFT   (7U)
#define	RDC_MRSA_SADR(x)
MREA - Memory Region End Address
#define	RDC_MREA_EADR_MASK   (0xFFFFFF80U)
#define	RDC_MREA_EADR_SHIFT   (7U)
#define	RDC_MREA_EADR(x)
MRC - Memory Region Control
#define	RDC_MRC_D0W_MASK   (0x1U)
#define	RDC_MRC_D0W_SHIFT   (0U)
#define	RDC_MRC_D0W(x)
#define	RDC_MRC_D0R_MASK   (0x2U)
#define	RDC_MRC_D0R_SHIFT   (1U)
#define	RDC_MRC_D0R(x)
#define	RDC_MRC_D1W_MASK   (0x4U)
#define	RDC_MRC_D1W_SHIFT   (2U)
#define	RDC_MRC_D1W(x)
#define	RDC_MRC_D1R_MASK   (0x8U)
#define	RDC_MRC_D1R_SHIFT   (3U)
#define	RDC_MRC_D1R(x)
#define	RDC_MRC_ENA_MASK   (0x40000000U)
#define	RDC_MRC_ENA_SHIFT   (30U)
#define	RDC_MRC_ENA(x)
#define	RDC_MRC_LCK_MASK   (0x80000000U)
#define	RDC_MRC_LCK_SHIFT   (31U)
#define	RDC_MRC_LCK(x)
MRVS - Memory Region Violation Status
#define	RDC_MRVS_VDID_MASK   (0x3U)
#define	RDC_MRVS_VDID_SHIFT   (0U)
#define	RDC_MRVS_VDID(x)
#define	RDC_MRVS_AD_MASK   (0x10U)
#define	RDC_MRVS_AD_SHIFT   (4U)
#define	RDC_MRVS_AD(x)
#define	RDC_MRVS_VADR_MASK   (0xFFFFFFE0U)
#define	RDC_MRVS_VADR_SHIFT   (5U)
#define	RDC_MRVS_VADR(x)
GATE - Gate Register
#define	RDC_SEMAPHORE_GATE_GTFSM_MASK   (0xFU)
#define	RDC_SEMAPHORE_GATE_GTFSM_SHIFT   (0U)
#define	RDC_SEMAPHORE_GATE_GTFSM(x)
#define	RDC_SEMAPHORE_GATE_LDOM_MASK   (0x30U)
#define	RDC_SEMAPHORE_GATE_LDOM_SHIFT   (4U)
#define	RDC_SEMAPHORE_GATE_LDOM(x)
RSTGT_R - Reset Gate Read
#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK   (0xFU)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT   (0U)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK   (0x30U)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT   (4U)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK   (0xFF00U)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT   (8U)
#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)
RSTGT_W - Reset Gate Write
#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK   (0xFFU)
#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT   (0U)
#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)
#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK   (0xFF00U)
#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT   (8U)
#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)
CS - Watchdog Control and Status Register
#define	RTWDOG_CS_STOP_MASK   (0x1U)
#define	RTWDOG_CS_STOP_SHIFT   (0U)
#define	RTWDOG_CS_STOP(x)
#define	RTWDOG_CS_WAIT_MASK   (0x2U)
#define	RTWDOG_CS_WAIT_SHIFT   (1U)
#define	RTWDOG_CS_WAIT(x)
#define	RTWDOG_CS_DBG_MASK   (0x4U)
#define	RTWDOG_CS_DBG_SHIFT   (2U)
#define	RTWDOG_CS_DBG(x)
#define	RTWDOG_CS_TST_MASK   (0x18U)
#define	RTWDOG_CS_TST_SHIFT   (3U)
#define	RTWDOG_CS_TST(x)
#define	RTWDOG_CS_UPDATE_MASK   (0x20U)
#define	RTWDOG_CS_UPDATE_SHIFT   (5U)
#define	RTWDOG_CS_UPDATE(x)
#define	RTWDOG_CS_INT_MASK   (0x40U)
#define	RTWDOG_CS_INT_SHIFT   (6U)
#define	RTWDOG_CS_INT(x)
#define	RTWDOG_CS_EN_MASK   (0x80U)
#define	RTWDOG_CS_EN_SHIFT   (7U)
#define	RTWDOG_CS_EN(x)
#define	RTWDOG_CS_CLK_MASK   (0x300U)
#define	RTWDOG_CS_CLK_SHIFT   (8U)
#define	RTWDOG_CS_CLK(x)
#define	RTWDOG_CS_RCS_MASK   (0x400U)
#define	RTWDOG_CS_RCS_SHIFT   (10U)
#define	RTWDOG_CS_RCS(x)
#define	RTWDOG_CS_ULK_MASK   (0x800U)
#define	RTWDOG_CS_ULK_SHIFT   (11U)
#define	RTWDOG_CS_ULK(x)
#define	RTWDOG_CS_PRES_MASK   (0x1000U)
#define	RTWDOG_CS_PRES_SHIFT   (12U)
#define	RTWDOG_CS_PRES(x)
#define	RTWDOG_CS_CMD32EN_MASK   (0x2000U)
#define	RTWDOG_CS_CMD32EN_SHIFT   (13U)
#define	RTWDOG_CS_CMD32EN(x)
#define	RTWDOG_CS_FLG_MASK   (0x4000U)
#define	RTWDOG_CS_FLG_SHIFT   (14U)
#define	RTWDOG_CS_FLG(x)
#define	RTWDOG_CS_WIN_MASK   (0x8000U)
#define	RTWDOG_CS_WIN_SHIFT   (15U)
#define	RTWDOG_CS_WIN(x)
CNT - Watchdog Counter Register
#define	RTWDOG_CNT_CNTLOW_MASK   (0xFFU)
#define	RTWDOG_CNT_CNTLOW_SHIFT   (0U)
#define	RTWDOG_CNT_CNTLOW(x)
#define	RTWDOG_CNT_CNTHIGH_MASK   (0xFF00U)
#define	RTWDOG_CNT_CNTHIGH_SHIFT   (8U)
#define	RTWDOG_CNT_CNTHIGH(x)
TOVAL - Watchdog Timeout Value Register
#define	RTWDOG_TOVAL_TOVALLOW_MASK   (0xFFU)
#define	RTWDOG_TOVAL_TOVALLOW_SHIFT   (0U)
#define	RTWDOG_TOVAL_TOVALLOW(x)
#define	RTWDOG_TOVAL_TOVALHIGH_MASK   (0xFF00U)
#define	RTWDOG_TOVAL_TOVALHIGH_SHIFT   (8U)
#define	RTWDOG_TOVAL_TOVALHIGH(x)
WIN - Watchdog Window Register
#define	RTWDOG_WIN_WINLOW_MASK   (0xFFU)
#define	RTWDOG_WIN_WINLOW_SHIFT   (0U)
#define	RTWDOG_WIN_WINLOW(x)
#define	RTWDOG_WIN_WINHIGH_MASK   (0xFF00U)
#define	RTWDOG_WIN_WINHIGH_SHIFT   (8U)
#define	RTWDOG_WIN_WINHIGH(x)
GATE - Semaphores Gate n Register
#define	SEMA4_GATE_GTFSM_MASK   (0x3U)
#define	SEMA4_GATE_GTFSM_SHIFT   (0U)
#define	SEMA4_GATE_GTFSM(x)
CPINE - Semaphores Processor n IRQ Notification Enable
#define	SEMA4_CPINE_INE7_MASK   (0x1U)
#define	SEMA4_CPINE_INE7_SHIFT   (0U)
#define	SEMA4_CPINE_INE7(x)
#define	SEMA4_CPINE_INE6_MASK   (0x2U)
#define	SEMA4_CPINE_INE6_SHIFT   (1U)
#define	SEMA4_CPINE_INE6(x)
#define	SEMA4_CPINE_INE5_MASK   (0x4U)
#define	SEMA4_CPINE_INE5_SHIFT   (2U)
#define	SEMA4_CPINE_INE5(x)
#define	SEMA4_CPINE_INE4_MASK   (0x8U)
#define	SEMA4_CPINE_INE4_SHIFT   (3U)
#define	SEMA4_CPINE_INE4(x)
#define	SEMA4_CPINE_INE3_MASK   (0x10U)
#define	SEMA4_CPINE_INE3_SHIFT   (4U)
#define	SEMA4_CPINE_INE3(x)
#define	SEMA4_CPINE_INE2_MASK   (0x20U)
#define	SEMA4_CPINE_INE2_SHIFT   (5U)
#define	SEMA4_CPINE_INE2(x)
#define	SEMA4_CPINE_INE1_MASK   (0x40U)
#define	SEMA4_CPINE_INE1_SHIFT   (6U)
#define	SEMA4_CPINE_INE1(x)
#define	SEMA4_CPINE_INE0_MASK   (0x80U)
#define	SEMA4_CPINE_INE0_SHIFT   (7U)
#define	SEMA4_CPINE_INE0(x)
#define	SEMA4_CPINE_INE15_MASK   (0x100U)
#define	SEMA4_CPINE_INE15_SHIFT   (8U)
#define	SEMA4_CPINE_INE15(x)
#define	SEMA4_CPINE_INE14_MASK   (0x200U)
#define	SEMA4_CPINE_INE14_SHIFT   (9U)
#define	SEMA4_CPINE_INE14(x)
#define	SEMA4_CPINE_INE13_MASK   (0x400U)
#define	SEMA4_CPINE_INE13_SHIFT   (10U)
#define	SEMA4_CPINE_INE13(x)
#define	SEMA4_CPINE_INE12_MASK   (0x800U)
#define	SEMA4_CPINE_INE12_SHIFT   (11U)
#define	SEMA4_CPINE_INE12(x)
#define	SEMA4_CPINE_INE11_MASK   (0x1000U)
#define	SEMA4_CPINE_INE11_SHIFT   (12U)
#define	SEMA4_CPINE_INE11(x)
#define	SEMA4_CPINE_INE10_MASK   (0x2000U)
#define	SEMA4_CPINE_INE10_SHIFT   (13U)
#define	SEMA4_CPINE_INE10(x)
#define	SEMA4_CPINE_INE9_MASK   (0x4000U)
#define	SEMA4_CPINE_INE9_SHIFT   (14U)
#define	SEMA4_CPINE_INE9(x)
#define	SEMA4_CPINE_INE8_MASK   (0x8000U)
#define	SEMA4_CPINE_INE8_SHIFT   (15U)
#define	SEMA4_CPINE_INE8(x)
CPNTF - Semaphores Processor n IRQ Notification
#define	SEMA4_CPNTF_GN7_MASK   (0x1U)
#define	SEMA4_CPNTF_GN7_SHIFT   (0U)
#define	SEMA4_CPNTF_GN7(x)
#define	SEMA4_CPNTF_GN6_MASK   (0x2U)
#define	SEMA4_CPNTF_GN6_SHIFT   (1U)
#define	SEMA4_CPNTF_GN6(x)
#define	SEMA4_CPNTF_GN5_MASK   (0x4U)
#define	SEMA4_CPNTF_GN5_SHIFT   (2U)
#define	SEMA4_CPNTF_GN5(x)
#define	SEMA4_CPNTF_GN4_MASK   (0x8U)
#define	SEMA4_CPNTF_GN4_SHIFT   (3U)
#define	SEMA4_CPNTF_GN4(x)
#define	SEMA4_CPNTF_GN3_MASK   (0x10U)
#define	SEMA4_CPNTF_GN3_SHIFT   (4U)
#define	SEMA4_CPNTF_GN3(x)
#define	SEMA4_CPNTF_GN2_MASK   (0x20U)
#define	SEMA4_CPNTF_GN2_SHIFT   (5U)
#define	SEMA4_CPNTF_GN2(x)
#define	SEMA4_CPNTF_GN1_MASK   (0x40U)
#define	SEMA4_CPNTF_GN1_SHIFT   (6U)
#define	SEMA4_CPNTF_GN1(x)
#define	SEMA4_CPNTF_GN0_MASK   (0x80U)
#define	SEMA4_CPNTF_GN0_SHIFT   (7U)
#define	SEMA4_CPNTF_GN0(x)
#define	SEMA4_CPNTF_GN15_MASK   (0x100U)
#define	SEMA4_CPNTF_GN15_SHIFT   (8U)
#define	SEMA4_CPNTF_GN15(x)
#define	SEMA4_CPNTF_GN14_MASK   (0x200U)
#define	SEMA4_CPNTF_GN14_SHIFT   (9U)
#define	SEMA4_CPNTF_GN14(x)
#define	SEMA4_CPNTF_GN13_MASK   (0x400U)
#define	SEMA4_CPNTF_GN13_SHIFT   (10U)
#define	SEMA4_CPNTF_GN13(x)
#define	SEMA4_CPNTF_GN12_MASK   (0x800U)
#define	SEMA4_CPNTF_GN12_SHIFT   (11U)
#define	SEMA4_CPNTF_GN12(x)
#define	SEMA4_CPNTF_GN11_MASK   (0x1000U)
#define	SEMA4_CPNTF_GN11_SHIFT   (12U)
#define	SEMA4_CPNTF_GN11(x)
#define	SEMA4_CPNTF_GN10_MASK   (0x2000U)
#define	SEMA4_CPNTF_GN10_SHIFT   (13U)
#define	SEMA4_CPNTF_GN10(x)
#define	SEMA4_CPNTF_GN9_MASK   (0x4000U)
#define	SEMA4_CPNTF_GN9_SHIFT   (14U)
#define	SEMA4_CPNTF_GN9(x)
#define	SEMA4_CPNTF_GN8_MASK   (0x8000U)
#define	SEMA4_CPNTF_GN8_SHIFT   (15U)
#define	SEMA4_CPNTF_GN8(x)
RSTGT - Semaphores (Secure) Reset Gate n
#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK   (0xFFU)
#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   (0U)
#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)
#define	SEMA4_RSTGT_RSTGTN_MASK   (0xFF00U)
#define	SEMA4_RSTGT_RSTGTN_SHIFT   (8U)
#define	SEMA4_RSTGT_RSTGTN(x)
RSTNTF - Semaphores (Secure) Reset IRQ Notification
#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   (0xFFU)
#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT   (0U)
#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)
#define	SEMA4_RSTNTF_RSTNTN_MASK   (0xFF00U)
#define	SEMA4_RSTNTF_RSTNTN_SHIFT   (8U)
#define	SEMA4_RSTNTF_RSTNTN(x)
MCR - Module Control Register
#define	SEMC_MCR_SWRST_MASK   (0x1U)
#define	SEMC_MCR_SWRST_SHIFT   (0U)
#define	SEMC_MCR_SWRST(x)
#define	SEMC_MCR_MDIS_MASK   (0x2U)
#define	SEMC_MCR_MDIS_SHIFT   (1U)
#define	SEMC_MCR_MDIS(x)
#define	SEMC_MCR_DQSMD_MASK   (0x4U)
#define	SEMC_MCR_DQSMD_SHIFT   (2U)
#define	SEMC_MCR_DQSMD(x)
#define	SEMC_MCR_WPOL0_MASK   (0x40U)
#define	SEMC_MCR_WPOL0_SHIFT   (6U)
#define	SEMC_MCR_WPOL0(x)
#define	SEMC_MCR_WPOL1_MASK   (0x80U)
#define	SEMC_MCR_WPOL1_SHIFT   (7U)
#define	SEMC_MCR_WPOL1(x)
#define	SEMC_MCR_CTO_MASK   (0xFF0000U)
#define	SEMC_MCR_CTO_SHIFT   (16U)
#define	SEMC_MCR_CTO(x)
#define	SEMC_MCR_BTO_MASK   (0x1F000000U)
#define	SEMC_MCR_BTO_SHIFT   (24U)
#define	SEMC_MCR_BTO(x)
#define	XRDC2_MCR_GVLDM_MASK   (0x1U)
#define	XRDC2_MCR_GVLDM_SHIFT   (0U)
#define	XRDC2_MCR_GVLDM(x)
#define	XRDC2_MCR_GVLDC_MASK   (0x2U)
#define	XRDC2_MCR_GVLDC_SHIFT   (1U)
#define	XRDC2_MCR_GVLDC(x)
#define	XRDC2_MCR_GCL_MASK   (0x30U)
#define	XRDC2_MCR_GCL_SHIFT   (4U)
#define	XRDC2_MCR_GCL(x)
IOCR - IO MUX Control Register
#define	SEMC_IOCR_MUX_A8_MASK   (0xFU)
#define	SEMC_IOCR_MUX_A8_SHIFT   (0U)
#define	SEMC_IOCR_MUX_A8(x)
#define	SEMC_IOCR_MUX_CSX0_MASK   (0xF0U)
#define	SEMC_IOCR_MUX_CSX0_SHIFT   (4U)
#define	SEMC_IOCR_MUX_CSX0(x)
#define	SEMC_IOCR_MUX_CSX1_MASK   (0xF00U)
#define	SEMC_IOCR_MUX_CSX1_SHIFT   (8U)
#define	SEMC_IOCR_MUX_CSX1(x)
#define	SEMC_IOCR_MUX_CSX2_MASK   (0xF000U)
#define	SEMC_IOCR_MUX_CSX2_SHIFT   (12U)
#define	SEMC_IOCR_MUX_CSX2(x)
#define	SEMC_IOCR_MUX_CSX3_MASK   (0xF0000U)
#define	SEMC_IOCR_MUX_CSX3_SHIFT   (16U)
#define	SEMC_IOCR_MUX_CSX3(x)
#define	SEMC_IOCR_MUX_RDY_MASK   (0xF00000U)
#define	SEMC_IOCR_MUX_RDY_SHIFT   (20U)
#define	SEMC_IOCR_MUX_RDY(x)
#define	SEMC_IOCR_MUX_CLKX0_MASK   (0x3000000U)
#define	SEMC_IOCR_MUX_CLKX0_SHIFT   (24U)
#define	SEMC_IOCR_MUX_CLKX0(x)
#define	SEMC_IOCR_MUX_CLKX1_MASK   (0xC000000U)
#define	SEMC_IOCR_MUX_CLKX1_SHIFT   (26U)
#define	SEMC_IOCR_MUX_CLKX1(x)
#define	SEMC_IOCR_CLKX0_AO_MASK   (0x10000000U)
#define	SEMC_IOCR_CLKX0_AO_SHIFT   (28U)
#define	SEMC_IOCR_CLKX0_AO(x)
#define	SEMC_IOCR_CLKX1_AO_MASK   (0x20000000U)
#define	SEMC_IOCR_CLKX1_AO_SHIFT   (29U)
#define	SEMC_IOCR_CLKX1_AO(x)
BMCR0 - Bus (AXI) Master Control Register 0
#define	SEMC_BMCR0_WQOS_MASK   (0xFU)
#define	SEMC_BMCR0_WQOS_SHIFT   (0U)
#define	SEMC_BMCR0_WQOS(x)
#define	SEMC_BMCR0_WAGE_MASK   (0xF0U)
#define	SEMC_BMCR0_WAGE_SHIFT   (4U)
#define	SEMC_BMCR0_WAGE(x)
#define	SEMC_BMCR0_WSH_MASK   (0xFF00U)
#define	SEMC_BMCR0_WSH_SHIFT   (8U)
#define	SEMC_BMCR0_WSH(x)
#define	SEMC_BMCR0_WRWS_MASK   (0xFF0000U)
#define	SEMC_BMCR0_WRWS_SHIFT   (16U)
#define	SEMC_BMCR0_WRWS(x)
BMCR1 - Bus (AXI) Master Control Register 1
#define	SEMC_BMCR1_WQOS_MASK   (0xFU)
#define	SEMC_BMCR1_WQOS_SHIFT   (0U)
#define	SEMC_BMCR1_WQOS(x)
#define	SEMC_BMCR1_WAGE_MASK   (0xF0U)
#define	SEMC_BMCR1_WAGE_SHIFT   (4U)
#define	SEMC_BMCR1_WAGE(x)
#define	SEMC_BMCR1_WPH_MASK   (0xFF00U)
#define	SEMC_BMCR1_WPH_SHIFT   (8U)
#define	SEMC_BMCR1_WPH(x)
#define	SEMC_BMCR1_WRWS_MASK   (0xFF0000U)
#define	SEMC_BMCR1_WRWS_SHIFT   (16U)
#define	SEMC_BMCR1_WRWS(x)
#define	SEMC_BMCR1_WBR_MASK   (0xFF000000U)
#define	SEMC_BMCR1_WBR_SHIFT   (24U)
#define	SEMC_BMCR1_WBR(x)
BR - Base Register 0..Base Register 8
#define	SEMC_BR_VLD_MASK   (0x1U)
#define	SEMC_BR_VLD_SHIFT   (0U)
#define	SEMC_BR_VLD(x)
#define	SEMC_BR_MS_MASK   (0x3EU)
#define	SEMC_BR_MS_SHIFT   (1U)
#define	SEMC_BR_MS(x)
#define	SEMC_BR_BA_MASK   (0xFFFFF000U)
#define	SEMC_BR_BA_SHIFT   (12U)
#define	SEMC_BR_BA(x)
DLLCR - DLL Control Register
#define	SEMC_DLLCR_DLLEN_MASK   (0x1U)
#define	SEMC_DLLCR_DLLEN_SHIFT   (0U)
#define	SEMC_DLLCR_DLLEN(x)
#define	SEMC_DLLCR_DLLRESET_MASK   (0x2U)
#define	SEMC_DLLCR_DLLRESET_SHIFT   (1U)
#define	SEMC_DLLCR_DLLRESET(x)
#define	SEMC_DLLCR_SLVDLYTARGET_MASK   (0x78U)
#define	SEMC_DLLCR_SLVDLYTARGET_SHIFT   (3U)
#define	SEMC_DLLCR_SLVDLYTARGET(x)
#define	SEMC_DLLCR_OVRDEN_MASK   (0x100U)
#define	SEMC_DLLCR_OVRDEN_SHIFT   (8U)
#define	SEMC_DLLCR_OVRDEN(x)
#define	SEMC_DLLCR_OVRDVAL_MASK   (0x7E00U)
#define	SEMC_DLLCR_OVRDVAL_SHIFT   (9U)
#define	SEMC_DLLCR_OVRDVAL(x)
SDRAMCR0 - SDRAM Control Register 0
#define	SEMC_SDRAMCR0_PS_MASK   (0x3U)
#define	SEMC_SDRAMCR0_PS_SHIFT   (0U)
#define	SEMC_SDRAMCR0_PS(x)
#define	SEMC_SDRAMCR0_BL_MASK   (0x70U)
#define	SEMC_SDRAMCR0_BL_SHIFT   (4U)
#define	SEMC_SDRAMCR0_BL(x)
#define	SEMC_SDRAMCR0_COL8_MASK   (0x80U)
#define	SEMC_SDRAMCR0_COL8_SHIFT   (7U)
#define	SEMC_SDRAMCR0_COL8(x)
#define	SEMC_SDRAMCR0_COL_MASK   (0x300U)
#define	SEMC_SDRAMCR0_COL_SHIFT   (8U)
#define	SEMC_SDRAMCR0_COL(x)
#define	SEMC_SDRAMCR0_CL_MASK   (0xC00U)
#define	SEMC_SDRAMCR0_CL_SHIFT   (10U)
#define	SEMC_SDRAMCR0_CL(x)
#define	SEMC_SDRAMCR0_BANK2_MASK   (0x4000U)
#define	SEMC_SDRAMCR0_BANK2_SHIFT   (14U)
#define	SEMC_SDRAMCR0_BANK2(x)
SDRAMCR1 - SDRAM Control Register 1
#define	SEMC_SDRAMCR1_PRE2ACT_MASK   (0xFU)
#define	SEMC_SDRAMCR1_PRE2ACT_SHIFT   (0U)
#define	SEMC_SDRAMCR1_PRE2ACT(x)
#define	SEMC_SDRAMCR1_ACT2RW_MASK   (0xF0U)
#define	SEMC_SDRAMCR1_ACT2RW_SHIFT   (4U)
#define	SEMC_SDRAMCR1_ACT2RW(x)
#define	SEMC_SDRAMCR1_RFRC_MASK   (0x1F00U)
#define	SEMC_SDRAMCR1_RFRC_SHIFT   (8U)
#define	SEMC_SDRAMCR1_RFRC(x)
#define	SEMC_SDRAMCR1_WRC_MASK   (0xE000U)
#define	SEMC_SDRAMCR1_WRC_SHIFT   (13U)
#define	SEMC_SDRAMCR1_WRC(x)
#define	SEMC_SDRAMCR1_CKEOFF_MASK   (0xF0000U)
#define	SEMC_SDRAMCR1_CKEOFF_SHIFT   (16U)
#define	SEMC_SDRAMCR1_CKEOFF(x)
#define	SEMC_SDRAMCR1_ACT2PRE_MASK   (0xF00000U)
#define	SEMC_SDRAMCR1_ACT2PRE_SHIFT   (20U)
#define	SEMC_SDRAMCR1_ACT2PRE(x)
SDRAMCR2 - SDRAM Control Register 2
#define	SEMC_SDRAMCR2_SRRC_MASK   (0xFFU)
#define	SEMC_SDRAMCR2_SRRC_SHIFT   (0U)
#define	SEMC_SDRAMCR2_SRRC(x)
#define	SEMC_SDRAMCR2_REF2REF_MASK   (0xFF00U)
#define	SEMC_SDRAMCR2_REF2REF_SHIFT   (8U)
#define	SEMC_SDRAMCR2_REF2REF(x)
#define	SEMC_SDRAMCR2_ACT2ACT_MASK   (0xFF0000U)
#define	SEMC_SDRAMCR2_ACT2ACT_SHIFT   (16U)
#define	SEMC_SDRAMCR2_ACT2ACT(x)
#define	SEMC_SDRAMCR2_ITO_MASK   (0xFF000000U)
#define	SEMC_SDRAMCR2_ITO_SHIFT   (24U)
#define	SEMC_SDRAMCR2_ITO(x)
SDRAMCR3 - SDRAM Control Register 3
#define	SEMC_SDRAMCR3_REN_MASK   (0x1U)
#define	SEMC_SDRAMCR3_REN_SHIFT   (0U)
#define	SEMC_SDRAMCR3_REN(x)
#define	SEMC_SDRAMCR3_REBL_MASK   (0xEU)
#define	SEMC_SDRAMCR3_REBL_SHIFT   (1U)
#define	SEMC_SDRAMCR3_REBL(x)
#define	SEMC_SDRAMCR3_PRESCALE_MASK   (0xFF00U)
#define	SEMC_SDRAMCR3_PRESCALE_SHIFT   (8U)
#define	SEMC_SDRAMCR3_PRESCALE(x)
#define	SEMC_SDRAMCR3_RT_MASK   (0xFF0000U)
#define	SEMC_SDRAMCR3_RT_SHIFT   (16U)
#define	SEMC_SDRAMCR3_RT(x)
#define	SEMC_SDRAMCR3_UT_MASK   (0xFF000000U)
#define	SEMC_SDRAMCR3_UT_SHIFT   (24U)
#define	SEMC_SDRAMCR3_UT(x)
NANDCR0 - NAND Control Register 0
#define	SEMC_NANDCR0_PS_MASK   (0x1U)
#define	SEMC_NANDCR0_PS_SHIFT   (0U)
#define	SEMC_NANDCR0_PS(x)
#define	SEMC_NANDCR0_SYNCEN_MASK   (0x2U)
#define	SEMC_NANDCR0_SYNCEN_SHIFT   (1U)
#define	SEMC_NANDCR0_SYNCEN(x)
#define	SEMC_NANDCR0_BL_MASK   (0x70U)
#define	SEMC_NANDCR0_BL_SHIFT   (4U)
#define	SEMC_NANDCR0_BL(x)
#define	SEMC_NANDCR0_EDO_MASK   (0x80U)
#define	SEMC_NANDCR0_EDO_SHIFT   (7U)
#define	SEMC_NANDCR0_EDO(x)
#define	SEMC_NANDCR0_COL_MASK   (0x700U)
#define	SEMC_NANDCR0_COL_SHIFT   (8U)
#define	SEMC_NANDCR0_COL(x)
NANDCR1 - NAND Control Register 1
#define	SEMC_NANDCR1_CES_MASK   (0xFU)
#define	SEMC_NANDCR1_CES_SHIFT   (0U)
#define	SEMC_NANDCR1_CES(x)
#define	SEMC_NANDCR1_CEH_MASK   (0xF0U)
#define	SEMC_NANDCR1_CEH_SHIFT   (4U)
#define	SEMC_NANDCR1_CEH(x)
#define	SEMC_NANDCR1_WEL_MASK   (0xF00U)
#define	SEMC_NANDCR1_WEL_SHIFT   (8U)
#define	SEMC_NANDCR1_WEL(x)
#define	SEMC_NANDCR1_WEH_MASK   (0xF000U)
#define	SEMC_NANDCR1_WEH_SHIFT   (12U)
#define	SEMC_NANDCR1_WEH(x)
#define	SEMC_NANDCR1_REL_MASK   (0xF0000U)
#define	SEMC_NANDCR1_REL_SHIFT   (16U)
#define	SEMC_NANDCR1_REL(x)
#define	SEMC_NANDCR1_REH_MASK   (0xF00000U)
#define	SEMC_NANDCR1_REH_SHIFT   (20U)
#define	SEMC_NANDCR1_REH(x)
#define	SEMC_NANDCR1_TA_MASK   (0xF000000U)
#define	SEMC_NANDCR1_TA_SHIFT   (24U)
#define	SEMC_NANDCR1_TA(x)
#define	SEMC_NANDCR1_CEITV_MASK   (0xF0000000U)
#define	SEMC_NANDCR1_CEITV_SHIFT   (28U)
#define	SEMC_NANDCR1_CEITV(x)
NANDCR2 - NAND Control Register 2
#define	SEMC_NANDCR2_TWHR_MASK   (0x3FU)
#define	SEMC_NANDCR2_TWHR_SHIFT   (0U)
#define	SEMC_NANDCR2_TWHR(x)
#define	SEMC_NANDCR2_TRHW_MASK   (0xFC0U)
#define	SEMC_NANDCR2_TRHW_SHIFT   (6U)
#define	SEMC_NANDCR2_TRHW(x)
#define	SEMC_NANDCR2_TADL_MASK   (0x3F000U)
#define	SEMC_NANDCR2_TADL_SHIFT   (12U)
#define	SEMC_NANDCR2_TADL(x)
#define	SEMC_NANDCR2_TRR_MASK   (0xFC0000U)
#define	SEMC_NANDCR2_TRR_SHIFT   (18U)
#define	SEMC_NANDCR2_TRR(x)
#define	SEMC_NANDCR2_TWB_MASK   (0x3F000000U)
#define	SEMC_NANDCR2_TWB_SHIFT   (24U)
#define	SEMC_NANDCR2_TWB(x)
NANDCR3 - NAND Control Register 3
#define	SEMC_NANDCR3_NDOPT1_MASK   (0x1U)
#define	SEMC_NANDCR3_NDOPT1_SHIFT   (0U)
#define	SEMC_NANDCR3_NDOPT1(x)
#define	SEMC_NANDCR3_NDOPT2_MASK   (0x2U)
#define	SEMC_NANDCR3_NDOPT2_SHIFT   (1U)
#define	SEMC_NANDCR3_NDOPT2(x)
#define	SEMC_NANDCR3_NDOPT3_MASK   (0x4U)
#define	SEMC_NANDCR3_NDOPT3_SHIFT   (2U)
#define	SEMC_NANDCR3_NDOPT3(x)
#define	SEMC_NANDCR3_CLE_MASK   (0x8U)
#define	SEMC_NANDCR3_CLE_SHIFT   (3U)
#define	SEMC_NANDCR3_CLE(x)
#define	SEMC_NANDCR3_RDS_MASK   (0xF0000U)
#define	SEMC_NANDCR3_RDS_SHIFT   (16U)
#define	SEMC_NANDCR3_RDS(x)
#define	SEMC_NANDCR3_RDH_MASK   (0xF00000U)
#define	SEMC_NANDCR3_RDH_SHIFT   (20U)
#define	SEMC_NANDCR3_RDH(x)
#define	SEMC_NANDCR3_WDS_MASK   (0xF000000U)
#define	SEMC_NANDCR3_WDS_SHIFT   (24U)
#define	SEMC_NANDCR3_WDS(x)
#define	SEMC_NANDCR3_WDH_MASK   (0xF0000000U)
#define	SEMC_NANDCR3_WDH_SHIFT   (28U)
#define	SEMC_NANDCR3_WDH(x)
NORCR0 - NOR Control Register 0
#define	SEMC_NORCR0_PS_MASK   (0x1U)
#define	SEMC_NORCR0_PS_SHIFT   (0U)
#define	SEMC_NORCR0_PS(x)
#define	SEMC_NORCR0_SYNCEN_MASK   (0x2U)
#define	SEMC_NORCR0_SYNCEN_SHIFT   (1U)
#define	SEMC_NORCR0_SYNCEN(x)
#define	SEMC_NORCR0_BL_MASK   (0x70U)
#define	SEMC_NORCR0_BL_SHIFT   (4U)
#define	SEMC_NORCR0_BL(x)
#define	SEMC_NORCR0_AM_MASK   (0x300U)
#define	SEMC_NORCR0_AM_SHIFT   (8U)
#define	SEMC_NORCR0_AM(x)
#define	SEMC_NORCR0_ADVP_MASK   (0x400U)
#define	SEMC_NORCR0_ADVP_SHIFT   (10U)
#define	SEMC_NORCR0_ADVP(x)
#define	SEMC_NORCR0_ADVH_MASK   (0x800U)
#define	SEMC_NORCR0_ADVH_SHIFT   (11U)
#define	SEMC_NORCR0_ADVH(x)
#define	SEMC_NORCR0_COL_MASK   (0xF000U)
#define	SEMC_NORCR0_COL_SHIFT   (12U)
#define	SEMC_NORCR0_COL(x)
NORCR1 - NOR Control Register 1
#define	SEMC_NORCR1_CES_MASK   (0xFU)
#define	SEMC_NORCR1_CES_SHIFT   (0U)
#define	SEMC_NORCR1_CES(x)
#define	SEMC_NORCR1_CEH_MASK   (0xF0U)
#define	SEMC_NORCR1_CEH_SHIFT   (4U)
#define	SEMC_NORCR1_CEH(x)
#define	SEMC_NORCR1_AS_MASK   (0xF00U)
#define	SEMC_NORCR1_AS_SHIFT   (8U)
#define	SEMC_NORCR1_AS(x)
#define	SEMC_NORCR1_AH_MASK   (0xF000U)
#define	SEMC_NORCR1_AH_SHIFT   (12U)
#define	SEMC_NORCR1_AH(x)
#define	SEMC_NORCR1_WEL_MASK   (0xF0000U)
#define	SEMC_NORCR1_WEL_SHIFT   (16U)
#define	SEMC_NORCR1_WEL(x)
#define	SEMC_NORCR1_WEH_MASK   (0xF00000U)
#define	SEMC_NORCR1_WEH_SHIFT   (20U)
#define	SEMC_NORCR1_WEH(x)
#define	SEMC_NORCR1_REL_MASK   (0xF000000U)
#define	SEMC_NORCR1_REL_SHIFT   (24U)
#define	SEMC_NORCR1_REL(x)
#define	SEMC_NORCR1_REH_MASK   (0xF0000000U)
#define	SEMC_NORCR1_REH_SHIFT   (28U)
#define	SEMC_NORCR1_REH(x)
NORCR2 - NOR Control Register 2
#define	SEMC_NORCR2_TA_MASK   (0xF00U)
#define	SEMC_NORCR2_TA_SHIFT   (8U)
#define	SEMC_NORCR2_TA(x)
#define	SEMC_NORCR2_AWDH_MASK   (0xF000U)
#define	SEMC_NORCR2_AWDH_SHIFT   (12U)
#define	SEMC_NORCR2_AWDH(x)
#define	SEMC_NORCR2_LC_MASK   (0xF0000U)
#define	SEMC_NORCR2_LC_SHIFT   (16U)
#define	SEMC_NORCR2_LC(x)
#define	SEMC_NORCR2_RD_MASK   (0xF00000U)
#define	SEMC_NORCR2_RD_SHIFT   (20U)
#define	SEMC_NORCR2_RD(x)
#define	SEMC_NORCR2_CEITV_MASK   (0xF000000U)
#define	SEMC_NORCR2_CEITV_SHIFT   (24U)
#define	SEMC_NORCR2_CEITV(x)
#define	SEMC_NORCR2_RDH_MASK   (0xF0000000U)
#define	SEMC_NORCR2_RDH_SHIFT   (28U)
#define	SEMC_NORCR2_RDH(x)
NORCR3 - NOR Control Register 3
#define	SEMC_NORCR3_ASSR_MASK   (0xFU)
#define	SEMC_NORCR3_ASSR_SHIFT   (0U)
#define	SEMC_NORCR3_ASSR(x)
#define	SEMC_NORCR3_AHSR_MASK   (0xF0U)
#define	SEMC_NORCR3_AHSR_SHIFT   (4U)
#define	SEMC_NORCR3_AHSR(x)
SRAMCR0 - SRAM Control Register 0
#define	SEMC_SRAMCR0_PS_MASK   (0x1U)
#define	SEMC_SRAMCR0_PS_SHIFT   (0U)
#define	SEMC_SRAMCR0_PS(x)
#define	SEMC_SRAMCR0_SYNCEN_MASK   (0x2U)
#define	SEMC_SRAMCR0_SYNCEN_SHIFT   (1U)
#define	SEMC_SRAMCR0_SYNCEN(x)
#define	SEMC_SRAMCR0_WAITEN_MASK   (0x4U)
#define	SEMC_SRAMCR0_WAITEN_SHIFT   (2U)
#define	SEMC_SRAMCR0_WAITEN(x)
#define	SEMC_SRAMCR0_WAITSP_MASK   (0x8U)
#define	SEMC_SRAMCR0_WAITSP_SHIFT   (3U)
#define	SEMC_SRAMCR0_WAITSP(x)
#define	SEMC_SRAMCR0_BL_MASK   (0x70U)
#define	SEMC_SRAMCR0_BL_SHIFT   (4U)
#define	SEMC_SRAMCR0_BL(x)
#define	SEMC_SRAMCR0_AM_MASK   (0x300U)
#define	SEMC_SRAMCR0_AM_SHIFT   (8U)
#define	SEMC_SRAMCR0_AM(x)
#define	SEMC_SRAMCR0_ADVP_MASK   (0x400U)
#define	SEMC_SRAMCR0_ADVP_SHIFT   (10U)
#define	SEMC_SRAMCR0_ADVP(x)
#define	SEMC_SRAMCR0_ADVH_MASK   (0x800U)
#define	SEMC_SRAMCR0_ADVH_SHIFT   (11U)
#define	SEMC_SRAMCR0_ADVH(x)
#define	SEMC_SRAMCR0_COL_MASK   (0xF000U)
#define	SEMC_SRAMCR0_COL_SHIFT   (12U)
#define	SEMC_SRAMCR0_COL(x)
SRAMCR1 - SRAM Control Register 1
#define	SEMC_SRAMCR1_CES_MASK   (0xFU)
#define	SEMC_SRAMCR1_CES_SHIFT   (0U)
#define	SEMC_SRAMCR1_CES(x)
#define	SEMC_SRAMCR1_CEH_MASK   (0xF0U)
#define	SEMC_SRAMCR1_CEH_SHIFT   (4U)
#define	SEMC_SRAMCR1_CEH(x)
#define	SEMC_SRAMCR1_AS_MASK   (0xF00U)
#define	SEMC_SRAMCR1_AS_SHIFT   (8U)
#define	SEMC_SRAMCR1_AS(x)
#define	SEMC_SRAMCR1_AH_MASK   (0xF000U)
#define	SEMC_SRAMCR1_AH_SHIFT   (12U)
#define	SEMC_SRAMCR1_AH(x)
#define	SEMC_SRAMCR1_WEL_MASK   (0xF0000U)
#define	SEMC_SRAMCR1_WEL_SHIFT   (16U)
#define	SEMC_SRAMCR1_WEL(x)
#define	SEMC_SRAMCR1_WEH_MASK   (0xF00000U)
#define	SEMC_SRAMCR1_WEH_SHIFT   (20U)
#define	SEMC_SRAMCR1_WEH(x)
#define	SEMC_SRAMCR1_REL_MASK   (0xF000000U)
#define	SEMC_SRAMCR1_REL_SHIFT   (24U)
#define	SEMC_SRAMCR1_REL(x)
#define	SEMC_SRAMCR1_REH_MASK   (0xF0000000U)
#define	SEMC_SRAMCR1_REH_SHIFT   (28U)
#define	SEMC_SRAMCR1_REH(x)
SRAMCR2 - SRAM Control Register 2
#define	SEMC_SRAMCR2_WDS_MASK   (0xFU)
#define	SEMC_SRAMCR2_WDS_SHIFT   (0U)
#define	SEMC_SRAMCR2_WDS(x)
#define	SEMC_SRAMCR2_WDH_MASK   (0xF0U)
#define	SEMC_SRAMCR2_WDH_SHIFT   (4U)
#define	SEMC_SRAMCR2_WDH(x)
#define	SEMC_SRAMCR2_TA_MASK   (0xF00U)
#define	SEMC_SRAMCR2_TA_SHIFT   (8U)
#define	SEMC_SRAMCR2_TA(x)
#define	SEMC_SRAMCR2_AWDH_MASK   (0xF000U)
#define	SEMC_SRAMCR2_AWDH_SHIFT   (12U)
#define	SEMC_SRAMCR2_AWDH(x)
#define	SEMC_SRAMCR2_LC_MASK   (0xF0000U)
#define	SEMC_SRAMCR2_LC_SHIFT   (16U)
#define	SEMC_SRAMCR2_LC(x)
#define	SEMC_SRAMCR2_RD_MASK   (0xF00000U)
#define	SEMC_SRAMCR2_RD_SHIFT   (20U)
#define	SEMC_SRAMCR2_RD(x)
#define	SEMC_SRAMCR2_CEITV_MASK   (0xF000000U)
#define	SEMC_SRAMCR2_CEITV_SHIFT   (24U)
#define	SEMC_SRAMCR2_CEITV(x)
#define	SEMC_SRAMCR2_RDH_MASK   (0xF0000000U)
#define	SEMC_SRAMCR2_RDH_SHIFT   (28U)
#define	SEMC_SRAMCR2_RDH(x)
DBICR0 - DBI-B Control Register 0
#define	SEMC_DBICR0_PS_MASK   (0x1U)
#define	SEMC_DBICR0_PS_SHIFT   (0U)
#define	SEMC_DBICR0_PS(x)
#define	SEMC_DBICR0_BL_MASK   (0x70U)
#define	SEMC_DBICR0_BL_SHIFT   (4U)
#define	SEMC_DBICR0_BL(x)
#define	SEMC_DBICR0_COL_MASK   (0xF000U)
#define	SEMC_DBICR0_COL_SHIFT   (12U)
#define	SEMC_DBICR0_COL(x)
DBICR1 - DBI-B Control Register 1
#define	SEMC_DBICR1_CES_MASK   (0xFU)
#define	SEMC_DBICR1_CES_SHIFT   (0U)
#define	SEMC_DBICR1_CES(x)
#define	SEMC_DBICR1_CEH_MASK   (0xF0U)
#define	SEMC_DBICR1_CEH_SHIFT   (4U)
#define	SEMC_DBICR1_CEH(x)
#define	SEMC_DBICR1_WEL_MASK   (0xF00U)
#define	SEMC_DBICR1_WEL_SHIFT   (8U)
#define	SEMC_DBICR1_WEL(x)
#define	SEMC_DBICR1_WEH_MASK   (0xF000U)
#define	SEMC_DBICR1_WEH_SHIFT   (12U)
#define	SEMC_DBICR1_WEH(x)
#define	SEMC_DBICR1_REL_MASK   (0x7F0000U)
#define	SEMC_DBICR1_REL_SHIFT   (16U)
#define	SEMC_DBICR1_REL(x)
#define	SEMC_DBICR1_REH_MASK   (0x7F000000U)
#define	SEMC_DBICR1_REH_SHIFT   (24U)
#define	SEMC_DBICR1_REH(x)
DBICR2 - DBI-B Control Register 2
#define	SEMC_DBICR2_CEITV_MASK   (0xFU)
#define	SEMC_DBICR2_CEITV_SHIFT   (0U)
#define	SEMC_DBICR2_CEITV(x)
IPCR0 - IP Command Control Register 0
#define	SEMC_IPCR0_SA_MASK   (0xFFFFFFFFU)
#define	SEMC_IPCR0_SA_SHIFT   (0U)
#define	SEMC_IPCR0_SA(x)
IPCR1 - IP Command Control Register 1
#define	SEMC_IPCR1_DATSZ_MASK   (0x7U)
#define	SEMC_IPCR1_DATSZ_SHIFT   (0U)
#define	SEMC_IPCR1_DATSZ(x)
#define	SEMC_IPCR1_NAND_EXT_ADDR_MASK   (0xFF00U)
#define	SEMC_IPCR1_NAND_EXT_ADDR_SHIFT   (8U)
#define	SEMC_IPCR1_NAND_EXT_ADDR(x)
IPCR2 - IP Command Control Register 2
#define	SEMC_IPCR2_BM0_MASK   (0x1U)
#define	SEMC_IPCR2_BM0_SHIFT   (0U)
#define	SEMC_IPCR2_BM0(x)
#define	SEMC_IPCR2_BM1_MASK   (0x2U)
#define	SEMC_IPCR2_BM1_SHIFT   (1U)
#define	SEMC_IPCR2_BM1(x)
#define	SEMC_IPCR2_BM2_MASK   (0x4U)
#define	SEMC_IPCR2_BM2_SHIFT   (2U)
#define	SEMC_IPCR2_BM2(x)
#define	SEMC_IPCR2_BM3_MASK   (0x8U)
#define	SEMC_IPCR2_BM3_SHIFT   (3U)
#define	SEMC_IPCR2_BM3(x)
IPTXDAT - TX DATA Register
#define	SEMC_IPTXDAT_DAT_MASK   (0xFFFFFFFFU)
#define	SEMC_IPTXDAT_DAT_SHIFT   (0U)
#define	SEMC_IPTXDAT_DAT(x)
IPRXDAT - RX DATA Register
#define	SEMC_IPRXDAT_DAT_MASK   (0xFFFFFFFFU)
#define	SEMC_IPRXDAT_DAT_SHIFT   (0U)
#define	SEMC_IPRXDAT_DAT(x)
STS12 - Status Register 12
#define	SEMC_STS12_NDADDR_MASK   (0xFFFFFFFFU)
#define	SEMC_STS12_NDADDR_SHIFT   (0U)
#define	SEMC_STS12_NDADDR(x)
STS13 - Status Register 13
#define	SEMC_STS13_SLVLOCK_MASK   (0x1U)
#define	SEMC_STS13_SLVLOCK_SHIFT   (0U)
#define	SEMC_STS13_SLVLOCK(x)
#define	SEMC_STS13_REFLOCK_MASK   (0x2U)
#define	SEMC_STS13_REFLOCK_SHIFT   (1U)
#define	SEMC_STS13_REFLOCK(x)
#define	SEMC_STS13_SLVSEL_MASK   (0xFCU)
#define	SEMC_STS13_SLVSEL_SHIFT   (2U)
#define	SEMC_STS13_SLVSEL(x)
#define	SEMC_STS13_REFSEL_MASK   (0x3F00U)
#define	SEMC_STS13_REFSEL_SHIFT   (8U)
#define	SEMC_STS13_REFSEL(x)
BR9 - Base Register 9
#define	SEMC_BR9_VLD_MASK   (0x1U)
#define	SEMC_BR9_VLD_SHIFT   (0U)
#define	SEMC_BR9_VLD(x)
#define	SEMC_BR9_MS_MASK   (0x3EU)
#define	SEMC_BR9_MS_SHIFT   (1U)
#define	SEMC_BR9_MS(x)
#define	SEMC_BR9_BA_MASK   (0xFFFFF000U)
#define	SEMC_BR9_BA_SHIFT   (12U)
#define	SEMC_BR9_BA(x)
BR10 - Base Register 10
#define	SEMC_BR10_VLD_MASK   (0x1U)
#define	SEMC_BR10_VLD_SHIFT   (0U)
#define	SEMC_BR10_VLD(x)
#define	SEMC_BR10_MS_MASK   (0x3EU)
#define	SEMC_BR10_MS_SHIFT   (1U)
#define	SEMC_BR10_MS(x)
#define	SEMC_BR10_BA_MASK   (0xFFFFF000U)
#define	SEMC_BR10_BA_SHIFT   (12U)
#define	SEMC_BR10_BA(x)
BR11 - Base Register 11
#define	SEMC_BR11_VLD_MASK   (0x1U)
#define	SEMC_BR11_VLD_SHIFT   (0U)
#define	SEMC_BR11_VLD(x)
#define	SEMC_BR11_MS_MASK   (0x3EU)
#define	SEMC_BR11_MS_SHIFT   (1U)
#define	SEMC_BR11_MS(x)
#define	SEMC_BR11_BA_MASK   (0xFFFFF000U)
#define	SEMC_BR11_BA_SHIFT   (12U)
#define	SEMC_BR11_BA(x)
SRAMCR4 - SRAM Control Register 4
#define	SEMC_SRAMCR4_PS_MASK   (0x1U)
#define	SEMC_SRAMCR4_PS_SHIFT   (0U)
#define	SEMC_SRAMCR4_PS(x)
#define	SEMC_SRAMCR4_SYNCEN_MASK   (0x2U)
#define	SEMC_SRAMCR4_SYNCEN_SHIFT   (1U)
#define	SEMC_SRAMCR4_SYNCEN(x)
#define	SEMC_SRAMCR4_WAITEN_MASK   (0x4U)
#define	SEMC_SRAMCR4_WAITEN_SHIFT   (2U)
#define	SEMC_SRAMCR4_WAITEN(x)
#define	SEMC_SRAMCR4_WAITSP_MASK   (0x8U)
#define	SEMC_SRAMCR4_WAITSP_SHIFT   (3U)
#define	SEMC_SRAMCR4_WAITSP(x)
#define	SEMC_SRAMCR4_BL_MASK   (0x70U)
#define	SEMC_SRAMCR4_BL_SHIFT   (4U)
#define	SEMC_SRAMCR4_BL(x)
#define	SEMC_SRAMCR4_AM_MASK   (0x300U)
#define	SEMC_SRAMCR4_AM_SHIFT   (8U)
#define	SEMC_SRAMCR4_AM(x)
#define	SEMC_SRAMCR4_ADVP_MASK   (0x400U)
#define	SEMC_SRAMCR4_ADVP_SHIFT   (10U)
#define	SEMC_SRAMCR4_ADVP(x)
#define	SEMC_SRAMCR4_ADVH_MASK   (0x800U)
#define	SEMC_SRAMCR4_ADVH_SHIFT   (11U)
#define	SEMC_SRAMCR4_ADVH(x)
#define	SEMC_SRAMCR4_COL_MASK   (0xF000U)
#define	SEMC_SRAMCR4_COL_SHIFT   (12U)
#define	SEMC_SRAMCR4_COL(x)
SRAMCR5 - SRAM Control Register 5
#define	SEMC_SRAMCR5_CES_MASK   (0xFU)
#define	SEMC_SRAMCR5_CES_SHIFT   (0U)
#define	SEMC_SRAMCR5_CES(x)
#define	SEMC_SRAMCR5_CEH_MASK   (0xF0U)
#define	SEMC_SRAMCR5_CEH_SHIFT   (4U)
#define	SEMC_SRAMCR5_CEH(x)
#define	SEMC_SRAMCR5_AS_MASK   (0xF00U)
#define	SEMC_SRAMCR5_AS_SHIFT   (8U)
#define	SEMC_SRAMCR5_AS(x)
#define	SEMC_SRAMCR5_AH_MASK   (0xF000U)
#define	SEMC_SRAMCR5_AH_SHIFT   (12U)
#define	SEMC_SRAMCR5_AH(x)
#define	SEMC_SRAMCR5_WEL_MASK   (0xF0000U)
#define	SEMC_SRAMCR5_WEL_SHIFT   (16U)
#define	SEMC_SRAMCR5_WEL(x)
#define	SEMC_SRAMCR5_WEH_MASK   (0xF00000U)
#define	SEMC_SRAMCR5_WEH_SHIFT   (20U)
#define	SEMC_SRAMCR5_WEH(x)
#define	SEMC_SRAMCR5_REL_MASK   (0xF000000U)
#define	SEMC_SRAMCR5_REL_SHIFT   (24U)
#define	SEMC_SRAMCR5_REL(x)
#define	SEMC_SRAMCR5_REH_MASK   (0xF0000000U)
#define	SEMC_SRAMCR5_REH_SHIFT   (28U)
#define	SEMC_SRAMCR5_REH(x)
SRAMCR6 - SRAM Control Register 6
#define	SEMC_SRAMCR6_WDS_MASK   (0xFU)
#define	SEMC_SRAMCR6_WDS_SHIFT   (0U)
#define	SEMC_SRAMCR6_WDS(x)
#define	SEMC_SRAMCR6_WDH_MASK   (0xF0U)
#define	SEMC_SRAMCR6_WDH_SHIFT   (4U)
#define	SEMC_SRAMCR6_WDH(x)
#define	SEMC_SRAMCR6_TA_MASK   (0xF00U)
#define	SEMC_SRAMCR6_TA_SHIFT   (8U)
#define	SEMC_SRAMCR6_TA(x)
#define	SEMC_SRAMCR6_AWDH_MASK   (0xF000U)
#define	SEMC_SRAMCR6_AWDH_SHIFT   (12U)
#define	SEMC_SRAMCR6_AWDH(x)
#define	SEMC_SRAMCR6_LC_MASK   (0xF0000U)
#define	SEMC_SRAMCR6_LC_SHIFT   (16U)
#define	SEMC_SRAMCR6_LC(x)
#define	SEMC_SRAMCR6_RD_MASK   (0xF00000U)
#define	SEMC_SRAMCR6_RD_SHIFT   (20U)
#define	SEMC_SRAMCR6_RD(x)
#define	SEMC_SRAMCR6_CEITV_MASK   (0xF000000U)
#define	SEMC_SRAMCR6_CEITV_SHIFT   (24U)
#define	SEMC_SRAMCR6_CEITV(x)
#define	SEMC_SRAMCR6_RDH_MASK   (0xF0000000U)
#define	SEMC_SRAMCR6_RDH_SHIFT   (28U)
#define	SEMC_SRAMCR6_RDH(x)
DCCR - Delay Chain Control Register
#define	SEMC_DCCR_SDRAMEN_MASK   (0x1U)
#define	SEMC_DCCR_SDRAMEN_SHIFT   (0U)
#define	SEMC_DCCR_SDRAMEN(x)
#define	SEMC_DCCR_SDRAMVAL_MASK   (0x3EU)
#define	SEMC_DCCR_SDRAMVAL_SHIFT   (1U)
#define	SEMC_DCCR_SDRAMVAL(x)
#define	SEMC_DCCR_NOREN_MASK   (0x100U)
#define	SEMC_DCCR_NOREN_SHIFT   (8U)
#define	SEMC_DCCR_NOREN(x)
#define	SEMC_DCCR_NORVAL_MASK   (0x3E00U)
#define	SEMC_DCCR_NORVAL_SHIFT   (9U)
#define	SEMC_DCCR_NORVAL(x)
#define	SEMC_DCCR_SRAM0EN_MASK   (0x10000U)
#define	SEMC_DCCR_SRAM0EN_SHIFT   (16U)
#define	SEMC_DCCR_SRAM0EN(x)
#define	SEMC_DCCR_SRAM0VAL_MASK   (0x3E0000U)
#define	SEMC_DCCR_SRAM0VAL_SHIFT   (17U)
#define	SEMC_DCCR_SRAM0VAL(x)
#define	SEMC_DCCR_SRAMXEN_MASK   (0x1000000U)
#define	SEMC_DCCR_SRAMXEN_SHIFT   (24U)
#define	SEMC_DCCR_SRAMXEN(x)
#define	SEMC_DCCR_SRAMXVAL_MASK   (0x3E000000U)
#define	SEMC_DCCR_SRAMXVAL_SHIFT   (25U)
#define	SEMC_DCCR_SRAMXVAL(x)
HPLR - SNVS_HP Lock Register
#define	SNVS_HPLR_ZMK_WSL_MASK   (0x1U)
#define	SNVS_HPLR_ZMK_WSL_SHIFT   (0U)
#define	SNVS_HPLR_ZMK_WSL(x)
#define	SNVS_HPLR_ZMK_RSL_MASK   (0x2U)
#define	SNVS_HPLR_ZMK_RSL_SHIFT   (1U)
#define	SNVS_HPLR_ZMK_RSL(x)
#define	SNVS_HPLR_SRTC_SL_MASK   (0x4U)
#define	SNVS_HPLR_SRTC_SL_SHIFT   (2U)
#define	SNVS_HPLR_SRTC_SL(x)
#define	SNVS_HPLR_LPCALB_SL_MASK   (0x8U)
#define	SNVS_HPLR_LPCALB_SL_SHIFT   (3U)
#define	SNVS_HPLR_LPCALB_SL(x)
#define	SNVS_HPLR_MC_SL_MASK   (0x10U)
#define	SNVS_HPLR_MC_SL_SHIFT   (4U)
#define	SNVS_HPLR_MC_SL(x)
#define	SNVS_HPLR_GPR_SL_MASK   (0x20U)
#define	SNVS_HPLR_GPR_SL_SHIFT   (5U)
#define	SNVS_HPLR_GPR_SL(x)
#define	SNVS_HPLR_LPSVCR_SL_MASK   (0x40U)
#define	SNVS_HPLR_LPSVCR_SL_SHIFT   (6U)
#define	SNVS_HPLR_LPSVCR_SL(x)
#define	SNVS_HPLR_LPTGFCR_SL_MASK   (0x80U)
#define	SNVS_HPLR_LPTGFCR_SL_SHIFT   (7U)
#define	SNVS_HPLR_LPTGFCR_SL(x)
#define	SNVS_HPLR_LPSECR_SL_MASK   (0x100U)
#define	SNVS_HPLR_LPSECR_SL_SHIFT   (8U)
#define	SNVS_HPLR_LPSECR_SL(x)
#define	SNVS_HPLR_MKS_SL_MASK   (0x200U)
#define	SNVS_HPLR_MKS_SL_SHIFT   (9U)
#define	SNVS_HPLR_MKS_SL(x)
#define	SNVS_HPLR_HPSVCR_L_MASK   (0x10000U)
#define	SNVS_HPLR_HPSVCR_L_SHIFT   (16U)
#define	SNVS_HPLR_HPSVCR_L(x)
#define	SNVS_HPLR_HPSICR_L_MASK   (0x20000U)
#define	SNVS_HPLR_HPSICR_L_SHIFT   (17U)
#define	SNVS_HPLR_HPSICR_L(x)
#define	SNVS_HPLR_HAC_L_MASK   (0x40000U)
#define	SNVS_HPLR_HAC_L_SHIFT   (18U)
#define	SNVS_HPLR_HAC_L(x)
#define	SNVS_HPLR_AT1_SL_MASK   (0x1000000U)
#define	SNVS_HPLR_AT1_SL_SHIFT   (24U)
#define	SNVS_HPLR_AT1_SL(x)
#define	SNVS_HPLR_AT2_SL_MASK   (0x2000000U)
#define	SNVS_HPLR_AT2_SL_SHIFT   (25U)
#define	SNVS_HPLR_AT2_SL(x)
#define	SNVS_HPLR_AT3_SL_MASK   (0x4000000U)
#define	SNVS_HPLR_AT3_SL_SHIFT   (26U)
#define	SNVS_HPLR_AT3_SL(x)
#define	SNVS_HPLR_AT4_SL_MASK   (0x8000000U)
#define	SNVS_HPLR_AT4_SL_SHIFT   (27U)
#define	SNVS_HPLR_AT4_SL(x)
#define	SNVS_HPLR_AT5_SL_MASK   (0x10000000U)
#define	SNVS_HPLR_AT5_SL_SHIFT   (28U)
#define	SNVS_HPLR_AT5_SL(x)
HPCOMR - SNVS_HP Command Register
#define	SNVS_HPCOMR_SSM_ST_MASK   (0x1U)
#define	SNVS_HPCOMR_SSM_ST_SHIFT   (0U)
#define	SNVS_HPCOMR_SSM_ST(x)
#define	SNVS_HPCOMR_SSM_ST_DIS_MASK   (0x2U)
#define	SNVS_HPCOMR_SSM_ST_DIS_SHIFT   (1U)
#define	SNVS_HPCOMR_SSM_ST_DIS(x)
#define	SNVS_HPCOMR_SSM_SFNS_DIS_MASK   (0x4U)
#define	SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT   (2U)
#define	SNVS_HPCOMR_SSM_SFNS_DIS(x)
#define	SNVS_HPCOMR_LP_SWR_MASK   (0x10U)
#define	SNVS_HPCOMR_LP_SWR_SHIFT   (4U)
#define	SNVS_HPCOMR_LP_SWR(x)
#define	SNVS_HPCOMR_LP_SWR_DIS_MASK   (0x20U)
#define	SNVS_HPCOMR_LP_SWR_DIS_SHIFT   (5U)
#define	SNVS_HPCOMR_LP_SWR_DIS(x)
#define	SNVS_HPCOMR_SW_SV_MASK   (0x100U)
#define	SNVS_HPCOMR_SW_SV_SHIFT   (8U)
#define	SNVS_HPCOMR_SW_SV(x)
#define	SNVS_HPCOMR_SW_FSV_MASK   (0x200U)
#define	SNVS_HPCOMR_SW_FSV_SHIFT   (9U)
#define	SNVS_HPCOMR_SW_FSV(x)
#define	SNVS_HPCOMR_SW_LPSV_MASK   (0x400U)
#define	SNVS_HPCOMR_SW_LPSV_SHIFT   (10U)
#define	SNVS_HPCOMR_SW_LPSV(x)
#define	SNVS_HPCOMR_PROG_ZMK_MASK   (0x1000U)
#define	SNVS_HPCOMR_PROG_ZMK_SHIFT   (12U)
#define	SNVS_HPCOMR_PROG_ZMK(x)
#define	SNVS_HPCOMR_MKS_EN_MASK   (0x2000U)
#define	SNVS_HPCOMR_MKS_EN_SHIFT   (13U)
#define	SNVS_HPCOMR_MKS_EN(x)
#define	SNVS_HPCOMR_HAC_EN_MASK   (0x10000U)
#define	SNVS_HPCOMR_HAC_EN_SHIFT   (16U)
#define	SNVS_HPCOMR_HAC_EN(x)
#define	SNVS_HPCOMR_HAC_LOAD_MASK   (0x20000U)
#define	SNVS_HPCOMR_HAC_LOAD_SHIFT   (17U)
#define	SNVS_HPCOMR_HAC_LOAD(x)
#define	SNVS_HPCOMR_HAC_CLEAR_MASK   (0x40000U)
#define	SNVS_HPCOMR_HAC_CLEAR_SHIFT   (18U)
#define	SNVS_HPCOMR_HAC_CLEAR(x)
#define	SNVS_HPCOMR_HAC_STOP_MASK   (0x80000U)
#define	SNVS_HPCOMR_HAC_STOP_SHIFT   (19U)
#define	SNVS_HPCOMR_HAC_STOP(x)
#define	SNVS_HPCOMR_NPSWA_EN_MASK   (0x80000000U)
#define	SNVS_HPCOMR_NPSWA_EN_SHIFT   (31U)
#define	SNVS_HPCOMR_NPSWA_EN(x)
HPCR - SNVS_HP Control Register
#define	SNVS_HPCR_RTC_EN_MASK   (0x1U)
#define	SNVS_HPCR_RTC_EN_SHIFT   (0U)
#define	SNVS_HPCR_RTC_EN(x)
#define	SNVS_HPCR_HPTA_EN_MASK   (0x2U)
#define	SNVS_HPCR_HPTA_EN_SHIFT   (1U)
#define	SNVS_HPCR_HPTA_EN(x)
#define	SNVS_HPCR_DIS_PI_MASK   (0x4U)
#define	SNVS_HPCR_DIS_PI_SHIFT   (2U)
#define	SNVS_HPCR_DIS_PI(x)
#define	SNVS_HPCR_PI_EN_MASK   (0x8U)
#define	SNVS_HPCR_PI_EN_SHIFT   (3U)
#define	SNVS_HPCR_PI_EN(x)
#define	SNVS_HPCR_PI_FREQ_MASK   (0xF0U)
#define	SNVS_HPCR_PI_FREQ_SHIFT   (4U)
#define	SNVS_HPCR_PI_FREQ(x)
#define	SNVS_HPCR_HPCALB_EN_MASK   (0x100U)
#define	SNVS_HPCR_HPCALB_EN_SHIFT   (8U)
#define	SNVS_HPCR_HPCALB_EN(x)
#define	SNVS_HPCR_HPCALB_VAL_MASK   (0x7C00U)
#define	SNVS_HPCR_HPCALB_VAL_SHIFT   (10U)
#define	SNVS_HPCR_HPCALB_VAL(x)
#define	SNVS_HPCR_HP_TS_MASK   (0x10000U)
#define	SNVS_HPCR_HP_TS_SHIFT   (16U)
#define	SNVS_HPCR_HP_TS(x)
#define	SNVS_HPCR_BTN_CONFIG_MASK   (0x7000000U)
#define	SNVS_HPCR_BTN_CONFIG_SHIFT   (24U)
#define	SNVS_HPCR_BTN_CONFIG(x)
#define	SNVS_HPCR_BTN_MASK_MASK   (0x8000000U)
#define	SNVS_HPCR_BTN_MASK_SHIFT   (27U)
#define	SNVS_HPCR_BTN_MASK(x)
HPSICR - SNVS_HP Security Interrupt Control Register
#define	SNVS_HPSICR_CAAM_EN_MASK   (0x1U)
#define	SNVS_HPSICR_CAAM_EN_SHIFT   (0U)
#define	SNVS_HPSICR_CAAM_EN(x)
#define	SNVS_HPSICR_JTAGC_EN_MASK   (0x2U)
#define	SNVS_HPSICR_JTAGC_EN_SHIFT   (1U)
#define	SNVS_HPSICR_JTAGC_EN(x)
#define	SNVS_HPSICR_WDOG2_EN_MASK   (0x4U)
#define	SNVS_HPSICR_WDOG2_EN_SHIFT   (2U)
#define	SNVS_HPSICR_WDOG2_EN(x)
#define	SNVS_HPSICR_SRC_EN_MASK   (0x10U)
#define	SNVS_HPSICR_SRC_EN_SHIFT   (4U)
#define	SNVS_HPSICR_SRC_EN(x)
#define	SNVS_HPSICR_OCOTP_EN_MASK   (0x20U)
#define	SNVS_HPSICR_OCOTP_EN_SHIFT   (5U)
#define	SNVS_HPSICR_OCOTP_EN(x)
#define	SNVS_HPSICR_LPSVI_EN_MASK   (0x80000000U)
#define	SNVS_HPSICR_LPSVI_EN_SHIFT   (31U)
#define	SNVS_HPSICR_LPSVI_EN(x)
HPSVCR - SNVS_HP Security Violation Control Register
#define	SNVS_HPSVCR_CAAM_CFG_MASK   (0x1U)
#define	SNVS_HPSVCR_CAAM_CFG_SHIFT   (0U)
#define	SNVS_HPSVCR_CAAM_CFG(x)
#define	SNVS_HPSVCR_JTAGC_CFG_MASK   (0x2U)
#define	SNVS_HPSVCR_JTAGC_CFG_SHIFT   (1U)
#define	SNVS_HPSVCR_JTAGC_CFG(x)
#define	SNVS_HPSVCR_WDOG2_CFG_MASK   (0x4U)
#define	SNVS_HPSVCR_WDOG2_CFG_SHIFT   (2U)
#define	SNVS_HPSVCR_WDOG2_CFG(x)
#define	SNVS_HPSVCR_SRC_CFG_MASK   (0x10U)
#define	SNVS_HPSVCR_SRC_CFG_SHIFT   (4U)
#define	SNVS_HPSVCR_SRC_CFG(x)
#define	SNVS_HPSVCR_OCOTP_CFG_MASK   (0x60U)
#define	SNVS_HPSVCR_OCOTP_CFG_SHIFT   (5U)
#define	SNVS_HPSVCR_OCOTP_CFG(x)
#define	SNVS_HPSVCR_LPSV_CFG_MASK   (0xC0000000U)
#define	SNVS_HPSVCR_LPSV_CFG_SHIFT   (30U)
#define	SNVS_HPSVCR_LPSV_CFG(x)
HPSR - SNVS_HP Status Register
#define	SNVS_HPSR_HPTA_MASK   (0x1U)
#define	SNVS_HPSR_HPTA_SHIFT   (0U)
#define	SNVS_HPSR_HPTA(x)
#define	SNVS_HPSR_PI_MASK   (0x2U)
#define	SNVS_HPSR_PI_SHIFT   (1U)
#define	SNVS_HPSR_PI(x)
#define	SNVS_HPSR_LPDIS_MASK   (0x10U)
#define	SNVS_HPSR_LPDIS_SHIFT   (4U)
#define	SNVS_HPSR_LPDIS(x)
#define	SNVS_HPSR_BTN_MASK   (0x40U)
#define	SNVS_HPSR_BTN_SHIFT   (6U)
#define	SNVS_HPSR_BTN(x)
#define	SNVS_HPSR_BI_MASK   (0x80U)
#define	SNVS_HPSR_BI_SHIFT   (7U)
#define	SNVS_HPSR_BI(x)
#define	SNVS_HPSR_SSM_STATE_MASK   (0xF00U)
#define	SNVS_HPSR_SSM_STATE_SHIFT   (8U)
#define	SNVS_HPSR_SSM_STATE(x)
#define	SNVS_HPSR_SYS_SECURITY_CFG_MASK   (0x7000U)
#define	SNVS_HPSR_SYS_SECURITY_CFG_SHIFT   (12U)
#define	SNVS_HPSR_SYS_SECURITY_CFG(x)
#define	SNVS_HPSR_SYS_SECURE_BOOT_MASK   (0x8000U)
#define	SNVS_HPSR_SYS_SECURE_BOOT_SHIFT   (15U)
#define	SNVS_HPSR_SYS_SECURE_BOOT(x)
#define	SNVS_HPSR_OTPMK_ZERO_MASK   (0x8000000U)
#define	SNVS_HPSR_OTPMK_ZERO_SHIFT   (27U)
#define	SNVS_HPSR_OTPMK_ZERO(x)
#define	SNVS_HPSR_ZMK_ZERO_MASK   (0x80000000U)
#define	SNVS_HPSR_ZMK_ZERO_SHIFT   (31U)
#define	SNVS_HPSR_ZMK_ZERO(x)
HPSVSR - SNVS_HP Security Violation Status Register
#define	SNVS_HPSVSR_CAAM_MASK   (0x1U)
#define	SNVS_HPSVSR_CAAM_SHIFT   (0U)
#define	SNVS_HPSVSR_CAAM(x)
#define	SNVS_HPSVSR_JTAGC_MASK   (0x2U)
#define	SNVS_HPSVSR_JTAGC_SHIFT   (1U)
#define	SNVS_HPSVSR_JTAGC(x)
#define	SNVS_HPSVSR_WDOG2_MASK   (0x4U)
#define	SNVS_HPSVSR_WDOG2_SHIFT   (2U)
#define	SNVS_HPSVSR_WDOG2(x)
#define	SNVS_HPSVSR_SRC_MASK   (0x10U)
#define	SNVS_HPSVSR_SRC_SHIFT   (4U)
#define	SNVS_HPSVSR_SRC(x)
#define	SNVS_HPSVSR_OCOTP_MASK   (0x20U)
#define	SNVS_HPSVSR_OCOTP_SHIFT   (5U)
#define	SNVS_HPSVSR_OCOTP(x)
#define	SNVS_HPSVSR_SW_SV_MASK   (0x2000U)
#define	SNVS_HPSVSR_SW_SV_SHIFT   (13U)
#define	SNVS_HPSVSR_SW_SV(x)
#define	SNVS_HPSVSR_SW_FSV_MASK   (0x4000U)
#define	SNVS_HPSVSR_SW_FSV_SHIFT   (14U)
#define	SNVS_HPSVSR_SW_FSV(x)
#define	SNVS_HPSVSR_SW_LPSV_MASK   (0x8000U)
#define	SNVS_HPSVSR_SW_LPSV_SHIFT   (15U)
#define	SNVS_HPSVSR_SW_LPSV(x)
#define	SNVS_HPSVSR_ZMK_SYNDROME_MASK   (0x1FF0000U)
#define	SNVS_HPSVSR_ZMK_SYNDROME_SHIFT   (16U)
#define	SNVS_HPSVSR_ZMK_SYNDROME(x)
#define	SNVS_HPSVSR_ZMK_ECC_FAIL_MASK   (0x8000000U)
#define	SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT   (27U)
#define	SNVS_HPSVSR_ZMK_ECC_FAIL(x)
#define	SNVS_HPSVSR_LP_SEC_VIO_MASK   (0x80000000U)
#define	SNVS_HPSVSR_LP_SEC_VIO_SHIFT   (31U)
#define	SNVS_HPSVSR_LP_SEC_VIO(x)
HPHACIVR - SNVS_HP High Assurance Counter IV Register
#define	SNVS_HPHACIVR_HAC_COUNTER_IV_MASK   (0xFFFFFFFFU)
#define	SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT   (0U)
#define	SNVS_HPHACIVR_HAC_COUNTER_IV(x)
HPHACR - SNVS_HP High Assurance Counter Register
#define	SNVS_HPHACR_HAC_COUNTER_MASK   (0xFFFFFFFFU)
#define	SNVS_HPHACR_HAC_COUNTER_SHIFT   (0U)
#define	SNVS_HPHACR_HAC_COUNTER(x)
HPRTCMR - SNVS_HP Real Time Counter MSB Register
#define	SNVS_HPRTCMR_RTC_MASK   (0x7FFFU)
#define	SNVS_HPRTCMR_RTC_SHIFT   (0U)
#define	SNVS_HPRTCMR_RTC(x)
HPRTCLR - SNVS_HP Real Time Counter LSB Register
#define	SNVS_HPRTCLR_RTC_MASK   (0xFFFFFFFFU)
#define	SNVS_HPRTCLR_RTC_SHIFT   (0U)
#define	SNVS_HPRTCLR_RTC(x)
HPTAMR - SNVS_HP Time Alarm MSB Register
#define	SNVS_HPTAMR_HPTA_MS_MASK   (0x7FFFU)
#define	SNVS_HPTAMR_HPTA_MS_SHIFT   (0U)
#define	SNVS_HPTAMR_HPTA_MS(x)
HPTALR - SNVS_HP Time Alarm LSB Register
#define	SNVS_HPTALR_HPTA_LS_MASK   (0xFFFFFFFFU)
#define	SNVS_HPTALR_HPTA_LS_SHIFT   (0U)
#define	SNVS_HPTALR_HPTA_LS(x)
LPLR - SNVS_LP Lock Register
#define	SNVS_LPLR_ZMK_WHL_MASK   (0x1U)
#define	SNVS_LPLR_ZMK_WHL_SHIFT   (0U)
#define	SNVS_LPLR_ZMK_WHL(x)
#define	SNVS_LPLR_ZMK_RHL_MASK   (0x2U)
#define	SNVS_LPLR_ZMK_RHL_SHIFT   (1U)
#define	SNVS_LPLR_ZMK_RHL(x)
#define	SNVS_LPLR_SRTC_HL_MASK   (0x4U)
#define	SNVS_LPLR_SRTC_HL_SHIFT   (2U)
#define	SNVS_LPLR_SRTC_HL(x)
#define	SNVS_LPLR_LPCALB_HL_MASK   (0x8U)
#define	SNVS_LPLR_LPCALB_HL_SHIFT   (3U)
#define	SNVS_LPLR_LPCALB_HL(x)
#define	SNVS_LPLR_MC_HL_MASK   (0x10U)
#define	SNVS_LPLR_MC_HL_SHIFT   (4U)
#define	SNVS_LPLR_MC_HL(x)
#define	SNVS_LPLR_GPR_HL_MASK   (0x20U)
#define	SNVS_LPLR_GPR_HL_SHIFT   (5U)
#define	SNVS_LPLR_GPR_HL(x)
#define	SNVS_LPLR_LPSVCR_HL_MASK   (0x40U)
#define	SNVS_LPLR_LPSVCR_HL_SHIFT   (6U)
#define	SNVS_LPLR_LPSVCR_HL(x)
#define	SNVS_LPLR_LPTGFCR_HL_MASK   (0x80U)
#define	SNVS_LPLR_LPTGFCR_HL_SHIFT   (7U)
#define	SNVS_LPLR_LPTGFCR_HL(x)
#define	SNVS_LPLR_LPSECR_HL_MASK   (0x100U)
#define	SNVS_LPLR_LPSECR_HL_SHIFT   (8U)
#define	SNVS_LPLR_LPSECR_HL(x)
#define	SNVS_LPLR_MKS_HL_MASK   (0x200U)
#define	SNVS_LPLR_MKS_HL_SHIFT   (9U)
#define	SNVS_LPLR_MKS_HL(x)
#define	SNVS_LPLR_AT1_HL_MASK   (0x1000000U)
#define	SNVS_LPLR_AT1_HL_SHIFT   (24U)
#define	SNVS_LPLR_AT1_HL(x)
#define	SNVS_LPLR_AT2_HL_MASK   (0x2000000U)
#define	SNVS_LPLR_AT2_HL_SHIFT   (25U)
#define	SNVS_LPLR_AT2_HL(x)
#define	SNVS_LPLR_AT3_HL_MASK   (0x4000000U)
#define	SNVS_LPLR_AT3_HL_SHIFT   (26U)
#define	SNVS_LPLR_AT3_HL(x)
#define	SNVS_LPLR_AT4_HL_MASK   (0x8000000U)
#define	SNVS_LPLR_AT4_HL_SHIFT   (27U)
#define	SNVS_LPLR_AT4_HL(x)
#define	SNVS_LPLR_AT5_HL_MASK   (0x10000000U)
#define	SNVS_LPLR_AT5_HL_SHIFT   (28U)
#define	SNVS_LPLR_AT5_HL(x)
LPCR - SNVS_LP Control Register
#define	SNVS_LPCR_SRTC_ENV_MASK   (0x1U)
#define	SNVS_LPCR_SRTC_ENV_SHIFT   (0U)
#define	SNVS_LPCR_SRTC_ENV(x)
#define	SNVS_LPCR_LPTA_EN_MASK   (0x2U)
#define	SNVS_LPCR_LPTA_EN_SHIFT   (1U)
#define	SNVS_LPCR_LPTA_EN(x)
#define	SNVS_LPCR_MC_ENV_MASK   (0x4U)
#define	SNVS_LPCR_MC_ENV_SHIFT   (2U)
#define	SNVS_LPCR_MC_ENV(x)
#define	SNVS_LPCR_LPWUI_EN_MASK   (0x8U)
#define	SNVS_LPCR_LPWUI_EN_SHIFT   (3U)
#define	SNVS_LPCR_LPWUI_EN(x)
#define	SNVS_LPCR_SRTC_INV_EN_MASK   (0x10U)
#define	SNVS_LPCR_SRTC_INV_EN_SHIFT   (4U)
#define	SNVS_LPCR_SRTC_INV_EN(x)
#define	SNVS_LPCR_DP_EN_MASK   (0x20U)
#define	SNVS_LPCR_DP_EN_SHIFT   (5U)
#define	SNVS_LPCR_DP_EN(x)
#define	SNVS_LPCR_TOP_MASK   (0x40U)
#define	SNVS_LPCR_TOP_SHIFT   (6U)
#define	SNVS_LPCR_TOP(x)
#define	SNVS_LPCR_LVD_EN_MASK   (0x80U)
#define	SNVS_LPCR_LVD_EN_SHIFT   (7U)
#define	SNVS_LPCR_LVD_EN(x)
#define	SNVS_LPCR_LPCALB_EN_MASK   (0x100U)
#define	SNVS_LPCR_LPCALB_EN_SHIFT   (8U)
#define	SNVS_LPCR_LPCALB_EN(x)
#define	SNVS_LPCR_LPCALB_VAL_MASK   (0x7C00U)
#define	SNVS_LPCR_LPCALB_VAL_SHIFT   (10U)
#define	SNVS_LPCR_LPCALB_VAL(x)
#define	SNVS_LPCR_BTN_PRESS_TIME_MASK   (0x30000U)
#define	SNVS_LPCR_BTN_PRESS_TIME_SHIFT   (16U)
#define	SNVS_LPCR_BTN_PRESS_TIME(x)
#define	SNVS_LPCR_DEBOUNCE_MASK   (0xC0000U)
#define	SNVS_LPCR_DEBOUNCE_SHIFT   (18U)
#define	SNVS_LPCR_DEBOUNCE(x)
#define	SNVS_LPCR_ON_TIME_MASK   (0x300000U)
#define	SNVS_LPCR_ON_TIME_SHIFT   (20U)
#define	SNVS_LPCR_ON_TIME(x)
#define	SNVS_LPCR_PK_EN_MASK   (0x400000U)
#define	SNVS_LPCR_PK_EN_SHIFT   (22U)
#define	SNVS_LPCR_PK_EN(x)
#define	SNVS_LPCR_PK_OVERRIDE_MASK   (0x800000U)
#define	SNVS_LPCR_PK_OVERRIDE_SHIFT   (23U)
#define	SNVS_LPCR_PK_OVERRIDE(x)
#define	SNVS_LPCR_GPR_Z_DIS_MASK   (0x1000000U)
#define	SNVS_LPCR_GPR_Z_DIS_SHIFT   (24U)
#define	SNVS_LPCR_GPR_Z_DIS(x)
LPMKCR - SNVS_LP Master Key Control Register
#define	SNVS_LPMKCR_MASTER_KEY_SEL_MASK   (0x3U)
#define	SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT   (0U)
#define	SNVS_LPMKCR_MASTER_KEY_SEL(x)
#define	SNVS_LPMKCR_ZMK_HWP_MASK   (0x4U)
#define	SNVS_LPMKCR_ZMK_HWP_SHIFT   (2U)
#define	SNVS_LPMKCR_ZMK_HWP(x)
#define	SNVS_LPMKCR_ZMK_VAL_MASK   (0x8U)
#define	SNVS_LPMKCR_ZMK_VAL_SHIFT   (3U)
#define	SNVS_LPMKCR_ZMK_VAL(x)
#define	SNVS_LPMKCR_ZMK_ECC_EN_MASK   (0x10U)
#define	SNVS_LPMKCR_ZMK_ECC_EN_SHIFT   (4U)
#define	SNVS_LPMKCR_ZMK_ECC_EN(x)
#define	SNVS_LPMKCR_ZMK_ECC_VALUE_MASK   (0xFF80U)
#define	SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT   (7U)
#define	SNVS_LPMKCR_ZMK_ECC_VALUE(x)
LPSVCR - SNVS_LP Security Violation Control Register
#define	SNVS_LPSVCR_CAAM_EN_MASK   (0x1U)
#define	SNVS_LPSVCR_CAAM_EN_SHIFT   (0U)
#define	SNVS_LPSVCR_CAAM_EN(x)
#define	SNVS_LPSVCR_JTAGC_EN_MASK   (0x2U)
#define	SNVS_LPSVCR_JTAGC_EN_SHIFT   (1U)
#define	SNVS_LPSVCR_JTAGC_EN(x)
#define	SNVS_LPSVCR_WDOG2_EN_MASK   (0x4U)
#define	SNVS_LPSVCR_WDOG2_EN_SHIFT   (2U)
#define	SNVS_LPSVCR_WDOG2_EN(x)
#define	SNVS_LPSVCR_SRC_EN_MASK   (0x10U)
#define	SNVS_LPSVCR_SRC_EN_SHIFT   (4U)
#define	SNVS_LPSVCR_SRC_EN(x)
#define	SNVS_LPSVCR_OCOTP_EN_MASK   (0x20U)
#define	SNVS_LPSVCR_OCOTP_EN_SHIFT   (5U)
#define	SNVS_LPSVCR_OCOTP_EN(x)
LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register
#define	SNVS_LPTGFCR_WMTGF_MASK   (0x1FU)
#define	SNVS_LPTGFCR_WMTGF_SHIFT   (0U)
#define	SNVS_LPTGFCR_WMTGF(x)
#define	SNVS_LPTGFCR_WMTGF_EN_MASK   (0x80U)
#define	SNVS_LPTGFCR_WMTGF_EN_SHIFT   (7U)
#define	SNVS_LPTGFCR_WMTGF_EN(x)
#define	SNVS_LPTGFCR_ETGF1_MASK   (0x7F0000U)
#define	SNVS_LPTGFCR_ETGF1_SHIFT   (16U)
#define	SNVS_LPTGFCR_ETGF1(x)
#define	SNVS_LPTGFCR_ETGF1_EN_MASK   (0x800000U)
#define	SNVS_LPTGFCR_ETGF1_EN_SHIFT   (23U)
#define	SNVS_LPTGFCR_ETGF1_EN(x)
#define	SNVS_LPTGFCR_ETGF2_MASK   (0x7F000000U)
#define	SNVS_LPTGFCR_ETGF2_SHIFT   (24U)
#define	SNVS_LPTGFCR_ETGF2(x)
#define	SNVS_LPTGFCR_ETGF2_EN_MASK   (0x80000000U)
#define	SNVS_LPTGFCR_ETGF2_EN_SHIFT   (31U)
#define	SNVS_LPTGFCR_ETGF2_EN(x)
LPTDCR - SNVS_LP Tamper Detect Configuration Register
#define	SNVS_LPTDCR_SRTCR_EN_MASK   (0x2U)
#define	SNVS_LPTDCR_SRTCR_EN_SHIFT   (1U)
#define	SNVS_LPTDCR_SRTCR_EN(x)
#define	SNVS_LPTDCR_MCR_EN_MASK   (0x4U)
#define	SNVS_LPTDCR_MCR_EN_SHIFT   (2U)
#define	SNVS_LPTDCR_MCR_EN(x)
#define	SNVS_LPTDCR_CT_EN_MASK   (0x10U)
#define	SNVS_LPTDCR_CT_EN_SHIFT   (4U)
#define	SNVS_LPTDCR_CT_EN(x)
#define	SNVS_LPTDCR_TT_EN_MASK   (0x20U)
#define	SNVS_LPTDCR_TT_EN_SHIFT   (5U)
#define	SNVS_LPTDCR_TT_EN(x)
#define	SNVS_LPTDCR_VT_EN_MASK   (0x40U)
#define	SNVS_LPTDCR_VT_EN_SHIFT   (6U)
#define	SNVS_LPTDCR_VT_EN(x)
#define	SNVS_LPTDCR_WMT1_EN_MASK   (0x80U)
#define	SNVS_LPTDCR_WMT1_EN_SHIFT   (7U)
#define	SNVS_LPTDCR_WMT1_EN(x)
#define	SNVS_LPTDCR_WMT2_EN_MASK   (0x100U)
#define	SNVS_LPTDCR_WMT2_EN_SHIFT   (8U)
#define	SNVS_LPTDCR_WMT2_EN(x)
#define	SNVS_LPTDCR_ET1_EN_MASK   (0x200U)
#define	SNVS_LPTDCR_ET1_EN_SHIFT   (9U)
#define	SNVS_LPTDCR_ET1_EN(x)
#define	SNVS_LPTDCR_ET2_EN_MASK   (0x400U)
#define	SNVS_LPTDCR_ET2_EN_SHIFT   (10U)
#define	SNVS_LPTDCR_ET2_EN(x)
#define	SNVS_LPTDCR_ET1P_MASK   (0x800U)
#define	SNVS_LPTDCR_ET1P_SHIFT   (11U)
#define	SNVS_LPTDCR_ET1P(x)
#define	SNVS_LPTDCR_ET2P_MASK   (0x1000U)
#define	SNVS_LPTDCR_ET2P_SHIFT   (12U)
#define	SNVS_LPTDCR_ET2P(x)
#define	SNVS_LPTDCR_PFD_OBSERV_MASK   (0x4000U)
#define	SNVS_LPTDCR_PFD_OBSERV_SHIFT   (14U)
#define	SNVS_LPTDCR_PFD_OBSERV(x)
#define	SNVS_LPTDCR_POR_OBSERV_MASK   (0x8000U)
#define	SNVS_LPTDCR_POR_OBSERV_SHIFT   (15U)
#define	SNVS_LPTDCR_POR_OBSERV(x)
#define	SNVS_LPTDCR_LTDC_MASK   (0x70000U)
#define	SNVS_LPTDCR_LTDC_SHIFT   (16U)
#define	SNVS_LPTDCR_LTDC(x)
#define	SNVS_LPTDCR_HTDC_MASK   (0x700000U)
#define	SNVS_LPTDCR_HTDC_SHIFT   (20U)
#define	SNVS_LPTDCR_HTDC(x)
#define	SNVS_LPTDCR_VRC_MASK   (0x7000000U)
#define	SNVS_LPTDCR_VRC_SHIFT   (24U)
#define	SNVS_LPTDCR_VRC(x)
#define	SNVS_LPTDCR_OSCB_MASK   (0x10000000U)
#define	SNVS_LPTDCR_OSCB_SHIFT   (28U)
#define	SNVS_LPTDCR_OSCB(x)
LPSR - SNVS_LP Status Register
#define	SNVS_LPSR_LPTA_MASK   (0x1U)
#define	SNVS_LPSR_LPTA_SHIFT   (0U)
#define	SNVS_LPSR_LPTA(x)
#define	SNVS_LPSR_SRTCR_MASK   (0x2U)
#define	SNVS_LPSR_SRTCR_SHIFT   (1U)
#define	SNVS_LPSR_SRTCR(x)
#define	SNVS_LPSR_MCR_MASK   (0x4U)
#define	SNVS_LPSR_MCR_SHIFT   (2U)
#define	SNVS_LPSR_MCR(x)
#define	SNVS_LPSR_LVD_MASK   (0x8U)
#define	SNVS_LPSR_LVD_SHIFT   (3U)
#define	SNVS_LPSR_LVD(x)
#define	SNVS_LPSR_CTD_MASK   (0x10U)
#define	SNVS_LPSR_CTD_SHIFT   (4U)
#define	SNVS_LPSR_CTD(x)
#define	SNVS_LPSR_TTD_MASK   (0x20U)
#define	SNVS_LPSR_TTD_SHIFT   (5U)
#define	SNVS_LPSR_TTD(x)
#define	SNVS_LPSR_VTD_MASK   (0x40U)
#define	SNVS_LPSR_VTD_SHIFT   (6U)
#define	SNVS_LPSR_VTD(x)
#define	SNVS_LPSR_WMT1D_MASK   (0x80U)
#define	SNVS_LPSR_WMT1D_SHIFT   (7U)
#define	SNVS_LPSR_WMT1D(x)
#define	SNVS_LPSR_WMT2D_MASK   (0x100U)
#define	SNVS_LPSR_WMT2D_SHIFT   (8U)
#define	SNVS_LPSR_WMT2D(x)
#define	SNVS_LPSR_ET1D_MASK   (0x200U)
#define	SNVS_LPSR_ET1D_SHIFT   (9U)
#define	SNVS_LPSR_ET1D(x)
#define	SNVS_LPSR_ET2D_MASK   (0x400U)
#define	SNVS_LPSR_ET2D_SHIFT   (10U)
#define	SNVS_LPSR_ET2D(x)
#define	SNVS_LPSR_ESVD_MASK   (0x10000U)
#define	SNVS_LPSR_ESVD_SHIFT   (16U)
#define	SNVS_LPSR_ESVD(x)
#define	SNVS_LPSR_EO_MASK   (0x20000U)
#define	SNVS_LPSR_EO_SHIFT   (17U)
#define	SNVS_LPSR_EO(x)
#define	SNVS_LPSR_SPOF_MASK   (0x40000U)
#define	SNVS_LPSR_SPOF_SHIFT   (18U)
#define	SNVS_LPSR_SPOF(x)
#define	SNVS_LPSR_LPNS_MASK   (0x40000000U)
#define	SNVS_LPSR_LPNS_SHIFT   (30U)
#define	SNVS_LPSR_LPNS(x)
#define	SNVS_LPSR_LPS_MASK   (0x80000000U)
#define	SNVS_LPSR_LPS_SHIFT   (31U)
#define	SNVS_LPSR_LPS(x)
LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register
#define	SNVS_LPSRTCMR_SRTC_MASK   (0x7FFFU)
#define	SNVS_LPSRTCMR_SRTC_SHIFT   (0U)
#define	SNVS_LPSRTCMR_SRTC(x)
LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register
#define	SNVS_LPSRTCLR_SRTC_MASK   (0xFFFFFFFFU)
#define	SNVS_LPSRTCLR_SRTC_SHIFT   (0U)
#define	SNVS_LPSRTCLR_SRTC(x)
LPTAR - SNVS_LP Time Alarm Register
#define	SNVS_LPTAR_LPTA_MASK   (0xFFFFFFFFU)
#define	SNVS_LPTAR_LPTA_SHIFT   (0U)
#define	SNVS_LPTAR_LPTA(x)
LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register
#define	SNVS_LPSMCMR_MON_COUNTER_MASK   (0xFFFFU)
#define	SNVS_LPSMCMR_MON_COUNTER_SHIFT   (0U)
#define	SNVS_LPSMCMR_MON_COUNTER(x)
#define	SNVS_LPSMCMR_MC_ERA_BITS_MASK   (0xFFFF0000U)
#define	SNVS_LPSMCMR_MC_ERA_BITS_SHIFT   (16U)
#define	SNVS_LPSMCMR_MC_ERA_BITS(x)
LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register
#define	SNVS_LPSMCLR_MON_COUNTER_MASK   (0xFFFFFFFFU)
#define	SNVS_LPSMCLR_MON_COUNTER_SHIFT   (0U)
#define	SNVS_LPSMCLR_MON_COUNTER(x)
LPLVDR - SNVS_LP Digital Low-Voltage Detector Register
#define	SNVS_LPLVDR_LVD_MASK   (0xFFFFFFFFU)
#define	SNVS_LPLVDR_LVD_SHIFT   (0U)
#define	SNVS_LPLVDR_LVD(x)
LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)
#define	SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK   (0xFFFFFFFFU)
#define	SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT   (0U)
#define	SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)
LPZMKR - SNVS_LP Zeroizable Master Key Register
#define	SNVS_LPZMKR_ZMK_MASK   (0xFFFFFFFFU)
#define	SNVS_LPZMKR_ZMK_SHIFT   (0U)
#define	SNVS_LPZMKR_ZMK(x)
LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3
#define	SNVS_LPGPR_ALIAS_GPR_MASK   (0xFFFFFFFFU)
#define	SNVS_LPGPR_ALIAS_GPR_SHIFT   (0U)
#define	SNVS_LPGPR_ALIAS_GPR(x)
LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register
#define	SNVS_LPTDC2R_ET3_EN_MASK   (0x1U)
#define	SNVS_LPTDC2R_ET3_EN_SHIFT   (0U)
#define	SNVS_LPTDC2R_ET3_EN(x)
#define	SNVS_LPTDC2R_ET4_EN_MASK   (0x2U)
#define	SNVS_LPTDC2R_ET4_EN_SHIFT   (1U)
#define	SNVS_LPTDC2R_ET4_EN(x)
#define	SNVS_LPTDC2R_ET5_EN_MASK   (0x4U)
#define	SNVS_LPTDC2R_ET5_EN_SHIFT   (2U)
#define	SNVS_LPTDC2R_ET5_EN(x)
#define	SNVS_LPTDC2R_ET6_EN_MASK   (0x8U)
#define	SNVS_LPTDC2R_ET6_EN_SHIFT   (3U)
#define	SNVS_LPTDC2R_ET6_EN(x)
#define	SNVS_LPTDC2R_ET7_EN_MASK   (0x10U)
#define	SNVS_LPTDC2R_ET7_EN_SHIFT   (4U)
#define	SNVS_LPTDC2R_ET7_EN(x)
#define	SNVS_LPTDC2R_ET8_EN_MASK   (0x20U)
#define	SNVS_LPTDC2R_ET8_EN_SHIFT   (5U)
#define	SNVS_LPTDC2R_ET8_EN(x)
#define	SNVS_LPTDC2R_ET9_EN_MASK   (0x40U)
#define	SNVS_LPTDC2R_ET9_EN_SHIFT   (6U)
#define	SNVS_LPTDC2R_ET9_EN(x)
#define	SNVS_LPTDC2R_ET10_EN_MASK   (0x80U)
#define	SNVS_LPTDC2R_ET10_EN_SHIFT   (7U)
#define	SNVS_LPTDC2R_ET10_EN(x)
#define	SNVS_LPTDC2R_ET3P_MASK   (0x10000U)
#define	SNVS_LPTDC2R_ET3P_SHIFT   (16U)
#define	SNVS_LPTDC2R_ET3P(x)
#define	SNVS_LPTDC2R_ET4P_MASK   (0x20000U)
#define	SNVS_LPTDC2R_ET4P_SHIFT   (17U)
#define	SNVS_LPTDC2R_ET4P(x)
#define	SNVS_LPTDC2R_ET5P_MASK   (0x40000U)
#define	SNVS_LPTDC2R_ET5P_SHIFT   (18U)
#define	SNVS_LPTDC2R_ET5P(x)
#define	SNVS_LPTDC2R_ET6P_MASK   (0x80000U)
#define	SNVS_LPTDC2R_ET6P_SHIFT   (19U)
#define	SNVS_LPTDC2R_ET6P(x)
#define	SNVS_LPTDC2R_ET7P_MASK   (0x100000U)
#define	SNVS_LPTDC2R_ET7P_SHIFT   (20U)
#define	SNVS_LPTDC2R_ET7P(x)
#define	SNVS_LPTDC2R_ET8P_MASK   (0x200000U)
#define	SNVS_LPTDC2R_ET8P_SHIFT   (21U)
#define	SNVS_LPTDC2R_ET8P(x)
#define	SNVS_LPTDC2R_ET9P_MASK   (0x400000U)
#define	SNVS_LPTDC2R_ET9P_SHIFT   (22U)
#define	SNVS_LPTDC2R_ET9P(x)
#define	SNVS_LPTDC2R_ET10P_MASK   (0x800000U)
#define	SNVS_LPTDC2R_ET10P_SHIFT   (23U)
#define	SNVS_LPTDC2R_ET10P(x)
LPTDSR - SNVS_LP Tamper Detectors Status Register
#define	SNVS_LPTDSR_ET3D_MASK   (0x1U)
#define	SNVS_LPTDSR_ET3D_SHIFT   (0U)
#define	SNVS_LPTDSR_ET3D(x)
#define	SNVS_LPTDSR_ET4D_MASK   (0x2U)
#define	SNVS_LPTDSR_ET4D_SHIFT   (1U)
#define	SNVS_LPTDSR_ET4D(x)
#define	SNVS_LPTDSR_ET5D_MASK   (0x4U)
#define	SNVS_LPTDSR_ET5D_SHIFT   (2U)
#define	SNVS_LPTDSR_ET5D(x)
#define	SNVS_LPTDSR_ET6D_MASK   (0x8U)
#define	SNVS_LPTDSR_ET6D_SHIFT   (3U)
#define	SNVS_LPTDSR_ET6D(x)
#define	SNVS_LPTDSR_ET7D_MASK   (0x10U)
#define	SNVS_LPTDSR_ET7D_SHIFT   (4U)
#define	SNVS_LPTDSR_ET7D(x)
#define	SNVS_LPTDSR_ET8D_MASK   (0x20U)
#define	SNVS_LPTDSR_ET8D_SHIFT   (5U)
#define	SNVS_LPTDSR_ET8D(x)
#define	SNVS_LPTDSR_ET9D_MASK   (0x40U)
#define	SNVS_LPTDSR_ET9D_SHIFT   (6U)
#define	SNVS_LPTDSR_ET9D(x)
#define	SNVS_LPTDSR_ET10D_MASK   (0x80U)
#define	SNVS_LPTDSR_ET10D_SHIFT   (7U)
#define	SNVS_LPTDSR_ET10D(x)
LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register
#define	SNVS_LPTGF1CR_ETGF3_MASK   (0x7FU)
#define	SNVS_LPTGF1CR_ETGF3_SHIFT   (0U)
#define	SNVS_LPTGF1CR_ETGF3(x)
#define	SNVS_LPTGF1CR_ETGF3_EN_MASK   (0x80U)
#define	SNVS_LPTGF1CR_ETGF3_EN_SHIFT   (7U)
#define	SNVS_LPTGF1CR_ETGF3_EN(x)
#define	SNVS_LPTGF1CR_ETGF4_MASK   (0x7F00U)
#define	SNVS_LPTGF1CR_ETGF4_SHIFT   (8U)
#define	SNVS_LPTGF1CR_ETGF4(x)
#define	SNVS_LPTGF1CR_ETGF4_EN_MASK   (0x8000U)
#define	SNVS_LPTGF1CR_ETGF4_EN_SHIFT   (15U)
#define	SNVS_LPTGF1CR_ETGF4_EN(x)
#define	SNVS_LPTGF1CR_ETGF5_MASK   (0x7F0000U)
#define	SNVS_LPTGF1CR_ETGF5_SHIFT   (16U)
#define	SNVS_LPTGF1CR_ETGF5(x)
#define	SNVS_LPTGF1CR_ETGF5_EN_MASK   (0x800000U)
#define	SNVS_LPTGF1CR_ETGF5_EN_SHIFT   (23U)
#define	SNVS_LPTGF1CR_ETGF5_EN(x)
#define	SNVS_LPTGF1CR_ETGF6_MASK   (0x7F000000U)
#define	SNVS_LPTGF1CR_ETGF6_SHIFT   (24U)
#define	SNVS_LPTGF1CR_ETGF6(x)
#define	SNVS_LPTGF1CR_ETGF6_EN_MASK   (0x80000000U)
#define	SNVS_LPTGF1CR_ETGF6_EN_SHIFT   (31U)
#define	SNVS_LPTGF1CR_ETGF6_EN(x)
LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register
#define	SNVS_LPTGF2CR_ETGF7_MASK   (0x7FU)
#define	SNVS_LPTGF2CR_ETGF7_SHIFT   (0U)
#define	SNVS_LPTGF2CR_ETGF7(x)
#define	SNVS_LPTGF2CR_ETGF7_EN_MASK   (0x80U)
#define	SNVS_LPTGF2CR_ETGF7_EN_SHIFT   (7U)
#define	SNVS_LPTGF2CR_ETGF7_EN(x)
#define	SNVS_LPTGF2CR_ETGF8_MASK   (0x7F00U)
#define	SNVS_LPTGF2CR_ETGF8_SHIFT   (8U)
#define	SNVS_LPTGF2CR_ETGF8(x)
#define	SNVS_LPTGF2CR_ETGF8_EN_MASK   (0x8000U)
#define	SNVS_LPTGF2CR_ETGF8_EN_SHIFT   (15U)
#define	SNVS_LPTGF2CR_ETGF8_EN(x)
#define	SNVS_LPTGF2CR_ETGF9_MASK   (0x7F0000U)
#define	SNVS_LPTGF2CR_ETGF9_SHIFT   (16U)
#define	SNVS_LPTGF2CR_ETGF9(x)
#define	SNVS_LPTGF2CR_ETGF9_EN_MASK   (0x800000U)
#define	SNVS_LPTGF2CR_ETGF9_EN_SHIFT   (23U)
#define	SNVS_LPTGF2CR_ETGF9_EN(x)
#define	SNVS_LPTGF2CR_ETGF10_MASK   (0x7F000000U)
#define	SNVS_LPTGF2CR_ETGF10_SHIFT   (24U)
#define	SNVS_LPTGF2CR_ETGF10(x)
#define	SNVS_LPTGF2CR_ETGF10_EN_MASK   (0x80000000U)
#define	SNVS_LPTGF2CR_ETGF10_EN_SHIFT   (31U)
#define	SNVS_LPTGF2CR_ETGF10_EN(x)
LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register
#define	SNVS_LPATCR_Seed_MASK   (0xFFFFU)
#define	SNVS_LPATCR_Seed_SHIFT   (0U)
#define	SNVS_LPATCR_Seed(x)
#define	SNVS_LPATCR_Polynomial_MASK   (0xFFFF0000U)
#define	SNVS_LPATCR_Polynomial_SHIFT   (16U)
#define	SNVS_LPATCR_Polynomial(x)
LPATCTLR - SNVS_LP Active Tamper Control Register
#define	SNVS_LPATCTLR_AT1_EN_MASK   (0x1U)
#define	SNVS_LPATCTLR_AT1_EN_SHIFT   (0U)
#define	SNVS_LPATCTLR_AT1_EN(x)
#define	SNVS_LPATCTLR_AT2_EN_MASK   (0x2U)
#define	SNVS_LPATCTLR_AT2_EN_SHIFT   (1U)
#define	SNVS_LPATCTLR_AT2_EN(x)
#define	SNVS_LPATCTLR_AT3_EN_MASK   (0x4U)
#define	SNVS_LPATCTLR_AT3_EN_SHIFT   (2U)
#define	SNVS_LPATCTLR_AT3_EN(x)
#define	SNVS_LPATCTLR_AT4_EN_MASK   (0x8U)
#define	SNVS_LPATCTLR_AT4_EN_SHIFT   (3U)
#define	SNVS_LPATCTLR_AT4_EN(x)
#define	SNVS_LPATCTLR_AT5_EN_MASK   (0x10U)
#define	SNVS_LPATCTLR_AT5_EN_SHIFT   (4U)
#define	SNVS_LPATCTLR_AT5_EN(x)
#define	SNVS_LPATCTLR_AT1_PAD_EN_MASK   (0x10000U)
#define	SNVS_LPATCTLR_AT1_PAD_EN_SHIFT   (16U)
#define	SNVS_LPATCTLR_AT1_PAD_EN(x)
#define	SNVS_LPATCTLR_AT2_PAD_EN_MASK   (0x20000U)
#define	SNVS_LPATCTLR_AT2_PAD_EN_SHIFT   (17U)
#define	SNVS_LPATCTLR_AT2_PAD_EN(x)
#define	SNVS_LPATCTLR_AT3_PAD_EN_MASK   (0x40000U)
#define	SNVS_LPATCTLR_AT3_PAD_EN_SHIFT   (18U)
#define	SNVS_LPATCTLR_AT3_PAD_EN(x)
#define	SNVS_LPATCTLR_AT4_PAD_EN_MASK   (0x80000U)
#define	SNVS_LPATCTLR_AT4_PAD_EN_SHIFT   (19U)
#define	SNVS_LPATCTLR_AT4_PAD_EN(x)
#define	SNVS_LPATCTLR_AT5_PAD_EN_MASK   (0x100000U)
#define	SNVS_LPATCTLR_AT5_PAD_EN_SHIFT   (20U)
#define	SNVS_LPATCTLR_AT5_PAD_EN(x)
LPATCLKR - SNVS_LP Active Tamper Clock Control Register
#define	SNVS_LPATCLKR_AT1_CLK_CTL_MASK   (0x3U)
#define	SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT   (0U)
#define	SNVS_LPATCLKR_AT1_CLK_CTL(x)
#define	SNVS_LPATCLKR_AT2_CLK_CTL_MASK   (0x30U)
#define	SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT   (4U)
#define	SNVS_LPATCLKR_AT2_CLK_CTL(x)
#define	SNVS_LPATCLKR_AT3_CLK_CTL_MASK   (0x300U)
#define	SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT   (8U)
#define	SNVS_LPATCLKR_AT3_CLK_CTL(x)
#define	SNVS_LPATCLKR_AT4_CLK_CTL_MASK   (0x3000U)
#define	SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT   (12U)
#define	SNVS_LPATCLKR_AT4_CLK_CTL(x)
#define	SNVS_LPATCLKR_AT5_CLK_CTL_MASK   (0x30000U)
#define	SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT   (16U)
#define	SNVS_LPATCLKR_AT5_CLK_CTL(x)
LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register
#define	SNVS_LPATRC1R_ET1RCTL_MASK   (0x7U)
#define	SNVS_LPATRC1R_ET1RCTL_SHIFT   (0U)
#define	SNVS_LPATRC1R_ET1RCTL(x)
#define	SNVS_LPATRC1R_ET2RCTL_MASK   (0x70U)
#define	SNVS_LPATRC1R_ET2RCTL_SHIFT   (4U)
#define	SNVS_LPATRC1R_ET2RCTL(x)
#define	SNVS_LPATRC1R_ET3RCTL_MASK   (0x700U)
#define	SNVS_LPATRC1R_ET3RCTL_SHIFT   (8U)
#define	SNVS_LPATRC1R_ET3RCTL(x)
#define	SNVS_LPATRC1R_ET4RCTL_MASK   (0x7000U)
#define	SNVS_LPATRC1R_ET4RCTL_SHIFT   (12U)
#define	SNVS_LPATRC1R_ET4RCTL(x)
#define	SNVS_LPATRC1R_ET5RCTL_MASK   (0x70000U)
#define	SNVS_LPATRC1R_ET5RCTL_SHIFT   (16U)
#define	SNVS_LPATRC1R_ET5RCTL(x)
#define	SNVS_LPATRC1R_ET6RCTL_MASK   (0x700000U)
#define	SNVS_LPATRC1R_ET6RCTL_SHIFT   (20U)
#define	SNVS_LPATRC1R_ET6RCTL(x)
#define	SNVS_LPATRC1R_ET7RCTL_MASK   (0x7000000U)
#define	SNVS_LPATRC1R_ET7RCTL_SHIFT   (24U)
#define	SNVS_LPATRC1R_ET7RCTL(x)
#define	SNVS_LPATRC1R_ET8RCTL_MASK   (0x70000000U)
#define	SNVS_LPATRC1R_ET8RCTL_SHIFT   (28U)
#define	SNVS_LPATRC1R_ET8RCTL(x)
LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register
#define	SNVS_LPATRC2R_ET9RCTL_MASK   (0x7U)
#define	SNVS_LPATRC2R_ET9RCTL_SHIFT   (0U)
#define	SNVS_LPATRC2R_ET9RCTL(x)
#define	SNVS_LPATRC2R_ET10RCTL_MASK   (0x70U)
#define	SNVS_LPATRC2R_ET10RCTL_SHIFT   (4U)
#define	SNVS_LPATRC2R_ET10RCTL(x)
LPGPR - SNVS_LP General Purpose Registers 0 .. 3
#define	SNVS_LPGPR_GPR_MASK   (0xFFFFFFFFU)
#define	SNVS_LPGPR_GPR_SHIFT   (0U)
#define	SNVS_LPGPR_GPR(x)
HPVIDR1 - SNVS_HP Version ID Register 1
#define	SNVS_HPVIDR1_MINOR_REV_MASK   (0xFFU)
#define	SNVS_HPVIDR1_MINOR_REV_SHIFT   (0U)
#define	SNVS_HPVIDR1_MINOR_REV(x)
#define	SNVS_HPVIDR1_MAJOR_REV_MASK   (0xFF00U)
#define	SNVS_HPVIDR1_MAJOR_REV_SHIFT   (8U)
#define	SNVS_HPVIDR1_MAJOR_REV(x)
#define	SNVS_HPVIDR1_IP_ID_MASK   (0xFFFF0000U)
#define	SNVS_HPVIDR1_IP_ID_SHIFT   (16U)
#define	SNVS_HPVIDR1_IP_ID(x)
HPVIDR2 - SNVS_HP Version ID Register 2
#define	SNVS_HPVIDR2_ECO_REV_MASK   (0xFF00U)
#define	SNVS_HPVIDR2_ECO_REV_SHIFT   (8U)
#define	SNVS_HPVIDR2_ECO_REV(x)
#define	SNVS_HPVIDR2_IP_ERA_MASK   (0xFF000000U)
#define	SNVS_HPVIDR2_IP_ERA_SHIFT   (24U)
#define	SNVS_HPVIDR2_IP_ERA(x)
SCR - SPDIF Configuration Register
#define	SPDIF_SCR_USRC_SEL_MASK   (0x3U)
#define	SPDIF_SCR_USRC_SEL_SHIFT   (0U)
#define	SPDIF_SCR_USRC_SEL(x)
#define	SPDIF_SCR_TXSEL_MASK   (0x1CU)
#define	SPDIF_SCR_TXSEL_SHIFT   (2U)
#define	SPDIF_SCR_TXSEL(x)
#define	SPDIF_SCR_VALCTRL_MASK   (0x20U)
#define	SPDIF_SCR_VALCTRL_SHIFT   (5U)
#define	SPDIF_SCR_VALCTRL(x)
#define	SPDIF_SCR_INPUTSRCSEL_MASK   (0xC0U)
#define	SPDIF_SCR_INPUTSRCSEL_SHIFT   (6U)
#define	SPDIF_SCR_INPUTSRCSEL(x)
#define	SPDIF_SCR_DMA_TX_EN_MASK   (0x100U)
#define	SPDIF_SCR_DMA_TX_EN_SHIFT   (8U)
#define	SPDIF_SCR_DMA_TX_EN(x)
#define	SPDIF_SCR_DMA_RX_EN_MASK   (0x200U)
#define	SPDIF_SCR_DMA_RX_EN_SHIFT   (9U)
#define	SPDIF_SCR_DMA_RX_EN(x)
#define	SPDIF_SCR_TXFIFO_CTRL_MASK   (0xC00U)
#define	SPDIF_SCR_TXFIFO_CTRL_SHIFT   (10U)
#define	SPDIF_SCR_TXFIFO_CTRL(x)
#define	SPDIF_SCR_SOFT_RESET_MASK   (0x1000U)
#define	SPDIF_SCR_SOFT_RESET_SHIFT   (12U)
#define	SPDIF_SCR_SOFT_RESET(x)
#define	SPDIF_SCR_LOW_POWER_MASK   (0x2000U)
#define	SPDIF_SCR_LOW_POWER_SHIFT   (13U)
#define	SPDIF_SCR_LOW_POWER(x)
#define	SPDIF_SCR_TXFIFOEMPTY_SEL_MASK   (0x18000U)
#define	SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT   (15U)
#define	SPDIF_SCR_TXFIFOEMPTY_SEL(x)
#define	SPDIF_SCR_TXAUTOSYNC_MASK   (0x20000U)
#define	SPDIF_SCR_TXAUTOSYNC_SHIFT   (17U)
#define	SPDIF_SCR_TXAUTOSYNC(x)
#define	SPDIF_SCR_RXAUTOSYNC_MASK   (0x40000U)
#define	SPDIF_SCR_RXAUTOSYNC_SHIFT   (18U)
#define	SPDIF_SCR_RXAUTOSYNC(x)
#define	SPDIF_SCR_RXFIFOFULL_SEL_MASK   (0x180000U)
#define	SPDIF_SCR_RXFIFOFULL_SEL_SHIFT   (19U)
#define	SPDIF_SCR_RXFIFOFULL_SEL(x)
#define	SPDIF_SCR_RXFIFO_RST_MASK   (0x200000U)
#define	SPDIF_SCR_RXFIFO_RST_SHIFT   (21U)
#define	SPDIF_SCR_RXFIFO_RST(x)
#define	SPDIF_SCR_RXFIFO_OFF_ON_MASK   (0x400000U)
#define	SPDIF_SCR_RXFIFO_OFF_ON_SHIFT   (22U)
#define	SPDIF_SCR_RXFIFO_OFF_ON(x)
#define	SPDIF_SCR_RXFIFO_CTRL_MASK   (0x800000U)
#define	SPDIF_SCR_RXFIFO_CTRL_SHIFT   (23U)
#define	SPDIF_SCR_RXFIFO_CTRL(x)
SRCD - CDText Control Register
#define	SPDIF_SRCD_USYNCMODE_MASK   (0x2U)
#define	SPDIF_SRCD_USYNCMODE_SHIFT   (1U)
#define	SPDIF_SRCD_USYNCMODE(x)
SRPC - PhaseConfig Register
#define	SPDIF_SRPC_GAINSEL_MASK   (0x38U)
#define	SPDIF_SRPC_GAINSEL_SHIFT   (3U)
#define	SPDIF_SRPC_GAINSEL(x)
#define	SPDIF_SRPC_LOCK_MASK   (0x40U)
#define	SPDIF_SRPC_LOCK_SHIFT   (6U)
#define	SPDIF_SRPC_LOCK(x)
#define	SPDIF_SRPC_CLKSRC_SEL_MASK   (0x780U)
#define	SPDIF_SRPC_CLKSRC_SEL_SHIFT   (7U)
#define	SPDIF_SRPC_CLKSRC_SEL(x)
SIE - InterruptEn Register
#define	SPDIF_SIE_RXFIFOFUL_MASK   (0x1U)
#define	SPDIF_SIE_RXFIFOFUL_SHIFT   (0U)
#define	SPDIF_SIE_RXFIFOFUL(x)
#define	SPDIF_SIE_TXEM_MASK   (0x2U)
#define	SPDIF_SIE_TXEM_SHIFT   (1U)
#define	SPDIF_SIE_TXEM(x)
#define	SPDIF_SIE_LOCKLOSS_MASK   (0x4U)
#define	SPDIF_SIE_LOCKLOSS_SHIFT   (2U)
#define	SPDIF_SIE_LOCKLOSS(x)
#define	SPDIF_SIE_RXFIFORESYN_MASK   (0x8U)
#define	SPDIF_SIE_RXFIFORESYN_SHIFT   (3U)
#define	SPDIF_SIE_RXFIFORESYN(x)
#define	SPDIF_SIE_RXFIFOUNOV_MASK   (0x10U)
#define	SPDIF_SIE_RXFIFOUNOV_SHIFT   (4U)
#define	SPDIF_SIE_RXFIFOUNOV(x)
#define	SPDIF_SIE_UQERR_MASK   (0x20U)
#define	SPDIF_SIE_UQERR_SHIFT   (5U)
#define	SPDIF_SIE_UQERR(x)
#define	SPDIF_SIE_UQSYNC_MASK   (0x40U)
#define	SPDIF_SIE_UQSYNC_SHIFT   (6U)
#define	SPDIF_SIE_UQSYNC(x)
#define	SPDIF_SIE_QRXOV_MASK   (0x80U)
#define	SPDIF_SIE_QRXOV_SHIFT   (7U)
#define	SPDIF_SIE_QRXOV(x)
#define	SPDIF_SIE_QRXFUL_MASK   (0x100U)
#define	SPDIF_SIE_QRXFUL_SHIFT   (8U)
#define	SPDIF_SIE_QRXFUL(x)
#define	SPDIF_SIE_URXOV_MASK   (0x200U)
#define	SPDIF_SIE_URXOV_SHIFT   (9U)
#define	SPDIF_SIE_URXOV(x)
#define	SPDIF_SIE_URXFUL_MASK   (0x400U)
#define	SPDIF_SIE_URXFUL_SHIFT   (10U)
#define	SPDIF_SIE_URXFUL(x)
#define	SPDIF_SIE_BITERR_MASK   (0x4000U)
#define	SPDIF_SIE_BITERR_SHIFT   (14U)
#define	SPDIF_SIE_BITERR(x)
#define	SPDIF_SIE_SYMERR_MASK   (0x8000U)
#define	SPDIF_SIE_SYMERR_SHIFT   (15U)
#define	SPDIF_SIE_SYMERR(x)
#define	SPDIF_SIE_VALNOGOOD_MASK   (0x10000U)
#define	SPDIF_SIE_VALNOGOOD_SHIFT   (16U)
#define	SPDIF_SIE_VALNOGOOD(x)
#define	SPDIF_SIE_CNEW_MASK   (0x20000U)
#define	SPDIF_SIE_CNEW_SHIFT   (17U)
#define	SPDIF_SIE_CNEW(x)
#define	SPDIF_SIE_TXRESYN_MASK   (0x40000U)
#define	SPDIF_SIE_TXRESYN_SHIFT   (18U)
#define	SPDIF_SIE_TXRESYN(x)
#define	SPDIF_SIE_TXUNOV_MASK   (0x80000U)
#define	SPDIF_SIE_TXUNOV_SHIFT   (19U)
#define	SPDIF_SIE_TXUNOV(x)
#define	SPDIF_SIE_LOCK_MASK   (0x100000U)
#define	SPDIF_SIE_LOCK_SHIFT   (20U)
#define	SPDIF_SIE_LOCK(x)
SIC - InterruptClear Register
#define	SPDIF_SIC_LOCKLOSS_MASK   (0x4U)
#define	SPDIF_SIC_LOCKLOSS_SHIFT   (2U)
#define	SPDIF_SIC_LOCKLOSS(x)
#define	SPDIF_SIC_RXFIFORESYN_MASK   (0x8U)
#define	SPDIF_SIC_RXFIFORESYN_SHIFT   (3U)
#define	SPDIF_SIC_RXFIFORESYN(x)
#define	SPDIF_SIC_RXFIFOUNOV_MASK   (0x10U)
#define	SPDIF_SIC_RXFIFOUNOV_SHIFT   (4U)
#define	SPDIF_SIC_RXFIFOUNOV(x)
#define	SPDIF_SIC_UQERR_MASK   (0x20U)
#define	SPDIF_SIC_UQERR_SHIFT   (5U)
#define	SPDIF_SIC_UQERR(x)
#define	SPDIF_SIC_UQSYNC_MASK   (0x40U)
#define	SPDIF_SIC_UQSYNC_SHIFT   (6U)
#define	SPDIF_SIC_UQSYNC(x)
#define	SPDIF_SIC_QRXOV_MASK   (0x80U)
#define	SPDIF_SIC_QRXOV_SHIFT   (7U)
#define	SPDIF_SIC_QRXOV(x)
#define	SPDIF_SIC_URXOV_MASK   (0x200U)
#define	SPDIF_SIC_URXOV_SHIFT   (9U)
#define	SPDIF_SIC_URXOV(x)
#define	SPDIF_SIC_BITERR_MASK   (0x4000U)
#define	SPDIF_SIC_BITERR_SHIFT   (14U)
#define	SPDIF_SIC_BITERR(x)
#define	SPDIF_SIC_SYMERR_MASK   (0x8000U)
#define	SPDIF_SIC_SYMERR_SHIFT   (15U)
#define	SPDIF_SIC_SYMERR(x)
#define	SPDIF_SIC_VALNOGOOD_MASK   (0x10000U)
#define	SPDIF_SIC_VALNOGOOD_SHIFT   (16U)
#define	SPDIF_SIC_VALNOGOOD(x)
#define	SPDIF_SIC_CNEW_MASK   (0x20000U)
#define	SPDIF_SIC_CNEW_SHIFT   (17U)
#define	SPDIF_SIC_CNEW(x)
#define	SPDIF_SIC_TXRESYN_MASK   (0x40000U)
#define	SPDIF_SIC_TXRESYN_SHIFT   (18U)
#define	SPDIF_SIC_TXRESYN(x)
#define	SPDIF_SIC_TXUNOV_MASK   (0x80000U)
#define	SPDIF_SIC_TXUNOV_SHIFT   (19U)
#define	SPDIF_SIC_TXUNOV(x)
#define	SPDIF_SIC_LOCK_MASK   (0x100000U)
#define	SPDIF_SIC_LOCK_SHIFT   (20U)
#define	SPDIF_SIC_LOCK(x)
SIS - InterruptStat Register
#define	SPDIF_SIS_RXFIFOFUL_MASK   (0x1U)
#define	SPDIF_SIS_RXFIFOFUL_SHIFT   (0U)
#define	SPDIF_SIS_RXFIFOFUL(x)
#define	SPDIF_SIS_TXEM_MASK   (0x2U)
#define	SPDIF_SIS_TXEM_SHIFT   (1U)
#define	SPDIF_SIS_TXEM(x)
#define	SPDIF_SIS_LOCKLOSS_MASK   (0x4U)
#define	SPDIF_SIS_LOCKLOSS_SHIFT   (2U)
#define	SPDIF_SIS_LOCKLOSS(x)
#define	SPDIF_SIS_RXFIFORESYN_MASK   (0x8U)
#define	SPDIF_SIS_RXFIFORESYN_SHIFT   (3U)
#define	SPDIF_SIS_RXFIFORESYN(x)
#define	SPDIF_SIS_RXFIFOUNOV_MASK   (0x10U)
#define	SPDIF_SIS_RXFIFOUNOV_SHIFT   (4U)
#define	SPDIF_SIS_RXFIFOUNOV(x)
#define	SPDIF_SIS_UQERR_MASK   (0x20U)
#define	SPDIF_SIS_UQERR_SHIFT   (5U)
#define	SPDIF_SIS_UQERR(x)
#define	SPDIF_SIS_UQSYNC_MASK   (0x40U)
#define	SPDIF_SIS_UQSYNC_SHIFT   (6U)
#define	SPDIF_SIS_UQSYNC(x)
#define	SPDIF_SIS_QRXOV_MASK   (0x80U)
#define	SPDIF_SIS_QRXOV_SHIFT   (7U)
#define	SPDIF_SIS_QRXOV(x)
#define	SPDIF_SIS_QRXFUL_MASK   (0x100U)
#define	SPDIF_SIS_QRXFUL_SHIFT   (8U)
#define	SPDIF_SIS_QRXFUL(x)
#define	SPDIF_SIS_URXOV_MASK   (0x200U)
#define	SPDIF_SIS_URXOV_SHIFT   (9U)
#define	SPDIF_SIS_URXOV(x)
#define	SPDIF_SIS_URXFUL_MASK   (0x400U)
#define	SPDIF_SIS_URXFUL_SHIFT   (10U)
#define	SPDIF_SIS_URXFUL(x)
#define	SPDIF_SIS_BITERR_MASK   (0x4000U)
#define	SPDIF_SIS_BITERR_SHIFT   (14U)
#define	SPDIF_SIS_BITERR(x)
#define	SPDIF_SIS_SYMERR_MASK   (0x8000U)
#define	SPDIF_SIS_SYMERR_SHIFT   (15U)
#define	SPDIF_SIS_SYMERR(x)
#define	SPDIF_SIS_VALNOGOOD_MASK   (0x10000U)
#define	SPDIF_SIS_VALNOGOOD_SHIFT   (16U)
#define	SPDIF_SIS_VALNOGOOD(x)
#define	SPDIF_SIS_CNEW_MASK   (0x20000U)
#define	SPDIF_SIS_CNEW_SHIFT   (17U)
#define	SPDIF_SIS_CNEW(x)
#define	SPDIF_SIS_TXRESYN_MASK   (0x40000U)
#define	SPDIF_SIS_TXRESYN_SHIFT   (18U)
#define	SPDIF_SIS_TXRESYN(x)
#define	SPDIF_SIS_TXUNOV_MASK   (0x80000U)
#define	SPDIF_SIS_TXUNOV_SHIFT   (19U)
#define	SPDIF_SIS_TXUNOV(x)
#define	SPDIF_SIS_LOCK_MASK   (0x100000U)
#define	SPDIF_SIS_LOCK_SHIFT   (20U)
#define	SPDIF_SIS_LOCK(x)
SRL - SPDIFRxLeft Register
#define	SPDIF_SRL_RXDATALEFT_MASK   (0xFFFFFFU)
#define	SPDIF_SRL_RXDATALEFT_SHIFT   (0U)
#define	SPDIF_SRL_RXDATALEFT(x)
SRR - SPDIFRxRight Register
#define	SPDIF_SRR_RXDATARIGHT_MASK   (0xFFFFFFU)
#define	SPDIF_SRR_RXDATARIGHT_SHIFT   (0U)
#define	SPDIF_SRR_RXDATARIGHT(x)
SRCSH - SPDIFRxCChannel_h Register
#define	SPDIF_SRCSH_RXCCHANNEL_H_MASK   (0xFFFFFFU)
#define	SPDIF_SRCSH_RXCCHANNEL_H_SHIFT   (0U)
#define	SPDIF_SRCSH_RXCCHANNEL_H(x)
SRCSL - SPDIFRxCChannel_l Register
#define	SPDIF_SRCSL_RXCCHANNEL_L_MASK   (0xFFFFFFU)
#define	SPDIF_SRCSL_RXCCHANNEL_L_SHIFT   (0U)
#define	SPDIF_SRCSL_RXCCHANNEL_L(x)
SRU - UchannelRx Register
#define	SPDIF_SRU_RXUCHANNEL_MASK   (0xFFFFFFU)
#define	SPDIF_SRU_RXUCHANNEL_SHIFT   (0U)
#define	SPDIF_SRU_RXUCHANNEL(x)
SRQ - QchannelRx Register
#define	SPDIF_SRQ_RXQCHANNEL_MASK   (0xFFFFFFU)
#define	SPDIF_SRQ_RXQCHANNEL_SHIFT   (0U)
#define	SPDIF_SRQ_RXQCHANNEL(x)
STL - SPDIFTxLeft Register
#define	SPDIF_STL_TXDATALEFT_MASK   (0xFFFFFFU)
#define	SPDIF_STL_TXDATALEFT_SHIFT   (0U)
#define	SPDIF_STL_TXDATALEFT(x)
STR - SPDIFTxRight Register
#define	SPDIF_STR_TXDATARIGHT_MASK   (0xFFFFFFU)
#define	SPDIF_STR_TXDATARIGHT_SHIFT   (0U)
#define	SPDIF_STR_TXDATARIGHT(x)
STCSCH - SPDIFTxCChannelCons_h Register
#define	SPDIF_STCSCH_TXCCHANNELCONS_H_MASK   (0xFFFFFFU)
#define	SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT   (0U)
#define	SPDIF_STCSCH_TXCCHANNELCONS_H(x)
STCSCL - SPDIFTxCChannelCons_l Register
#define	SPDIF_STCSCL_TXCCHANNELCONS_L_MASK   (0xFFFFFFU)
#define	SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT   (0U)
#define	SPDIF_STCSCL_TXCCHANNELCONS_L(x)
SRFM - FreqMeas Register
#define	SPDIF_SRFM_FREQMEAS_MASK   (0xFFFFFFU)
#define	SPDIF_SRFM_FREQMEAS_SHIFT   (0U)
#define	SPDIF_SRFM_FREQMEAS(x)
STC - SPDIFTxClk Register
#define	SPDIF_STC_TXCLK_DF_MASK   (0x7FU)
#define	SPDIF_STC_TXCLK_DF_SHIFT   (0U)
#define	SPDIF_STC_TXCLK_DF(x)
#define	SPDIF_STC_TX_ALL_CLK_EN_MASK   (0x80U)
#define	SPDIF_STC_TX_ALL_CLK_EN_SHIFT   (7U)
#define	SPDIF_STC_TX_ALL_CLK_EN(x)
#define	SPDIF_STC_TXCLK_SOURCE_MASK   (0x700U)
#define	SPDIF_STC_TXCLK_SOURCE_SHIFT   (8U)
#define	SPDIF_STC_TXCLK_SOURCE(x)
#define	SPDIF_STC_SYSCLK_DF_MASK   (0xFF800U)
#define	SPDIF_STC_SYSCLK_DF_SHIFT   (11U)
#define	SPDIF_STC_SYSCLK_DF(x)
SCR - SRC Control Register
#define	SRC_SCR_BT_RELEASE_M4_MASK   (0x1U)
#define	SRC_SCR_BT_RELEASE_M4_SHIFT   (0U)
#define	SRC_SCR_BT_RELEASE_M4(x)
#define	SRC_SCR_BT_RELEASE_M7_MASK   (0x2U)
#define	SRC_SCR_BT_RELEASE_M7_SHIFT   (1U)
#define	SRC_SCR_BT_RELEASE_M7(x)
SRMR - SRC Reset Mode Register
#define	SRC_SRMR_WDOG_RESET_MODE_MASK   (0x3U)
#define	SRC_SRMR_WDOG_RESET_MODE_SHIFT   (0U)
#define	SRC_SRMR_WDOG_RESET_MODE(x)
#define	SRC_SRMR_WDOG3_RESET_MODE_MASK   (0xCU)
#define	SRC_SRMR_WDOG3_RESET_MODE_SHIFT   (2U)
#define	SRC_SRMR_WDOG3_RESET_MODE(x)
#define	SRC_SRMR_WDOG4_RESET_MODE_MASK   (0x30U)
#define	SRC_SRMR_WDOG4_RESET_MODE_SHIFT   (4U)
#define	SRC_SRMR_WDOG4_RESET_MODE(x)
#define	SRC_SRMR_M4LOCKUP_RESET_MODE_MASK   (0xC0U)
#define	SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT   (6U)
#define	SRC_SRMR_M4LOCKUP_RESET_MODE(x)
#define	SRC_SRMR_M7LOCKUP_RESET_MODE_MASK   (0x300U)
#define	SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT   (8U)
#define	SRC_SRMR_M7LOCKUP_RESET_MODE(x)
#define	SRC_SRMR_M4REQ_RESET_MODE_MASK   (0xC00U)
#define	SRC_SRMR_M4REQ_RESET_MODE_SHIFT   (10U)
#define	SRC_SRMR_M4REQ_RESET_MODE(x)
#define	SRC_SRMR_M7REQ_RESET_MODE_MASK   (0x3000U)
#define	SRC_SRMR_M7REQ_RESET_MODE_SHIFT   (12U)
#define	SRC_SRMR_M7REQ_RESET_MODE(x)
#define	SRC_SRMR_TEMPSENSE_RESET_MODE_MASK   (0xC000U)
#define	SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT   (14U)
#define	SRC_SRMR_TEMPSENSE_RESET_MODE(x)
#define	SRC_SRMR_CSU_RESET_MODE_MASK   (0x30000U)
#define	SRC_SRMR_CSU_RESET_MODE_SHIFT   (16U)
#define	SRC_SRMR_CSU_RESET_MODE(x)
#define	SRC_SRMR_JTAGSW_RESET_MODE_MASK   (0xC0000U)
#define	SRC_SRMR_JTAGSW_RESET_MODE_SHIFT   (18U)
#define	SRC_SRMR_JTAGSW_RESET_MODE(x)
#define	SRC_SRMR_OVERVOLT_RESET_MODE_MASK   (0x300000U)
#define	SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT   (20U)
#define	SRC_SRMR_OVERVOLT_RESET_MODE(x)
SBMR1 - SRC Boot Mode Register 1
#define	SRC_SBMR1_BOOT_CFG1_MASK   (0xFFU)
#define	SRC_SBMR1_BOOT_CFG1_SHIFT   (0U)
#define	SRC_SBMR1_BOOT_CFG1(x)
#define	SRC_SBMR1_BOOT_CFG2_MASK   (0xFF00U)
#define	SRC_SBMR1_BOOT_CFG2_SHIFT   (8U)
#define	SRC_SBMR1_BOOT_CFG2(x)
#define	SRC_SBMR1_BOOT_CFG3_MASK   (0xFF0000U)
#define	SRC_SBMR1_BOOT_CFG3_SHIFT   (16U)
#define	SRC_SBMR1_BOOT_CFG3(x)
#define	SRC_SBMR1_BOOT_CFG4_MASK   (0xFF000000U)
#define	SRC_SBMR1_BOOT_CFG4_SHIFT   (24U)
#define	SRC_SBMR1_BOOT_CFG4(x)
SBMR2 - SRC Boot Mode Register 2
#define	SRC_SBMR2_SEC_CONFIG_MASK   (0x3U)
#define	SRC_SBMR2_SEC_CONFIG_SHIFT   (0U)
#define	SRC_SBMR2_SEC_CONFIG(x)
#define	SRC_SBMR2_BT_FUSE_SEL_MASK   (0x10U)
#define	SRC_SBMR2_BT_FUSE_SEL_SHIFT   (4U)
#define	SRC_SBMR2_BT_FUSE_SEL(x)
#define	SRC_SBMR2_BMOD_MASK   (0x3000000U)
#define	SRC_SBMR2_BMOD_SHIFT   (24U)
#define	SRC_SBMR2_BMOD(x)
SRSR - SRC Reset Status Register
#define	SRC_SRSR_IPP_RESET_B_M7_MASK   (0x1U)
#define	SRC_SRSR_IPP_RESET_B_M7_SHIFT   (0U)
#define	SRC_SRSR_IPP_RESET_B_M7(x)
#define	SRC_SRSR_M7_REQUEST_M7_MASK   (0x2U)
#define	SRC_SRSR_M7_REQUEST_M7_SHIFT   (1U)
#define	SRC_SRSR_M7_REQUEST_M7(x)
#define	SRC_SRSR_M7_LOCKUP_M7_MASK   (0x4U)
#define	SRC_SRSR_M7_LOCKUP_M7_SHIFT   (2U)
#define	SRC_SRSR_M7_LOCKUP_M7(x)
#define	SRC_SRSR_CSU_RESET_B_M7_MASK   (0x8U)
#define	SRC_SRSR_CSU_RESET_B_M7_SHIFT   (3U)
#define	SRC_SRSR_CSU_RESET_B_M7(x)
#define	SRC_SRSR_IPP_USER_RESET_B_M7_MASK   (0x10U)
#define	SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT   (4U)
#define	SRC_SRSR_IPP_USER_RESET_B_M7(x)
#define	SRC_SRSR_WDOG_RST_B_M7_MASK   (0x20U)
#define	SRC_SRSR_WDOG_RST_B_M7_SHIFT   (5U)
#define	SRC_SRSR_WDOG_RST_B_M7(x)
#define	SRC_SRSR_JTAG_RST_B_M7_MASK   (0x40U)
#define	SRC_SRSR_JTAG_RST_B_M7_SHIFT   (6U)
#define	SRC_SRSR_JTAG_RST_B_M7(x)
#define	SRC_SRSR_JTAG_SW_RST_M7_MASK   (0x80U)
#define	SRC_SRSR_JTAG_SW_RST_M7_SHIFT   (7U)
#define	SRC_SRSR_JTAG_SW_RST_M7(x)
#define	SRC_SRSR_WDOG3_RST_B_M7_MASK   (0x100U)
#define	SRC_SRSR_WDOG3_RST_B_M7_SHIFT   (8U)
#define	SRC_SRSR_WDOG3_RST_B_M7(x)
#define	SRC_SRSR_WDOG4_RST_B_M7_MASK   (0x200U)
#define	SRC_SRSR_WDOG4_RST_B_M7_SHIFT   (9U)
#define	SRC_SRSR_WDOG4_RST_B_M7(x)
#define	SRC_SRSR_TEMPSENSE_RST_B_M7_MASK   (0x400U)
#define	SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT   (10U)
#define	SRC_SRSR_TEMPSENSE_RST_B_M7(x)
#define	SRC_SRSR_M4_REQUEST_M7_MASK   (0x800U)
#define	SRC_SRSR_M4_REQUEST_M7_SHIFT   (11U)
#define	SRC_SRSR_M4_REQUEST_M7(x)
#define	SRC_SRSR_M4_LOCKUP_M7_MASK   (0x1000U)
#define	SRC_SRSR_M4_LOCKUP_M7_SHIFT   (12U)
#define	SRC_SRSR_M4_LOCKUP_M7(x)
#define	SRC_SRSR_OVERVOLT_RST_M7_MASK   (0x2000U)
#define	SRC_SRSR_OVERVOLT_RST_M7_SHIFT   (13U)
#define	SRC_SRSR_OVERVOLT_RST_M7(x)
#define	SRC_SRSR_CDOG_RST_M7_MASK   (0x4000U)
#define	SRC_SRSR_CDOG_RST_M7_SHIFT   (14U)
#define	SRC_SRSR_CDOG_RST_M7(x)
#define	SRC_SRSR_IPP_RESET_B_M4_MASK   (0x10000U)
#define	SRC_SRSR_IPP_RESET_B_M4_SHIFT   (16U)
#define	SRC_SRSR_IPP_RESET_B_M4(x)
#define	SRC_SRSR_M4_REQUEST_M4_MASK   (0x20000U)
#define	SRC_SRSR_M4_REQUEST_M4_SHIFT   (17U)
#define	SRC_SRSR_M4_REQUEST_M4(x)
#define	SRC_SRSR_M4_LOCKUP_M4_MASK   (0x40000U)
#define	SRC_SRSR_M4_LOCKUP_M4_SHIFT   (18U)
#define	SRC_SRSR_M4_LOCKUP_M4(x)
#define	SRC_SRSR_CSU_RESET_B_M4_MASK   (0x80000U)
#define	SRC_SRSR_CSU_RESET_B_M4_SHIFT   (19U)
#define	SRC_SRSR_CSU_RESET_B_M4(x)
#define	SRC_SRSR_IPP_USER_RESET_B_M4_MASK   (0x100000U)
#define	SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT   (20U)
#define	SRC_SRSR_IPP_USER_RESET_B_M4(x)
#define	SRC_SRSR_WDOG_RST_B_M4_MASK   (0x200000U)
#define	SRC_SRSR_WDOG_RST_B_M4_SHIFT   (21U)
#define	SRC_SRSR_WDOG_RST_B_M4(x)
#define	SRC_SRSR_JTAG_RST_B_M4_MASK   (0x400000U)
#define	SRC_SRSR_JTAG_RST_B_M4_SHIFT   (22U)
#define	SRC_SRSR_JTAG_RST_B_M4(x)
#define	SRC_SRSR_JTAG_SW_RST_M4_MASK   (0x800000U)
#define	SRC_SRSR_JTAG_SW_RST_M4_SHIFT   (23U)
#define	SRC_SRSR_JTAG_SW_RST_M4(x)
#define	SRC_SRSR_WDOG3_RST_B_M4_MASK   (0x1000000U)
#define	SRC_SRSR_WDOG3_RST_B_M4_SHIFT   (24U)
#define	SRC_SRSR_WDOG3_RST_B_M4(x)
#define	SRC_SRSR_WDOG4_RST_B_M4_MASK   (0x2000000U)
#define	SRC_SRSR_WDOG4_RST_B_M4_SHIFT   (25U)
#define	SRC_SRSR_WDOG4_RST_B_M4(x)
#define	SRC_SRSR_TEMPSENSE_RST_B_M4_MASK   (0x4000000U)
#define	SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT   (26U)
#define	SRC_SRSR_TEMPSENSE_RST_B_M4(x)
#define	SRC_SRSR_M7_REQUEST_M4_MASK   (0x8000000U)
#define	SRC_SRSR_M7_REQUEST_M4_SHIFT   (27U)
#define	SRC_SRSR_M7_REQUEST_M4(x)
#define	SRC_SRSR_M7_LOCKUP_M4_MASK   (0x10000000U)
#define	SRC_SRSR_M7_LOCKUP_M4_SHIFT   (28U)
#define	SRC_SRSR_M7_LOCKUP_M4(x)
#define	SRC_SRSR_OVERVOLT_RST_M4_MASK   (0x20000000U)
#define	SRC_SRSR_OVERVOLT_RST_M4_SHIFT   (29U)
#define	SRC_SRSR_OVERVOLT_RST_M4(x)
#define	SRC_SRSR_CDOG_RST_M4_MASK   (0x40000000U)
#define	SRC_SRSR_CDOG_RST_M4_SHIFT   (30U)
#define	SRC_SRSR_CDOG_RST_M4(x)
GPR - SRC General Purpose Register
#define	SRC_GPR_GPR_MASK   (0xFFFFFFFFU)
#define	SRC_GPR_GPR_SHIFT   (0U)
#define	SRC_GPR_GPR(x)
AUTHEN_MEGA - Slice Authentication Register
#define	SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_MEGA_DOMAIN_MODE(x)
#define	SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_MEGA_SETPOINT_MODE(x)
#define	SRC_AUTHEN_MEGA_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_MEGA_LOCK_MODE(x)
#define	SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_MEGA_ASSIGN_LIST(x)
#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_MEGA_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_MEGA_WHITE_LIST(x)
#define	SRC_AUTHEN_MEGA_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_MEGA_LOCK_LIST(x)
#define	SRC_AUTHEN_MEGA_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_MEGA_USER_SHIFT   (24U)
#define	SRC_AUTHEN_MEGA_USER(x)
#define	SRC_AUTHEN_MEGA_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_MEGA_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_MEGA_NONSECURE(x)
#define	SRC_AUTHEN_MEGA_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_MEGA_LOCK_SETTING(x)
CTRL_MEGA - Slice Control Register
#define	SRC_CTRL_MEGA_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_MEGA_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_MEGA_SW_RESET(x)
SETPOINT_MEGA - Slice Setpoint Config Register
#define	SRC_SETPOINT_MEGA_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_MEGA_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_MEGA_SETPOINT0(x)
#define	SRC_SETPOINT_MEGA_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_MEGA_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_MEGA_SETPOINT1(x)
#define	SRC_SETPOINT_MEGA_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_MEGA_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_MEGA_SETPOINT2(x)
#define	SRC_SETPOINT_MEGA_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_MEGA_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_MEGA_SETPOINT3(x)
#define	SRC_SETPOINT_MEGA_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_MEGA_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_MEGA_SETPOINT4(x)
#define	SRC_SETPOINT_MEGA_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_MEGA_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_MEGA_SETPOINT5(x)
#define	SRC_SETPOINT_MEGA_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_MEGA_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_MEGA_SETPOINT6(x)
#define	SRC_SETPOINT_MEGA_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_MEGA_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_MEGA_SETPOINT7(x)
#define	SRC_SETPOINT_MEGA_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_MEGA_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_MEGA_SETPOINT8(x)
#define	SRC_SETPOINT_MEGA_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_MEGA_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_MEGA_SETPOINT9(x)
#define	SRC_SETPOINT_MEGA_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_MEGA_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_MEGA_SETPOINT10(x)
#define	SRC_SETPOINT_MEGA_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_MEGA_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_MEGA_SETPOINT11(x)
#define	SRC_SETPOINT_MEGA_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_MEGA_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_MEGA_SETPOINT12(x)
#define	SRC_SETPOINT_MEGA_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_MEGA_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_MEGA_SETPOINT13(x)
#define	SRC_SETPOINT_MEGA_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_MEGA_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_MEGA_SETPOINT14(x)
#define	SRC_SETPOINT_MEGA_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_MEGA_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_MEGA_SETPOINT15(x)
DOMAIN_MEGA - Slice Domain Config Register
#define	SRC_DOMAIN_MEGA_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_MEGA_CPU0_RUN(x)
#define	SRC_DOMAIN_MEGA_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_MEGA_CPU0_WAIT(x)
#define	SRC_DOMAIN_MEGA_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_MEGA_CPU0_STOP(x)
#define	SRC_DOMAIN_MEGA_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_MEGA_CPU0_SUSP(x)
#define	SRC_DOMAIN_MEGA_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_MEGA_CPU1_RUN(x)
#define	SRC_DOMAIN_MEGA_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_MEGA_CPU1_WAIT(x)
#define	SRC_DOMAIN_MEGA_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_MEGA_CPU1_STOP(x)
#define	SRC_DOMAIN_MEGA_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_MEGA_CPU1_SUSP(x)
STAT_MEGA - Slice Status Register
#define	SRC_STAT_MEGA_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_MEGA_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_MEGA_UNDER_RST(x)
#define	SRC_STAT_MEGA_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_MEGA_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_MEGA_RST_BY_HW(x)
#define	SRC_STAT_MEGA_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_MEGA_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_MEGA_RST_BY_SW(x)
AUTHEN_DISPLAY - Slice Authentication Register
#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x)
#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x)
#define	SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_DISPLAY_LOCK_MODE(x)
#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x)
#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_DISPLAY_WHITE_LIST(x)
#define	SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_DISPLAY_LOCK_LIST(x)
#define	SRC_AUTHEN_DISPLAY_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_DISPLAY_USER_SHIFT   (24U)
#define	SRC_AUTHEN_DISPLAY_USER(x)
#define	SRC_AUTHEN_DISPLAY_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_DISPLAY_NONSECURE(x)
#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING(x)
CTRL_DISPLAY - Slice Control Register
#define	SRC_CTRL_DISPLAY_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_DISPLAY_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_DISPLAY_SW_RESET(x)
SETPOINT_DISPLAY - Slice Setpoint Config Register
#define	SRC_SETPOINT_DISPLAY_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT0(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT1(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT2(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT3(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT4(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT5(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT6(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT7(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT8(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT9(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT10(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT11(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT12(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT13(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT14(x)
#define	SRC_SETPOINT_DISPLAY_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_DISPLAY_SETPOINT15(x)
DOMAIN_DISPLAY - Slice Domain Config Register
#define	SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_DISPLAY_CPU0_RUN(x)
#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT(x)
#define	SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_DISPLAY_CPU0_STOP(x)
#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP(x)
#define	SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_DISPLAY_CPU1_RUN(x)
#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT(x)
#define	SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_DISPLAY_CPU1_STOP(x)
#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP(x)
STAT_DISPLAY - Slice Status Register
#define	SRC_STAT_DISPLAY_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_DISPLAY_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_DISPLAY_UNDER_RST(x)
#define	SRC_STAT_DISPLAY_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_DISPLAY_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_DISPLAY_RST_BY_HW(x)
#define	SRC_STAT_DISPLAY_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_DISPLAY_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_DISPLAY_RST_BY_SW(x)
AUTHEN_WAKEUP - Slice Authentication Register
#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x)
#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x)
#define	SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_WAKEUP_LOCK_MODE(x)
#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x)
#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_WAKEUP_WHITE_LIST(x)
#define	SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_WAKEUP_LOCK_LIST(x)
#define	SRC_AUTHEN_WAKEUP_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_WAKEUP_USER_SHIFT   (24U)
#define	SRC_AUTHEN_WAKEUP_USER(x)
#define	SRC_AUTHEN_WAKEUP_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_WAKEUP_NONSECURE(x)
#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING(x)
CTRL_WAKEUP - Slice Control Register
#define	SRC_CTRL_WAKEUP_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_WAKEUP_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_WAKEUP_SW_RESET(x)
SETPOINT_WAKEUP - Slice Setpoint Config Register
#define	SRC_SETPOINT_WAKEUP_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT0(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT1(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT2(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT3(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT4(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT5(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT6(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT7(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT8(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT9(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT10(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT11(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT12(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT13(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT14(x)
#define	SRC_SETPOINT_WAKEUP_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_WAKEUP_SETPOINT15(x)
DOMAIN_WAKEUP - Slice Domain Config Register
#define	SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_WAKEUP_CPU0_RUN(x)
#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT(x)
#define	SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_WAKEUP_CPU0_STOP(x)
#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP(x)
#define	SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_WAKEUP_CPU1_RUN(x)
#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT(x)
#define	SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_WAKEUP_CPU1_STOP(x)
#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP(x)
STAT_WAKEUP - Slice Status Register
#define	SRC_STAT_WAKEUP_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_WAKEUP_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_WAKEUP_UNDER_RST(x)
#define	SRC_STAT_WAKEUP_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_WAKEUP_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_WAKEUP_RST_BY_HW(x)
#define	SRC_STAT_WAKEUP_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_WAKEUP_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_WAKEUP_RST_BY_SW(x)
AUTHEN_M4CORE - Slice Authentication Register
#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE(x)
#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE(x)
#define	SRC_AUTHEN_M4CORE_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_M4CORE_LOCK_MODE(x)
#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST(x)
#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_M4CORE_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_M4CORE_WHITE_LIST(x)
#define	SRC_AUTHEN_M4CORE_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_M4CORE_LOCK_LIST(x)
#define	SRC_AUTHEN_M4CORE_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_M4CORE_USER_SHIFT   (24U)
#define	SRC_AUTHEN_M4CORE_USER(x)
#define	SRC_AUTHEN_M4CORE_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_M4CORE_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_M4CORE_NONSECURE(x)
#define	SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_M4CORE_LOCK_SETTING(x)
CTRL_M4CORE - Slice Control Register
#define	SRC_CTRL_M4CORE_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_M4CORE_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_M4CORE_SW_RESET(x)
SETPOINT_M4CORE - Slice Setpoint Config Register
#define	SRC_SETPOINT_M4CORE_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_M4CORE_SETPOINT0(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_M4CORE_SETPOINT1(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_M4CORE_SETPOINT2(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_M4CORE_SETPOINT3(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_M4CORE_SETPOINT4(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_M4CORE_SETPOINT5(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_M4CORE_SETPOINT6(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_M4CORE_SETPOINT7(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_M4CORE_SETPOINT8(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_M4CORE_SETPOINT9(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_M4CORE_SETPOINT10(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_M4CORE_SETPOINT11(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_M4CORE_SETPOINT12(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_M4CORE_SETPOINT13(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_M4CORE_SETPOINT14(x)
#define	SRC_SETPOINT_M4CORE_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_M4CORE_SETPOINT15(x)
DOMAIN_M4CORE - Slice Domain Config Register
#define	SRC_DOMAIN_M4CORE_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_M4CORE_CPU0_RUN(x)
#define	SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_M4CORE_CPU0_WAIT(x)
#define	SRC_DOMAIN_M4CORE_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_M4CORE_CPU0_STOP(x)
#define	SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_M4CORE_CPU0_SUSP(x)
#define	SRC_DOMAIN_M4CORE_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_M4CORE_CPU1_RUN(x)
#define	SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_M4CORE_CPU1_WAIT(x)
#define	SRC_DOMAIN_M4CORE_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_M4CORE_CPU1_STOP(x)
#define	SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_M4CORE_CPU1_SUSP(x)
STAT_M4CORE - Slice Status Register
#define	SRC_STAT_M4CORE_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_M4CORE_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_M4CORE_UNDER_RST(x)
#define	SRC_STAT_M4CORE_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_M4CORE_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_M4CORE_RST_BY_HW(x)
#define	SRC_STAT_M4CORE_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_M4CORE_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_M4CORE_RST_BY_SW(x)
AUTHEN_M7CORE - Slice Authentication Register
#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE(x)
#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE(x)
#define	SRC_AUTHEN_M7CORE_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_M7CORE_LOCK_MODE(x)
#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST(x)
#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_M7CORE_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_M7CORE_WHITE_LIST(x)
#define	SRC_AUTHEN_M7CORE_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_M7CORE_LOCK_LIST(x)
#define	SRC_AUTHEN_M7CORE_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_M7CORE_USER_SHIFT   (24U)
#define	SRC_AUTHEN_M7CORE_USER(x)
#define	SRC_AUTHEN_M7CORE_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_M7CORE_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_M7CORE_NONSECURE(x)
#define	SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_M7CORE_LOCK_SETTING(x)
CTRL_M7CORE - Slice Control Register
#define	SRC_CTRL_M7CORE_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_M7CORE_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_M7CORE_SW_RESET(x)
SETPOINT_M7CORE - Slice Setpoint Config Register
#define	SRC_SETPOINT_M7CORE_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_M7CORE_SETPOINT0(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_M7CORE_SETPOINT1(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_M7CORE_SETPOINT2(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_M7CORE_SETPOINT3(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_M7CORE_SETPOINT4(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_M7CORE_SETPOINT5(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_M7CORE_SETPOINT6(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_M7CORE_SETPOINT7(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_M7CORE_SETPOINT8(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_M7CORE_SETPOINT9(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_M7CORE_SETPOINT10(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_M7CORE_SETPOINT11(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_M7CORE_SETPOINT12(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_M7CORE_SETPOINT13(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_M7CORE_SETPOINT14(x)
#define	SRC_SETPOINT_M7CORE_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_M7CORE_SETPOINT15(x)
DOMAIN_M7CORE - Slice Domain Config Register
#define	SRC_DOMAIN_M7CORE_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_M7CORE_CPU0_RUN(x)
#define	SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_M7CORE_CPU0_WAIT(x)
#define	SRC_DOMAIN_M7CORE_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_M7CORE_CPU0_STOP(x)
#define	SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_M7CORE_CPU0_SUSP(x)
#define	SRC_DOMAIN_M7CORE_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_M7CORE_CPU1_RUN(x)
#define	SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_M7CORE_CPU1_WAIT(x)
#define	SRC_DOMAIN_M7CORE_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_M7CORE_CPU1_STOP(x)
#define	SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_M7CORE_CPU1_SUSP(x)
STAT_M7CORE - Slice Status Register
#define	SRC_STAT_M7CORE_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_M7CORE_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_M7CORE_UNDER_RST(x)
#define	SRC_STAT_M7CORE_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_M7CORE_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_M7CORE_RST_BY_HW(x)
#define	SRC_STAT_M7CORE_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_M7CORE_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_M7CORE_RST_BY_SW(x)
AUTHEN_M4DEBUG - Slice Authentication Register
#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x)
#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x)
#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE(x)
#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x)
#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST(x)
#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST(x)
#define	SRC_AUTHEN_M4DEBUG_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_M4DEBUG_USER_SHIFT   (24U)
#define	SRC_AUTHEN_M4DEBUG_USER(x)
#define	SRC_AUTHEN_M4DEBUG_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_M4DEBUG_NONSECURE(x)
#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x)
CTRL_M4DEBUG - Slice Control Register
#define	SRC_CTRL_M4DEBUG_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_M4DEBUG_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_M4DEBUG_SW_RESET(x)
SETPOINT_M4DEBUG - Slice Setpoint Config Register
#define	SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT0(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT1(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT2(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT3(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT4(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT5(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT6(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT7(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT8(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT9(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT10(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT11(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT12(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT13(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT14(x)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_M4DEBUG_SETPOINT15(x)
DOMAIN_M4DEBUG - Slice Domain Config Register
#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN(x)
#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x)
#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP(x)
#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x)
#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN(x)
#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x)
#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP(x)
#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x)
STAT_M4DEBUG - Slice Status Register
#define	SRC_STAT_M4DEBUG_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_M4DEBUG_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_M4DEBUG_UNDER_RST(x)
#define	SRC_STAT_M4DEBUG_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_M4DEBUG_RST_BY_HW(x)
#define	SRC_STAT_M4DEBUG_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_M4DEBUG_RST_BY_SW(x)
AUTHEN_M7DEBUG - Slice Authentication Register
#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x)
#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x)
#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE(x)
#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x)
#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST(x)
#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST(x)
#define	SRC_AUTHEN_M7DEBUG_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_M7DEBUG_USER_SHIFT   (24U)
#define	SRC_AUTHEN_M7DEBUG_USER(x)
#define	SRC_AUTHEN_M7DEBUG_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_M7DEBUG_NONSECURE(x)
#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x)
CTRL_M7DEBUG - Slice Control Register
#define	SRC_CTRL_M7DEBUG_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_M7DEBUG_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_M7DEBUG_SW_RESET(x)
SETPOINT_M7DEBUG - Slice Setpoint Config Register
#define	SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT0(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT1(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT2(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT3(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT4(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT5(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT6(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT7(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT8(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT9(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT10(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT11(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT12(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT13(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT14(x)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_M7DEBUG_SETPOINT15(x)
DOMAIN_M7DEBUG - Slice Domain Config Register
#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN(x)
#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x)
#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP(x)
#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x)
#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN(x)
#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x)
#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP(x)
#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x)
STAT_M7DEBUG - Slice Status Register
#define	SRC_STAT_M7DEBUG_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_M7DEBUG_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_M7DEBUG_UNDER_RST(x)
#define	SRC_STAT_M7DEBUG_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_M7DEBUG_RST_BY_HW(x)
#define	SRC_STAT_M7DEBUG_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_M7DEBUG_RST_BY_SW(x)
AUTHEN_USBPHY1 - Slice Authentication Register
#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x)
#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x)
#define	SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_USBPHY1_LOCK_MODE(x)
#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x)
#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_USBPHY1_WHITE_LIST(x)
#define	SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_USBPHY1_LOCK_LIST(x)
#define	SRC_AUTHEN_USBPHY1_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_USBPHY1_USER_SHIFT   (24U)
#define	SRC_AUTHEN_USBPHY1_USER(x)
#define	SRC_AUTHEN_USBPHY1_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_USBPHY1_NONSECURE(x)
#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING(x)
CTRL_USBPHY1 - Slice Control Register
#define	SRC_CTRL_USBPHY1_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_USBPHY1_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_USBPHY1_SW_RESET(x)
SETPOINT_USBPHY1 - Slice Setpoint Config Register
#define	SRC_SETPOINT_USBPHY1_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT0(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT1(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT2(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT3(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT4(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT5(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT6(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT7(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT8(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT9(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT10(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT11(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT12(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT13(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT14(x)
#define	SRC_SETPOINT_USBPHY1_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_USBPHY1_SETPOINT15(x)
DOMAIN_USBPHY1 - Slice Domain Config Register
#define	SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_USBPHY1_CPU0_RUN(x)
#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT(x)
#define	SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_USBPHY1_CPU0_STOP(x)
#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP(x)
#define	SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_USBPHY1_CPU1_RUN(x)
#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT(x)
#define	SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_USBPHY1_CPU1_STOP(x)
#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP(x)
STAT_USBPHY1 - Slice Status Register
#define	SRC_STAT_USBPHY1_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_USBPHY1_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_USBPHY1_UNDER_RST(x)
#define	SRC_STAT_USBPHY1_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_USBPHY1_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_USBPHY1_RST_BY_HW(x)
#define	SRC_STAT_USBPHY1_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_USBPHY1_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_USBPHY1_RST_BY_SW(x)
AUTHEN_USBPHY2 - Slice Authentication Register
#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK   (0x1U)
#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT   (0U)
#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x)
#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK   (0x2U)
#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT   (1U)
#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x)
#define	SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK   (0x80U)
#define	SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT   (7U)
#define	SRC_AUTHEN_USBPHY2_LOCK_MODE(x)
#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK   (0xF00U)
#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT   (8U)
#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x)
#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK   (0x8000U)
#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT   (15U)
#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x)
#define	SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK   (0xF0000U)
#define	SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT   (16U)
#define	SRC_AUTHEN_USBPHY2_WHITE_LIST(x)
#define	SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK   (0x800000U)
#define	SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT   (23U)
#define	SRC_AUTHEN_USBPHY2_LOCK_LIST(x)
#define	SRC_AUTHEN_USBPHY2_USER_MASK   (0x1000000U)
#define	SRC_AUTHEN_USBPHY2_USER_SHIFT   (24U)
#define	SRC_AUTHEN_USBPHY2_USER(x)
#define	SRC_AUTHEN_USBPHY2_NONSECURE_MASK   (0x2000000U)
#define	SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT   (25U)
#define	SRC_AUTHEN_USBPHY2_NONSECURE(x)
#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK   (0x80000000U)
#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT   (31U)
#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING(x)
CTRL_USBPHY2 - Slice Control Register
#define	SRC_CTRL_USBPHY2_SW_RESET_MASK   (0x1U)
#define	SRC_CTRL_USBPHY2_SW_RESET_SHIFT   (0U)
#define	SRC_CTRL_USBPHY2_SW_RESET(x)
SETPOINT_USBPHY2 - Slice Setpoint Config Register
#define	SRC_SETPOINT_USBPHY2_SETPOINT0_MASK   (0x1U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT   (0U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT0(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT1_MASK   (0x2U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT   (1U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT1(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT2_MASK   (0x4U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT   (2U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT2(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT3_MASK   (0x8U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT   (3U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT3(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT4_MASK   (0x10U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT   (4U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT4(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT5_MASK   (0x20U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT   (5U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT5(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT6_MASK   (0x40U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT   (6U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT6(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT7_MASK   (0x80U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT   (7U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT7(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT8_MASK   (0x100U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT   (8U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT8(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT9_MASK   (0x200U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT   (9U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT9(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT10_MASK   (0x400U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT   (10U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT10(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT11_MASK   (0x800U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT   (11U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT11(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT12_MASK   (0x1000U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT   (12U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT12(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT13_MASK   (0x2000U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT   (13U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT13(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT14_MASK   (0x4000U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT   (14U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT14(x)
#define	SRC_SETPOINT_USBPHY2_SETPOINT15_MASK   (0x8000U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT   (15U)
#define	SRC_SETPOINT_USBPHY2_SETPOINT15(x)
DOMAIN_USBPHY2 - Slice Domain Config Register
#define	SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK   (0x1U)
#define	SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT   (0U)
#define	SRC_DOMAIN_USBPHY2_CPU0_RUN(x)
#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK   (0x2U)
#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT   (1U)
#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT(x)
#define	SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK   (0x4U)
#define	SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT   (2U)
#define	SRC_DOMAIN_USBPHY2_CPU0_STOP(x)
#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK   (0x8U)
#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT   (3U)
#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP(x)
#define	SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK   (0x10U)
#define	SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT   (4U)
#define	SRC_DOMAIN_USBPHY2_CPU1_RUN(x)
#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK   (0x20U)
#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT   (5U)
#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT(x)
#define	SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK   (0x40U)
#define	SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT   (6U)
#define	SRC_DOMAIN_USBPHY2_CPU1_STOP(x)
#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK   (0x80U)
#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT   (7U)
#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP(x)
STAT_USBPHY2 - Slice Status Register
#define	SRC_STAT_USBPHY2_UNDER_RST_MASK   (0x1U)
#define	SRC_STAT_USBPHY2_UNDER_RST_SHIFT   (0U)
#define	SRC_STAT_USBPHY2_UNDER_RST(x)
#define	SRC_STAT_USBPHY2_RST_BY_HW_MASK   (0x4U)
#define	SRC_STAT_USBPHY2_RST_BY_HW_SHIFT   (2U)
#define	SRC_STAT_USBPHY2_RST_BY_HW(x)
#define	SRC_STAT_USBPHY2_RST_BY_SW_MASK   (0x8U)
#define	SRC_STAT_USBPHY2_RST_BY_SW_SHIFT   (3U)
#define	SRC_STAT_USBPHY2_RST_BY_SW(x)
SRAM0 - Description Address Register
#define	SSARC_HP_SRAM0_ADDR_MASK   (0xFFFFFFFFU)
#define	SSARC_HP_SRAM0_ADDR_SHIFT   (0U)
#define	SSARC_HP_SRAM0_ADDR(x)
SRAM1 - Description Data Register
#define	SSARC_HP_SRAM1_DATA_MASK   (0xFFFFFFFFU)
#define	SSARC_HP_SRAM1_DATA_SHIFT   (0U)
#define	SSARC_HP_SRAM1_DATA(x)
SRAM2 - Description Control Register
#define	SSARC_HP_SRAM2_TYPE_MASK   (0x7U)
#define	SSARC_HP_SRAM2_TYPE_SHIFT   (0U)
#define	SSARC_HP_SRAM2_TYPE(x)
#define	SSARC_HP_SRAM2_SV_EN_MASK   (0x10U)
#define	SSARC_HP_SRAM2_SV_EN_SHIFT   (4U)
#define	SSARC_HP_SRAM2_SV_EN(x)
#define	SSARC_HP_SRAM2_RT_EN_MASK   (0x20U)
#define	SSARC_HP_SRAM2_RT_EN_SHIFT   (5U)
#define	SSARC_HP_SRAM2_RT_EN(x)
#define	SSARC_HP_SRAM2_SIZE_MASK   (0xC0U)
#define	SSARC_HP_SRAM2_SIZE_SHIFT   (6U)
#define	SSARC_HP_SRAM2_SIZE(x)
DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register
#define	SSARC_LP_DESC_CTRL0_START_MASK   (0x3FFU)
#define	SSARC_LP_DESC_CTRL0_START_SHIFT   (0U)
#define	SSARC_LP_DESC_CTRL0_START(x)
#define	SSARC_LP_DESC_CTRL0_END_MASK   (0xFFC00U)
#define	SSARC_LP_DESC_CTRL0_END_SHIFT   (10U)
#define	SSARC_LP_DESC_CTRL0_END(x)
#define	SSARC_LP_DESC_CTRL0_SV_ORDER_MASK   (0x100000U)
#define	SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT   (20U)
#define	SSARC_LP_DESC_CTRL0_SV_ORDER(x)
#define	SSARC_LP_DESC_CTRL0_RT_ORDER_MASK   (0x200000U)
#define	SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT   (21U)
#define	SSARC_LP_DESC_CTRL0_RT_ORDER(x)
DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register
#define	SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK   (0x1U)
#define	SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT   (0U)
#define	SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x)
#define	SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK   (0x2U)
#define	SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT   (1U)
#define	SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x)
#define	SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK   (0x70U)
#define	SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT   (4U)
#define	SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x)
#define	SSARC_LP_DESC_CTRL1_GP_EN_MASK   (0x80U)
#define	SSARC_LP_DESC_CTRL1_GP_EN_SHIFT   (7U)
#define	SSARC_LP_DESC_CTRL1_GP_EN(x)
#define	SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK   (0xF00U)
#define	SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT   (8U)
#define	SSARC_LP_DESC_CTRL1_SV_PRIORITY(x)
#define	SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK   (0xF000U)
#define	SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT   (12U)
#define	SSARC_LP_DESC_CTRL1_RT_PRIORITY(x)
#define	SSARC_LP_DESC_CTRL1_CPUD_MASK   (0x30000U)
#define	SSARC_LP_DESC_CTRL1_CPUD_SHIFT   (16U)
#define	SSARC_LP_DESC_CTRL1_CPUD(x)
#define	SSARC_LP_DESC_CTRL1_RL_MASK   (0x40000U)
#define	SSARC_LP_DESC_CTRL1_RL_SHIFT   (18U)
#define	SSARC_LP_DESC_CTRL1_RL(x)
#define	SSARC_LP_DESC_CTRL1_WL_MASK   (0x80000U)
#define	SSARC_LP_DESC_CTRL1_WL_SHIFT   (19U)
#define	SSARC_LP_DESC_CTRL1_WL(x)
#define	SSARC_LP_DESC_CTRL1_DL_MASK   (0x100000U)
#define	SSARC_LP_DESC_CTRL1_DL_SHIFT   (20U)
#define	SSARC_LP_DESC_CTRL1_DL(x)
DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register
#define	SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK   (0xFFFFFFFFU)
#define	SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT   (0U)
#define	SSARC_LP_DESC_ADDR_UP_ADDR_UP(x)
DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register
#define	SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK   (0xFFFFFFFFU)
#define	SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT   (0U)
#define	SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x)
HP_TIMEOUT - HP Timeout Register
#define	SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK   (0xFFFFFFFFU)
#define	SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT   (0U)
#define	SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x)
HW_GROUP_PENDING - Hardware Request Pending Register
#define	SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK   (0xFFFFU)
#define	SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT   (0U)
#define	SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x)
#define	SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK   (0xFFFF0000U)
#define	SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT   (16U)
#define	SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x)
SW_GROUP_PENDING - Software Request Pending Register
#define	SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK   (0xFFFFU)
#define	SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT   (0U)
#define	SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x)
#define	SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK   (0xFFFF0000U)
#define	SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT   (16U)
#define	SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x)
CTRL0 - Temperature Sensor Control Register 0
#define	TMPSNS_CTRL0_SLOPE_CAL_MASK   (0x3FU)
#define	TMPSNS_CTRL0_SLOPE_CAL_SHIFT   (0U)
#define	TMPSNS_CTRL0_SLOPE_CAL(x)
#define	TMPSNS_CTRL0_V_SEL_MASK   (0x300U)
#define	TMPSNS_CTRL0_V_SEL_SHIFT   (8U)
#define	TMPSNS_CTRL0_V_SEL(x)
#define	TMPSNS_CTRL0_IBIAS_TRIM_MASK   (0xF000U)
#define	TMPSNS_CTRL0_IBIAS_TRIM_SHIFT   (12U)
#define	TMPSNS_CTRL0_IBIAS_TRIM(x)
CTRL0_SET - Temperature Sensor Control Register 0
#define	TMPSNS_CTRL0_SET_SLOPE_CAL_MASK   (0x3FU)
#define	TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT   (0U)
#define	TMPSNS_CTRL0_SET_SLOPE_CAL(x)
#define	TMPSNS_CTRL0_SET_V_SEL_MASK   (0x300U)
#define	TMPSNS_CTRL0_SET_V_SEL_SHIFT   (8U)
#define	TMPSNS_CTRL0_SET_V_SEL(x)
#define	TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK   (0xF000U)
#define	TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT   (12U)
#define	TMPSNS_CTRL0_SET_IBIAS_TRIM(x)
CTRL0_CLR - Temperature Sensor Control Register 0
#define	TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK   (0x3FU)
#define	TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT   (0U)
#define	TMPSNS_CTRL0_CLR_SLOPE_CAL(x)
#define	TMPSNS_CTRL0_CLR_V_SEL_MASK   (0x300U)
#define	TMPSNS_CTRL0_CLR_V_SEL_SHIFT   (8U)
#define	TMPSNS_CTRL0_CLR_V_SEL(x)
#define	TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK   (0xF000U)
#define	TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT   (12U)
#define	TMPSNS_CTRL0_CLR_IBIAS_TRIM(x)
CTRL0_TOG - Temperature Sensor Control Register 0
#define	TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK   (0x3FU)
#define	TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT   (0U)
#define	TMPSNS_CTRL0_TOG_SLOPE_CAL(x)
#define	TMPSNS_CTRL0_TOG_V_SEL_MASK   (0x300U)
#define	TMPSNS_CTRL0_TOG_V_SEL_SHIFT   (8U)
#define	TMPSNS_CTRL0_TOG_V_SEL(x)
#define	TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK   (0xF000U)
#define	TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT   (12U)
#define	TMPSNS_CTRL0_TOG_IBIAS_TRIM(x)
CTRL1 - Temperature Sensor Control Register 1
#define	TMPSNS_CTRL1_FREQ_MASK   (0xFFFFU)
#define	TMPSNS_CTRL1_FREQ_SHIFT   (0U)
#define	TMPSNS_CTRL1_FREQ(x)
#define	TMPSNS_CTRL1_FINISH_IE_MASK   (0x10000U)
#define	TMPSNS_CTRL1_FINISH_IE_SHIFT   (16U)
#define	TMPSNS_CTRL1_FINISH_IE(x)
#define	TMPSNS_CTRL1_LOW_TEMP_IE_MASK   (0x20000U)
#define	TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT   (17U)
#define	TMPSNS_CTRL1_LOW_TEMP_IE(x)
#define	TMPSNS_CTRL1_HIGH_TEMP_IE_MASK   (0x40000U)
#define	TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT   (18U)
#define	TMPSNS_CTRL1_HIGH_TEMP_IE(x)
#define	TMPSNS_CTRL1_PANIC_TEMP_IE_MASK   (0x80000U)
#define	TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT   (19U)
#define	TMPSNS_CTRL1_PANIC_TEMP_IE(x)
#define	TMPSNS_CTRL1_START_MASK   (0x400000U)
#define	TMPSNS_CTRL1_START_SHIFT   (22U)
#define	TMPSNS_CTRL1_START(x)
#define	TMPSNS_CTRL1_PWD_MASK   (0x800000U)
#define	TMPSNS_CTRL1_PWD_SHIFT   (23U)
#define	TMPSNS_CTRL1_PWD(x)
#define	TMPSNS_CTRL1_RFU_MASK   (0x7F000000U)
#define	TMPSNS_CTRL1_RFU_SHIFT   (24U)
#define	TMPSNS_CTRL1_RFU(x)
#define	TMPSNS_CTRL1_PWD_FULL_MASK   (0x80000000U)
#define	TMPSNS_CTRL1_PWD_FULL_SHIFT   (31U)
#define	TMPSNS_CTRL1_PWD_FULL(x)
CTRL1_SET - Temperature Sensor Control Register 1
#define	TMPSNS_CTRL1_SET_FREQ_MASK   (0xFFFFU)
#define	TMPSNS_CTRL1_SET_FREQ_SHIFT   (0U)
#define	TMPSNS_CTRL1_SET_FREQ(x)
#define	TMPSNS_CTRL1_SET_FINISH_IE_MASK   (0x10000U)
#define	TMPSNS_CTRL1_SET_FINISH_IE_SHIFT   (16U)
#define	TMPSNS_CTRL1_SET_FINISH_IE(x)
#define	TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK   (0x20000U)
#define	TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT   (17U)
#define	TMPSNS_CTRL1_SET_LOW_TEMP_IE(x)
#define	TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK   (0x40000U)
#define	TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT   (18U)
#define	TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x)
#define	TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK   (0x80000U)
#define	TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT   (19U)
#define	TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x)
#define	TMPSNS_CTRL1_SET_START_MASK   (0x400000U)
#define	TMPSNS_CTRL1_SET_START_SHIFT   (22U)
#define	TMPSNS_CTRL1_SET_START(x)
#define	TMPSNS_CTRL1_SET_PWD_MASK   (0x800000U)
#define	TMPSNS_CTRL1_SET_PWD_SHIFT   (23U)
#define	TMPSNS_CTRL1_SET_PWD(x)
#define	TMPSNS_CTRL1_SET_RFU_MASK   (0x7F000000U)
#define	TMPSNS_CTRL1_SET_RFU_SHIFT   (24U)
#define	TMPSNS_CTRL1_SET_RFU(x)
#define	TMPSNS_CTRL1_SET_PWD_FULL_MASK   (0x80000000U)
#define	TMPSNS_CTRL1_SET_PWD_FULL_SHIFT   (31U)
#define	TMPSNS_CTRL1_SET_PWD_FULL(x)
CTRL1_CLR - Temperature Sensor Control Register 1
#define	TMPSNS_CTRL1_CLR_FREQ_MASK   (0xFFFFU)
#define	TMPSNS_CTRL1_CLR_FREQ_SHIFT   (0U)
#define	TMPSNS_CTRL1_CLR_FREQ(x)
#define	TMPSNS_CTRL1_CLR_FINISH_IE_MASK   (0x10000U)
#define	TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT   (16U)
#define	TMPSNS_CTRL1_CLR_FINISH_IE(x)
#define	TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK   (0x20000U)
#define	TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT   (17U)
#define	TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x)
#define	TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK   (0x40000U)
#define	TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT   (18U)
#define	TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x)
#define	TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK   (0x80000U)
#define	TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT   (19U)
#define	TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x)
#define	TMPSNS_CTRL1_CLR_START_MASK   (0x400000U)
#define	TMPSNS_CTRL1_CLR_START_SHIFT   (22U)
#define	TMPSNS_CTRL1_CLR_START(x)
#define	TMPSNS_CTRL1_CLR_PWD_MASK   (0x800000U)
#define	TMPSNS_CTRL1_CLR_PWD_SHIFT   (23U)
#define	TMPSNS_CTRL1_CLR_PWD(x)
#define	TMPSNS_CTRL1_CLR_RFU_MASK   (0x7F000000U)
#define	TMPSNS_CTRL1_CLR_RFU_SHIFT   (24U)
#define	TMPSNS_CTRL1_CLR_RFU(x)
#define	TMPSNS_CTRL1_CLR_PWD_FULL_MASK   (0x80000000U)
#define	TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT   (31U)
#define	TMPSNS_CTRL1_CLR_PWD_FULL(x)
CTRL1_TOG - Temperature Sensor Control Register 1
#define	TMPSNS_CTRL1_TOG_FREQ_MASK   (0xFFFFU)
#define	TMPSNS_CTRL1_TOG_FREQ_SHIFT   (0U)
#define	TMPSNS_CTRL1_TOG_FREQ(x)
#define	TMPSNS_CTRL1_TOG_FINISH_IE_MASK   (0x10000U)
#define	TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT   (16U)
#define	TMPSNS_CTRL1_TOG_FINISH_IE(x)
#define	TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK   (0x20000U)
#define	TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT   (17U)
#define	TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x)
#define	TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK   (0x40000U)
#define	TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT   (18U)
#define	TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x)
#define	TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK   (0x80000U)
#define	TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT   (19U)
#define	TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x)
#define	TMPSNS_CTRL1_TOG_START_MASK   (0x400000U)
#define	TMPSNS_CTRL1_TOG_START_SHIFT   (22U)
#define	TMPSNS_CTRL1_TOG_START(x)
#define	TMPSNS_CTRL1_TOG_PWD_MASK   (0x800000U)
#define	TMPSNS_CTRL1_TOG_PWD_SHIFT   (23U)
#define	TMPSNS_CTRL1_TOG_PWD(x)
#define	TMPSNS_CTRL1_TOG_RFU_MASK   (0x7F000000U)
#define	TMPSNS_CTRL1_TOG_RFU_SHIFT   (24U)
#define	TMPSNS_CTRL1_TOG_RFU(x)
#define	TMPSNS_CTRL1_TOG_PWD_FULL_MASK   (0x80000000U)
#define	TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT   (31U)
#define	TMPSNS_CTRL1_TOG_PWD_FULL(x)
RANGE0 - Temperature Sensor Range Register 0
#define	TMPSNS_RANGE0_LOW_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE0_LOW_TEMP_VAL(x)
#define	TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK   (0xFFF0000U)
#define	TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT   (16U)
#define	TMPSNS_RANGE0_HIGH_TEMP_VAL(x)
RANGE0_SET - Temperature Sensor Range Register 0
#define	TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x)
#define	TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK   (0xFFF0000U)
#define	TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT   (16U)
#define	TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x)
RANGE0_CLR - Temperature Sensor Range Register 0
#define	TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x)
#define	TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK   (0xFFF0000U)
#define	TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT   (16U)
#define	TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x)
RANGE0_TOG - Temperature Sensor Range Register 0
#define	TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x)
#define	TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK   (0xFFF0000U)
#define	TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT   (16U)
#define	TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x)
RANGE1 - Temperature Sensor Range Register 1
#define	TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE1_PANIC_TEMP_VAL(x)
RANGE1_SET - Temperature Sensor Range Register 1
#define	TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x)
RANGE1_CLR - Temperature Sensor Range Register 1
#define	TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x)
RANGE1_TOG - Temperature Sensor Range Register 1
#define	TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x)
STATUS0 - Temperature Sensor Status Register 0
#define	TMPSNS_STATUS0_TEMP_VAL_MASK   (0xFFFU)
#define	TMPSNS_STATUS0_TEMP_VAL_SHIFT   (0U)
#define	TMPSNS_STATUS0_TEMP_VAL(x)
#define	TMPSNS_STATUS0_FINISH_MASK   (0x10000U)
#define	TMPSNS_STATUS0_FINISH_SHIFT   (16U)
#define	TMPSNS_STATUS0_FINISH(x)
#define	TMPSNS_STATUS0_LOW_TEMP_MASK   (0x20000U)
#define	TMPSNS_STATUS0_LOW_TEMP_SHIFT   (17U)
#define	TMPSNS_STATUS0_LOW_TEMP(x)
#define	TMPSNS_STATUS0_HIGH_TEMP_MASK   (0x40000U)
#define	TMPSNS_STATUS0_HIGH_TEMP_SHIFT   (18U)
#define	TMPSNS_STATUS0_HIGH_TEMP(x)
#define	TMPSNS_STATUS0_PANIC_TEMP_MASK   (0x80000U)
#define	TMPSNS_STATUS0_PANIC_TEMP_SHIFT   (19U)
#define	TMPSNS_STATUS0_PANIC_TEMP(x)
COMP1 - Timer Channel Compare Register 1
#define	TMR_COMP1_COMPARISON_1_MASK   (0xFFFFU)
#define	TMR_COMP1_COMPARISON_1_SHIFT   (0U)
#define	TMR_COMP1_COMPARISON_1(x)
COMP2 - Timer Channel Compare Register 2
#define	TMR_COMP2_COMPARISON_2_MASK   (0xFFFFU)
#define	TMR_COMP2_COMPARISON_2_SHIFT   (0U)
#define	TMR_COMP2_COMPARISON_2(x)
CAPT - Timer Channel Capture Register
#define	TMR_CAPT_CAPTURE_MASK   (0xFFFFU)
#define	TMR_CAPT_CAPTURE_SHIFT   (0U)
#define	TMR_CAPT_CAPTURE(x)
LOAD - Timer Channel Load Register
#define	TMR_LOAD_LOAD_MASK   (0xFFFFU)
#define	TMR_LOAD_LOAD_SHIFT   (0U)
#define	TMR_LOAD_LOAD(x)
HOLD - Timer Channel Hold Register
#define	TMR_HOLD_HOLD_MASK   (0xFFFFU)
#define	TMR_HOLD_HOLD_SHIFT   (0U)
#define	TMR_HOLD_HOLD(x)
CNTR - Timer Channel Counter Register
#define	TMR_CNTR_COUNTER_MASK   (0xFFFFU)
#define	TMR_CNTR_COUNTER_SHIFT   (0U)
#define	TMR_CNTR_COUNTER(x)
CTRL - Timer Channel Control Register
#define	TMR_CTRL_OUTMODE_MASK   (0x7U)
#define	TMR_CTRL_OUTMODE_SHIFT   (0U)
#define	TMR_CTRL_OUTMODE(x)
#define	TMR_CTRL_COINIT_MASK   (0x8U)
#define	TMR_CTRL_COINIT_SHIFT   (3U)
#define	TMR_CTRL_COINIT(x)
#define	TMR_CTRL_DIR_MASK   (0x10U)
#define	TMR_CTRL_DIR_SHIFT   (4U)
#define	TMR_CTRL_DIR(x)
#define	TMR_CTRL_LENGTH_MASK   (0x20U)
#define	TMR_CTRL_LENGTH_SHIFT   (5U)
#define	TMR_CTRL_LENGTH(x)
#define	TMR_CTRL_ONCE_MASK   (0x40U)
#define	TMR_CTRL_ONCE_SHIFT   (6U)
#define	TMR_CTRL_ONCE(x)
#define	TMR_CTRL_SCS_MASK   (0x180U)
#define	TMR_CTRL_SCS_SHIFT   (7U)
#define	TMR_CTRL_SCS(x)
#define	TMR_CTRL_PCS_MASK   (0x1E00U)
#define	TMR_CTRL_PCS_SHIFT   (9U)
#define	TMR_CTRL_PCS(x)
#define	TMR_CTRL_CM_MASK   (0xE000U)
#define	TMR_CTRL_CM_SHIFT   (13U)
#define	TMR_CTRL_CM(x)
SCTRL - Timer Channel Status and Control Register
#define	TMR_SCTRL_OEN_MASK   (0x1U)
#define	TMR_SCTRL_OEN_SHIFT   (0U)
#define	TMR_SCTRL_OEN(x)
#define	TMR_SCTRL_OPS_MASK   (0x2U)
#define	TMR_SCTRL_OPS_SHIFT   (1U)
#define	TMR_SCTRL_OPS(x)
#define	TMR_SCTRL_FORCE_MASK   (0x4U)
#define	TMR_SCTRL_FORCE_SHIFT   (2U)
#define	TMR_SCTRL_FORCE(x)
#define	TMR_SCTRL_VAL_MASK   (0x8U)
#define	TMR_SCTRL_VAL_SHIFT   (3U)
#define	TMR_SCTRL_VAL(x)
#define	TMR_SCTRL_EEOF_MASK   (0x10U)
#define	TMR_SCTRL_EEOF_SHIFT   (4U)
#define	TMR_SCTRL_EEOF(x)
#define	TMR_SCTRL_MSTR_MASK   (0x20U)
#define	TMR_SCTRL_MSTR_SHIFT   (5U)
#define	TMR_SCTRL_MSTR(x)
#define	TMR_SCTRL_CAPTURE_MODE_MASK   (0xC0U)
#define	TMR_SCTRL_CAPTURE_MODE_SHIFT   (6U)
#define	TMR_SCTRL_CAPTURE_MODE(x)
#define	TMR_SCTRL_INPUT_MASK   (0x100U)
#define	TMR_SCTRL_INPUT_SHIFT   (8U)
#define	TMR_SCTRL_INPUT(x)
#define	TMR_SCTRL_IPS_MASK   (0x200U)
#define	TMR_SCTRL_IPS_SHIFT   (9U)
#define	TMR_SCTRL_IPS(x)
#define	TMR_SCTRL_IEFIE_MASK   (0x400U)
#define	TMR_SCTRL_IEFIE_SHIFT   (10U)
#define	TMR_SCTRL_IEFIE(x)
#define	TMR_SCTRL_IEF_MASK   (0x800U)
#define	TMR_SCTRL_IEF_SHIFT   (11U)
#define	TMR_SCTRL_IEF(x)
#define	TMR_SCTRL_TOFIE_MASK   (0x1000U)
#define	TMR_SCTRL_TOFIE_SHIFT   (12U)
#define	TMR_SCTRL_TOFIE(x)
#define	TMR_SCTRL_TOF_MASK   (0x2000U)
#define	TMR_SCTRL_TOF_SHIFT   (13U)
#define	TMR_SCTRL_TOF(x)
#define	TMR_SCTRL_TCFIE_MASK   (0x4000U)
#define	TMR_SCTRL_TCFIE_SHIFT   (14U)
#define	TMR_SCTRL_TCFIE(x)
#define	TMR_SCTRL_TCF_MASK   (0x8000U)
#define	TMR_SCTRL_TCF_SHIFT   (15U)
#define	TMR_SCTRL_TCF(x)
CMPLD1 - Timer Channel Comparator Load Register 1
#define	TMR_CMPLD1_COMPARATOR_LOAD_1_MASK   (0xFFFFU)
#define	TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT   (0U)
#define	TMR_CMPLD1_COMPARATOR_LOAD_1(x)
CMPLD2 - Timer Channel Comparator Load Register 2
#define	TMR_CMPLD2_COMPARATOR_LOAD_2_MASK   (0xFFFFU)
#define	TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT   (0U)
#define	TMR_CMPLD2_COMPARATOR_LOAD_2(x)
CSCTRL - Timer Channel Comparator Status and Control Register
#define	TMR_CSCTRL_CL1_MASK   (0x3U)
#define	TMR_CSCTRL_CL1_SHIFT   (0U)
#define	TMR_CSCTRL_CL1(x)
#define	TMR_CSCTRL_CL2_MASK   (0xCU)
#define	TMR_CSCTRL_CL2_SHIFT   (2U)
#define	TMR_CSCTRL_CL2(x)
#define	TMR_CSCTRL_TCF1_MASK   (0x10U)
#define	TMR_CSCTRL_TCF1_SHIFT   (4U)
#define	TMR_CSCTRL_TCF1(x)
#define	TMR_CSCTRL_TCF2_MASK   (0x20U)
#define	TMR_CSCTRL_TCF2_SHIFT   (5U)
#define	TMR_CSCTRL_TCF2(x)
#define	TMR_CSCTRL_TCF1EN_MASK   (0x40U)
#define	TMR_CSCTRL_TCF1EN_SHIFT   (6U)
#define	TMR_CSCTRL_TCF1EN(x)
#define	TMR_CSCTRL_TCF2EN_MASK   (0x80U)
#define	TMR_CSCTRL_TCF2EN_SHIFT   (7U)
#define	TMR_CSCTRL_TCF2EN(x)
#define	TMR_CSCTRL_UP_MASK   (0x200U)
#define	TMR_CSCTRL_UP_SHIFT   (9U)
#define	TMR_CSCTRL_UP(x)
#define	TMR_CSCTRL_TCI_MASK   (0x400U)
#define	TMR_CSCTRL_TCI_SHIFT   (10U)
#define	TMR_CSCTRL_TCI(x)
#define	TMR_CSCTRL_ROC_MASK   (0x800U)
#define	TMR_CSCTRL_ROC_SHIFT   (11U)
#define	TMR_CSCTRL_ROC(x)
#define	TMR_CSCTRL_ALT_LOAD_MASK   (0x1000U)
#define	TMR_CSCTRL_ALT_LOAD_SHIFT   (12U)
#define	TMR_CSCTRL_ALT_LOAD(x)
#define	TMR_CSCTRL_FAULT_MASK   (0x2000U)
#define	TMR_CSCTRL_FAULT_SHIFT   (13U)
#define	TMR_CSCTRL_FAULT(x)
#define	TMR_CSCTRL_DBG_EN_MASK   (0xC000U)
#define	TMR_CSCTRL_DBG_EN_SHIFT   (14U)
#define	TMR_CSCTRL_DBG_EN(x)
FILT - Timer Channel Input Filter Register
#define	TMR_FILT_FILT_PER_MASK   (0xFFU)
#define	TMR_FILT_FILT_PER_SHIFT   (0U)
#define	TMR_FILT_FILT_PER(x)
#define	TMR_FILT_FILT_CNT_MASK   (0x700U)
#define	TMR_FILT_FILT_CNT_SHIFT   (8U)
#define	TMR_FILT_FILT_CNT(x)
DMA - Timer Channel DMA Enable Register
#define	TMR_DMA_IEFDE_MASK   (0x1U)
#define	TMR_DMA_IEFDE_SHIFT   (0U)
#define	TMR_DMA_IEFDE(x)
#define	TMR_DMA_CMPLD1DE_MASK   (0x2U)
#define	TMR_DMA_CMPLD1DE_SHIFT   (1U)
#define	TMR_DMA_CMPLD1DE(x)
#define	TMR_DMA_CMPLD2DE_MASK   (0x4U)
#define	TMR_DMA_CMPLD2DE_SHIFT   (2U)
#define	TMR_DMA_CMPLD2DE(x)
ENBL - Timer Channel Enable Register
#define	TMR_ENBL_ENBL_MASK   (0xFU)
#define	TMR_ENBL_ENBL_SHIFT   (0U)
#define	TMR_ENBL_ENBL(x)
ID - Identification register
#define	USB_ID_ID_MASK   (0x3FU)
#define	USB_ID_ID_SHIFT   (0U)
#define	USB_ID_ID(x)
#define	USB_ID_NID_MASK   (0x3F00U)
#define	USB_ID_NID_SHIFT   (8U)
#define	USB_ID_NID(x)
#define	USB_ID_REVISION_MASK   (0xFF0000U)
#define	USB_ID_REVISION_SHIFT   (16U)
#define	USB_ID_REVISION(x)
HWGENERAL - Hardware General
#define	USB_HWGENERAL_PHYW_MASK   (0x30U)
#define	USB_HWGENERAL_PHYW_SHIFT   (4U)
#define	USB_HWGENERAL_PHYW(x)
#define	USB_HWGENERAL_PHYM_MASK   (0x1C0U)
#define	USB_HWGENERAL_PHYM_SHIFT   (6U)
#define	USB_HWGENERAL_PHYM(x)
#define	USB_HWGENERAL_SM_MASK   (0x600U)
#define	USB_HWGENERAL_SM_SHIFT   (9U)
#define	USB_HWGENERAL_SM(x)
HWHOST - Host Hardware Parameters
#define	USB_HWHOST_HC_MASK   (0x1U)
#define	USB_HWHOST_HC_SHIFT   (0U)
#define	USB_HWHOST_HC(x)
#define	USB_HWHOST_NPORT_MASK   (0xEU)
#define	USB_HWHOST_NPORT_SHIFT   (1U)
#define	USB_HWHOST_NPORT(x)
HWDEVICE - Device Hardware Parameters
#define	USB_HWDEVICE_DC_MASK   (0x1U)
#define	USB_HWDEVICE_DC_SHIFT   (0U)
#define	USB_HWDEVICE_DC(x)
#define	USB_HWDEVICE_DEVEP_MASK   (0x3EU)
#define	USB_HWDEVICE_DEVEP_SHIFT   (1U)
#define	USB_HWDEVICE_DEVEP(x)
HWTXBUF - TX Buffer Hardware Parameters
#define	USB_HWTXBUF_TXBURST_MASK   (0xFFU)
#define	USB_HWTXBUF_TXBURST_SHIFT   (0U)
#define	USB_HWTXBUF_TXBURST(x)
#define	USB_HWTXBUF_TXCHANADD_MASK   (0xFF0000U)
#define	USB_HWTXBUF_TXCHANADD_SHIFT   (16U)
#define	USB_HWTXBUF_TXCHANADD(x)
HWRXBUF - RX Buffer Hardware Parameters
#define	USB_HWRXBUF_RXBURST_MASK   (0xFFU)
#define	USB_HWRXBUF_RXBURST_SHIFT   (0U)
#define	USB_HWRXBUF_RXBURST(x)
#define	USB_HWRXBUF_RXADD_MASK   (0xFF00U)
#define	USB_HWRXBUF_RXADD_SHIFT   (8U)
#define	USB_HWRXBUF_RXADD(x)
GPTIMER0LD - General Purpose Timer #0 Load
#define	USB_GPTIMER0LD_GPTLD_MASK   (0xFFFFFFU)
#define	USB_GPTIMER0LD_GPTLD_SHIFT   (0U)
#define	USB_GPTIMER0LD_GPTLD(x)
GPTIMER0CTRL - General Purpose Timer #0 Controller
#define	USB_GPTIMER0CTRL_GPTCNT_MASK   (0xFFFFFFU)
#define	USB_GPTIMER0CTRL_GPTCNT_SHIFT   (0U)
#define	USB_GPTIMER0CTRL_GPTCNT(x)
#define	USB_GPTIMER0CTRL_GPTMODE_MASK   (0x1000000U)
#define	USB_GPTIMER0CTRL_GPTMODE_SHIFT   (24U)
#define	USB_GPTIMER0CTRL_GPTMODE(x)
#define	USB_GPTIMER0CTRL_GPTRST_MASK   (0x40000000U)
#define	USB_GPTIMER0CTRL_GPTRST_SHIFT   (30U)
#define	USB_GPTIMER0CTRL_GPTRST(x)
#define	USB_GPTIMER0CTRL_GPTRUN_MASK   (0x80000000U)
#define	USB_GPTIMER0CTRL_GPTRUN_SHIFT   (31U)
#define	USB_GPTIMER0CTRL_GPTRUN(x)
GPTIMER1LD - General Purpose Timer #1 Load
#define	USB_GPTIMER1LD_GPTLD_MASK   (0xFFFFFFU)
#define	USB_GPTIMER1LD_GPTLD_SHIFT   (0U)
#define	USB_GPTIMER1LD_GPTLD(x)
GPTIMER1CTRL - General Purpose Timer #1 Controller
#define	USB_GPTIMER1CTRL_GPTCNT_MASK   (0xFFFFFFU)
#define	USB_GPTIMER1CTRL_GPTCNT_SHIFT   (0U)
#define	USB_GPTIMER1CTRL_GPTCNT(x)
#define	USB_GPTIMER1CTRL_GPTMODE_MASK   (0x1000000U)
#define	USB_GPTIMER1CTRL_GPTMODE_SHIFT   (24U)
#define	USB_GPTIMER1CTRL_GPTMODE(x)
#define	USB_GPTIMER1CTRL_GPTRST_MASK   (0x40000000U)
#define	USB_GPTIMER1CTRL_GPTRST_SHIFT   (30U)
#define	USB_GPTIMER1CTRL_GPTRST(x)
#define	USB_GPTIMER1CTRL_GPTRUN_MASK   (0x80000000U)
#define	USB_GPTIMER1CTRL_GPTRUN_SHIFT   (31U)
#define	USB_GPTIMER1CTRL_GPTRUN(x)
SBUSCFG - System Bus Config
#define	USB_SBUSCFG_AHBBRST_MASK   (0x7U)
#define	USB_SBUSCFG_AHBBRST_SHIFT   (0U)
#define	USB_SBUSCFG_AHBBRST(x)
CAPLENGTH - Capability Registers Length
#define	USB_CAPLENGTH_CAPLENGTH_MASK   (0xFFU)
#define	USB_CAPLENGTH_CAPLENGTH_SHIFT   (0U)
#define	USB_CAPLENGTH_CAPLENGTH(x)
HCIVERSION - Host Controller Interface Version
#define	USB_HCIVERSION_HCIVERSION_MASK   (0xFFFFU)
#define	USB_HCIVERSION_HCIVERSION_SHIFT   (0U)
#define	USB_HCIVERSION_HCIVERSION(x)
HCSPARAMS - Host Controller Structural Parameters
#define	USB_HCSPARAMS_N_PORTS_MASK   (0xFU)
#define	USB_HCSPARAMS_N_PORTS_SHIFT   (0U)
#define	USB_HCSPARAMS_N_PORTS(x)
#define	USB_HCSPARAMS_PPC_MASK   (0x10U)
#define	USB_HCSPARAMS_PPC_SHIFT   (4U)
#define	USB_HCSPARAMS_PPC(x)
#define	USB_HCSPARAMS_N_PCC_MASK   (0xF00U)
#define	USB_HCSPARAMS_N_PCC_SHIFT   (8U)
#define	USB_HCSPARAMS_N_PCC(x)
#define	USB_HCSPARAMS_N_CC_MASK   (0xF000U)
#define	USB_HCSPARAMS_N_CC_SHIFT   (12U)
#define	USB_HCSPARAMS_N_CC(x)
#define	USB_HCSPARAMS_PI_MASK   (0x10000U)
#define	USB_HCSPARAMS_PI_SHIFT   (16U)
#define	USB_HCSPARAMS_PI(x)
#define	USB_HCSPARAMS_N_PTT_MASK   (0xF00000U)
#define	USB_HCSPARAMS_N_PTT_SHIFT   (20U)
#define	USB_HCSPARAMS_N_PTT(x)
#define	USB_HCSPARAMS_N_TT_MASK   (0xF000000U)
#define	USB_HCSPARAMS_N_TT_SHIFT   (24U)
#define	USB_HCSPARAMS_N_TT(x)
HCCPARAMS - Host Controller Capability Parameters
#define	USB_HCCPARAMS_ADC_MASK   (0x1U)
#define	USB_HCCPARAMS_ADC_SHIFT   (0U)
#define	USB_HCCPARAMS_ADC(x)
#define	USB_HCCPARAMS_PFL_MASK   (0x2U)
#define	USB_HCCPARAMS_PFL_SHIFT   (1U)
#define	USB_HCCPARAMS_PFL(x)
#define	USB_HCCPARAMS_ASP_MASK   (0x4U)
#define	USB_HCCPARAMS_ASP_SHIFT   (2U)
#define	USB_HCCPARAMS_ASP(x)
#define	USB_HCCPARAMS_IST_MASK   (0xF0U)
#define	USB_HCCPARAMS_IST_SHIFT   (4U)
#define	USB_HCCPARAMS_IST(x)
#define	USB_HCCPARAMS_EECP_MASK   (0xFF00U)
#define	USB_HCCPARAMS_EECP_SHIFT   (8U)
#define	USB_HCCPARAMS_EECP(x)
DCIVERSION - Device Controller Interface Version
#define	USB_DCIVERSION_DCIVERSION_MASK   (0xFFFFU)
#define	USB_DCIVERSION_DCIVERSION_SHIFT   (0U)
#define	USB_DCIVERSION_DCIVERSION(x)
DCCPARAMS - Device Controller Capability Parameters
#define	USB_DCCPARAMS_DEN_MASK   (0x1FU)
#define	USB_DCCPARAMS_DEN_SHIFT   (0U)
#define	USB_DCCPARAMS_DEN(x)
#define	USB_DCCPARAMS_DC_MASK   (0x80U)
#define	USB_DCCPARAMS_DC_SHIFT   (7U)
#define	USB_DCCPARAMS_DC(x)
#define	USB_DCCPARAMS_HC_MASK   (0x100U)
#define	USB_DCCPARAMS_HC_SHIFT   (8U)
#define	USB_DCCPARAMS_HC(x)
USBCMD - USB Command Register
#define	USB_USBCMD_RS_MASK   (0x1U)
#define	USB_USBCMD_RS_SHIFT   (0U)
#define	USB_USBCMD_RS(x)
#define	USB_USBCMD_RST_MASK   (0x2U)
#define	USB_USBCMD_RST_SHIFT   (1U)
#define	USB_USBCMD_RST(x)
#define	USB_USBCMD_FS_1_MASK   (0xCU)
#define	USB_USBCMD_FS_1_SHIFT   (2U)
#define	USB_USBCMD_FS_1(x)
#define	USB_USBCMD_PSE_MASK   (0x10U)
#define	USB_USBCMD_PSE_SHIFT   (4U)
#define	USB_USBCMD_PSE(x)
#define	USB_USBCMD_ASE_MASK   (0x20U)
#define	USB_USBCMD_ASE_SHIFT   (5U)
#define	USB_USBCMD_ASE(x)
#define	USB_USBCMD_IAA_MASK   (0x40U)
#define	USB_USBCMD_IAA_SHIFT   (6U)
#define	USB_USBCMD_IAA(x)
#define	USB_USBCMD_ASP_MASK   (0x300U)
#define	USB_USBCMD_ASP_SHIFT   (8U)
#define	USB_USBCMD_ASP(x)
#define	USB_USBCMD_ASPE_MASK   (0x800U)
#define	USB_USBCMD_ASPE_SHIFT   (11U)
#define	USB_USBCMD_ASPE(x)
#define	USB_USBCMD_SUTW_MASK   (0x2000U)
#define	USB_USBCMD_SUTW_SHIFT   (13U)
#define	USB_USBCMD_SUTW(x)
#define	USB_USBCMD_ATDTW_MASK   (0x4000U)
#define	USB_USBCMD_ATDTW_SHIFT   (14U)
#define	USB_USBCMD_ATDTW(x)
#define	USB_USBCMD_FS_2_MASK   (0x8000U)
#define	USB_USBCMD_FS_2_SHIFT   (15U)
#define	USB_USBCMD_FS_2(x)
#define	USB_USBCMD_ITC_MASK   (0xFF0000U)
#define	USB_USBCMD_ITC_SHIFT   (16U)
#define	USB_USBCMD_ITC(x)
USBSTS - USB Status Register
#define	USB_USBSTS_UI_MASK   (0x1U)
#define	USB_USBSTS_UI_SHIFT   (0U)
#define	USB_USBSTS_UI(x)
#define	USB_USBSTS_UEI_MASK   (0x2U)
#define	USB_USBSTS_UEI_SHIFT   (1U)
#define	USB_USBSTS_UEI(x)
#define	USB_USBSTS_PCI_MASK   (0x4U)
#define	USB_USBSTS_PCI_SHIFT   (2U)
#define	USB_USBSTS_PCI(x)
#define	USB_USBSTS_FRI_MASK   (0x8U)
#define	USB_USBSTS_FRI_SHIFT   (3U)
#define	USB_USBSTS_FRI(x)
#define	USB_USBSTS_SEI_MASK   (0x10U)
#define	USB_USBSTS_SEI_SHIFT   (4U)
#define	USB_USBSTS_SEI(x)
#define	USB_USBSTS_AAI_MASK   (0x20U)
#define	USB_USBSTS_AAI_SHIFT   (5U)
#define	USB_USBSTS_AAI(x)
#define	USB_USBSTS_URI_MASK   (0x40U)
#define	USB_USBSTS_URI_SHIFT   (6U)
#define	USB_USBSTS_URI(x)
#define	USB_USBSTS_SRI_MASK   (0x80U)
#define	USB_USBSTS_SRI_SHIFT   (7U)
#define	USB_USBSTS_SRI(x)
#define	USB_USBSTS_SLI_MASK   (0x100U)
#define	USB_USBSTS_SLI_SHIFT   (8U)
#define	USB_USBSTS_SLI(x)
#define	USB_USBSTS_ULPII_MASK   (0x400U)
#define	USB_USBSTS_ULPII_SHIFT   (10U)
#define	USB_USBSTS_ULPII(x)
#define	USB_USBSTS_HCH_MASK   (0x1000U)
#define	USB_USBSTS_HCH_SHIFT   (12U)
#define	USB_USBSTS_HCH(x)
#define	USB_USBSTS_RCL_MASK   (0x2000U)
#define	USB_USBSTS_RCL_SHIFT   (13U)
#define	USB_USBSTS_RCL(x)
#define	USB_USBSTS_PS_MASK   (0x4000U)
#define	USB_USBSTS_PS_SHIFT   (14U)
#define	USB_USBSTS_PS(x)
#define	USB_USBSTS_AS_MASK   (0x8000U)
#define	USB_USBSTS_AS_SHIFT   (15U)
#define	USB_USBSTS_AS(x)
#define	USB_USBSTS_NAKI_MASK   (0x10000U)
#define	USB_USBSTS_NAKI_SHIFT   (16U)
#define	USB_USBSTS_NAKI(x)
#define	USB_USBSTS_TI0_MASK   (0x1000000U)
#define	USB_USBSTS_TI0_SHIFT   (24U)
#define	USB_USBSTS_TI0(x)
#define	USB_USBSTS_TI1_MASK   (0x2000000U)
#define	USB_USBSTS_TI1_SHIFT   (25U)
#define	USB_USBSTS_TI1(x)
USBINTR - Interrupt Enable Register
#define	USB_USBINTR_UE_MASK   (0x1U)
#define	USB_USBINTR_UE_SHIFT   (0U)
#define	USB_USBINTR_UE(x)
#define	USB_USBINTR_UEE_MASK   (0x2U)
#define	USB_USBINTR_UEE_SHIFT   (1U)
#define	USB_USBINTR_UEE(x)
#define	USB_USBINTR_PCE_MASK   (0x4U)
#define	USB_USBINTR_PCE_SHIFT   (2U)
#define	USB_USBINTR_PCE(x)
#define	USB_USBINTR_FRE_MASK   (0x8U)
#define	USB_USBINTR_FRE_SHIFT   (3U)
#define	USB_USBINTR_FRE(x)
#define	USB_USBINTR_SEE_MASK   (0x10U)
#define	USB_USBINTR_SEE_SHIFT   (4U)
#define	USB_USBINTR_SEE(x)
#define	USB_USBINTR_AAE_MASK   (0x20U)
#define	USB_USBINTR_AAE_SHIFT   (5U)
#define	USB_USBINTR_AAE(x)
#define	USB_USBINTR_URE_MASK   (0x40U)
#define	USB_USBINTR_URE_SHIFT   (6U)
#define	USB_USBINTR_URE(x)
#define	USB_USBINTR_SRE_MASK   (0x80U)
#define	USB_USBINTR_SRE_SHIFT   (7U)
#define	USB_USBINTR_SRE(x)
#define	USB_USBINTR_SLE_MASK   (0x100U)
#define	USB_USBINTR_SLE_SHIFT   (8U)
#define	USB_USBINTR_SLE(x)
#define	USB_USBINTR_ULPIE_MASK   (0x400U)
#define	USB_USBINTR_ULPIE_SHIFT   (10U)
#define	USB_USBINTR_ULPIE(x)
#define	USB_USBINTR_NAKE_MASK   (0x10000U)
#define	USB_USBINTR_NAKE_SHIFT   (16U)
#define	USB_USBINTR_NAKE(x)
#define	USB_USBINTR_UAIE_MASK   (0x40000U)
#define	USB_USBINTR_UAIE_SHIFT   (18U)
#define	USB_USBINTR_UAIE(x)
#define	USB_USBINTR_UPIE_MASK   (0x80000U)
#define	USB_USBINTR_UPIE_SHIFT   (19U)
#define	USB_USBINTR_UPIE(x)
#define	USB_USBINTR_TIE0_MASK   (0x1000000U)
#define	USB_USBINTR_TIE0_SHIFT   (24U)
#define	USB_USBINTR_TIE0(x)
#define	USB_USBINTR_TIE1_MASK   (0x2000000U)
#define	USB_USBINTR_TIE1_SHIFT   (25U)
#define	USB_USBINTR_TIE1(x)
FRINDEX - USB Frame Index
#define	USB_FRINDEX_FRINDEX_MASK   (0x3FFFU)
#define	USB_FRINDEX_FRINDEX_SHIFT   (0U)
#define	USB_FRINDEX_FRINDEX(x)
DEVICEADDR - Device Address
#define	USB_DEVICEADDR_USBADRA_MASK   (0x1000000U)
#define	USB_DEVICEADDR_USBADRA_SHIFT   (24U)
#define	USB_DEVICEADDR_USBADRA(x)
#define	USB_DEVICEADDR_USBADR_MASK   (0xFE000000U)
#define	USB_DEVICEADDR_USBADR_SHIFT   (25U)
#define	USB_DEVICEADDR_USBADR(x)
PERIODICLISTBASE - Frame List Base Address
#define	USB_PERIODICLISTBASE_BASEADR_MASK   (0xFFFFF000U)
#define	USB_PERIODICLISTBASE_BASEADR_SHIFT   (12U)
#define	USB_PERIODICLISTBASE_BASEADR(x)
ASYNCLISTADDR - Next Asynch. Address
#define	USB_ASYNCLISTADDR_ASYBASE_MASK   (0xFFFFFFE0U)
#define	USB_ASYNCLISTADDR_ASYBASE_SHIFT   (5U)
#define	USB_ASYNCLISTADDR_ASYBASE(x)
ENDPTLISTADDR - Endpoint List Address
#define	USB_ENDPTLISTADDR_EPBASE_MASK   (0xFFFFF800U)
#define	USB_ENDPTLISTADDR_EPBASE_SHIFT   (11U)
#define	USB_ENDPTLISTADDR_EPBASE(x)
BURSTSIZE - Programmable Burst Size
#define	USB_BURSTSIZE_RXPBURST_MASK   (0xFFU)
#define	USB_BURSTSIZE_RXPBURST_SHIFT   (0U)
#define	USB_BURSTSIZE_RXPBURST(x)
#define	USB_BURSTSIZE_TXPBURST_MASK   (0x1FF00U)
#define	USB_BURSTSIZE_TXPBURST_SHIFT   (8U)
#define	USB_BURSTSIZE_TXPBURST(x)
TXFILLTUNING - TX FIFO Fill Tuning
#define	USB_TXFILLTUNING_TXSCHOH_MASK   (0xFFU)
#define	USB_TXFILLTUNING_TXSCHOH_SHIFT   (0U)
#define	USB_TXFILLTUNING_TXSCHOH(x)
#define	USB_TXFILLTUNING_TXSCHHEALTH_MASK   (0x1F00U)
#define	USB_TXFILLTUNING_TXSCHHEALTH_SHIFT   (8U)
#define	USB_TXFILLTUNING_TXSCHHEALTH(x)
#define	USB_TXFILLTUNING_TXFIFOTHRES_MASK   (0x3F0000U)
#define	USB_TXFILLTUNING_TXFIFOTHRES_SHIFT   (16U)
#define	USB_TXFILLTUNING_TXFIFOTHRES(x)
ENDPTNAK - Endpoint NAK
#define	USB_ENDPTNAK_EPRN_MASK   (0xFFU)
#define	USB_ENDPTNAK_EPRN_SHIFT   (0U)
#define	USB_ENDPTNAK_EPRN(x)
#define	USB_ENDPTNAK_EPTN_MASK   (0xFF0000U)
#define	USB_ENDPTNAK_EPTN_SHIFT   (16U)
#define	USB_ENDPTNAK_EPTN(x)
ENDPTNAKEN - Endpoint NAK Enable
#define	USB_ENDPTNAKEN_EPRNE_MASK   (0xFFU)
#define	USB_ENDPTNAKEN_EPRNE_SHIFT   (0U)
#define	USB_ENDPTNAKEN_EPRNE(x)
#define	USB_ENDPTNAKEN_EPTNE_MASK   (0xFF0000U)
#define	USB_ENDPTNAKEN_EPTNE_SHIFT   (16U)
#define	USB_ENDPTNAKEN_EPTNE(x)
CONFIGFLAG - Configure Flag Register
#define	USB_CONFIGFLAG_CF_MASK   (0x1U)
#define	USB_CONFIGFLAG_CF_SHIFT   (0U)
#define	USB_CONFIGFLAG_CF(x)
PORTSC1 - Port Status & Control
#define	USB_PORTSC1_CCS_MASK   (0x1U)
#define	USB_PORTSC1_CCS_SHIFT   (0U)
#define	USB_PORTSC1_CCS(x)
#define	USB_PORTSC1_CSC_MASK   (0x2U)
#define	USB_PORTSC1_CSC_SHIFT   (1U)
#define	USB_PORTSC1_CSC(x)
#define	USB_PORTSC1_PE_MASK   (0x4U)
#define	USB_PORTSC1_PE_SHIFT   (2U)
#define	USB_PORTSC1_PE(x)
#define	USB_PORTSC1_PEC_MASK   (0x8U)
#define	USB_PORTSC1_PEC_SHIFT   (3U)
#define	USB_PORTSC1_PEC(x)
#define	USB_PORTSC1_OCA_MASK   (0x10U)
#define	USB_PORTSC1_OCA_SHIFT   (4U)
#define	USB_PORTSC1_OCA(x)
#define	USB_PORTSC1_OCC_MASK   (0x20U)
#define	USB_PORTSC1_OCC_SHIFT   (5U)
#define	USB_PORTSC1_OCC(x)
#define	USB_PORTSC1_FPR_MASK   (0x40U)
#define	USB_PORTSC1_FPR_SHIFT   (6U)
#define	USB_PORTSC1_FPR(x)
#define	USB_PORTSC1_SUSP_MASK   (0x80U)
#define	USB_PORTSC1_SUSP_SHIFT   (7U)
#define	USB_PORTSC1_SUSP(x)
#define	USB_PORTSC1_PR_MASK   (0x100U)
#define	USB_PORTSC1_PR_SHIFT   (8U)
#define	USB_PORTSC1_PR(x)
#define	USB_PORTSC1_HSP_MASK   (0x200U)
#define	USB_PORTSC1_HSP_SHIFT   (9U)
#define	USB_PORTSC1_HSP(x)
#define	USB_PORTSC1_LS_MASK   (0xC00U)
#define	USB_PORTSC1_LS_SHIFT   (10U)
#define	USB_PORTSC1_LS(x)
#define	USB_PORTSC1_PP_MASK   (0x1000U)
#define	USB_PORTSC1_PP_SHIFT   (12U)
#define	USB_PORTSC1_PP(x)
#define	USB_PORTSC1_PO_MASK   (0x2000U)
#define	USB_PORTSC1_PO_SHIFT   (13U)
#define	USB_PORTSC1_PO(x)
#define	USB_PORTSC1_PIC_MASK   (0xC000U)
#define	USB_PORTSC1_PIC_SHIFT   (14U)
#define	USB_PORTSC1_PIC(x)
#define	USB_PORTSC1_PTC_MASK   (0xF0000U)
#define	USB_PORTSC1_PTC_SHIFT   (16U)
#define	USB_PORTSC1_PTC(x)
#define	USB_PORTSC1_WKCN_MASK   (0x100000U)
#define	USB_PORTSC1_WKCN_SHIFT   (20U)
#define	USB_PORTSC1_WKCN(x)
#define	USB_PORTSC1_WKDC_MASK   (0x200000U)
#define	USB_PORTSC1_WKDC_SHIFT   (21U)
#define	USB_PORTSC1_WKDC(x)
#define	USB_PORTSC1_WKOC_MASK   (0x400000U)
#define	USB_PORTSC1_WKOC_SHIFT   (22U)
#define	USB_PORTSC1_WKOC(x)
#define	USB_PORTSC1_PHCD_MASK   (0x800000U)
#define	USB_PORTSC1_PHCD_SHIFT   (23U)
#define	USB_PORTSC1_PHCD(x)
#define	USB_PORTSC1_PFSC_MASK   (0x1000000U)
#define	USB_PORTSC1_PFSC_SHIFT   (24U)
#define	USB_PORTSC1_PFSC(x)
#define	USB_PORTSC1_PTS_2_MASK   (0x2000000U)
#define	USB_PORTSC1_PTS_2_SHIFT   (25U)
#define	USB_PORTSC1_PTS_2(x)
#define	USB_PORTSC1_PSPD_MASK   (0xC000000U)
#define	USB_PORTSC1_PSPD_SHIFT   (26U)
#define	USB_PORTSC1_PSPD(x)
#define	USB_PORTSC1_PTW_MASK   (0x10000000U)
#define	USB_PORTSC1_PTW_SHIFT   (28U)
#define	USB_PORTSC1_PTW(x)
#define	USB_PORTSC1_STS_MASK   (0x20000000U)
#define	USB_PORTSC1_STS_SHIFT   (29U)
#define	USB_PORTSC1_STS(x)
#define	USB_PORTSC1_PTS_1_MASK   (0xC0000000U)
#define	USB_PORTSC1_PTS_1_SHIFT   (30U)
#define	USB_PORTSC1_PTS_1(x)
OTGSC - On-The-Go Status & control
#define	USB_OTGSC_VD_MASK   (0x1U)
#define	USB_OTGSC_VD_SHIFT   (0U)
#define	USB_OTGSC_VD(x)
#define	USB_OTGSC_VC_MASK   (0x2U)
#define	USB_OTGSC_VC_SHIFT   (1U)
#define	USB_OTGSC_VC(x)
#define	USB_OTGSC_OT_MASK   (0x8U)
#define	USB_OTGSC_OT_SHIFT   (3U)
#define	USB_OTGSC_OT(x)
#define	USB_OTGSC_DP_MASK   (0x10U)
#define	USB_OTGSC_DP_SHIFT   (4U)
#define	USB_OTGSC_DP(x)
#define	USB_OTGSC_IDPU_MASK   (0x20U)
#define	USB_OTGSC_IDPU_SHIFT   (5U)
#define	USB_OTGSC_IDPU(x)
#define	USB_OTGSC_ID_MASK   (0x100U)
#define	USB_OTGSC_ID_SHIFT   (8U)
#define	USB_OTGSC_ID(x)
#define	USB_OTGSC_AVV_MASK   (0x200U)
#define	USB_OTGSC_AVV_SHIFT   (9U)
#define	USB_OTGSC_AVV(x)
#define	USB_OTGSC_ASV_MASK   (0x400U)
#define	USB_OTGSC_ASV_SHIFT   (10U)
#define	USB_OTGSC_ASV(x)
#define	USB_OTGSC_BSV_MASK   (0x800U)
#define	USB_OTGSC_BSV_SHIFT   (11U)
#define	USB_OTGSC_BSV(x)
#define	USB_OTGSC_BSE_MASK   (0x1000U)
#define	USB_OTGSC_BSE_SHIFT   (12U)
#define	USB_OTGSC_BSE(x)
#define	USB_OTGSC_TOG_1MS_MASK   (0x2000U)
#define	USB_OTGSC_TOG_1MS_SHIFT   (13U)
#define	USB_OTGSC_TOG_1MS(x)
#define	USB_OTGSC_DPS_MASK   (0x4000U)
#define	USB_OTGSC_DPS_SHIFT   (14U)
#define	USB_OTGSC_DPS(x)
#define	USB_OTGSC_IDIS_MASK   (0x10000U)
#define	USB_OTGSC_IDIS_SHIFT   (16U)
#define	USB_OTGSC_IDIS(x)
#define	USB_OTGSC_AVVIS_MASK   (0x20000U)
#define	USB_OTGSC_AVVIS_SHIFT   (17U)
#define	USB_OTGSC_AVVIS(x)
#define	USB_OTGSC_ASVIS_MASK   (0x40000U)
#define	USB_OTGSC_ASVIS_SHIFT   (18U)
#define	USB_OTGSC_ASVIS(x)
#define	USB_OTGSC_BSVIS_MASK   (0x80000U)
#define	USB_OTGSC_BSVIS_SHIFT   (19U)
#define	USB_OTGSC_BSVIS(x)
#define	USB_OTGSC_BSEIS_MASK   (0x100000U)
#define	USB_OTGSC_BSEIS_SHIFT   (20U)
#define	USB_OTGSC_BSEIS(x)
#define	USB_OTGSC_STATUS_1MS_MASK   (0x200000U)
#define	USB_OTGSC_STATUS_1MS_SHIFT   (21U)
#define	USB_OTGSC_STATUS_1MS(x)
#define	USB_OTGSC_DPIS_MASK   (0x400000U)
#define	USB_OTGSC_DPIS_SHIFT   (22U)
#define	USB_OTGSC_DPIS(x)
#define	USB_OTGSC_IDIE_MASK   (0x1000000U)
#define	USB_OTGSC_IDIE_SHIFT   (24U)
#define	USB_OTGSC_IDIE(x)
#define	USB_OTGSC_AVVIE_MASK   (0x2000000U)
#define	USB_OTGSC_AVVIE_SHIFT   (25U)
#define	USB_OTGSC_AVVIE(x)
#define	USB_OTGSC_ASVIE_MASK   (0x4000000U)
#define	USB_OTGSC_ASVIE_SHIFT   (26U)
#define	USB_OTGSC_ASVIE(x)
#define	USB_OTGSC_BSVIE_MASK   (0x8000000U)
#define	USB_OTGSC_BSVIE_SHIFT   (27U)
#define	USB_OTGSC_BSVIE(x)
#define	USB_OTGSC_BSEIE_MASK   (0x10000000U)
#define	USB_OTGSC_BSEIE_SHIFT   (28U)
#define	USB_OTGSC_BSEIE(x)
#define	USB_OTGSC_EN_1MS_MASK   (0x20000000U)
#define	USB_OTGSC_EN_1MS_SHIFT   (29U)
#define	USB_OTGSC_EN_1MS(x)
#define	USB_OTGSC_DPIE_MASK   (0x40000000U)
#define	USB_OTGSC_DPIE_SHIFT   (30U)
#define	USB_OTGSC_DPIE(x)
USBMODE - USB Device Mode
#define	USB_USBMODE_CM_MASK   (0x3U)
#define	USB_USBMODE_CM_SHIFT   (0U)
#define	USB_USBMODE_CM(x)
#define	USB_USBMODE_ES_MASK   (0x4U)
#define	USB_USBMODE_ES_SHIFT   (2U)
#define	USB_USBMODE_ES(x)
#define	USB_USBMODE_SLOM_MASK   (0x8U)
#define	USB_USBMODE_SLOM_SHIFT   (3U)
#define	USB_USBMODE_SLOM(x)
#define	USB_USBMODE_SDIS_MASK   (0x10U)
#define	USB_USBMODE_SDIS_SHIFT   (4U)
#define	USB_USBMODE_SDIS(x)
ENDPTSETUPSTAT - Endpoint Setup Status
#define	USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
#define	USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT   (0U)
#define	USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
ENDPTPRIME - Endpoint Prime
#define	USB_ENDPTPRIME_PERB_MASK   (0xFFU)
#define	USB_ENDPTPRIME_PERB_SHIFT   (0U)
#define	USB_ENDPTPRIME_PERB(x)
#define	USB_ENDPTPRIME_PETB_MASK   (0xFF0000U)
#define	USB_ENDPTPRIME_PETB_SHIFT   (16U)
#define	USB_ENDPTPRIME_PETB(x)
ENDPTFLUSH - Endpoint Flush
#define	USB_ENDPTFLUSH_FERB_MASK   (0xFFU)
#define	USB_ENDPTFLUSH_FERB_SHIFT   (0U)
#define	USB_ENDPTFLUSH_FERB(x)
#define	USB_ENDPTFLUSH_FETB_MASK   (0xFF0000U)
#define	USB_ENDPTFLUSH_FETB_SHIFT   (16U)
#define	USB_ENDPTFLUSH_FETB(x)
ENDPTSTAT - Endpoint Status
#define	USB_ENDPTSTAT_ERBR_MASK   (0xFFU)
#define	USB_ENDPTSTAT_ERBR_SHIFT   (0U)
#define	USB_ENDPTSTAT_ERBR(x)
#define	USB_ENDPTSTAT_ETBR_MASK   (0xFF0000U)
#define	USB_ENDPTSTAT_ETBR_SHIFT   (16U)
#define	USB_ENDPTSTAT_ETBR(x)
ENDPTCOMPLETE - Endpoint Complete
#define	USB_ENDPTCOMPLETE_ERCE_MASK   (0xFFU)
#define	USB_ENDPTCOMPLETE_ERCE_SHIFT   (0U)
#define	USB_ENDPTCOMPLETE_ERCE(x)
#define	USB_ENDPTCOMPLETE_ETCE_MASK   (0xFF0000U)
#define	USB_ENDPTCOMPLETE_ETCE_SHIFT   (16U)
#define	USB_ENDPTCOMPLETE_ETCE(x)
ENDPTCTRL0 - Endpoint Control0
#define	USB_ENDPTCTRL0_RXS_MASK   (0x1U)
#define	USB_ENDPTCTRL0_RXS_SHIFT   (0U)
#define	USB_ENDPTCTRL0_RXS(x)
#define	USB_ENDPTCTRL0_RXT_MASK   (0xCU)
#define	USB_ENDPTCTRL0_RXT_SHIFT   (2U)
#define	USB_ENDPTCTRL0_RXT(x)
#define	USB_ENDPTCTRL0_RXE_MASK   (0x80U)
#define	USB_ENDPTCTRL0_RXE_SHIFT   (7U)
#define	USB_ENDPTCTRL0_RXE(x)
#define	USB_ENDPTCTRL0_TXS_MASK   (0x10000U)
#define	USB_ENDPTCTRL0_TXS_SHIFT   (16U)
#define	USB_ENDPTCTRL0_TXS(x)
#define	USB_ENDPTCTRL0_TXT_MASK   (0xC0000U)
#define	USB_ENDPTCTRL0_TXT_SHIFT   (18U)
#define	USB_ENDPTCTRL0_TXT(x)
#define	USB_ENDPTCTRL0_TXE_MASK   (0x800000U)
#define	USB_ENDPTCTRL0_TXE_SHIFT   (23U)
#define	USB_ENDPTCTRL0_TXE(x)
ENDPTCTRL - Endpoint Control 1..Endpoint Control 7
#define	USB_ENDPTCTRL_RXS_MASK   (0x1U)
#define	USB_ENDPTCTRL_RXS_SHIFT   (0U)
#define	USB_ENDPTCTRL_RXS(x)
#define	USB_ENDPTCTRL_RXD_MASK   (0x2U)
#define	USB_ENDPTCTRL_RXD_SHIFT   (1U)
#define	USB_ENDPTCTRL_RXD(x)
#define	USB_ENDPTCTRL_RXT_MASK   (0xCU)
#define	USB_ENDPTCTRL_RXT_SHIFT   (2U)
#define	USB_ENDPTCTRL_RXT(x)
#define	USB_ENDPTCTRL_RXI_MASK   (0x20U)
#define	USB_ENDPTCTRL_RXI_SHIFT   (5U)
#define	USB_ENDPTCTRL_RXI(x)
#define	USB_ENDPTCTRL_RXR_MASK   (0x40U)
#define	USB_ENDPTCTRL_RXR_SHIFT   (6U)
#define	USB_ENDPTCTRL_RXR(x)
#define	USB_ENDPTCTRL_RXE_MASK   (0x80U)
#define	USB_ENDPTCTRL_RXE_SHIFT   (7U)
#define	USB_ENDPTCTRL_RXE(x)
#define	USB_ENDPTCTRL_TXS_MASK   (0x10000U)
#define	USB_ENDPTCTRL_TXS_SHIFT   (16U)
#define	USB_ENDPTCTRL_TXS(x)
#define	USB_ENDPTCTRL_TXD_MASK   (0x20000U)
#define	USB_ENDPTCTRL_TXD_SHIFT   (17U)
#define	USB_ENDPTCTRL_TXD(x)
#define	USB_ENDPTCTRL_TXT_MASK   (0xC0000U)
#define	USB_ENDPTCTRL_TXT_SHIFT   (18U)
#define	USB_ENDPTCTRL_TXT(x)
#define	USB_ENDPTCTRL_TXI_MASK   (0x200000U)
#define	USB_ENDPTCTRL_TXI_SHIFT   (21U)
#define	USB_ENDPTCTRL_TXI(x)
#define	USB_ENDPTCTRL_TXR_MASK   (0x400000U)
#define	USB_ENDPTCTRL_TXR_SHIFT   (22U)
#define	USB_ENDPTCTRL_TXR(x)
#define	USB_ENDPTCTRL_TXE_MASK   (0x800000U)
#define	USB_ENDPTCTRL_TXE_SHIFT   (23U)
#define	USB_ENDPTCTRL_TXE(x)
CONTROL - Control register
#define	USBHSDCD_CONTROL_IACK_MASK   (0x1U)
#define	USBHSDCD_CONTROL_IACK_SHIFT   (0U)
#define	USBHSDCD_CONTROL_IACK(x)
#define	USBHSDCD_CONTROL_IF_MASK   (0x100U)
#define	USBHSDCD_CONTROL_IF_SHIFT   (8U)
#define	USBHSDCD_CONTROL_IF(x)
#define	USBHSDCD_CONTROL_IE_MASK   (0x10000U)
#define	USBHSDCD_CONTROL_IE_SHIFT   (16U)
#define	USBHSDCD_CONTROL_IE(x)
#define	USBHSDCD_CONTROL_BC12_MASK   (0x20000U)
#define	USBHSDCD_CONTROL_BC12_SHIFT   (17U)
#define	USBHSDCD_CONTROL_BC12(x)
#define	USBHSDCD_CONTROL_START_MASK   (0x1000000U)
#define	USBHSDCD_CONTROL_START_SHIFT   (24U)
#define	USBHSDCD_CONTROL_START(x)
#define	USBHSDCD_CONTROL_SR_MASK   (0x2000000U)
#define	USBHSDCD_CONTROL_SR_SHIFT   (25U)
#define	USBHSDCD_CONTROL_SR(x)
CLOCK - Clock register
#define	USBHSDCD_CLOCK_CLOCK_UNIT_MASK   (0x1U)
#define	USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT   (0U)
#define	USBHSDCD_CLOCK_CLOCK_UNIT(x)
#define	USBHSDCD_CLOCK_CLOCK_SPEED_MASK   (0xFFCU)
#define	USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT   (2U)
#define	USBHSDCD_CLOCK_CLOCK_SPEED(x)
STATUS - Status register
#define	USBHSDCD_STATUS_SEQ_RES_MASK   (0x30000U)
#define	USBHSDCD_STATUS_SEQ_RES_SHIFT   (16U)
#define	USBHSDCD_STATUS_SEQ_RES(x)
#define	USBHSDCD_STATUS_SEQ_STAT_MASK   (0xC0000U)
#define	USBHSDCD_STATUS_SEQ_STAT_SHIFT   (18U)
#define	USBHSDCD_STATUS_SEQ_STAT(x)
#define	USBHSDCD_STATUS_ERR_MASK   (0x100000U)
#define	USBHSDCD_STATUS_ERR_SHIFT   (20U)
#define	USBHSDCD_STATUS_ERR(x)
#define	USBHSDCD_STATUS_TO_MASK   (0x200000U)
#define	USBHSDCD_STATUS_TO_SHIFT   (21U)
#define	USBHSDCD_STATUS_TO(x)
#define	USBHSDCD_STATUS_ACTIVE_MASK   (0x400000U)
#define	USBHSDCD_STATUS_ACTIVE_SHIFT   (22U)
#define	USBHSDCD_STATUS_ACTIVE(x)
SIGNAL_OVERRIDE - Signal Override Register
#define	USBHSDCD_SIGNAL_OVERRIDE_PS_MASK   (0x3U)
#define	USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT   (0U)
#define	USBHSDCD_SIGNAL_OVERRIDE_PS(x)
TIMER0 - TIMER0 register
#define	USBHSDCD_TIMER0_TUNITCON_MASK   (0xFFFU)
#define	USBHSDCD_TIMER0_TUNITCON_SHIFT   (0U)
#define	USBHSDCD_TIMER0_TUNITCON(x)
#define	USBHSDCD_TIMER0_TSEQ_INIT_MASK   (0x3FF0000U)
#define	USBHSDCD_TIMER0_TSEQ_INIT_SHIFT   (16U)
#define	USBHSDCD_TIMER0_TSEQ_INIT(x)
TIMER1 - TIMER1 register
#define	USBHSDCD_TIMER1_TVDPSRC_ON_MASK   (0x3FFU)
#define	USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT   (0U)
#define	USBHSDCD_TIMER1_TVDPSRC_ON(x)
#define	USBHSDCD_TIMER1_TDCD_DBNC_MASK   (0x3FF0000U)
#define	USBHSDCD_TIMER1_TDCD_DBNC_SHIFT   (16U)
#define	USBHSDCD_TIMER1_TDCD_DBNC(x)
TIMER2_BC11 - TIMER2_BC11 register
#define	USBHSDCD_TIMER2_BC11_CHECK_DM_MASK   (0xFU)
#define	USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT   (0U)
#define	USBHSDCD_TIMER2_BC11_CHECK_DM(x)
#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK   (0x3FF0000U)
#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)
TIMER2_BC12 - TIMER2_BC12 register
#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK   (0x3FFU)
#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT   (0U)
#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)
#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK   (0x3FF0000U)
#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT   (16U)
#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)
CTRL1 - USB OTG Control 1 Register
#define	USBNC_CTRL1_OVER_CUR_DIS_MASK   (0x80U)
#define	USBNC_CTRL1_OVER_CUR_DIS_SHIFT   (7U)
#define	USBNC_CTRL1_OVER_CUR_DIS(x)
#define	USBNC_CTRL1_OVER_CUR_POL_MASK   (0x100U)
#define	USBNC_CTRL1_OVER_CUR_POL_SHIFT   (8U)
#define	USBNC_CTRL1_OVER_CUR_POL(x)
#define	USBNC_CTRL1_PWR_POL_MASK   (0x200U)
#define	USBNC_CTRL1_PWR_POL_SHIFT   (9U)
#define	USBNC_CTRL1_PWR_POL(x)
#define	USBNC_CTRL1_WIE_MASK   (0x400U)
#define	USBNC_CTRL1_WIE_SHIFT   (10U)
#define	USBNC_CTRL1_WIE(x)
#define	USBNC_CTRL1_WKUP_SW_EN_MASK   (0x4000U)
#define	USBNC_CTRL1_WKUP_SW_EN_SHIFT   (14U)
#define	USBNC_CTRL1_WKUP_SW_EN(x)
#define	USBNC_CTRL1_WKUP_SW_MASK   (0x8000U)
#define	USBNC_CTRL1_WKUP_SW_SHIFT   (15U)
#define	USBNC_CTRL1_WKUP_SW(x)
#define	USBNC_CTRL1_WKUP_ID_EN_MASK   (0x10000U)
#define	USBNC_CTRL1_WKUP_ID_EN_SHIFT   (16U)
#define	USBNC_CTRL1_WKUP_ID_EN(x)
#define	USBNC_CTRL1_WKUP_VBUS_EN_MASK   (0x20000U)
#define	USBNC_CTRL1_WKUP_VBUS_EN_SHIFT   (17U)
#define	USBNC_CTRL1_WKUP_VBUS_EN(x)
#define	USBNC_CTRL1_WKUP_DPDM_EN_MASK   (0x20000000U)
#define	USBNC_CTRL1_WKUP_DPDM_EN_SHIFT   (29U)
#define	USBNC_CTRL1_WKUP_DPDM_EN(x)
#define	USBNC_CTRL1_WIR_MASK   (0x80000000U)
#define	USBNC_CTRL1_WIR_SHIFT   (31U)
#define	USBNC_CTRL1_WIR(x)
CTRL2 - USB OTG Control 2 Register
#define	USBNC_CTRL2_VBUS_SOURCE_SEL_MASK   (0x3U)
#define	USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT   (0U)
#define	USBNC_CTRL2_VBUS_SOURCE_SEL(x)
#define	USBNC_CTRL2_AUTURESUME_EN_MASK   (0x4U)
#define	USBNC_CTRL2_AUTURESUME_EN_SHIFT   (2U)
#define	USBNC_CTRL2_AUTURESUME_EN(x)
#define	USBNC_CTRL2_LOWSPEED_EN_MASK   (0x8U)
#define	USBNC_CTRL2_LOWSPEED_EN_SHIFT   (3U)
#define	USBNC_CTRL2_LOWSPEED_EN(x)
#define	USBNC_CTRL2_UTMI_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_CTRL2_UTMI_CLK_VLD_SHIFT   (31U)
#define	USBNC_CTRL2_UTMI_CLK_VLD(x)
HSIC_CTRL - USB Host HSIC Control Register
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK   (0x800U)
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT   (11U)
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON(x)
#define	USBNC_HSIC_CTRL_HSIC_EN_MASK   (0x1000U)
#define	USBNC_HSIC_CTRL_HSIC_EN_SHIFT   (12U)
#define	USBNC_HSIC_CTRL_HSIC_EN(x)
#define	USBNC_HSIC_CTRL_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_HSIC_CTRL_CLK_VLD_SHIFT   (31U)
#define	USBNC_HSIC_CTRL_CLK_VLD(x)
PWD - USB PHY Power-Down Register
#define	USBPHY_PWD_TXPWDFS_MASK   (0x400U)
#define	USBPHY_PWD_TXPWDFS_SHIFT   (10U)
#define	USBPHY_PWD_TXPWDFS(x)
#define	USBPHY_PWD_TXPWDIBIAS_MASK   (0x800U)
#define	USBPHY_PWD_TXPWDIBIAS_SHIFT   (11U)
#define	USBPHY_PWD_TXPWDIBIAS(x)
#define	USBPHY_PWD_TXPWDV2I_MASK   (0x1000U)
#define	USBPHY_PWD_TXPWDV2I_SHIFT   (12U)
#define	USBPHY_PWD_TXPWDV2I(x)
#define	USBPHY_PWD_RXPWDENV_MASK   (0x20000U)
#define	USBPHY_PWD_RXPWDENV_SHIFT   (17U)
#define	USBPHY_PWD_RXPWDENV(x)
#define	USBPHY_PWD_RXPWD1PT1_MASK   (0x40000U)
#define	USBPHY_PWD_RXPWD1PT1_SHIFT   (18U)
#define	USBPHY_PWD_RXPWD1PT1(x)
#define	USBPHY_PWD_RXPWDDIFF_MASK   (0x80000U)
#define	USBPHY_PWD_RXPWDDIFF_SHIFT   (19U)
#define	USBPHY_PWD_RXPWDDIFF(x)
#define	USBPHY_PWD_RXPWDRX_MASK   (0x100000U)
#define	USBPHY_PWD_RXPWDRX_SHIFT   (20U)
#define	USBPHY_PWD_RXPWDRX(x)
PWD_SET - USB PHY Power-Down Register
#define	USBPHY_PWD_SET_TXPWDFS_MASK   (0x400U)
#define	USBPHY_PWD_SET_TXPWDFS_SHIFT   (10U)
#define	USBPHY_PWD_SET_TXPWDFS(x)
#define	USBPHY_PWD_SET_TXPWDIBIAS_MASK   (0x800U)
#define	USBPHY_PWD_SET_TXPWDIBIAS_SHIFT   (11U)
#define	USBPHY_PWD_SET_TXPWDIBIAS(x)
#define	USBPHY_PWD_SET_TXPWDV2I_MASK   (0x1000U)
#define	USBPHY_PWD_SET_TXPWDV2I_SHIFT   (12U)
#define	USBPHY_PWD_SET_TXPWDV2I(x)
#define	USBPHY_PWD_SET_RXPWDENV_MASK   (0x20000U)
#define	USBPHY_PWD_SET_RXPWDENV_SHIFT   (17U)
#define	USBPHY_PWD_SET_RXPWDENV(x)
#define	USBPHY_PWD_SET_RXPWD1PT1_MASK   (0x40000U)
#define	USBPHY_PWD_SET_RXPWD1PT1_SHIFT   (18U)
#define	USBPHY_PWD_SET_RXPWD1PT1(x)
#define	USBPHY_PWD_SET_RXPWDDIFF_MASK   (0x80000U)
#define	USBPHY_PWD_SET_RXPWDDIFF_SHIFT   (19U)
#define	USBPHY_PWD_SET_RXPWDDIFF(x)
#define	USBPHY_PWD_SET_RXPWDRX_MASK   (0x100000U)
#define	USBPHY_PWD_SET_RXPWDRX_SHIFT   (20U)
#define	USBPHY_PWD_SET_RXPWDRX(x)
PWD_CLR - USB PHY Power-Down Register
#define	USBPHY_PWD_CLR_TXPWDFS_MASK   (0x400U)
#define	USBPHY_PWD_CLR_TXPWDFS_SHIFT   (10U)
#define	USBPHY_PWD_CLR_TXPWDFS(x)
#define	USBPHY_PWD_CLR_TXPWDIBIAS_MASK   (0x800U)
#define	USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT   (11U)
#define	USBPHY_PWD_CLR_TXPWDIBIAS(x)
#define	USBPHY_PWD_CLR_TXPWDV2I_MASK   (0x1000U)
#define	USBPHY_PWD_CLR_TXPWDV2I_SHIFT   (12U)
#define	USBPHY_PWD_CLR_TXPWDV2I(x)
#define	USBPHY_PWD_CLR_RXPWDENV_MASK   (0x20000U)
#define	USBPHY_PWD_CLR_RXPWDENV_SHIFT   (17U)
#define	USBPHY_PWD_CLR_RXPWDENV(x)
#define	USBPHY_PWD_CLR_RXPWD1PT1_MASK   (0x40000U)
#define	USBPHY_PWD_CLR_RXPWD1PT1_SHIFT   (18U)
#define	USBPHY_PWD_CLR_RXPWD1PT1(x)
#define	USBPHY_PWD_CLR_RXPWDDIFF_MASK   (0x80000U)
#define	USBPHY_PWD_CLR_RXPWDDIFF_SHIFT   (19U)
#define	USBPHY_PWD_CLR_RXPWDDIFF(x)
#define	USBPHY_PWD_CLR_RXPWDRX_MASK   (0x100000U)
#define	USBPHY_PWD_CLR_RXPWDRX_SHIFT   (20U)
#define	USBPHY_PWD_CLR_RXPWDRX(x)
PWD_TOG - USB PHY Power-Down Register
#define	USBPHY_PWD_TOG_TXPWDFS_MASK   (0x400U)
#define	USBPHY_PWD_TOG_TXPWDFS_SHIFT   (10U)
#define	USBPHY_PWD_TOG_TXPWDFS(x)
#define	USBPHY_PWD_TOG_TXPWDIBIAS_MASK   (0x800U)
#define	USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT   (11U)
#define	USBPHY_PWD_TOG_TXPWDIBIAS(x)
#define	USBPHY_PWD_TOG_TXPWDV2I_MASK   (0x1000U)
#define	USBPHY_PWD_TOG_TXPWDV2I_SHIFT   (12U)
#define	USBPHY_PWD_TOG_TXPWDV2I(x)
#define	USBPHY_PWD_TOG_RXPWDENV_MASK   (0x20000U)
#define	USBPHY_PWD_TOG_RXPWDENV_SHIFT   (17U)
#define	USBPHY_PWD_TOG_RXPWDENV(x)
#define	USBPHY_PWD_TOG_RXPWD1PT1_MASK   (0x40000U)
#define	USBPHY_PWD_TOG_RXPWD1PT1_SHIFT   (18U)
#define	USBPHY_PWD_TOG_RXPWD1PT1(x)
#define	USBPHY_PWD_TOG_RXPWDDIFF_MASK   (0x80000U)
#define	USBPHY_PWD_TOG_RXPWDDIFF_SHIFT   (19U)
#define	USBPHY_PWD_TOG_RXPWDDIFF(x)
#define	USBPHY_PWD_TOG_RXPWDRX_MASK   (0x100000U)
#define	USBPHY_PWD_TOG_RXPWDRX_SHIFT   (20U)
#define	USBPHY_PWD_TOG_RXPWDRX(x)
TX - USB PHY Transmitter Control Register
#define	USBPHY_TX_D_CAL_MASK   (0xFU)
#define	USBPHY_TX_D_CAL_SHIFT   (0U)
#define	USBPHY_TX_D_CAL(x)
#define	USBPHY_TX_TXCAL45DN_MASK   (0xF00U)
#define	USBPHY_TX_TXCAL45DN_SHIFT   (8U)
#define	USBPHY_TX_TXCAL45DN(x)
#define	USBPHY_TX_TXCAL45DP_MASK   (0xF0000U)
#define	USBPHY_TX_TXCAL45DP_SHIFT   (16U)
#define	USBPHY_TX_TXCAL45DP(x)
TX_SET - USB PHY Transmitter Control Register
#define	USBPHY_TX_SET_D_CAL_MASK   (0xFU)
#define	USBPHY_TX_SET_D_CAL_SHIFT   (0U)
#define	USBPHY_TX_SET_D_CAL(x)
#define	USBPHY_TX_SET_TXCAL45DN_MASK   (0xF00U)
#define	USBPHY_TX_SET_TXCAL45DN_SHIFT   (8U)
#define	USBPHY_TX_SET_TXCAL45DN(x)
#define	USBPHY_TX_SET_TXCAL45DP_MASK   (0xF0000U)
#define	USBPHY_TX_SET_TXCAL45DP_SHIFT   (16U)
#define	USBPHY_TX_SET_TXCAL45DP(x)
TX_CLR - USB PHY Transmitter Control Register
#define	USBPHY_TX_CLR_D_CAL_MASK   (0xFU)
#define	USBPHY_TX_CLR_D_CAL_SHIFT   (0U)
#define	USBPHY_TX_CLR_D_CAL(x)
#define	USBPHY_TX_CLR_TXCAL45DN_MASK   (0xF00U)
#define	USBPHY_TX_CLR_TXCAL45DN_SHIFT   (8U)
#define	USBPHY_TX_CLR_TXCAL45DN(x)
#define	USBPHY_TX_CLR_TXCAL45DP_MASK   (0xF0000U)
#define	USBPHY_TX_CLR_TXCAL45DP_SHIFT   (16U)
#define	USBPHY_TX_CLR_TXCAL45DP(x)
TX_TOG - USB PHY Transmitter Control Register
#define	USBPHY_TX_TOG_D_CAL_MASK   (0xFU)
#define	USBPHY_TX_TOG_D_CAL_SHIFT   (0U)
#define	USBPHY_TX_TOG_D_CAL(x)
#define	USBPHY_TX_TOG_TXCAL45DN_MASK   (0xF00U)
#define	USBPHY_TX_TOG_TXCAL45DN_SHIFT   (8U)
#define	USBPHY_TX_TOG_TXCAL45DN(x)
#define	USBPHY_TX_TOG_TXCAL45DP_MASK   (0xF0000U)
#define	USBPHY_TX_TOG_TXCAL45DP_SHIFT   (16U)
#define	USBPHY_TX_TOG_TXCAL45DP(x)
RX - USB PHY Receiver Control Register
#define	USBPHY_RX_ENVADJ_MASK   (0x7U)
#define	USBPHY_RX_ENVADJ_SHIFT   (0U)
#define	USBPHY_RX_ENVADJ(x)
#define	USBPHY_RX_DISCONADJ_MASK   (0x70U)
#define	USBPHY_RX_DISCONADJ_SHIFT   (4U)
#define	USBPHY_RX_DISCONADJ(x)
#define	USBPHY_RX_RXDBYPASS_MASK   (0x400000U)
#define	USBPHY_RX_RXDBYPASS_SHIFT   (22U)
#define	USBPHY_RX_RXDBYPASS(x)
RX_SET - USB PHY Receiver Control Register
#define	USBPHY_RX_SET_ENVADJ_MASK   (0x7U)
#define	USBPHY_RX_SET_ENVADJ_SHIFT   (0U)
#define	USBPHY_RX_SET_ENVADJ(x)
#define	USBPHY_RX_SET_DISCONADJ_MASK   (0x70U)
#define	USBPHY_RX_SET_DISCONADJ_SHIFT   (4U)
#define	USBPHY_RX_SET_DISCONADJ(x)
#define	USBPHY_RX_SET_RXDBYPASS_MASK   (0x400000U)
#define	USBPHY_RX_SET_RXDBYPASS_SHIFT   (22U)
#define	USBPHY_RX_SET_RXDBYPASS(x)
RX_CLR - USB PHY Receiver Control Register
#define	USBPHY_RX_CLR_ENVADJ_MASK   (0x7U)
#define	USBPHY_RX_CLR_ENVADJ_SHIFT   (0U)
#define	USBPHY_RX_CLR_ENVADJ(x)
#define	USBPHY_RX_CLR_DISCONADJ_MASK   (0x70U)
#define	USBPHY_RX_CLR_DISCONADJ_SHIFT   (4U)
#define	USBPHY_RX_CLR_DISCONADJ(x)
#define	USBPHY_RX_CLR_RXDBYPASS_MASK   (0x400000U)
#define	USBPHY_RX_CLR_RXDBYPASS_SHIFT   (22U)
#define	USBPHY_RX_CLR_RXDBYPASS(x)
RX_TOG - USB PHY Receiver Control Register
#define	USBPHY_RX_TOG_ENVADJ_MASK   (0x7U)
#define	USBPHY_RX_TOG_ENVADJ_SHIFT   (0U)
#define	USBPHY_RX_TOG_ENVADJ(x)
#define	USBPHY_RX_TOG_DISCONADJ_MASK   (0x70U)
#define	USBPHY_RX_TOG_DISCONADJ_SHIFT   (4U)
#define	USBPHY_RX_TOG_DISCONADJ(x)
#define	USBPHY_RX_TOG_RXDBYPASS_MASK   (0x400000U)
#define	USBPHY_RX_TOG_RXDBYPASS_SHIFT   (22U)
#define	USBPHY_RX_TOG_RXDBYPASS(x)
CTRL - USB PHY General Control Register
#define	USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK   (0x1U)
#define	USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
#define	USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_ENHOSTDISCONDETECT_MASK   (0x2U)
#define	USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT   (1U)
#define	USBPHY_CTRL_ENHOSTDISCONDETECT(x)
#define	USBPHY_CTRL_ENIRQHOSTDISCON_MASK   (0x4U)
#define	USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT   (2U)
#define	USBPHY_CTRL_ENIRQHOSTDISCON(x)
#define	USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK   (0x8U)
#define	USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
#define	USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)
#define	USBPHY_CTRL_ENDEVPLUGINDETECT_MASK   (0x10U)
#define	USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT   (4U)
#define	USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define	USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK   (0x20U)
#define	USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT   (5U)
#define	USBPHY_CTRL_DEVPLUGIN_POLARITY(x)
#define	USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK   (0x40U)
#define	USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT   (6U)
#define	USBPHY_CTRL_OTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_ENOTGIDDETECT_MASK   (0x80U)
#define	USBPHY_CTRL_ENOTGIDDETECT_SHIFT   (7U)
#define	USBPHY_CTRL_ENOTGIDDETECT(x)
#define	USBPHY_CTRL_RESUMEIRQSTICKY_MASK   (0x100U)
#define	USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT   (8U)
#define	USBPHY_CTRL_RESUMEIRQSTICKY(x)
#define	USBPHY_CTRL_ENIRQRESUMEDETECT_MASK   (0x200U)
#define	USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT   (9U)
#define	USBPHY_CTRL_ENIRQRESUMEDETECT(x)
#define	USBPHY_CTRL_RESUME_IRQ_MASK   (0x400U)
#define	USBPHY_CTRL_RESUME_IRQ_SHIFT   (10U)
#define	USBPHY_CTRL_RESUME_IRQ(x)
#define	USBPHY_CTRL_ENIRQDEVPLUGIN_MASK   (0x800U)
#define	USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT   (11U)
#define	USBPHY_CTRL_ENIRQDEVPLUGIN(x)
#define	USBPHY_CTRL_DEVPLUGIN_IRQ_MASK   (0x1000U)
#define	USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT   (12U)
#define	USBPHY_CTRL_DEVPLUGIN_IRQ(x)
#define	USBPHY_CTRL_ENUTMILEVEL2_MASK   (0x4000U)
#define	USBPHY_CTRL_ENUTMILEVEL2_SHIFT   (14U)
#define	USBPHY_CTRL_ENUTMILEVEL2(x)
#define	USBPHY_CTRL_ENUTMILEVEL3_MASK   (0x8000U)
#define	USBPHY_CTRL_ENUTMILEVEL3_SHIFT   (15U)
#define	USBPHY_CTRL_ENUTMILEVEL3(x)
#define	USBPHY_CTRL_ENIRQWAKEUP_MASK   (0x10000U)
#define	USBPHY_CTRL_ENIRQWAKEUP_SHIFT   (16U)
#define	USBPHY_CTRL_ENIRQWAKEUP(x)
#define	USBPHY_CTRL_WAKEUP_IRQ_MASK   (0x20000U)
#define	USBPHY_CTRL_WAKEUP_IRQ_SHIFT   (17U)
#define	USBPHY_CTRL_WAKEUP_IRQ(x)
#define	USBPHY_CTRL_AUTORESUME_EN_MASK   (0x40000U)
#define	USBPHY_CTRL_AUTORESUME_EN_SHIFT   (18U)
#define	USBPHY_CTRL_AUTORESUME_EN(x)
#define	USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define	USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT   (19U)
#define	USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)
#define	USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define	USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT   (20U)
#define	USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)
#define	USBPHY_CTRL_ENDPDMCHG_WKUP_MASK   (0x200000U)
#define	USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT   (21U)
#define	USBPHY_CTRL_ENDPDMCHG_WKUP(x)
#define	USBPHY_CTRL_ENIDCHG_WKUP_MASK   (0x400000U)
#define	USBPHY_CTRL_ENIDCHG_WKUP_SHIFT   (22U)
#define	USBPHY_CTRL_ENIDCHG_WKUP(x)
#define	USBPHY_CTRL_ENVBUSCHG_WKUP_MASK   (0x800000U)
#define	USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT   (23U)
#define	USBPHY_CTRL_ENVBUSCHG_WKUP(x)
#define	USBPHY_CTRL_FSDLL_RST_EN_MASK   (0x1000000U)
#define	USBPHY_CTRL_FSDLL_RST_EN_SHIFT   (24U)
#define	USBPHY_CTRL_FSDLL_RST_EN(x)
#define	USBPHY_CTRL_OTG_ID_VALUE_MASK   (0x8000000U)
#define	USBPHY_CTRL_OTG_ID_VALUE_SHIFT   (27U)
#define	USBPHY_CTRL_OTG_ID_VALUE(x)
#define	USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define	USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT   (28U)
#define	USBPHY_CTRL_HOST_FORCE_LS_SE0(x)
#define	USBPHY_CTRL_UTMI_SUSPENDM_MASK   (0x20000000U)
#define	USBPHY_CTRL_UTMI_SUSPENDM_SHIFT   (29U)
#define	USBPHY_CTRL_UTMI_SUSPENDM(x)
#define	USBPHY_CTRL_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_CTRL_CLKGATE_SHIFT   (30U)
#define	USBPHY_CTRL_CLKGATE(x)
#define	USBPHY_CTRL_SFTRST_MASK   (0x80000000U)
#define	USBPHY_CTRL_SFTRST_SHIFT   (31U)
#define	USBPHY_CTRL_SFTRST(x)
CTRL_SET - USB PHY General Control Register
#define	USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK   (0x1U)
#define	USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
#define	USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK   (0x2U)
#define	USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT   (1U)
#define	USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)
#define	USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK   (0x4U)
#define	USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT   (2U)
#define	USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)
#define	USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK   (0x8U)
#define	USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
#define	USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)
#define	USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
#define	USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT   (4U)
#define	USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)
#define	USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK   (0x20U)
#define	USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT   (5U)
#define	USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)
#define	USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK   (0x40U)
#define	USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT   (6U)
#define	USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_SET_ENOTGIDDETECT_MASK   (0x80U)
#define	USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT   (7U)
#define	USBPHY_CTRL_SET_ENOTGIDDETECT(x)
#define	USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK   (0x100U)
#define	USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT   (8U)
#define	USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)
#define	USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
#define	USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT   (9U)
#define	USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)
#define	USBPHY_CTRL_SET_RESUME_IRQ_MASK   (0x400U)
#define	USBPHY_CTRL_SET_RESUME_IRQ_SHIFT   (10U)
#define	USBPHY_CTRL_SET_RESUME_IRQ(x)
#define	USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK   (0x800U)
#define	USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT   (11U)
#define	USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)
#define	USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK   (0x1000U)
#define	USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT   (12U)
#define	USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)
#define	USBPHY_CTRL_SET_ENUTMILEVEL2_MASK   (0x4000U)
#define	USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT   (14U)
#define	USBPHY_CTRL_SET_ENUTMILEVEL2(x)
#define	USBPHY_CTRL_SET_ENUTMILEVEL3_MASK   (0x8000U)
#define	USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT   (15U)
#define	USBPHY_CTRL_SET_ENUTMILEVEL3(x)
#define	USBPHY_CTRL_SET_ENIRQWAKEUP_MASK   (0x10000U)
#define	USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT   (16U)
#define	USBPHY_CTRL_SET_ENIRQWAKEUP(x)
#define	USBPHY_CTRL_SET_WAKEUP_IRQ_MASK   (0x20000U)
#define	USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT   (17U)
#define	USBPHY_CTRL_SET_WAKEUP_IRQ(x)
#define	USBPHY_CTRL_SET_AUTORESUME_EN_MASK   (0x40000U)
#define	USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT   (18U)
#define	USBPHY_CTRL_SET_AUTORESUME_EN(x)
#define	USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define	USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT   (19U)
#define	USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)
#define	USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define	USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT   (20U)
#define	USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)
#define	USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK   (0x200000U)
#define	USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT   (21U)
#define	USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)
#define	USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK   (0x400000U)
#define	USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT   (22U)
#define	USBPHY_CTRL_SET_ENIDCHG_WKUP(x)
#define	USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK   (0x800000U)
#define	USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT   (23U)
#define	USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)
#define	USBPHY_CTRL_SET_FSDLL_RST_EN_MASK   (0x1000000U)
#define	USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT   (24U)
#define	USBPHY_CTRL_SET_FSDLL_RST_EN(x)
#define	USBPHY_CTRL_SET_OTG_ID_VALUE_MASK   (0x8000000U)
#define	USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT   (27U)
#define	USBPHY_CTRL_SET_OTG_ID_VALUE(x)
#define	USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define	USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT   (28U)
#define	USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)
#define	USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK   (0x20000000U)
#define	USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT   (29U)
#define	USBPHY_CTRL_SET_UTMI_SUSPENDM(x)
#define	USBPHY_CTRL_SET_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_CTRL_SET_CLKGATE_SHIFT   (30U)
#define	USBPHY_CTRL_SET_CLKGATE(x)
#define	USBPHY_CTRL_SET_SFTRST_MASK   (0x80000000U)
#define	USBPHY_CTRL_SET_SFTRST_SHIFT   (31U)
#define	USBPHY_CTRL_SET_SFTRST(x)
CTRL_CLR - USB PHY General Control Register
#define	USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK   (0x1U)
#define	USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
#define	USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK   (0x2U)
#define	USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT   (1U)
#define	USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)
#define	USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK   (0x4U)
#define	USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT   (2U)
#define	USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)
#define	USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK   (0x8U)
#define	USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
#define	USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)
#define	USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
#define	USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT   (4U)
#define	USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)
#define	USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK   (0x20U)
#define	USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT   (5U)
#define	USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)
#define	USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK   (0x40U)
#define	USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT   (6U)
#define	USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK   (0x80U)
#define	USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT   (7U)
#define	USBPHY_CTRL_CLR_ENOTGIDDETECT(x)
#define	USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK   (0x100U)
#define	USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT   (8U)
#define	USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)
#define	USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
#define	USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT   (9U)
#define	USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)
#define	USBPHY_CTRL_CLR_RESUME_IRQ_MASK   (0x400U)
#define	USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT   (10U)
#define	USBPHY_CTRL_CLR_RESUME_IRQ(x)
#define	USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK   (0x800U)
#define	USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT   (11U)
#define	USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)
#define	USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK   (0x1000U)
#define	USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT   (12U)
#define	USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)
#define	USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK   (0x4000U)
#define	USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT   (14U)
#define	USBPHY_CTRL_CLR_ENUTMILEVEL2(x)
#define	USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK   (0x8000U)
#define	USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT   (15U)
#define	USBPHY_CTRL_CLR_ENUTMILEVEL3(x)
#define	USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK   (0x10000U)
#define	USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT   (16U)
#define	USBPHY_CTRL_CLR_ENIRQWAKEUP(x)
#define	USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK   (0x20000U)
#define	USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT   (17U)
#define	USBPHY_CTRL_CLR_WAKEUP_IRQ(x)
#define	USBPHY_CTRL_CLR_AUTORESUME_EN_MASK   (0x40000U)
#define	USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT   (18U)
#define	USBPHY_CTRL_CLR_AUTORESUME_EN(x)
#define	USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define	USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT   (19U)
#define	USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)
#define	USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define	USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT   (20U)
#define	USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)
#define	USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK   (0x200000U)
#define	USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT   (21U)
#define	USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)
#define	USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK   (0x400000U)
#define	USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT   (22U)
#define	USBPHY_CTRL_CLR_ENIDCHG_WKUP(x)
#define	USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK   (0x800000U)
#define	USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT   (23U)
#define	USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)
#define	USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK   (0x1000000U)
#define	USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT   (24U)
#define	USBPHY_CTRL_CLR_FSDLL_RST_EN(x)
#define	USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK   (0x8000000U)
#define	USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT   (27U)
#define	USBPHY_CTRL_CLR_OTG_ID_VALUE(x)
#define	USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define	USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT   (28U)
#define	USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)
#define	USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK   (0x20000000U)
#define	USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT   (29U)
#define	USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)
#define	USBPHY_CTRL_CLR_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_CTRL_CLR_CLKGATE_SHIFT   (30U)
#define	USBPHY_CTRL_CLR_CLKGATE(x)
#define	USBPHY_CTRL_CLR_SFTRST_MASK   (0x80000000U)
#define	USBPHY_CTRL_CLR_SFTRST_SHIFT   (31U)
#define	USBPHY_CTRL_CLR_SFTRST(x)
CTRL_TOG - USB PHY General Control Register
#define	USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK   (0x1U)
#define	USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
#define	USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK   (0x2U)
#define	USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT   (1U)
#define	USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)
#define	USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK   (0x4U)
#define	USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT   (2U)
#define	USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)
#define	USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK   (0x8U)
#define	USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
#define	USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)
#define	USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
#define	USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT   (4U)
#define	USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)
#define	USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK   (0x20U)
#define	USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT   (5U)
#define	USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)
#define	USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK   (0x40U)
#define	USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT   (6U)
#define	USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)
#define	USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK   (0x80U)
#define	USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT   (7U)
#define	USBPHY_CTRL_TOG_ENOTGIDDETECT(x)
#define	USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK   (0x100U)
#define	USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT   (8U)
#define	USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)
#define	USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
#define	USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT   (9U)
#define	USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)
#define	USBPHY_CTRL_TOG_RESUME_IRQ_MASK   (0x400U)
#define	USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT   (10U)
#define	USBPHY_CTRL_TOG_RESUME_IRQ(x)
#define	USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK   (0x800U)
#define	USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT   (11U)
#define	USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)
#define	USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK   (0x1000U)
#define	USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT   (12U)
#define	USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)
#define	USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK   (0x4000U)
#define	USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT   (14U)
#define	USBPHY_CTRL_TOG_ENUTMILEVEL2(x)
#define	USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK   (0x8000U)
#define	USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT   (15U)
#define	USBPHY_CTRL_TOG_ENUTMILEVEL3(x)
#define	USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK   (0x10000U)
#define	USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT   (16U)
#define	USBPHY_CTRL_TOG_ENIRQWAKEUP(x)
#define	USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK   (0x20000U)
#define	USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT   (17U)
#define	USBPHY_CTRL_TOG_WAKEUP_IRQ(x)
#define	USBPHY_CTRL_TOG_AUTORESUME_EN_MASK   (0x40000U)
#define	USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT   (18U)
#define	USBPHY_CTRL_TOG_AUTORESUME_EN(x)
#define	USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define	USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT   (19U)
#define	USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)
#define	USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define	USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT   (20U)
#define	USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)
#define	USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK   (0x200000U)
#define	USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT   (21U)
#define	USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)
#define	USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK   (0x400000U)
#define	USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT   (22U)
#define	USBPHY_CTRL_TOG_ENIDCHG_WKUP(x)
#define	USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK   (0x800000U)
#define	USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT   (23U)
#define	USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)
#define	USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK   (0x1000000U)
#define	USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT   (24U)
#define	USBPHY_CTRL_TOG_FSDLL_RST_EN(x)
#define	USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK   (0x8000000U)
#define	USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT   (27U)
#define	USBPHY_CTRL_TOG_OTG_ID_VALUE(x)
#define	USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define	USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT   (28U)
#define	USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)
#define	USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK   (0x20000000U)
#define	USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT   (29U)
#define	USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)
#define	USBPHY_CTRL_TOG_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_CTRL_TOG_CLKGATE_SHIFT   (30U)
#define	USBPHY_CTRL_TOG_CLKGATE(x)
#define	USBPHY_CTRL_TOG_SFTRST_MASK   (0x80000000U)
#define	USBPHY_CTRL_TOG_SFTRST_SHIFT   (31U)
#define	USBPHY_CTRL_TOG_SFTRST(x)
STATUS - USB PHY Status Register
#define	USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK   (0x8U)
#define	USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT   (3U)
#define	USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x)
#define	USBPHY_STATUS_DEVPLUGIN_STATUS_MASK   (0x40U)
#define	USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT   (6U)
#define	USBPHY_STATUS_DEVPLUGIN_STATUS(x)
#define	USBPHY_STATUS_OTGID_STATUS_MASK   (0x100U)
#define	USBPHY_STATUS_OTGID_STATUS_SHIFT   (8U)
#define	USBPHY_STATUS_OTGID_STATUS(x)
#define	USBPHY_STATUS_RESUME_STATUS_MASK   (0x400U)
#define	USBPHY_STATUS_RESUME_STATUS_SHIFT   (10U)
#define	USBPHY_STATUS_RESUME_STATUS(x)
DEBUG - USB PHY Debug Register
#define	USBPHY_DEBUG_OTGIDPIOLOCK_MASK   (0x1U)
#define	USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT   (0U)
#define	USBPHY_DEBUG_OTGIDPIOLOCK(x)
#define	USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
#define	USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT   (1U)
#define	USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)
#define	USBPHY_DEBUG_HSTPULLDOWN_MASK   (0xCU)
#define	USBPHY_DEBUG_HSTPULLDOWN_SHIFT   (2U)
#define	USBPHY_DEBUG_HSTPULLDOWN(x)
#define	USBPHY_DEBUG_ENHSTPULLDOWN_MASK   (0x30U)
#define	USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT   (4U)
#define	USBPHY_DEBUG_ENHSTPULLDOWN(x)
#define	USBPHY_DEBUG_TX2RXCOUNT_MASK   (0xF00U)
#define	USBPHY_DEBUG_TX2RXCOUNT_SHIFT   (8U)
#define	USBPHY_DEBUG_TX2RXCOUNT(x)
#define	USBPHY_DEBUG_ENTX2RXCOUNT_MASK   (0x1000U)
#define	USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT   (12U)
#define	USBPHY_DEBUG_ENTX2RXCOUNT(x)
#define	USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK   (0x1F0000U)
#define	USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT   (16U)
#define	USBPHY_DEBUG_SQUELCHRESETCOUNT(x)
#define	USBPHY_DEBUG_ENSQUELCHRESET_MASK   (0x1000000U)
#define	USBPHY_DEBUG_ENSQUELCHRESET_SHIFT   (24U)
#define	USBPHY_DEBUG_ENSQUELCHRESET(x)
#define	USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK   (0x1E000000U)
#define	USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT   (25U)
#define	USBPHY_DEBUG_SQUELCHRESETLENGTH(x)
#define	USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK   (0x20000000U)
#define	USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT   (29U)
#define	USBPHY_DEBUG_HOST_RESUME_DEBUG(x)
#define	USBPHY_DEBUG_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_DEBUG_CLKGATE_SHIFT   (30U)
#define	USBPHY_DEBUG_CLKGATE(x)
DEBUG_SET - USB PHY Debug Register
#define	USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK   (0x1U)
#define	USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT   (0U)
#define	USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)
#define	USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
#define	USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT   (1U)
#define	USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x)
#define	USBPHY_DEBUG_SET_HSTPULLDOWN_MASK   (0xCU)
#define	USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT   (2U)
#define	USBPHY_DEBUG_SET_HSTPULLDOWN(x)
#define	USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK   (0x30U)
#define	USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT   (4U)
#define	USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)
#define	USBPHY_DEBUG_SET_TX2RXCOUNT_MASK   (0xF00U)
#define	USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT   (8U)
#define	USBPHY_DEBUG_SET_TX2RXCOUNT(x)
#define	USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK   (0x1000U)
#define	USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT   (12U)
#define	USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)
#define	USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK   (0x1F0000U)
#define	USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT   (16U)
#define	USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)
#define	USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK   (0x1000000U)
#define	USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT   (24U)
#define	USBPHY_DEBUG_SET_ENSQUELCHRESET(x)
#define	USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK   (0x1E000000U)
#define	USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT   (25U)
#define	USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)
#define	USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK   (0x20000000U)
#define	USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT   (29U)
#define	USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)
#define	USBPHY_DEBUG_SET_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_DEBUG_SET_CLKGATE_SHIFT   (30U)
#define	USBPHY_DEBUG_SET_CLKGATE(x)
DEBUG_CLR - USB PHY Debug Register
#define	USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK   (0x1U)
#define	USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT   (0U)
#define	USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)
#define	USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
#define	USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT   (1U)
#define	USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x)
#define	USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK   (0xCU)
#define	USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT   (2U)
#define	USBPHY_DEBUG_CLR_HSTPULLDOWN(x)
#define	USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK   (0x30U)
#define	USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT   (4U)
#define	USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)
#define	USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK   (0xF00U)
#define	USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT   (8U)
#define	USBPHY_DEBUG_CLR_TX2RXCOUNT(x)
#define	USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK   (0x1000U)
#define	USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT   (12U)
#define	USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)
#define	USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK   (0x1F0000U)
#define	USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT   (16U)
#define	USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)
#define	USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK   (0x1000000U)
#define	USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT   (24U)
#define	USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)
#define	USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK   (0x1E000000U)
#define	USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT   (25U)
#define	USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)
#define	USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK   (0x20000000U)
#define	USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT   (29U)
#define	USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)
#define	USBPHY_DEBUG_CLR_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_DEBUG_CLR_CLKGATE_SHIFT   (30U)
#define	USBPHY_DEBUG_CLR_CLKGATE(x)
DEBUG_TOG - USB PHY Debug Register
#define	USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK   (0x1U)
#define	USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT   (0U)
#define	USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)
#define	USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
#define	USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT   (1U)
#define	USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x)
#define	USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK   (0xCU)
#define	USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT   (2U)
#define	USBPHY_DEBUG_TOG_HSTPULLDOWN(x)
#define	USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK   (0x30U)
#define	USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT   (4U)
#define	USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)
#define	USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK   (0xF00U)
#define	USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT   (8U)
#define	USBPHY_DEBUG_TOG_TX2RXCOUNT(x)
#define	USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK   (0x1000U)
#define	USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT   (12U)
#define	USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)
#define	USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK   (0x1F0000U)
#define	USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT   (16U)
#define	USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)
#define	USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK   (0x1000000U)
#define	USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT   (24U)
#define	USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)
#define	USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK   (0x1E000000U)
#define	USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT   (25U)
#define	USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)
#define	USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK   (0x20000000U)
#define	USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT   (29U)
#define	USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)
#define	USBPHY_DEBUG_TOG_CLKGATE_MASK   (0x40000000U)
#define	USBPHY_DEBUG_TOG_CLKGATE_SHIFT   (30U)
#define	USBPHY_DEBUG_TOG_CLKGATE(x)
DEBUG0_STATUS - UTMI Debug Status Register 0
#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK   (0xFFFFU)
#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT   (0U)
#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x)
#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK   (0x3FF0000U)
#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT   (16U)
#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x)
#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK   (0xFC000000U)
#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT   (26U)
#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)
DEBUG1 - UTMI Debug Status Register 1
#define	USBPHY_DEBUG1_ENTAILADJVD_MASK   (0x6000U)
#define	USBPHY_DEBUG1_ENTAILADJVD_SHIFT   (13U)
#define	USBPHY_DEBUG1_ENTAILADJVD(x)
#define	USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK   (0x8000U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT   (15U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x)
#define	USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK   (0x10000U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT   (16U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x)
#define	USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT   (17U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x)
#define	USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT   (18U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK   (0x600000U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT   (21U)
#define	USBPHY_DEBUG1_USB2_REFBIAS_TST(x)
DEBUG1_SET - UTMI Debug Status Register 1
#define	USBPHY_DEBUG1_SET_ENTAILADJVD_MASK   (0x6000U)
#define	USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT   (13U)
#define	USBPHY_DEBUG1_SET_ENTAILADJVD(x)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK   (0x8000U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT   (15U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK   (0x10000U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT   (16U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT   (17U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT   (18U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK   (0x600000U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT   (21U)
#define	USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)
DEBUG1_CLR - UTMI Debug Status Register 1
#define	USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK   (0x6000U)
#define	USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT   (13U)
#define	USBPHY_DEBUG1_CLR_ENTAILADJVD(x)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK   (0x8000U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT   (15U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK   (0x10000U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT   (16U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT   (17U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT   (18U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK   (0x600000U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT   (21U)
#define	USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)
DEBUG1_TOG - UTMI Debug Status Register 1
#define	USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK   (0x6000U)
#define	USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT   (13U)
#define	USBPHY_DEBUG1_TOG_ENTAILADJVD(x)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK   (0x8000U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT   (15U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK   (0x10000U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT   (16U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT   (17U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT   (18U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK   (0x600000U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT   (21U)
#define	USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)
VERSION - UTMI RTL Version
#define	USBPHY_VERSION_STEP_MASK   (0xFFFFU)
#define	USBPHY_VERSION_STEP_SHIFT   (0U)
#define	USBPHY_VERSION_STEP(x)
#define	USBPHY_VERSION_MINOR_MASK   (0xFF0000U)
#define	USBPHY_VERSION_MINOR_SHIFT   (16U)
#define	USBPHY_VERSION_MINOR(x)
#define	USBPHY_VERSION_MAJOR_MASK   (0xFF000000U)
#define	USBPHY_VERSION_MAJOR_SHIFT   (24U)
#define	USBPHY_VERSION_MAJOR(x)
PLL_SIC - USB PHY PLL Control/Status Register
#define	USBPHY_PLL_SIC_PLL_POSTDIV_MASK   (0x1CU)
#define	USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT   (2U)
#define	USBPHY_PLL_SIC_PLL_POSTDIV(x)
#define	USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK   (0x40U)
#define	USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT   (6U)
#define	USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)
#define	USBPHY_PLL_SIC_PLL_POWER_MASK   (0x1000U)
#define	USBPHY_PLL_SIC_PLL_POWER_SHIFT   (12U)
#define	USBPHY_PLL_SIC_PLL_POWER(x)
#define	USBPHY_PLL_SIC_PLL_ENABLE_MASK   (0x2000U)
#define	USBPHY_PLL_SIC_PLL_ENABLE_SHIFT   (13U)
#define	USBPHY_PLL_SIC_PLL_ENABLE(x)
#define	USBPHY_PLL_SIC_PLL_BYPASS_MASK   (0x10000U)
#define	USBPHY_PLL_SIC_PLL_BYPASS_SHIFT   (16U)
#define	USBPHY_PLL_SIC_PLL_BYPASS(x)
#define	USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK   (0x80000U)
#define	USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT   (19U)
#define	USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)
#define	USBPHY_PLL_SIC_REFBIAS_PWD_MASK   (0x100000U)
#define	USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT   (20U)
#define	USBPHY_PLL_SIC_REFBIAS_PWD(x)
#define	USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK   (0x200000U)
#define	USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT   (21U)
#define	USBPHY_PLL_SIC_PLL_REG_ENABLE(x)
#define	USBPHY_PLL_SIC_PLL_DIV_SEL_MASK   (0x1C00000U)
#define	USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT   (22U)
#define	USBPHY_PLL_SIC_PLL_DIV_SEL(x)
#define	USBPHY_PLL_SIC_PLL_LOCK_MASK   (0x80000000U)
#define	USBPHY_PLL_SIC_PLL_LOCK_SHIFT   (31U)
#define	USBPHY_PLL_SIC_PLL_LOCK(x)
PLL_SIC_SET - USB PHY PLL Control/Status Register
#define	USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK   (0x1CU)
#define	USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT   (2U)
#define	USBPHY_PLL_SIC_SET_PLL_POSTDIV(x)
#define	USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK   (0x40U)
#define	USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT   (6U)
#define	USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)
#define	USBPHY_PLL_SIC_SET_PLL_POWER_MASK   (0x1000U)
#define	USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT   (12U)
#define	USBPHY_PLL_SIC_SET_PLL_POWER(x)
#define	USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK   (0x2000U)
#define	USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT   (13U)
#define	USBPHY_PLL_SIC_SET_PLL_ENABLE(x)
#define	USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK   (0x10000U)
#define	USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT   (16U)
#define	USBPHY_PLL_SIC_SET_PLL_BYPASS(x)
#define	USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK   (0x80000U)
#define	USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT   (19U)
#define	USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)
#define	USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK   (0x100000U)
#define	USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT   (20U)
#define	USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)
#define	USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
#define	USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT   (21U)
#define	USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)
#define	USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK   (0x1C00000U)
#define	USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT   (22U)
#define	USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)
#define	USBPHY_PLL_SIC_SET_PLL_LOCK_MASK   (0x80000000U)
#define	USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT   (31U)
#define	USBPHY_PLL_SIC_SET_PLL_LOCK(x)
PLL_SIC_CLR - USB PHY PLL Control/Status Register
#define	USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK   (0x1CU)
#define	USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT   (2U)
#define	USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x)
#define	USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK   (0x40U)
#define	USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT   (6U)
#define	USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)
#define	USBPHY_PLL_SIC_CLR_PLL_POWER_MASK   (0x1000U)
#define	USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT   (12U)
#define	USBPHY_PLL_SIC_CLR_PLL_POWER(x)
#define	USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK   (0x2000U)
#define	USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT   (13U)
#define	USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)
#define	USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK   (0x10000U)
#define	USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT   (16U)
#define	USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)
#define	USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK   (0x80000U)
#define	USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT   (19U)
#define	USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)
#define	USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK   (0x100000U)
#define	USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT   (20U)
#define	USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)
#define	USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
#define	USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT   (21U)
#define	USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)
#define	USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK   (0x1C00000U)
#define	USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT   (22U)
#define	USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)
#define	USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK   (0x80000000U)
#define	USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT   (31U)
#define	USBPHY_PLL_SIC_CLR_PLL_LOCK(x)
PLL_SIC_TOG - USB PHY PLL Control/Status Register
#define	USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK   (0x1CU)
#define	USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT   (2U)
#define	USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x)
#define	USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK   (0x40U)
#define	USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT   (6U)
#define	USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)
#define	USBPHY_PLL_SIC_TOG_PLL_POWER_MASK   (0x1000U)
#define	USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT   (12U)
#define	USBPHY_PLL_SIC_TOG_PLL_POWER(x)
#define	USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK   (0x2000U)
#define	USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT   (13U)
#define	USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)
#define	USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK   (0x10000U)
#define	USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT   (16U)
#define	USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)
#define	USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK   (0x80000U)
#define	USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT   (19U)
#define	USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)
#define	USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK   (0x100000U)
#define	USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT   (20U)
#define	USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)
#define	USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
#define	USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT   (21U)
#define	USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)
#define	USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK   (0x1C00000U)
#define	USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT   (22U)
#define	USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)
#define	USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK   (0x80000000U)
#define	USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT   (31U)
#define	USBPHY_PLL_SIC_TOG_PLL_LOCK(x)
USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK   (0x7U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT   (0U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x)
#define	USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK   (0x8U)
#define	USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT   (3U)
#define	USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK   (0x10U)
#define	USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT   (4U)
#define	USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK   (0x20U)
#define	USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT   (5U)
#define	USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK   (0x40U)
#define	USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT   (6U)
#define	USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK   (0x80U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT   (7U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK   (0x100U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT   (8U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK   (0x600U)
#define	USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT   (9U)
#define	USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK   (0x800U)
#define	USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT   (11U)
#define	USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK   (0x1000U)
#define	USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT   (12U)
#define	USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK   (0x40000U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT   (18U)
#define	USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x)
#define	USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK   (0x700000U)
#define	USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT   (20U)
#define	USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)
#define	USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK   (0x4000000U)
#define	USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT   (26U)
#define	USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x)
#define	USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK   (0x80000000U)
#define	USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT   (31U)
#define	USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x)
USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK   (0x7U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT   (0U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK   (0x8U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT   (3U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK   (0x10U)
#define	USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT   (4U)
#define	USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK   (0x20U)
#define	USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT   (5U)
#define	USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK   (0x40U)
#define	USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT   (6U)
#define	USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK   (0x80U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT   (7U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK   (0x100U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT   (8U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK   (0x600U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT   (9U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK   (0x800U)
#define	USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT   (11U)
#define	USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK   (0x1000U)
#define	USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT   (12U)
#define	USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK   (0x40000U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT   (18U)
#define	USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK   (0x700000U)
#define	USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT   (20U)
#define	USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK   (0x4000000U)
#define	USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT   (26U)
#define	USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x)
#define	USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK   (0x80000000U)
#define	USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT   (31U)
#define	USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x)
USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK   (0x7U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT   (0U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK   (0x8U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT   (3U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK   (0x10U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT   (4U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK   (0x20U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT   (5U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK   (0x40U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT   (6U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK   (0x80U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT   (7U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK   (0x100U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT   (8U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK   (0x600U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT   (9U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK   (0x800U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT   (11U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK   (0x1000U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT   (12U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK   (0x40000U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT   (18U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK   (0x700000U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT   (20U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK   (0x4000000U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT   (26U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x)
#define	USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK   (0x80000000U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT   (31U)
#define	USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x)
USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK   (0x7U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT   (0U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK   (0x8U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT   (3U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK   (0x10U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT   (4U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK   (0x20U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT   (5U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK   (0x40U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT   (6U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK   (0x80U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT   (7U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK   (0x100U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT   (8U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK   (0x600U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT   (9U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK   (0x800U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT   (11U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK   (0x1000U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT   (12U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK   (0x40000U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT   (18U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK   (0x700000U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT   (20U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK   (0x4000000U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT   (26U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x)
#define	USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK   (0x80000000U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT   (31U)
#define	USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x)
USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register
#define	USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
#define	USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT   (0U)
#define	USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)
#define	USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK   (0x2U)
#define	USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
#define	USBPHY_USB1_VBUS_DET_STAT_BVALID(x)
#define	USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK   (0x4U)
#define	USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
#define	USBPHY_USB1_VBUS_DET_STAT_AVALID(x)
#define	USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK   (0x8U)
#define	USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT   (3U)
#define	USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)
#define	USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK   (0x10U)
#define	USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT   (4U)
#define	USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x)
USB1_CHRG_DETECT - USB PHY Charger Detect Control Register
#define	USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
#define	USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT   (2U)
#define	USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)
#define	USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK   (0x800000U)
#define	USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT   (23U)
#define	USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x)
USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register
#define	USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK   (0x4U)
#define	USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT   (2U)
#define	USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x)
#define	USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK   (0x800000U)
#define	USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT   (23U)
#define	USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x)
USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register
#define	USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK   (0x4U)
#define	USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT   (2U)
#define	USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x)
#define	USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK   (0x800000U)
#define	USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT   (23U)
#define	USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x)
USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register
#define	USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK   (0x4U)
#define	USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT   (2U)
#define	USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x)
#define	USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK   (0x800000U)
#define	USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT   (23U)
#define	USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x)
USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register
#define	USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK   (0x1U)
#define	USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT   (0U)
#define	USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x)
#define	USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK   (0x2U)
#define	USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT   (1U)
#define	USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x)
#define	USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK   (0x4U)
#define	USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT   (2U)
#define	USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x)
#define	USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK   (0x8U)
#define	USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT   (3U)
#define	USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)
#define	USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK   (0x10U)
#define	USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT   (4U)
#define	USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)
ANACTRL - USB PHY Analog Control Register
#define	USBPHY_ANACTRL_DEV_PULLDOWN_MASK   (0x400U)
#define	USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT   (10U)
#define	USBPHY_ANACTRL_DEV_PULLDOWN(x)
ANACTRL_SET - USB PHY Analog Control Register
#define	USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK   (0x400U)
#define	USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT   (10U)
#define	USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)
ANACTRL_CLR - USB PHY Analog Control Register
#define	USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK   (0x400U)
#define	USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT   (10U)
#define	USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)
ANACTRL_TOG - USB PHY Analog Control Register
#define	USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK   (0x400U)
#define	USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT   (10U)
#define	USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)
USB1_LOOPBACK - USB PHY Loopback Control/Status Register
#define	USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK   (0x1U)
#define	USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)
#define	USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK   (0x2U)
#define	USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT   (1U)
#define	USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK   (0x4U)
#define	USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT   (2U)
#define	USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK   (0x8U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT   (3U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK   (0x10U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT   (4U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK   (0x20U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT   (5U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK   (0x40U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
#define	USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)
#define	USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK   (0x80U)
#define	USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT   (7U)
#define	USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK   (0x100U)
#define	USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT   (8U)
#define	USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK   (0x8000U)
#define	USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT   (15U)
#define	USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x)
#define	USBPHY_USB1_LOOPBACK_TSTPKT_MASK   (0xFF0000U)
#define	USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_TSTPKT(x)
USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK   (0x1U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK   (0x2U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT   (1U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK   (0x4U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT   (2U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK   (0x8U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT   (3U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK   (0x10U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT   (4U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK   (0x20U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT   (5U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK   (0x40U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT   (6U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)
#define	USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK   (0x80U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT   (7U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK   (0x100U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT   (8U)
#define	USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK   (0x8000U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT   (15U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x)
#define	USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK   (0xFF0000U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)
USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK   (0x1U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK   (0x2U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT   (1U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK   (0x4U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT   (2U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK   (0x8U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT   (3U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK   (0x10U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT   (4U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK   (0x20U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT   (5U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK   (0x40U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT   (6U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK   (0x80U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT   (7U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK   (0x100U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT   (8U)
#define	USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK   (0x8000U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT   (15U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK   (0xFF0000U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)
USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK   (0x1U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK   (0x2U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT   (1U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK   (0x4U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT   (2U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK   (0x8U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT   (3U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK   (0x10U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT   (4U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK   (0x20U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT   (5U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK   (0x40U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT   (6U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK   (0x80U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT   (7U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK   (0x100U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT   (8U)
#define	USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK   (0x8000U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT   (15U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK   (0xFF0000U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)
USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK   (0xFFFFU)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK   (0xFFFF0000U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x)
USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK   (0xFFFFU)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK   (0xFFFF0000U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x)
USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK   (0xFFFFU)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK   (0xFFFF0000U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x)
USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK   (0xFFFFU)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT   (0U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK   (0xFFFF0000U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT   (16U)
#define	USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x)
TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK   (0x1U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT   (0U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK   (0x2U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT   (1U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK   (0x4U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT   (2U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK   (0x8U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT   (3U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK   (0x10U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT   (4U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK   (0x20U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT   (5U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK   (0x40U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT   (6U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK   (0x1C00U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT   (10U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK   (0x6000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT   (13U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK   (0x38000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT   (15U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK   (0xC0000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT   (18U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK   (0xF00000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT   (20U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK   (0xF000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT   (24U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK   (0xF0000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT   (28U)
#define	USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x)
TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK   (0x1U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT   (0U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK   (0x2U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT   (1U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK   (0x4U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT   (2U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK   (0x8U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT   (3U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK   (0x10U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT   (4U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK   (0x20U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT   (5U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK   (0x40U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT   (6U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK   (0x1C00U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT   (10U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK   (0x6000U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT   (13U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK   (0x38000U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT   (15U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK   (0xC0000U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT   (18U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK   (0xF00000U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT   (20U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK   (0xF000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT   (24U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK   (0xF0000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT   (28U)
#define	USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x)
TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK   (0x1U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT   (0U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK   (0x2U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT   (1U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK   (0x4U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT   (2U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK   (0x8U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT   (3U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK   (0x10U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT   (4U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK   (0x20U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT   (5U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK   (0x40U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT   (6U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK   (0x1C00U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT   (10U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK   (0x6000U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT   (13U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK   (0x38000U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT   (15U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK   (0xC0000U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT   (18U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK   (0xF00000U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT   (20U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK   (0xF000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT   (24U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK   (0xF0000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT   (28U)
#define	USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x)
TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK   (0x1U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT   (0U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK   (0x2U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT   (1U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK   (0x4U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT   (2U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK   (0x8U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT   (3U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK   (0x10U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT   (4U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK   (0x20U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT   (5U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK   (0x40U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT   (6U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK   (0x1C00U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT   (10U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK   (0x6000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT   (13U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK   (0x38000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT   (15U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK   (0xC0000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT   (18U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK   (0xF00000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT   (20U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK   (0xF000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT   (24U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK   (0xF0000000U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT   (28U)
#define	USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x)
DS_ADDR - DMA System Address
#define	USDHC_DS_ADDR_DS_ADDR_MASK   (0xFFFFFFFFU)
#define	USDHC_DS_ADDR_DS_ADDR_SHIFT   (0U)
#define	USDHC_DS_ADDR_DS_ADDR(x)
BLK_ATT - Block Attributes
#define	USDHC_BLK_ATT_BLKSIZE_MASK   (0x1FFFU)
#define	USDHC_BLK_ATT_BLKSIZE_SHIFT   (0U)
#define	USDHC_BLK_ATT_BLKSIZE(x)
#define	USDHC_BLK_ATT_BLKCNT_MASK   (0xFFFF0000U)
#define	USDHC_BLK_ATT_BLKCNT_SHIFT   (16U)
#define	USDHC_BLK_ATT_BLKCNT(x)
CMD_ARG - Command Argument
#define	USDHC_CMD_ARG_CMDARG_MASK   (0xFFFFFFFFU)
#define	USDHC_CMD_ARG_CMDARG_SHIFT   (0U)
#define	USDHC_CMD_ARG_CMDARG(x)
CMD_XFR_TYP - Command Transfer Type
#define	USDHC_CMD_XFR_TYP_RSPTYP_MASK   (0x30000U)
#define	USDHC_CMD_XFR_TYP_RSPTYP_SHIFT   (16U)
#define	USDHC_CMD_XFR_TYP_RSPTYP(x)
#define	USDHC_CMD_XFR_TYP_CCCEN_MASK   (0x80000U)
#define	USDHC_CMD_XFR_TYP_CCCEN_SHIFT   (19U)
#define	USDHC_CMD_XFR_TYP_CCCEN(x)
#define	USDHC_CMD_XFR_TYP_CICEN_MASK   (0x100000U)
#define	USDHC_CMD_XFR_TYP_CICEN_SHIFT   (20U)
#define	USDHC_CMD_XFR_TYP_CICEN(x)
#define	USDHC_CMD_XFR_TYP_DPSEL_MASK   (0x200000U)
#define	USDHC_CMD_XFR_TYP_DPSEL_SHIFT   (21U)
#define	USDHC_CMD_XFR_TYP_DPSEL(x)
#define	USDHC_CMD_XFR_TYP_CMDTYP_MASK   (0xC00000U)
#define	USDHC_CMD_XFR_TYP_CMDTYP_SHIFT   (22U)
#define	USDHC_CMD_XFR_TYP_CMDTYP(x)
#define	USDHC_CMD_XFR_TYP_CMDINX_MASK   (0x3F000000U)
#define	USDHC_CMD_XFR_TYP_CMDINX_SHIFT   (24U)
#define	USDHC_CMD_XFR_TYP_CMDINX(x)
CMD_RSP0 - Command Response0
#define	USDHC_CMD_RSP0_CMDRSP0_MASK   (0xFFFFFFFFU)
#define	USDHC_CMD_RSP0_CMDRSP0_SHIFT   (0U)
#define	USDHC_CMD_RSP0_CMDRSP0(x)
CMD_RSP1 - Command Response1
#define	USDHC_CMD_RSP1_CMDRSP1_MASK   (0xFFFFFFFFU)
#define	USDHC_CMD_RSP1_CMDRSP1_SHIFT   (0U)
#define	USDHC_CMD_RSP1_CMDRSP1(x)
CMD_RSP2 - Command Response2
#define	USDHC_CMD_RSP2_CMDRSP2_MASK   (0xFFFFFFFFU)
#define	USDHC_CMD_RSP2_CMDRSP2_SHIFT   (0U)
#define	USDHC_CMD_RSP2_CMDRSP2(x)
CMD_RSP3 - Command Response3
#define	USDHC_CMD_RSP3_CMDRSP3_MASK   (0xFFFFFFFFU)
#define	USDHC_CMD_RSP3_CMDRSP3_SHIFT   (0U)
#define	USDHC_CMD_RSP3_CMDRSP3(x)
DATA_BUFF_ACC_PORT - Data Buffer Access Port
#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK   (0xFFFFFFFFU)
#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)
PRES_STATE - Present State
#define	USDHC_PRES_STATE_CIHB_MASK   (0x1U)
#define	USDHC_PRES_STATE_CIHB_SHIFT   (0U)
#define	USDHC_PRES_STATE_CIHB(x)
#define	USDHC_PRES_STATE_CDIHB_MASK   (0x2U)
#define	USDHC_PRES_STATE_CDIHB_SHIFT   (1U)
#define	USDHC_PRES_STATE_CDIHB(x)
#define	USDHC_PRES_STATE_DLA_MASK   (0x4U)
#define	USDHC_PRES_STATE_DLA_SHIFT   (2U)
#define	USDHC_PRES_STATE_DLA(x)
#define	USDHC_PRES_STATE_SDSTB_MASK   (0x8U)
#define	USDHC_PRES_STATE_SDSTB_SHIFT   (3U)
#define	USDHC_PRES_STATE_SDSTB(x)
#define	USDHC_PRES_STATE_IPGOFF_MASK   (0x10U)
#define	USDHC_PRES_STATE_IPGOFF_SHIFT   (4U)
#define	USDHC_PRES_STATE_IPGOFF(x)
#define	USDHC_PRES_STATE_HCKOFF_MASK   (0x20U)
#define	USDHC_PRES_STATE_HCKOFF_SHIFT   (5U)
#define	USDHC_PRES_STATE_HCKOFF(x)
#define	USDHC_PRES_STATE_PEROFF_MASK   (0x40U)
#define	USDHC_PRES_STATE_PEROFF_SHIFT   (6U)
#define	USDHC_PRES_STATE_PEROFF(x)
#define	USDHC_PRES_STATE_SDOFF_MASK   (0x80U)
#define	USDHC_PRES_STATE_SDOFF_SHIFT   (7U)
#define	USDHC_PRES_STATE_SDOFF(x)
#define	USDHC_PRES_STATE_WTA_MASK   (0x100U)
#define	USDHC_PRES_STATE_WTA_SHIFT   (8U)
#define	USDHC_PRES_STATE_WTA(x)
#define	USDHC_PRES_STATE_RTA_MASK   (0x200U)
#define	USDHC_PRES_STATE_RTA_SHIFT   (9U)
#define	USDHC_PRES_STATE_RTA(x)
#define	USDHC_PRES_STATE_BWEN_MASK   (0x400U)
#define	USDHC_PRES_STATE_BWEN_SHIFT   (10U)
#define	USDHC_PRES_STATE_BWEN(x)
#define	USDHC_PRES_STATE_BREN_MASK   (0x800U)
#define	USDHC_PRES_STATE_BREN_SHIFT   (11U)
#define	USDHC_PRES_STATE_BREN(x)
#define	USDHC_PRES_STATE_RTR_MASK   (0x1000U)
#define	USDHC_PRES_STATE_RTR_SHIFT   (12U)
#define	USDHC_PRES_STATE_RTR(x)
#define	USDHC_PRES_STATE_TSCD_MASK   (0x8000U)
#define	USDHC_PRES_STATE_TSCD_SHIFT   (15U)
#define	USDHC_PRES_STATE_TSCD(x)
#define	USDHC_PRES_STATE_CINST_MASK   (0x10000U)
#define	USDHC_PRES_STATE_CINST_SHIFT   (16U)
#define	USDHC_PRES_STATE_CINST(x)
#define	USDHC_PRES_STATE_CDPL_MASK   (0x40000U)
#define	USDHC_PRES_STATE_CDPL_SHIFT   (18U)
#define	USDHC_PRES_STATE_CDPL(x)
#define	USDHC_PRES_STATE_WPSPL_MASK   (0x80000U)
#define	USDHC_PRES_STATE_WPSPL_SHIFT   (19U)
#define	USDHC_PRES_STATE_WPSPL(x)
#define	USDHC_PRES_STATE_CLSL_MASK   (0x800000U)
#define	USDHC_PRES_STATE_CLSL_SHIFT   (23U)
#define	USDHC_PRES_STATE_CLSL(x)
#define	USDHC_PRES_STATE_DLSL_MASK   (0xFF000000U)
#define	USDHC_PRES_STATE_DLSL_SHIFT   (24U)
#define	USDHC_PRES_STATE_DLSL(x)
PROT_CTRL - Protocol Control
#define	USDHC_PROT_CTRL_DTW_MASK   (0x6U)
#define	USDHC_PROT_CTRL_DTW_SHIFT   (1U)
#define	USDHC_PROT_CTRL_DTW(x)
#define	USDHC_PROT_CTRL_D3CD_MASK   (0x8U)
#define	USDHC_PROT_CTRL_D3CD_SHIFT   (3U)
#define	USDHC_PROT_CTRL_D3CD(x)
#define	USDHC_PROT_CTRL_EMODE_MASK   (0x30U)
#define	USDHC_PROT_CTRL_EMODE_SHIFT   (4U)
#define	USDHC_PROT_CTRL_EMODE(x)
#define	USDHC_PROT_CTRL_CDTL_MASK   (0x40U)
#define	USDHC_PROT_CTRL_CDTL_SHIFT   (6U)
#define	USDHC_PROT_CTRL_CDTL(x)
#define	USDHC_PROT_CTRL_CDSS_MASK   (0x80U)
#define	USDHC_PROT_CTRL_CDSS_SHIFT   (7U)
#define	USDHC_PROT_CTRL_CDSS(x)
#define	USDHC_PROT_CTRL_DMASEL_MASK   (0x300U)
#define	USDHC_PROT_CTRL_DMASEL_SHIFT   (8U)
#define	USDHC_PROT_CTRL_DMASEL(x)
#define	USDHC_PROT_CTRL_SABGREQ_MASK   (0x10000U)
#define	USDHC_PROT_CTRL_SABGREQ_SHIFT   (16U)
#define	USDHC_PROT_CTRL_SABGREQ(x)
#define	USDHC_PROT_CTRL_CREQ_MASK   (0x20000U)
#define	USDHC_PROT_CTRL_CREQ_SHIFT   (17U)
#define	USDHC_PROT_CTRL_CREQ(x)
#define	USDHC_PROT_CTRL_RWCTL_MASK   (0x40000U)
#define	USDHC_PROT_CTRL_RWCTL_SHIFT   (18U)
#define	USDHC_PROT_CTRL_RWCTL(x)
#define	USDHC_PROT_CTRL_IABG_MASK   (0x80000U)
#define	USDHC_PROT_CTRL_IABG_SHIFT   (19U)
#define	USDHC_PROT_CTRL_IABG(x)
#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK   (0x100000U)
#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT   (20U)
#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)
#define	USDHC_PROT_CTRL_WECINT_MASK   (0x1000000U)
#define	USDHC_PROT_CTRL_WECINT_SHIFT   (24U)
#define	USDHC_PROT_CTRL_WECINT(x)
#define	USDHC_PROT_CTRL_WECINS_MASK   (0x2000000U)
#define	USDHC_PROT_CTRL_WECINS_SHIFT   (25U)
#define	USDHC_PROT_CTRL_WECINS(x)
#define	USDHC_PROT_CTRL_WECRM_MASK   (0x4000000U)
#define	USDHC_PROT_CTRL_WECRM_SHIFT   (26U)
#define	USDHC_PROT_CTRL_WECRM(x)
#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK   (0x40000000U)
#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)
SYS_CTRL - System Control
#define	USDHC_SYS_CTRL_DVS_MASK   (0xF0U)
#define	USDHC_SYS_CTRL_DVS_SHIFT   (4U)
#define	USDHC_SYS_CTRL_DVS(x)
#define	USDHC_SYS_CTRL_SDCLKFS_MASK   (0xFF00U)
#define	USDHC_SYS_CTRL_SDCLKFS_SHIFT   (8U)
#define	USDHC_SYS_CTRL_SDCLKFS(x)
#define	USDHC_SYS_CTRL_DTOCV_MASK   (0xF0000U)
#define	USDHC_SYS_CTRL_DTOCV_SHIFT   (16U)
#define	USDHC_SYS_CTRL_DTOCV(x)
#define	USDHC_SYS_CTRL_IPP_RST_N_MASK   (0x800000U)
#define	USDHC_SYS_CTRL_IPP_RST_N_SHIFT   (23U)
#define	USDHC_SYS_CTRL_IPP_RST_N(x)
#define	USDHC_SYS_CTRL_RSTA_MASK   (0x1000000U)
#define	USDHC_SYS_CTRL_RSTA_SHIFT   (24U)
#define	USDHC_SYS_CTRL_RSTA(x)
#define	USDHC_SYS_CTRL_RSTC_MASK   (0x2000000U)
#define	USDHC_SYS_CTRL_RSTC_SHIFT   (25U)
#define	USDHC_SYS_CTRL_RSTC(x)
#define	USDHC_SYS_CTRL_RSTD_MASK   (0x4000000U)
#define	USDHC_SYS_CTRL_RSTD_SHIFT   (26U)
#define	USDHC_SYS_CTRL_RSTD(x)
#define	USDHC_SYS_CTRL_INITA_MASK   (0x8000000U)
#define	USDHC_SYS_CTRL_INITA_SHIFT   (27U)
#define	USDHC_SYS_CTRL_INITA(x)
#define	USDHC_SYS_CTRL_RSTT_MASK   (0x10000000U)
#define	USDHC_SYS_CTRL_RSTT_SHIFT   (28U)
#define	USDHC_SYS_CTRL_RSTT(x)
INT_STATUS - Interrupt Status
#define	USDHC_INT_STATUS_CC_MASK   (0x1U)
#define	USDHC_INT_STATUS_CC_SHIFT   (0U)
#define	USDHC_INT_STATUS_CC(x)
#define	USDHC_INT_STATUS_TC_MASK   (0x2U)
#define	USDHC_INT_STATUS_TC_SHIFT   (1U)
#define	USDHC_INT_STATUS_TC(x)
#define	USDHC_INT_STATUS_BGE_MASK   (0x4U)
#define	USDHC_INT_STATUS_BGE_SHIFT   (2U)
#define	USDHC_INT_STATUS_BGE(x)
#define	USDHC_INT_STATUS_DINT_MASK   (0x8U)
#define	USDHC_INT_STATUS_DINT_SHIFT   (3U)
#define	USDHC_INT_STATUS_DINT(x)
#define	USDHC_INT_STATUS_BWR_MASK   (0x10U)
#define	USDHC_INT_STATUS_BWR_SHIFT   (4U)
#define	USDHC_INT_STATUS_BWR(x)
#define	USDHC_INT_STATUS_BRR_MASK   (0x20U)
#define	USDHC_INT_STATUS_BRR_SHIFT   (5U)
#define	USDHC_INT_STATUS_BRR(x)
#define	USDHC_INT_STATUS_CINS_MASK   (0x40U)
#define	USDHC_INT_STATUS_CINS_SHIFT   (6U)
#define	USDHC_INT_STATUS_CINS(x)
#define	USDHC_INT_STATUS_CRM_MASK   (0x80U)
#define	USDHC_INT_STATUS_CRM_SHIFT   (7U)
#define	USDHC_INT_STATUS_CRM(x)
#define	USDHC_INT_STATUS_CINT_MASK   (0x100U)
#define	USDHC_INT_STATUS_CINT_SHIFT   (8U)
#define	USDHC_INT_STATUS_CINT(x)
#define	USDHC_INT_STATUS_RTE_MASK   (0x1000U)
#define	USDHC_INT_STATUS_RTE_SHIFT   (12U)
#define	USDHC_INT_STATUS_RTE(x)
#define	USDHC_INT_STATUS_TP_MASK   (0x4000U)
#define	USDHC_INT_STATUS_TP_SHIFT   (14U)
#define	USDHC_INT_STATUS_TP(x)
#define	USDHC_INT_STATUS_CTOE_MASK   (0x10000U)
#define	USDHC_INT_STATUS_CTOE_SHIFT   (16U)
#define	USDHC_INT_STATUS_CTOE(x)
#define	USDHC_INT_STATUS_CCE_MASK   (0x20000U)
#define	USDHC_INT_STATUS_CCE_SHIFT   (17U)
#define	USDHC_INT_STATUS_CCE(x)
#define	USDHC_INT_STATUS_CEBE_MASK   (0x40000U)
#define	USDHC_INT_STATUS_CEBE_SHIFT   (18U)
#define	USDHC_INT_STATUS_CEBE(x)
#define	USDHC_INT_STATUS_CIE_MASK   (0x80000U)
#define	USDHC_INT_STATUS_CIE_SHIFT   (19U)
#define	USDHC_INT_STATUS_CIE(x)
#define	USDHC_INT_STATUS_DTOE_MASK   (0x100000U)
#define	USDHC_INT_STATUS_DTOE_SHIFT   (20U)
#define	USDHC_INT_STATUS_DTOE(x)
#define	USDHC_INT_STATUS_DCE_MASK   (0x200000U)
#define	USDHC_INT_STATUS_DCE_SHIFT   (21U)
#define	USDHC_INT_STATUS_DCE(x)
#define	USDHC_INT_STATUS_DEBE_MASK   (0x400000U)
#define	USDHC_INT_STATUS_DEBE_SHIFT   (22U)
#define	USDHC_INT_STATUS_DEBE(x)
#define	USDHC_INT_STATUS_AC12E_MASK   (0x1000000U)
#define	USDHC_INT_STATUS_AC12E_SHIFT   (24U)
#define	USDHC_INT_STATUS_AC12E(x)
#define	USDHC_INT_STATUS_TNE_MASK   (0x4000000U)
#define	USDHC_INT_STATUS_TNE_SHIFT   (26U)
#define	USDHC_INT_STATUS_TNE(x)
#define	USDHC_INT_STATUS_DMAE_MASK   (0x10000000U)
#define	USDHC_INT_STATUS_DMAE_SHIFT   (28U)
#define	USDHC_INT_STATUS_DMAE(x)
INT_STATUS_EN - Interrupt Status Enable
#define	USDHC_INT_STATUS_EN_CCSEN_MASK   (0x1U)
#define	USDHC_INT_STATUS_EN_CCSEN_SHIFT   (0U)
#define	USDHC_INT_STATUS_EN_CCSEN(x)
#define	USDHC_INT_STATUS_EN_TCSEN_MASK   (0x2U)
#define	USDHC_INT_STATUS_EN_TCSEN_SHIFT   (1U)
#define	USDHC_INT_STATUS_EN_TCSEN(x)
#define	USDHC_INT_STATUS_EN_BGESEN_MASK   (0x4U)
#define	USDHC_INT_STATUS_EN_BGESEN_SHIFT   (2U)
#define	USDHC_INT_STATUS_EN_BGESEN(x)
#define	USDHC_INT_STATUS_EN_DINTSEN_MASK   (0x8U)
#define	USDHC_INT_STATUS_EN_DINTSEN_SHIFT   (3U)
#define	USDHC_INT_STATUS_EN_DINTSEN(x)
#define	USDHC_INT_STATUS_EN_BWRSEN_MASK   (0x10U)
#define	USDHC_INT_STATUS_EN_BWRSEN_SHIFT   (4U)
#define	USDHC_INT_STATUS_EN_BWRSEN(x)
#define	USDHC_INT_STATUS_EN_BRRSEN_MASK   (0x20U)
#define	USDHC_INT_STATUS_EN_BRRSEN_SHIFT   (5U)
#define	USDHC_INT_STATUS_EN_BRRSEN(x)
#define	USDHC_INT_STATUS_EN_CINSSEN_MASK   (0x40U)
#define	USDHC_INT_STATUS_EN_CINSSEN_SHIFT   (6U)
#define	USDHC_INT_STATUS_EN_CINSSEN(x)
#define	USDHC_INT_STATUS_EN_CRMSEN_MASK   (0x80U)
#define	USDHC_INT_STATUS_EN_CRMSEN_SHIFT   (7U)
#define	USDHC_INT_STATUS_EN_CRMSEN(x)
#define	USDHC_INT_STATUS_EN_CINTSEN_MASK   (0x100U)
#define	USDHC_INT_STATUS_EN_CINTSEN_SHIFT   (8U)
#define	USDHC_INT_STATUS_EN_CINTSEN(x)
#define	USDHC_INT_STATUS_EN_RTESEN_MASK   (0x1000U)
#define	USDHC_INT_STATUS_EN_RTESEN_SHIFT   (12U)
#define	USDHC_INT_STATUS_EN_RTESEN(x)
#define	USDHC_INT_STATUS_EN_TPSEN_MASK   (0x4000U)
#define	USDHC_INT_STATUS_EN_TPSEN_SHIFT   (14U)
#define	USDHC_INT_STATUS_EN_TPSEN(x)
#define	USDHC_INT_STATUS_EN_CTOESEN_MASK   (0x10000U)
#define	USDHC_INT_STATUS_EN_CTOESEN_SHIFT   (16U)
#define	USDHC_INT_STATUS_EN_CTOESEN(x)
#define	USDHC_INT_STATUS_EN_CCESEN_MASK   (0x20000U)
#define	USDHC_INT_STATUS_EN_CCESEN_SHIFT   (17U)
#define	USDHC_INT_STATUS_EN_CCESEN(x)
#define	USDHC_INT_STATUS_EN_CEBESEN_MASK   (0x40000U)
#define	USDHC_INT_STATUS_EN_CEBESEN_SHIFT   (18U)
#define	USDHC_INT_STATUS_EN_CEBESEN(x)
#define	USDHC_INT_STATUS_EN_CIESEN_MASK   (0x80000U)
#define	USDHC_INT_STATUS_EN_CIESEN_SHIFT   (19U)
#define	USDHC_INT_STATUS_EN_CIESEN(x)
#define	USDHC_INT_STATUS_EN_DTOESEN_MASK   (0x100000U)
#define	USDHC_INT_STATUS_EN_DTOESEN_SHIFT   (20U)
#define	USDHC_INT_STATUS_EN_DTOESEN(x)
#define	USDHC_INT_STATUS_EN_DCESEN_MASK   (0x200000U)
#define	USDHC_INT_STATUS_EN_DCESEN_SHIFT   (21U)
#define	USDHC_INT_STATUS_EN_DCESEN(x)
#define	USDHC_INT_STATUS_EN_DEBESEN_MASK   (0x400000U)
#define	USDHC_INT_STATUS_EN_DEBESEN_SHIFT   (22U)
#define	USDHC_INT_STATUS_EN_DEBESEN(x)
#define	USDHC_INT_STATUS_EN_AC12ESEN_MASK   (0x1000000U)
#define	USDHC_INT_STATUS_EN_AC12ESEN_SHIFT   (24U)
#define	USDHC_INT_STATUS_EN_AC12ESEN(x)
#define	USDHC_INT_STATUS_EN_TNESEN_MASK   (0x4000000U)
#define	USDHC_INT_STATUS_EN_TNESEN_SHIFT   (26U)
#define	USDHC_INT_STATUS_EN_TNESEN(x)
#define	USDHC_INT_STATUS_EN_DMAESEN_MASK   (0x10000000U)
#define	USDHC_INT_STATUS_EN_DMAESEN_SHIFT   (28U)
#define	USDHC_INT_STATUS_EN_DMAESEN(x)
INT_SIGNAL_EN - Interrupt Signal Enable
#define	USDHC_INT_SIGNAL_EN_CCIEN_MASK   (0x1U)
#define	USDHC_INT_SIGNAL_EN_CCIEN_SHIFT   (0U)
#define	USDHC_INT_SIGNAL_EN_CCIEN(x)
#define	USDHC_INT_SIGNAL_EN_TCIEN_MASK   (0x2U)
#define	USDHC_INT_SIGNAL_EN_TCIEN_SHIFT   (1U)
#define	USDHC_INT_SIGNAL_EN_TCIEN(x)
#define	USDHC_INT_SIGNAL_EN_BGEIEN_MASK   (0x4U)
#define	USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT   (2U)
#define	USDHC_INT_SIGNAL_EN_BGEIEN(x)
#define	USDHC_INT_SIGNAL_EN_DINTIEN_MASK   (0x8U)
#define	USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT   (3U)
#define	USDHC_INT_SIGNAL_EN_DINTIEN(x)
#define	USDHC_INT_SIGNAL_EN_BWRIEN_MASK   (0x10U)
#define	USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT   (4U)
#define	USDHC_INT_SIGNAL_EN_BWRIEN(x)
#define	USDHC_INT_SIGNAL_EN_BRRIEN_MASK   (0x20U)
#define	USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT   (5U)
#define	USDHC_INT_SIGNAL_EN_BRRIEN(x)
#define	USDHC_INT_SIGNAL_EN_CINSIEN_MASK   (0x40U)
#define	USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT   (6U)
#define	USDHC_INT_SIGNAL_EN_CINSIEN(x)
#define	USDHC_INT_SIGNAL_EN_CRMIEN_MASK   (0x80U)
#define	USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT   (7U)
#define	USDHC_INT_SIGNAL_EN_CRMIEN(x)
#define	USDHC_INT_SIGNAL_EN_CINTIEN_MASK   (0x100U)
#define	USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT   (8U)
#define	USDHC_INT_SIGNAL_EN_CINTIEN(x)
#define	USDHC_INT_SIGNAL_EN_RTEIEN_MASK   (0x1000U)
#define	USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT   (12U)
#define	USDHC_INT_SIGNAL_EN_RTEIEN(x)
#define	USDHC_INT_SIGNAL_EN_TPIEN_MASK   (0x4000U)
#define	USDHC_INT_SIGNAL_EN_TPIEN_SHIFT   (14U)
#define	USDHC_INT_SIGNAL_EN_TPIEN(x)
#define	USDHC_INT_SIGNAL_EN_CTOEIEN_MASK   (0x10000U)
#define	USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT   (16U)
#define	USDHC_INT_SIGNAL_EN_CTOEIEN(x)
#define	USDHC_INT_SIGNAL_EN_CCEIEN_MASK   (0x20000U)
#define	USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT   (17U)
#define	USDHC_INT_SIGNAL_EN_CCEIEN(x)
#define	USDHC_INT_SIGNAL_EN_CEBEIEN_MASK   (0x40000U)
#define	USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT   (18U)
#define	USDHC_INT_SIGNAL_EN_CEBEIEN(x)
#define	USDHC_INT_SIGNAL_EN_CIEIEN_MASK   (0x80000U)
#define	USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT   (19U)
#define	USDHC_INT_SIGNAL_EN_CIEIEN(x)
#define	USDHC_INT_SIGNAL_EN_DTOEIEN_MASK   (0x100000U)
#define	USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT   (20U)
#define	USDHC_INT_SIGNAL_EN_DTOEIEN(x)
#define	USDHC_INT_SIGNAL_EN_DCEIEN_MASK   (0x200000U)
#define	USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT   (21U)
#define	USDHC_INT_SIGNAL_EN_DCEIEN(x)
#define	USDHC_INT_SIGNAL_EN_DEBEIEN_MASK   (0x400000U)
#define	USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT   (22U)
#define	USDHC_INT_SIGNAL_EN_DEBEIEN(x)
#define	USDHC_INT_SIGNAL_EN_AC12EIEN_MASK   (0x1000000U)
#define	USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT   (24U)
#define	USDHC_INT_SIGNAL_EN_AC12EIEN(x)
#define	USDHC_INT_SIGNAL_EN_TNEIEN_MASK   (0x4000000U)
#define	USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT   (26U)
#define	USDHC_INT_SIGNAL_EN_TNEIEN(x)
#define	USDHC_INT_SIGNAL_EN_DMAEIEN_MASK   (0x10000000U)
#define	USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT   (28U)
#define	USDHC_INT_SIGNAL_EN_DMAEIEN(x)
AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT   (0U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK   (0x2U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT   (1U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK   (0x4U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT   (2U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT   (3U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT   (4U)
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK   (0x80U)
#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT   (7U)
#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK   (0x400000U)
#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT   (22U)
#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x)
#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK   (0x800000U)
#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT   (23U)
#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x)
HOST_CTRL_CAP - Host Controller Capabilities
#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT   (0U)
#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)
#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK   (0x2U)
#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT   (1U)
#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)
#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT   (2U)
#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)
#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK   (0x2000U)
#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT   (13U)
#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)
#define	USDHC_HOST_CTRL_CAP_MBL_MASK   (0x70000U)
#define	USDHC_HOST_CTRL_CAP_MBL_SHIFT   (16U)
#define	USDHC_HOST_CTRL_CAP_MBL(x)
#define	USDHC_HOST_CTRL_CAP_ADMAS_MASK   (0x100000U)
#define	USDHC_HOST_CTRL_CAP_ADMAS_SHIFT   (20U)
#define	USDHC_HOST_CTRL_CAP_ADMAS(x)
#define	USDHC_HOST_CTRL_CAP_HSS_MASK   (0x200000U)
#define	USDHC_HOST_CTRL_CAP_HSS_SHIFT   (21U)
#define	USDHC_HOST_CTRL_CAP_HSS(x)
#define	USDHC_HOST_CTRL_CAP_DMAS_MASK   (0x400000U)
#define	USDHC_HOST_CTRL_CAP_DMAS_SHIFT   (22U)
#define	USDHC_HOST_CTRL_CAP_DMAS(x)
#define	USDHC_HOST_CTRL_CAP_SRS_MASK   (0x800000U)
#define	USDHC_HOST_CTRL_CAP_SRS_SHIFT   (23U)
#define	USDHC_HOST_CTRL_CAP_SRS(x)
#define	USDHC_HOST_CTRL_CAP_VS33_MASK   (0x1000000U)
#define	USDHC_HOST_CTRL_CAP_VS33_SHIFT   (24U)
#define	USDHC_HOST_CTRL_CAP_VS33(x)
#define	USDHC_HOST_CTRL_CAP_VS30_MASK   (0x2000000U)
#define	USDHC_HOST_CTRL_CAP_VS30_SHIFT   (25U)
#define	USDHC_HOST_CTRL_CAP_VS30(x)
#define	USDHC_HOST_CTRL_CAP_VS18_MASK   (0x4000000U)
#define	USDHC_HOST_CTRL_CAP_VS18_SHIFT   (26U)
#define	USDHC_HOST_CTRL_CAP_VS18(x)
WTMK_LVL - Watermark Level
#define	USDHC_WTMK_LVL_RD_WML_MASK   (0xFFU)
#define	USDHC_WTMK_LVL_RD_WML_SHIFT   (0U)
#define	USDHC_WTMK_LVL_RD_WML(x)
#define	USDHC_WTMK_LVL_WR_WML_MASK   (0xFF0000U)
#define	USDHC_WTMK_LVL_WR_WML_SHIFT   (16U)
#define	USDHC_WTMK_LVL_WR_WML(x)
MIX_CTRL - Mixer Control
#define	USDHC_MIX_CTRL_DMAEN_MASK   (0x1U)
#define	USDHC_MIX_CTRL_DMAEN_SHIFT   (0U)
#define	USDHC_MIX_CTRL_DMAEN(x)
#define	USDHC_MIX_CTRL_BCEN_MASK   (0x2U)
#define	USDHC_MIX_CTRL_BCEN_SHIFT   (1U)
#define	USDHC_MIX_CTRL_BCEN(x)
#define	USDHC_MIX_CTRL_AC12EN_MASK   (0x4U)
#define	USDHC_MIX_CTRL_AC12EN_SHIFT   (2U)
#define	USDHC_MIX_CTRL_AC12EN(x)
#define	USDHC_MIX_CTRL_DDR_EN_MASK   (0x8U)
#define	USDHC_MIX_CTRL_DDR_EN_SHIFT   (3U)
#define	USDHC_MIX_CTRL_DDR_EN(x)
#define	USDHC_MIX_CTRL_DTDSEL_MASK   (0x10U)
#define	USDHC_MIX_CTRL_DTDSEL_SHIFT   (4U)
#define	USDHC_MIX_CTRL_DTDSEL(x)
#define	USDHC_MIX_CTRL_MSBSEL_MASK   (0x20U)
#define	USDHC_MIX_CTRL_MSBSEL_SHIFT   (5U)
#define	USDHC_MIX_CTRL_MSBSEL(x)
#define	USDHC_MIX_CTRL_NIBBLE_POS_MASK   (0x40U)
#define	USDHC_MIX_CTRL_NIBBLE_POS_SHIFT   (6U)
#define	USDHC_MIX_CTRL_NIBBLE_POS(x)
#define	USDHC_MIX_CTRL_AC23EN_MASK   (0x80U)
#define	USDHC_MIX_CTRL_AC23EN_SHIFT   (7U)
#define	USDHC_MIX_CTRL_AC23EN(x)
#define	USDHC_MIX_CTRL_EXE_TUNE_MASK   (0x400000U)
#define	USDHC_MIX_CTRL_EXE_TUNE_SHIFT   (22U)
#define	USDHC_MIX_CTRL_EXE_TUNE(x)
#define	USDHC_MIX_CTRL_SMP_CLK_SEL_MASK   (0x800000U)
#define	USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT   (23U)
#define	USDHC_MIX_CTRL_SMP_CLK_SEL(x)
#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK   (0x1000000U)
#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT   (24U)
#define	USDHC_MIX_CTRL_AUTO_TUNE_EN(x)
#define	USDHC_MIX_CTRL_FBCLK_SEL_MASK   (0x2000000U)
#define	USDHC_MIX_CTRL_FBCLK_SEL_SHIFT   (25U)
#define	USDHC_MIX_CTRL_FBCLK_SEL(x)
#define	USDHC_MIX_CTRL_HS400_MODE_MASK   (0x4000000U)
#define	USDHC_MIX_CTRL_HS400_MODE_SHIFT   (26U)
#define	USDHC_MIX_CTRL_HS400_MODE(x)
FORCE_EVENT - Force Event
#define	USDHC_FORCE_EVENT_FEVTAC12NE_MASK   (0x1U)
#define	USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT   (0U)
#define	USDHC_FORCE_EVENT_FEVTAC12NE(x)
#define	USDHC_FORCE_EVENT_FEVTAC12TOE_MASK   (0x2U)
#define	USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT   (1U)
#define	USDHC_FORCE_EVENT_FEVTAC12TOE(x)
#define	USDHC_FORCE_EVENT_FEVTAC12CE_MASK   (0x4U)
#define	USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT   (2U)
#define	USDHC_FORCE_EVENT_FEVTAC12CE(x)
#define	USDHC_FORCE_EVENT_FEVTAC12EBE_MASK   (0x8U)
#define	USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT   (3U)
#define	USDHC_FORCE_EVENT_FEVTAC12EBE(x)
#define	USDHC_FORCE_EVENT_FEVTAC12IE_MASK   (0x10U)
#define	USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT   (4U)
#define	USDHC_FORCE_EVENT_FEVTAC12IE(x)
#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK   (0x80U)
#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT   (7U)
#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)
#define	USDHC_FORCE_EVENT_FEVTCTOE_MASK   (0x10000U)
#define	USDHC_FORCE_EVENT_FEVTCTOE_SHIFT   (16U)
#define	USDHC_FORCE_EVENT_FEVTCTOE(x)
#define	USDHC_FORCE_EVENT_FEVTCCE_MASK   (0x20000U)
#define	USDHC_FORCE_EVENT_FEVTCCE_SHIFT   (17U)
#define	USDHC_FORCE_EVENT_FEVTCCE(x)
#define	USDHC_FORCE_EVENT_FEVTCEBE_MASK   (0x40000U)
#define	USDHC_FORCE_EVENT_FEVTCEBE_SHIFT   (18U)
#define	USDHC_FORCE_EVENT_FEVTCEBE(x)
#define	USDHC_FORCE_EVENT_FEVTCIE_MASK   (0x80000U)
#define	USDHC_FORCE_EVENT_FEVTCIE_SHIFT   (19U)
#define	USDHC_FORCE_EVENT_FEVTCIE(x)
#define	USDHC_FORCE_EVENT_FEVTDTOE_MASK   (0x100000U)
#define	USDHC_FORCE_EVENT_FEVTDTOE_SHIFT   (20U)
#define	USDHC_FORCE_EVENT_FEVTDTOE(x)
#define	USDHC_FORCE_EVENT_FEVTDCE_MASK   (0x200000U)
#define	USDHC_FORCE_EVENT_FEVTDCE_SHIFT   (21U)
#define	USDHC_FORCE_EVENT_FEVTDCE(x)
#define	USDHC_FORCE_EVENT_FEVTDEBE_MASK   (0x400000U)
#define	USDHC_FORCE_EVENT_FEVTDEBE_SHIFT   (22U)
#define	USDHC_FORCE_EVENT_FEVTDEBE(x)
#define	USDHC_FORCE_EVENT_FEVTAC12E_MASK   (0x1000000U)
#define	USDHC_FORCE_EVENT_FEVTAC12E_SHIFT   (24U)
#define	USDHC_FORCE_EVENT_FEVTAC12E(x)
#define	USDHC_FORCE_EVENT_FEVTTNE_MASK   (0x4000000U)
#define	USDHC_FORCE_EVENT_FEVTTNE_SHIFT   (26U)
#define	USDHC_FORCE_EVENT_FEVTTNE(x)
#define	USDHC_FORCE_EVENT_FEVTDMAE_MASK   (0x10000000U)
#define	USDHC_FORCE_EVENT_FEVTDMAE_SHIFT   (28U)
#define	USDHC_FORCE_EVENT_FEVTDMAE(x)
#define	USDHC_FORCE_EVENT_FEVTCINT_MASK   (0x80000000U)
#define	USDHC_FORCE_EVENT_FEVTCINT_SHIFT   (31U)
#define	USDHC_FORCE_EVENT_FEVTCINT(x)
ADMA_ERR_STATUS - ADMA Error Status
#define	USDHC_ADMA_ERR_STATUS_ADMAES_MASK   (0x3U)
#define	USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT   (0U)
#define	USDHC_ADMA_ERR_STATUS_ADMAES(x)
#define	USDHC_ADMA_ERR_STATUS_ADMALME_MASK   (0x4U)
#define	USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT   (2U)
#define	USDHC_ADMA_ERR_STATUS_ADMALME(x)
#define	USDHC_ADMA_ERR_STATUS_ADMADCE_MASK   (0x8U)
#define	USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT   (3U)
#define	USDHC_ADMA_ERR_STATUS_ADMADCE(x)
ADMA_SYS_ADDR - ADMA System Address
#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK   (0xFFFFFFFCU)
#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT   (2U)
#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)
DLL_CTRL - DLL (Delay Line) Control
#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK   (0x1U)
#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT   (0U)
#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK   (0x2U)
#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT   (1U)
#define	USDHC_DLL_CTRL_DLL_CTRL_RESET(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK   (0x4U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT   (2U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK   (0x78U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT   (3U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK   (0x80U)
#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT   (7U)
#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK   (0x100U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT   (8U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK   (0xFE00U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT   (9U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK   (0x70000U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT   (16U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK   (0xFF00000U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT   (20U)
#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x)
#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK   (0xF0000000U)
#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT   (28U)
#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x)
DLL_STATUS - DLL Status
#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT   (0U)
#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)
#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT   (1U)
#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)
#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK   (0x1FCU)
#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)
#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK   (0xFE00U)
#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)
CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK   (0xFU)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT   (0U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK   (0xF0U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT   (4U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK   (0x7F00U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT   (8U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK   (0x8000U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT   (15U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK   (0xF0000U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT   (16U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK   (0xF00000U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT   (20U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK   (0x7F000000U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT   (24U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x)
#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK   (0x80000000U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT   (31U)
#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)
STROBE_DLL_CTRL - Strobe DLL control
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK   (0x1U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT   (0U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK   (0x2U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT   (1U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK   (0x4U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT   (2U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK   (0x78U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT   (3U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK   (0x80U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT   (7U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK   (0x100U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT   (8U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK   (0xFE00U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT   (9U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK   (0xFF00000U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT   (20U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK   (0xF0000000U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT   (28U)
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x)
STROBE_DLL_STATUS - Strobe DLL status
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK   (0x1U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT   (0U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK   (0x2U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT   (1U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK   (0x1FCU)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT   (2U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK   (0xFE00U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT   (9U)
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x)
VEND_SPEC - Vendor Specific Register
#define	USDHC_VEND_SPEC_VSELECT_MASK   (0x2U)
#define	USDHC_VEND_SPEC_VSELECT_SHIFT   (1U)
#define	USDHC_VEND_SPEC_VSELECT(x)
#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK   (0x4U)
#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT   (2U)
#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)
#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK   (0x8U)
#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT   (3U)
#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)
#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK   (0x100U)
#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT   (8U)
#define	USDHC_VEND_SPEC_FRC_SDCLK_ON(x)
#define	USDHC_VEND_SPEC_CRC_CHK_DIS_MASK   (0x8000U)
#define	USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT   (15U)
#define	USDHC_VEND_SPEC_CRC_CHK_DIS(x)
#define	USDHC_VEND_SPEC_CMD_BYTE_EN_MASK   (0x80000000U)
#define	USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT   (31U)
#define	USDHC_VEND_SPEC_CMD_BYTE_EN(x)
MMC_BOOT - MMC Boot
#define	USDHC_MMC_BOOT_DTOCV_ACK_MASK   (0xFU)
#define	USDHC_MMC_BOOT_DTOCV_ACK_SHIFT   (0U)
#define	USDHC_MMC_BOOT_DTOCV_ACK(x)
#define	USDHC_MMC_BOOT_BOOT_ACK_MASK   (0x10U)
#define	USDHC_MMC_BOOT_BOOT_ACK_SHIFT   (4U)
#define	USDHC_MMC_BOOT_BOOT_ACK(x)
#define	USDHC_MMC_BOOT_BOOT_MODE_MASK   (0x20U)
#define	USDHC_MMC_BOOT_BOOT_MODE_SHIFT   (5U)
#define	USDHC_MMC_BOOT_BOOT_MODE(x)
#define	USDHC_MMC_BOOT_BOOT_EN_MASK   (0x40U)
#define	USDHC_MMC_BOOT_BOOT_EN_SHIFT   (6U)
#define	USDHC_MMC_BOOT_BOOT_EN(x)
#define	USDHC_MMC_BOOT_AUTO_SABG_EN_MASK   (0x80U)
#define	USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT   (7U)
#define	USDHC_MMC_BOOT_AUTO_SABG_EN(x)
#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK   (0x100U)
#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT   (8U)
#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)
#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK   (0xFFFF0000U)
#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT   (16U)
#define	USDHC_MMC_BOOT_BOOT_BLK_CNT(x)
VEND_SPEC2 - Vendor Specific 2 Register
#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT   (3U)
#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)
#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK   (0x10U)
#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT   (4U)
#define	USDHC_VEND_SPEC2_TUNING_8bit_EN(x)
#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK   (0x20U)
#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT   (5U)
#define	USDHC_VEND_SPEC2_TUNING_1bit_EN(x)
#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK   (0x40U)
#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT   (6U)
#define	USDHC_VEND_SPEC2_TUNING_CMD_EN(x)
#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK   (0x400U)
#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT   (10U)
#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x)
#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK   (0x800U)
#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT   (11U)
#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x)
#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK   (0x1000U)
#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)
TUNING_CTRL - Tuning Control
#define	USDHC_TUNING_CTRL_TUNING_START_TAP_MASK   (0x7FU)
#define	USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT   (0U)
#define	USDHC_TUNING_CTRL_TUNING_START_TAP(x)
#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK   (0x80U)
#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT   (7U)
#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x)
#define	USDHC_TUNING_CTRL_TUNING_COUNTER_MASK   (0xFF00U)
#define	USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
#define	USDHC_TUNING_CTRL_TUNING_COUNTER(x)
#define	USDHC_TUNING_CTRL_TUNING_STEP_MASK   (0x70000U)
#define	USDHC_TUNING_CTRL_TUNING_STEP_SHIFT   (16U)
#define	USDHC_TUNING_CTRL_TUNING_STEP(x)
#define	USDHC_TUNING_CTRL_TUNING_WINDOW_MASK   (0x700000U)
#define	USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT   (20U)
#define	USDHC_TUNING_CTRL_TUNING_WINDOW(x)
#define	USDHC_TUNING_CTRL_STD_TUNING_EN_MASK   (0x1000000U)
#define	USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT   (24U)
#define	USDHC_TUNING_CTRL_STD_TUNING_EN(x)
VID_MUX_CTRL - Video mux Control Register
#define	VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK   (0x1U)
#define	VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT   (0U)
#define	VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x)
#define	VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK   (0x2U)
#define	VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT   (1U)
#define	VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x)
#define	VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK   (0x4U)
#define	VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT   (2U)
#define	VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x)
#define	VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK   (0x8U)
#define	VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT   (3U)
#define	VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x)
PLM_CTRL - Pixel Link Master(PLM) Control Register
#define	VIDEO_MUX_PLM_CTRL_ENABLE_MASK   (0x1U)
#define	VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT   (0U)
#define	VIDEO_MUX_PLM_CTRL_ENABLE(x)
#define	VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK   (0x2U)
#define	VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT   (1U)
#define	VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x)
#define	VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK   (0x4U)
#define	VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT   (2U)
#define	VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x)
#define	VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK   (0x8U)
#define	VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT   (3U)
#define	VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x)
#define	VIDEO_MUX_PLM_CTRL_POLARITY_MASK   (0x10U)
#define	VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT   (4U)
#define	VIDEO_MUX_PLM_CTRL_POLARITY(x)
YUV420_CTRL - YUV420 Control Register
#define	VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK   (0x1U)
#define	VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT   (0U)
#define	VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x)
CFG_DT_DISABLE - Data Disable Register
#define	VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK   (0xFFFFFFU)
#define	VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT   (0U)
#define	VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x)
MIPI_DSI_CTRL - MIPI DSI Control Register
#define	VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK   (0x1U)
#define	VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT   (0U)
#define	VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x)
#define	VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK   (0x2U)
#define	VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT   (1U)
#define	VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x)
WCR - Watchdog Control Register
#define	WDOG_WCR_WDZST_MASK   (0x1U)
#define	WDOG_WCR_WDZST_SHIFT   (0U)
#define	WDOG_WCR_WDZST(x)
#define	WDOG_WCR_WDBG_MASK   (0x2U)
#define	WDOG_WCR_WDBG_SHIFT   (1U)
#define	WDOG_WCR_WDBG(x)
#define	WDOG_WCR_WDE_MASK   (0x4U)
#define	WDOG_WCR_WDE_SHIFT   (2U)
#define	WDOG_WCR_WDE(x)
#define	WDOG_WCR_WDT_MASK   (0x8U)
#define	WDOG_WCR_WDT_SHIFT   (3U)
#define	WDOG_WCR_WDT(x)
#define	WDOG_WCR_SRS_MASK   (0x10U)
#define	WDOG_WCR_SRS_SHIFT   (4U)
#define	WDOG_WCR_SRS(x)
#define	WDOG_WCR_WDA_MASK   (0x20U)
#define	WDOG_WCR_WDA_SHIFT   (5U)
#define	WDOG_WCR_WDA(x)
#define	WDOG_WCR_SRE_MASK   (0x40U)
#define	WDOG_WCR_SRE_SHIFT   (6U)
#define	WDOG_WCR_SRE(x)
#define	WDOG_WCR_WDW_MASK   (0x80U)
#define	WDOG_WCR_WDW_SHIFT   (7U)
#define	WDOG_WCR_WDW(x)
#define	WDOG_WCR_WT_MASK   (0xFF00U)
#define	WDOG_WCR_WT_SHIFT   (8U)
#define	WDOG_WCR_WT(x)
WSR - Watchdog Service Register
#define	WDOG_WSR_WSR_MASK   (0xFFFFU)
#define	WDOG_WSR_WSR_SHIFT   (0U)
#define	WDOG_WSR_WSR(x)
WRSR - Watchdog Reset Status Register
#define	WDOG_WRSR_SFTW_MASK   (0x1U)
#define	WDOG_WRSR_SFTW_SHIFT   (0U)
#define	WDOG_WRSR_SFTW(x)
#define	WDOG_WRSR_TOUT_MASK   (0x2U)
#define	WDOG_WRSR_TOUT_SHIFT   (1U)
#define	WDOG_WRSR_TOUT(x)
#define	WDOG_WRSR_POR_MASK   (0x10U)
#define	WDOG_WRSR_POR_SHIFT   (4U)
#define	WDOG_WRSR_POR(x)
WICR - Watchdog Interrupt Control Register
#define	WDOG_WICR_WICT_MASK   (0xFFU)
#define	WDOG_WICR_WICT_SHIFT   (0U)
#define	WDOG_WICR_WICT(x)
#define	WDOG_WICR_WTIS_MASK   (0x4000U)
#define	WDOG_WICR_WTIS_SHIFT   (14U)
#define	WDOG_WICR_WTIS(x)
#define	WDOG_WICR_WIE_MASK   (0x8000U)
#define	WDOG_WICR_WIE_SHIFT   (15U)
#define	WDOG_WICR_WIE(x)
WMCR - Watchdog Miscellaneous Control Register
#define	WDOG_WMCR_PDE_MASK   (0x1U)
#define	WDOG_WMCR_PDE_SHIFT   (0U)
#define	WDOG_WMCR_PDE(x)
SEL0 - Crossbar A Select Register 0
#define	XBARA_SEL0_SEL0_MASK   (0xFFU)
#define	XBARA_SEL0_SEL0_SHIFT   (0U)
#define	XBARA_SEL0_SEL0(x)
#define	XBARA_SEL0_SEL1_MASK   (0xFF00U)
#define	XBARA_SEL0_SEL1_SHIFT   (8U)
#define	XBARA_SEL0_SEL1(x)
SEL1 - Crossbar A Select Register 1
#define	XBARA_SEL1_SEL2_MASK   (0xFFU)
#define	XBARA_SEL1_SEL2_SHIFT   (0U)
#define	XBARA_SEL1_SEL2(x)
#define	XBARA_SEL1_SEL3_MASK   (0xFF00U)
#define	XBARA_SEL1_SEL3_SHIFT   (8U)
#define	XBARA_SEL1_SEL3(x)
SEL2 - Crossbar A Select Register 2
#define	XBARA_SEL2_SEL4_MASK   (0xFFU)
#define	XBARA_SEL2_SEL4_SHIFT   (0U)
#define	XBARA_SEL2_SEL4(x)
#define	XBARA_SEL2_SEL5_MASK   (0xFF00U)
#define	XBARA_SEL2_SEL5_SHIFT   (8U)
#define	XBARA_SEL2_SEL5(x)
SEL3 - Crossbar A Select Register 3
#define	XBARA_SEL3_SEL6_MASK   (0xFFU)
#define	XBARA_SEL3_SEL6_SHIFT   (0U)
#define	XBARA_SEL3_SEL6(x)
#define	XBARA_SEL3_SEL7_MASK   (0xFF00U)
#define	XBARA_SEL3_SEL7_SHIFT   (8U)
#define	XBARA_SEL3_SEL7(x)
SEL4 - Crossbar A Select Register 4
#define	XBARA_SEL4_SEL8_MASK   (0xFFU)
#define	XBARA_SEL4_SEL8_SHIFT   (0U)
#define	XBARA_SEL4_SEL8(x)
#define	XBARA_SEL4_SEL9_MASK   (0xFF00U)
#define	XBARA_SEL4_SEL9_SHIFT   (8U)
#define	XBARA_SEL4_SEL9(x)
SEL5 - Crossbar A Select Register 5
#define	XBARA_SEL5_SEL10_MASK   (0xFFU)
#define	XBARA_SEL5_SEL10_SHIFT   (0U)
#define	XBARA_SEL5_SEL10(x)
#define	XBARA_SEL5_SEL11_MASK   (0xFF00U)
#define	XBARA_SEL5_SEL11_SHIFT   (8U)
#define	XBARA_SEL5_SEL11(x)
SEL6 - Crossbar A Select Register 6
#define	XBARA_SEL6_SEL12_MASK   (0xFFU)
#define	XBARA_SEL6_SEL12_SHIFT   (0U)
#define	XBARA_SEL6_SEL12(x)
#define	XBARA_SEL6_SEL13_MASK   (0xFF00U)
#define	XBARA_SEL6_SEL13_SHIFT   (8U)
#define	XBARA_SEL6_SEL13(x)
SEL7 - Crossbar A Select Register 7
#define	XBARA_SEL7_SEL14_MASK   (0xFFU)
#define	XBARA_SEL7_SEL14_SHIFT   (0U)
#define	XBARA_SEL7_SEL14(x)
#define	XBARA_SEL7_SEL15_MASK   (0xFF00U)
#define	XBARA_SEL7_SEL15_SHIFT   (8U)
#define	XBARA_SEL7_SEL15(x)
SEL8 - Crossbar A Select Register 8
#define	XBARA_SEL8_SEL16_MASK   (0xFFU)
#define	XBARA_SEL8_SEL16_SHIFT   (0U)
#define	XBARA_SEL8_SEL16(x)
#define	XBARA_SEL8_SEL17_MASK   (0xFF00U)
#define	XBARA_SEL8_SEL17_SHIFT   (8U)
#define	XBARA_SEL8_SEL17(x)
SEL9 - Crossbar A Select Register 9
#define	XBARA_SEL9_SEL18_MASK   (0xFFU)
#define	XBARA_SEL9_SEL18_SHIFT   (0U)
#define	XBARA_SEL9_SEL18(x)
#define	XBARA_SEL9_SEL19_MASK   (0xFF00U)
#define	XBARA_SEL9_SEL19_SHIFT   (8U)
#define	XBARA_SEL9_SEL19(x)
SEL10 - Crossbar A Select Register 10
#define	XBARA_SEL10_SEL20_MASK   (0xFFU)
#define	XBARA_SEL10_SEL20_SHIFT   (0U)
#define	XBARA_SEL10_SEL20(x)
#define	XBARA_SEL10_SEL21_MASK   (0xFF00U)
#define	XBARA_SEL10_SEL21_SHIFT   (8U)
#define	XBARA_SEL10_SEL21(x)
SEL11 - Crossbar A Select Register 11
#define	XBARA_SEL11_SEL22_MASK   (0xFFU)
#define	XBARA_SEL11_SEL22_SHIFT   (0U)
#define	XBARA_SEL11_SEL22(x)
#define	XBARA_SEL11_SEL23_MASK   (0xFF00U)
#define	XBARA_SEL11_SEL23_SHIFT   (8U)
#define	XBARA_SEL11_SEL23(x)
SEL12 - Crossbar A Select Register 12
#define	XBARA_SEL12_SEL24_MASK   (0xFFU)
#define	XBARA_SEL12_SEL24_SHIFT   (0U)
#define	XBARA_SEL12_SEL24(x)
#define	XBARA_SEL12_SEL25_MASK   (0xFF00U)
#define	XBARA_SEL12_SEL25_SHIFT   (8U)
#define	XBARA_SEL12_SEL25(x)
SEL13 - Crossbar A Select Register 13
#define	XBARA_SEL13_SEL26_MASK   (0xFFU)
#define	XBARA_SEL13_SEL26_SHIFT   (0U)
#define	XBARA_SEL13_SEL26(x)
#define	XBARA_SEL13_SEL27_MASK   (0xFF00U)
#define	XBARA_SEL13_SEL27_SHIFT   (8U)
#define	XBARA_SEL13_SEL27(x)
SEL14 - Crossbar A Select Register 14
#define	XBARA_SEL14_SEL28_MASK   (0xFFU)
#define	XBARA_SEL14_SEL28_SHIFT   (0U)
#define	XBARA_SEL14_SEL28(x)
#define	XBARA_SEL14_SEL29_MASK   (0xFF00U)
#define	XBARA_SEL14_SEL29_SHIFT   (8U)
#define	XBARA_SEL14_SEL29(x)
SEL15 - Crossbar A Select Register 15
#define	XBARA_SEL15_SEL30_MASK   (0xFFU)
#define	XBARA_SEL15_SEL30_SHIFT   (0U)
#define	XBARA_SEL15_SEL30(x)
#define	XBARA_SEL15_SEL31_MASK   (0xFF00U)
#define	XBARA_SEL15_SEL31_SHIFT   (8U)
#define	XBARA_SEL15_SEL31(x)
SEL16 - Crossbar A Select Register 16
#define	XBARA_SEL16_SEL32_MASK   (0xFFU)
#define	XBARA_SEL16_SEL32_SHIFT   (0U)
#define	XBARA_SEL16_SEL32(x)
#define	XBARA_SEL16_SEL33_MASK   (0xFF00U)
#define	XBARA_SEL16_SEL33_SHIFT   (8U)
#define	XBARA_SEL16_SEL33(x)
SEL17 - Crossbar A Select Register 17
#define	XBARA_SEL17_SEL34_MASK   (0xFFU)
#define	XBARA_SEL17_SEL34_SHIFT   (0U)
#define	XBARA_SEL17_SEL34(x)
#define	XBARA_SEL17_SEL35_MASK   (0xFF00U)
#define	XBARA_SEL17_SEL35_SHIFT   (8U)
#define	XBARA_SEL17_SEL35(x)
SEL18 - Crossbar A Select Register 18
#define	XBARA_SEL18_SEL36_MASK   (0xFFU)
#define	XBARA_SEL18_SEL36_SHIFT   (0U)
#define	XBARA_SEL18_SEL36(x)
#define	XBARA_SEL18_SEL37_MASK   (0xFF00U)
#define	XBARA_SEL18_SEL37_SHIFT   (8U)
#define	XBARA_SEL18_SEL37(x)
SEL19 - Crossbar A Select Register 19
#define	XBARA_SEL19_SEL38_MASK   (0xFFU)
#define	XBARA_SEL19_SEL38_SHIFT   (0U)
#define	XBARA_SEL19_SEL38(x)
#define	XBARA_SEL19_SEL39_MASK   (0xFF00U)
#define	XBARA_SEL19_SEL39_SHIFT   (8U)
#define	XBARA_SEL19_SEL39(x)
SEL20 - Crossbar A Select Register 20
#define	XBARA_SEL20_SEL40_MASK   (0xFFU)
#define	XBARA_SEL20_SEL40_SHIFT   (0U)
#define	XBARA_SEL20_SEL40(x)
#define	XBARA_SEL20_SEL41_MASK   (0xFF00U)
#define	XBARA_SEL20_SEL41_SHIFT   (8U)
#define	XBARA_SEL20_SEL41(x)
SEL21 - Crossbar A Select Register 21
#define	XBARA_SEL21_SEL42_MASK   (0xFFU)
#define	XBARA_SEL21_SEL42_SHIFT   (0U)
#define	XBARA_SEL21_SEL42(x)
#define	XBARA_SEL21_SEL43_MASK   (0xFF00U)
#define	XBARA_SEL21_SEL43_SHIFT   (8U)
#define	XBARA_SEL21_SEL43(x)
SEL22 - Crossbar A Select Register 22
#define	XBARA_SEL22_SEL44_MASK   (0xFFU)
#define	XBARA_SEL22_SEL44_SHIFT   (0U)
#define	XBARA_SEL22_SEL44(x)
#define	XBARA_SEL22_SEL45_MASK   (0xFF00U)
#define	XBARA_SEL22_SEL45_SHIFT   (8U)
#define	XBARA_SEL22_SEL45(x)
SEL23 - Crossbar A Select Register 23
#define	XBARA_SEL23_SEL46_MASK   (0xFFU)
#define	XBARA_SEL23_SEL46_SHIFT   (0U)
#define	XBARA_SEL23_SEL46(x)
#define	XBARA_SEL23_SEL47_MASK   (0xFF00U)
#define	XBARA_SEL23_SEL47_SHIFT   (8U)
#define	XBARA_SEL23_SEL47(x)
SEL24 - Crossbar A Select Register 24
#define	XBARA_SEL24_SEL48_MASK   (0xFFU)
#define	XBARA_SEL24_SEL48_SHIFT   (0U)
#define	XBARA_SEL24_SEL48(x)
#define	XBARA_SEL24_SEL49_MASK   (0xFF00U)
#define	XBARA_SEL24_SEL49_SHIFT   (8U)
#define	XBARA_SEL24_SEL49(x)
SEL25 - Crossbar A Select Register 25
#define	XBARA_SEL25_SEL50_MASK   (0xFFU)
#define	XBARA_SEL25_SEL50_SHIFT   (0U)
#define	XBARA_SEL25_SEL50(x)
#define	XBARA_SEL25_SEL51_MASK   (0xFF00U)
#define	XBARA_SEL25_SEL51_SHIFT   (8U)
#define	XBARA_SEL25_SEL51(x)
SEL26 - Crossbar A Select Register 26
#define	XBARA_SEL26_SEL52_MASK   (0xFFU)
#define	XBARA_SEL26_SEL52_SHIFT   (0U)
#define	XBARA_SEL26_SEL52(x)
#define	XBARA_SEL26_SEL53_MASK   (0xFF00U)
#define	XBARA_SEL26_SEL53_SHIFT   (8U)
#define	XBARA_SEL26_SEL53(x)
SEL27 - Crossbar A Select Register 27
#define	XBARA_SEL27_SEL54_MASK   (0xFFU)
#define	XBARA_SEL27_SEL54_SHIFT   (0U)
#define	XBARA_SEL27_SEL54(x)
#define	XBARA_SEL27_SEL55_MASK   (0xFF00U)
#define	XBARA_SEL27_SEL55_SHIFT   (8U)
#define	XBARA_SEL27_SEL55(x)
SEL28 - Crossbar A Select Register 28
#define	XBARA_SEL28_SEL56_MASK   (0xFFU)
#define	XBARA_SEL28_SEL56_SHIFT   (0U)
#define	XBARA_SEL28_SEL56(x)
#define	XBARA_SEL28_SEL57_MASK   (0xFF00U)
#define	XBARA_SEL28_SEL57_SHIFT   (8U)
#define	XBARA_SEL28_SEL57(x)
SEL29 - Crossbar A Select Register 29
#define	XBARA_SEL29_SEL58_MASK   (0xFFU)
#define	XBARA_SEL29_SEL58_SHIFT   (0U)
#define	XBARA_SEL29_SEL58(x)
#define	XBARA_SEL29_SEL59_MASK   (0xFF00U)
#define	XBARA_SEL29_SEL59_SHIFT   (8U)
#define	XBARA_SEL29_SEL59(x)
SEL30 - Crossbar A Select Register 30
#define	XBARA_SEL30_SEL60_MASK   (0xFFU)
#define	XBARA_SEL30_SEL60_SHIFT   (0U)
#define	XBARA_SEL30_SEL60(x)
#define	XBARA_SEL30_SEL61_MASK   (0xFF00U)
#define	XBARA_SEL30_SEL61_SHIFT   (8U)
#define	XBARA_SEL30_SEL61(x)
SEL31 - Crossbar A Select Register 31
#define	XBARA_SEL31_SEL62_MASK   (0xFFU)
#define	XBARA_SEL31_SEL62_SHIFT   (0U)
#define	XBARA_SEL31_SEL62(x)
#define	XBARA_SEL31_SEL63_MASK   (0xFF00U)
#define	XBARA_SEL31_SEL63_SHIFT   (8U)
#define	XBARA_SEL31_SEL63(x)
SEL32 - Crossbar A Select Register 32
#define	XBARA_SEL32_SEL64_MASK   (0xFFU)
#define	XBARA_SEL32_SEL64_SHIFT   (0U)
#define	XBARA_SEL32_SEL64(x)
#define	XBARA_SEL32_SEL65_MASK   (0xFF00U)
#define	XBARA_SEL32_SEL65_SHIFT   (8U)
#define	XBARA_SEL32_SEL65(x)
SEL33 - Crossbar A Select Register 33
#define	XBARA_SEL33_SEL66_MASK   (0xFFU)
#define	XBARA_SEL33_SEL66_SHIFT   (0U)
#define	XBARA_SEL33_SEL66(x)
#define	XBARA_SEL33_SEL67_MASK   (0xFF00U)
#define	XBARA_SEL33_SEL67_SHIFT   (8U)
#define	XBARA_SEL33_SEL67(x)
SEL34 - Crossbar A Select Register 34
#define	XBARA_SEL34_SEL68_MASK   (0xFFU)
#define	XBARA_SEL34_SEL68_SHIFT   (0U)
#define	XBARA_SEL34_SEL68(x)
#define	XBARA_SEL34_SEL69_MASK   (0xFF00U)
#define	XBARA_SEL34_SEL69_SHIFT   (8U)
#define	XBARA_SEL34_SEL69(x)
SEL35 - Crossbar A Select Register 35
#define	XBARA_SEL35_SEL70_MASK   (0xFFU)
#define	XBARA_SEL35_SEL70_SHIFT   (0U)
#define	XBARA_SEL35_SEL70(x)
#define	XBARA_SEL35_SEL71_MASK   (0xFF00U)
#define	XBARA_SEL35_SEL71_SHIFT   (8U)
#define	XBARA_SEL35_SEL71(x)
SEL36 - Crossbar A Select Register 36
#define	XBARA_SEL36_SEL72_MASK   (0xFFU)
#define	XBARA_SEL36_SEL72_SHIFT   (0U)
#define	XBARA_SEL36_SEL72(x)
#define	XBARA_SEL36_SEL73_MASK   (0xFF00U)
#define	XBARA_SEL36_SEL73_SHIFT   (8U)
#define	XBARA_SEL36_SEL73(x)
SEL37 - Crossbar A Select Register 37
#define	XBARA_SEL37_SEL74_MASK   (0xFFU)
#define	XBARA_SEL37_SEL74_SHIFT   (0U)
#define	XBARA_SEL37_SEL74(x)
#define	XBARA_SEL37_SEL75_MASK   (0xFF00U)
#define	XBARA_SEL37_SEL75_SHIFT   (8U)
#define	XBARA_SEL37_SEL75(x)
SEL38 - Crossbar A Select Register 38
#define	XBARA_SEL38_SEL76_MASK   (0xFFU)
#define	XBARA_SEL38_SEL76_SHIFT   (0U)
#define	XBARA_SEL38_SEL76(x)
#define	XBARA_SEL38_SEL77_MASK   (0xFF00U)
#define	XBARA_SEL38_SEL77_SHIFT   (8U)
#define	XBARA_SEL38_SEL77(x)
SEL39 - Crossbar A Select Register 39
#define	XBARA_SEL39_SEL78_MASK   (0xFFU)
#define	XBARA_SEL39_SEL78_SHIFT   (0U)
#define	XBARA_SEL39_SEL78(x)
#define	XBARA_SEL39_SEL79_MASK   (0xFF00U)
#define	XBARA_SEL39_SEL79_SHIFT   (8U)
#define	XBARA_SEL39_SEL79(x)
SEL40 - Crossbar A Select Register 40
#define	XBARA_SEL40_SEL80_MASK   (0xFFU)
#define	XBARA_SEL40_SEL80_SHIFT   (0U)
#define	XBARA_SEL40_SEL80(x)
#define	XBARA_SEL40_SEL81_MASK   (0xFF00U)
#define	XBARA_SEL40_SEL81_SHIFT   (8U)
#define	XBARA_SEL40_SEL81(x)
SEL41 - Crossbar A Select Register 41
#define	XBARA_SEL41_SEL82_MASK   (0xFFU)
#define	XBARA_SEL41_SEL82_SHIFT   (0U)
#define	XBARA_SEL41_SEL82(x)
#define	XBARA_SEL41_SEL83_MASK   (0xFF00U)
#define	XBARA_SEL41_SEL83_SHIFT   (8U)
#define	XBARA_SEL41_SEL83(x)
SEL42 - Crossbar A Select Register 42
#define	XBARA_SEL42_SEL84_MASK   (0xFFU)
#define	XBARA_SEL42_SEL84_SHIFT   (0U)
#define	XBARA_SEL42_SEL84(x)
#define	XBARA_SEL42_SEL85_MASK   (0xFF00U)
#define	XBARA_SEL42_SEL85_SHIFT   (8U)
#define	XBARA_SEL42_SEL85(x)
SEL43 - Crossbar A Select Register 43
#define	XBARA_SEL43_SEL86_MASK   (0xFFU)
#define	XBARA_SEL43_SEL86_SHIFT   (0U)
#define	XBARA_SEL43_SEL86(x)
#define	XBARA_SEL43_SEL87_MASK   (0xFF00U)
#define	XBARA_SEL43_SEL87_SHIFT   (8U)
#define	XBARA_SEL43_SEL87(x)
SEL44 - Crossbar A Select Register 44
#define	XBARA_SEL44_SEL88_MASK   (0xFFU)
#define	XBARA_SEL44_SEL88_SHIFT   (0U)
#define	XBARA_SEL44_SEL88(x)
#define	XBARA_SEL44_SEL89_MASK   (0xFF00U)
#define	XBARA_SEL44_SEL89_SHIFT   (8U)
#define	XBARA_SEL44_SEL89(x)
SEL45 - Crossbar A Select Register 45
#define	XBARA_SEL45_SEL90_MASK   (0xFFU)
#define	XBARA_SEL45_SEL90_SHIFT   (0U)
#define	XBARA_SEL45_SEL90(x)
#define	XBARA_SEL45_SEL91_MASK   (0xFF00U)
#define	XBARA_SEL45_SEL91_SHIFT   (8U)
#define	XBARA_SEL45_SEL91(x)
SEL46 - Crossbar A Select Register 46
#define	XBARA_SEL46_SEL92_MASK   (0xFFU)
#define	XBARA_SEL46_SEL92_SHIFT   (0U)
#define	XBARA_SEL46_SEL92(x)
#define	XBARA_SEL46_SEL93_MASK   (0xFF00U)
#define	XBARA_SEL46_SEL93_SHIFT   (8U)
#define	XBARA_SEL46_SEL93(x)
SEL47 - Crossbar A Select Register 47
#define	XBARA_SEL47_SEL94_MASK   (0xFFU)
#define	XBARA_SEL47_SEL94_SHIFT   (0U)
#define	XBARA_SEL47_SEL94(x)
#define	XBARA_SEL47_SEL95_MASK   (0xFF00U)
#define	XBARA_SEL47_SEL95_SHIFT   (8U)
#define	XBARA_SEL47_SEL95(x)
SEL48 - Crossbar A Select Register 48
#define	XBARA_SEL48_SEL96_MASK   (0xFFU)
#define	XBARA_SEL48_SEL96_SHIFT   (0U)
#define	XBARA_SEL48_SEL96(x)
#define	XBARA_SEL48_SEL97_MASK   (0xFF00U)
#define	XBARA_SEL48_SEL97_SHIFT   (8U)
#define	XBARA_SEL48_SEL97(x)
SEL49 - Crossbar A Select Register 49
#define	XBARA_SEL49_SEL98_MASK   (0xFFU)
#define	XBARA_SEL49_SEL98_SHIFT   (0U)
#define	XBARA_SEL49_SEL98(x)
#define	XBARA_SEL49_SEL99_MASK   (0xFF00U)
#define	XBARA_SEL49_SEL99_SHIFT   (8U)
#define	XBARA_SEL49_SEL99(x)
SEL50 - Crossbar A Select Register 50
#define	XBARA_SEL50_SEL100_MASK   (0xFFU)
#define	XBARA_SEL50_SEL100_SHIFT   (0U)
#define	XBARA_SEL50_SEL100(x)
#define	XBARA_SEL50_SEL101_MASK   (0xFF00U)
#define	XBARA_SEL50_SEL101_SHIFT   (8U)
#define	XBARA_SEL50_SEL101(x)
SEL51 - Crossbar A Select Register 51
#define	XBARA_SEL51_SEL102_MASK   (0xFFU)
#define	XBARA_SEL51_SEL102_SHIFT   (0U)
#define	XBARA_SEL51_SEL102(x)
#define	XBARA_SEL51_SEL103_MASK   (0xFF00U)
#define	XBARA_SEL51_SEL103_SHIFT   (8U)
#define	XBARA_SEL51_SEL103(x)
SEL52 - Crossbar A Select Register 52
#define	XBARA_SEL52_SEL104_MASK   (0xFFU)
#define	XBARA_SEL52_SEL104_SHIFT   (0U)
#define	XBARA_SEL52_SEL104(x)
#define	XBARA_SEL52_SEL105_MASK   (0xFF00U)
#define	XBARA_SEL52_SEL105_SHIFT   (8U)
#define	XBARA_SEL52_SEL105(x)
SEL53 - Crossbar A Select Register 53
#define	XBARA_SEL53_SEL106_MASK   (0xFFU)
#define	XBARA_SEL53_SEL106_SHIFT   (0U)
#define	XBARA_SEL53_SEL106(x)
#define	XBARA_SEL53_SEL107_MASK   (0xFF00U)
#define	XBARA_SEL53_SEL107_SHIFT   (8U)
#define	XBARA_SEL53_SEL107(x)
SEL54 - Crossbar A Select Register 54
#define	XBARA_SEL54_SEL108_MASK   (0xFFU)
#define	XBARA_SEL54_SEL108_SHIFT   (0U)
#define	XBARA_SEL54_SEL108(x)
#define	XBARA_SEL54_SEL109_MASK   (0xFF00U)
#define	XBARA_SEL54_SEL109_SHIFT   (8U)
#define	XBARA_SEL54_SEL109(x)
SEL55 - Crossbar A Select Register 55
#define	XBARA_SEL55_SEL110_MASK   (0xFFU)
#define	XBARA_SEL55_SEL110_SHIFT   (0U)
#define	XBARA_SEL55_SEL110(x)
#define	XBARA_SEL55_SEL111_MASK   (0xFF00U)
#define	XBARA_SEL55_SEL111_SHIFT   (8U)
#define	XBARA_SEL55_SEL111(x)
SEL56 - Crossbar A Select Register 56
#define	XBARA_SEL56_SEL112_MASK   (0xFFU)
#define	XBARA_SEL56_SEL112_SHIFT   (0U)
#define	XBARA_SEL56_SEL112(x)
#define	XBARA_SEL56_SEL113_MASK   (0xFF00U)
#define	XBARA_SEL56_SEL113_SHIFT   (8U)
#define	XBARA_SEL56_SEL113(x)
SEL57 - Crossbar A Select Register 57
#define	XBARA_SEL57_SEL114_MASK   (0xFFU)
#define	XBARA_SEL57_SEL114_SHIFT   (0U)
#define	XBARA_SEL57_SEL114(x)
#define	XBARA_SEL57_SEL115_MASK   (0xFF00U)
#define	XBARA_SEL57_SEL115_SHIFT   (8U)
#define	XBARA_SEL57_SEL115(x)
SEL58 - Crossbar A Select Register 58
#define	XBARA_SEL58_SEL116_MASK   (0xFFU)
#define	XBARA_SEL58_SEL116_SHIFT   (0U)
#define	XBARA_SEL58_SEL116(x)
#define	XBARA_SEL58_SEL117_MASK   (0xFF00U)
#define	XBARA_SEL58_SEL117_SHIFT   (8U)
#define	XBARA_SEL58_SEL117(x)
SEL59 - Crossbar A Select Register 59
#define	XBARA_SEL59_SEL118_MASK   (0xFFU)
#define	XBARA_SEL59_SEL118_SHIFT   (0U)
#define	XBARA_SEL59_SEL118(x)
#define	XBARA_SEL59_SEL119_MASK   (0xFF00U)
#define	XBARA_SEL59_SEL119_SHIFT   (8U)
#define	XBARA_SEL59_SEL119(x)
SEL60 - Crossbar A Select Register 60
#define	XBARA_SEL60_SEL120_MASK   (0xFFU)
#define	XBARA_SEL60_SEL120_SHIFT   (0U)
#define	XBARA_SEL60_SEL120(x)
#define	XBARA_SEL60_SEL121_MASK   (0xFF00U)
#define	XBARA_SEL60_SEL121_SHIFT   (8U)
#define	XBARA_SEL60_SEL121(x)
SEL61 - Crossbar A Select Register 61
#define	XBARA_SEL61_SEL122_MASK   (0xFFU)
#define	XBARA_SEL61_SEL122_SHIFT   (0U)
#define	XBARA_SEL61_SEL122(x)
#define	XBARA_SEL61_SEL123_MASK   (0xFF00U)
#define	XBARA_SEL61_SEL123_SHIFT   (8U)
#define	XBARA_SEL61_SEL123(x)
SEL62 - Crossbar A Select Register 62
#define	XBARA_SEL62_SEL124_MASK   (0xFFU)
#define	XBARA_SEL62_SEL124_SHIFT   (0U)
#define	XBARA_SEL62_SEL124(x)
#define	XBARA_SEL62_SEL125_MASK   (0xFF00U)
#define	XBARA_SEL62_SEL125_SHIFT   (8U)
#define	XBARA_SEL62_SEL125(x)
SEL63 - Crossbar A Select Register 63
#define	XBARA_SEL63_SEL126_MASK   (0xFFU)
#define	XBARA_SEL63_SEL126_SHIFT   (0U)
#define	XBARA_SEL63_SEL126(x)
#define	XBARA_SEL63_SEL127_MASK   (0xFF00U)
#define	XBARA_SEL63_SEL127_SHIFT   (8U)
#define	XBARA_SEL63_SEL127(x)
SEL64 - Crossbar A Select Register 64
#define	XBARA_SEL64_SEL128_MASK   (0xFFU)
#define	XBARA_SEL64_SEL128_SHIFT   (0U)
#define	XBARA_SEL64_SEL128(x)
#define	XBARA_SEL64_SEL129_MASK   (0xFF00U)
#define	XBARA_SEL64_SEL129_SHIFT   (8U)
#define	XBARA_SEL64_SEL129(x)
SEL65 - Crossbar A Select Register 65
#define	XBARA_SEL65_SEL130_MASK   (0xFFU)
#define	XBARA_SEL65_SEL130_SHIFT   (0U)
#define	XBARA_SEL65_SEL130(x)
#define	XBARA_SEL65_SEL131_MASK   (0xFF00U)
#define	XBARA_SEL65_SEL131_SHIFT   (8U)
#define	XBARA_SEL65_SEL131(x)
SEL66 - Crossbar A Select Register 66
#define	XBARA_SEL66_SEL132_MASK   (0xFFU)
#define	XBARA_SEL66_SEL132_SHIFT   (0U)
#define	XBARA_SEL66_SEL132(x)
#define	XBARA_SEL66_SEL133_MASK   (0xFF00U)
#define	XBARA_SEL66_SEL133_SHIFT   (8U)
#define	XBARA_SEL66_SEL133(x)
SEL67 - Crossbar A Select Register 67
#define	XBARA_SEL67_SEL134_MASK   (0xFFU)
#define	XBARA_SEL67_SEL134_SHIFT   (0U)
#define	XBARA_SEL67_SEL134(x)
#define	XBARA_SEL67_SEL135_MASK   (0xFF00U)
#define	XBARA_SEL67_SEL135_SHIFT   (8U)
#define	XBARA_SEL67_SEL135(x)
SEL68 - Crossbar A Select Register 68
#define	XBARA_SEL68_SEL136_MASK   (0xFFU)
#define	XBARA_SEL68_SEL136_SHIFT   (0U)
#define	XBARA_SEL68_SEL136(x)
#define	XBARA_SEL68_SEL137_MASK   (0xFF00U)
#define	XBARA_SEL68_SEL137_SHIFT   (8U)
#define	XBARA_SEL68_SEL137(x)
SEL69 - Crossbar A Select Register 69
#define	XBARA_SEL69_SEL138_MASK   (0xFFU)
#define	XBARA_SEL69_SEL138_SHIFT   (0U)
#define	XBARA_SEL69_SEL138(x)
#define	XBARA_SEL69_SEL139_MASK   (0xFF00U)
#define	XBARA_SEL69_SEL139_SHIFT   (8U)
#define	XBARA_SEL69_SEL139(x)
SEL70 - Crossbar A Select Register 70
#define	XBARA_SEL70_SEL140_MASK   (0xFFU)
#define	XBARA_SEL70_SEL140_SHIFT   (0U)
#define	XBARA_SEL70_SEL140(x)
#define	XBARA_SEL70_SEL141_MASK   (0xFF00U)
#define	XBARA_SEL70_SEL141_SHIFT   (8U)
#define	XBARA_SEL70_SEL141(x)
SEL71 - Crossbar A Select Register 71
#define	XBARA_SEL71_SEL142_MASK   (0xFFU)
#define	XBARA_SEL71_SEL142_SHIFT   (0U)
#define	XBARA_SEL71_SEL142(x)
#define	XBARA_SEL71_SEL143_MASK   (0xFF00U)
#define	XBARA_SEL71_SEL143_SHIFT   (8U)
#define	XBARA_SEL71_SEL143(x)
SEL72 - Crossbar A Select Register 72
#define	XBARA_SEL72_SEL144_MASK   (0xFFU)
#define	XBARA_SEL72_SEL144_SHIFT   (0U)
#define	XBARA_SEL72_SEL144(x)
#define	XBARA_SEL72_SEL145_MASK   (0xFF00U)
#define	XBARA_SEL72_SEL145_SHIFT   (8U)
#define	XBARA_SEL72_SEL145(x)
SEL73 - Crossbar A Select Register 73
#define	XBARA_SEL73_SEL146_MASK   (0xFFU)
#define	XBARA_SEL73_SEL146_SHIFT   (0U)
#define	XBARA_SEL73_SEL146(x)
#define	XBARA_SEL73_SEL147_MASK   (0xFF00U)
#define	XBARA_SEL73_SEL147_SHIFT   (8U)
#define	XBARA_SEL73_SEL147(x)
SEL74 - Crossbar A Select Register 74
#define	XBARA_SEL74_SEL148_MASK   (0xFFU)
#define	XBARA_SEL74_SEL148_SHIFT   (0U)
#define	XBARA_SEL74_SEL148(x)
#define	XBARA_SEL74_SEL149_MASK   (0xFF00U)
#define	XBARA_SEL74_SEL149_SHIFT   (8U)
#define	XBARA_SEL74_SEL149(x)
SEL75 - Crossbar A Select Register 75
#define	XBARA_SEL75_SEL150_MASK   (0xFFU)
#define	XBARA_SEL75_SEL150_SHIFT   (0U)
#define	XBARA_SEL75_SEL150(x)
#define	XBARA_SEL75_SEL151_MASK   (0xFF00U)
#define	XBARA_SEL75_SEL151_SHIFT   (8U)
#define	XBARA_SEL75_SEL151(x)
SEL76 - Crossbar A Select Register 76
#define	XBARA_SEL76_SEL152_MASK   (0xFFU)
#define	XBARA_SEL76_SEL152_SHIFT   (0U)
#define	XBARA_SEL76_SEL152(x)
#define	XBARA_SEL76_SEL153_MASK   (0xFF00U)
#define	XBARA_SEL76_SEL153_SHIFT   (8U)
#define	XBARA_SEL76_SEL153(x)
SEL77 - Crossbar A Select Register 77
#define	XBARA_SEL77_SEL154_MASK   (0xFFU)
#define	XBARA_SEL77_SEL154_SHIFT   (0U)
#define	XBARA_SEL77_SEL154(x)
#define	XBARA_SEL77_SEL155_MASK   (0xFF00U)
#define	XBARA_SEL77_SEL155_SHIFT   (8U)
#define	XBARA_SEL77_SEL155(x)
SEL78 - Crossbar A Select Register 78
#define	XBARA_SEL78_SEL156_MASK   (0xFFU)
#define	XBARA_SEL78_SEL156_SHIFT   (0U)
#define	XBARA_SEL78_SEL156(x)
#define	XBARA_SEL78_SEL157_MASK   (0xFF00U)
#define	XBARA_SEL78_SEL157_SHIFT   (8U)
#define	XBARA_SEL78_SEL157(x)
SEL79 - Crossbar A Select Register 79
#define	XBARA_SEL79_SEL158_MASK   (0xFFU)
#define	XBARA_SEL79_SEL158_SHIFT   (0U)
#define	XBARA_SEL79_SEL158(x)
#define	XBARA_SEL79_SEL159_MASK   (0xFF00U)
#define	XBARA_SEL79_SEL159_SHIFT   (8U)
#define	XBARA_SEL79_SEL159(x)
SEL80 - Crossbar A Select Register 80
#define	XBARA_SEL80_SEL160_MASK   (0xFFU)
#define	XBARA_SEL80_SEL160_SHIFT   (0U)
#define	XBARA_SEL80_SEL160(x)
#define	XBARA_SEL80_SEL161_MASK   (0xFF00U)
#define	XBARA_SEL80_SEL161_SHIFT   (8U)
#define	XBARA_SEL80_SEL161(x)
SEL81 - Crossbar A Select Register 81
#define	XBARA_SEL81_SEL162_MASK   (0xFFU)
#define	XBARA_SEL81_SEL162_SHIFT   (0U)
#define	XBARA_SEL81_SEL162(x)
#define	XBARA_SEL81_SEL163_MASK   (0xFF00U)
#define	XBARA_SEL81_SEL163_SHIFT   (8U)
#define	XBARA_SEL81_SEL163(x)
SEL82 - Crossbar A Select Register 82
#define	XBARA_SEL82_SEL164_MASK   (0xFFU)
#define	XBARA_SEL82_SEL164_SHIFT   (0U)
#define	XBARA_SEL82_SEL164(x)
#define	XBARA_SEL82_SEL165_MASK   (0xFF00U)
#define	XBARA_SEL82_SEL165_SHIFT   (8U)
#define	XBARA_SEL82_SEL165(x)
SEL83 - Crossbar A Select Register 83
#define	XBARA_SEL83_SEL166_MASK   (0xFFU)
#define	XBARA_SEL83_SEL166_SHIFT   (0U)
#define	XBARA_SEL83_SEL166(x)
#define	XBARA_SEL83_SEL167_MASK   (0xFF00U)
#define	XBARA_SEL83_SEL167_SHIFT   (8U)
#define	XBARA_SEL83_SEL167(x)
SEL84 - Crossbar A Select Register 84
#define	XBARA_SEL84_SEL168_MASK   (0xFFU)
#define	XBARA_SEL84_SEL168_SHIFT   (0U)
#define	XBARA_SEL84_SEL168(x)
#define	XBARA_SEL84_SEL169_MASK   (0xFF00U)
#define	XBARA_SEL84_SEL169_SHIFT   (8U)
#define	XBARA_SEL84_SEL169(x)
SEL85 - Crossbar A Select Register 85
#define	XBARA_SEL85_SEL170_MASK   (0xFFU)
#define	XBARA_SEL85_SEL170_SHIFT   (0U)
#define	XBARA_SEL85_SEL170(x)
#define	XBARA_SEL85_SEL171_MASK   (0xFF00U)
#define	XBARA_SEL85_SEL171_SHIFT   (8U)
#define	XBARA_SEL85_SEL171(x)
SEL86 - Crossbar A Select Register 86
#define	XBARA_SEL86_SEL172_MASK   (0xFFU)
#define	XBARA_SEL86_SEL172_SHIFT   (0U)
#define	XBARA_SEL86_SEL172(x)
#define	XBARA_SEL86_SEL173_MASK   (0xFF00U)
#define	XBARA_SEL86_SEL173_SHIFT   (8U)
#define	XBARA_SEL86_SEL173(x)
SEL87 - Crossbar A Select Register 87
#define	XBARA_SEL87_SEL174_MASK   (0xFFU)
#define	XBARA_SEL87_SEL174_SHIFT   (0U)
#define	XBARA_SEL87_SEL174(x)
#define	XBARA_SEL87_SEL175_MASK   (0xFF00U)
#define	XBARA_SEL87_SEL175_SHIFT   (8U)
#define	XBARA_SEL87_SEL175(x)
CTRL0 - Crossbar A Control Register 0
#define	XBARA_CTRL0_DEN0_MASK   (0x1U)
#define	XBARA_CTRL0_DEN0_SHIFT   (0U)
#define	XBARA_CTRL0_DEN0(x)
#define	XBARA_CTRL0_IEN0_MASK   (0x2U)
#define	XBARA_CTRL0_IEN0_SHIFT   (1U)
#define	XBARA_CTRL0_IEN0(x)
#define	XBARA_CTRL0_EDGE0_MASK   (0xCU)
#define	XBARA_CTRL0_EDGE0_SHIFT   (2U)
#define	XBARA_CTRL0_EDGE0(x)
#define	XBARA_CTRL0_STS0_MASK   (0x10U)
#define	XBARA_CTRL0_STS0_SHIFT   (4U)
#define	XBARA_CTRL0_STS0(x)
#define	XBARA_CTRL0_DEN1_MASK   (0x100U)
#define	XBARA_CTRL0_DEN1_SHIFT   (8U)
#define	XBARA_CTRL0_DEN1(x)
#define	XBARA_CTRL0_IEN1_MASK   (0x200U)
#define	XBARA_CTRL0_IEN1_SHIFT   (9U)
#define	XBARA_CTRL0_IEN1(x)
#define	XBARA_CTRL0_EDGE1_MASK   (0xC00U)
#define	XBARA_CTRL0_EDGE1_SHIFT   (10U)
#define	XBARA_CTRL0_EDGE1(x)
#define	XBARA_CTRL0_STS1_MASK   (0x1000U)
#define	XBARA_CTRL0_STS1_SHIFT   (12U)
#define	XBARA_CTRL0_STS1(x)
CTRL1 - Crossbar A Control Register 1
#define	XBARA_CTRL1_DEN2_MASK   (0x1U)
#define	XBARA_CTRL1_DEN2_SHIFT   (0U)
#define	XBARA_CTRL1_DEN2(x)
#define	XBARA_CTRL1_IEN2_MASK   (0x2U)
#define	XBARA_CTRL1_IEN2_SHIFT   (1U)
#define	XBARA_CTRL1_IEN2(x)
#define	XBARA_CTRL1_EDGE2_MASK   (0xCU)
#define	XBARA_CTRL1_EDGE2_SHIFT   (2U)
#define	XBARA_CTRL1_EDGE2(x)
#define	XBARA_CTRL1_STS2_MASK   (0x10U)
#define	XBARA_CTRL1_STS2_SHIFT   (4U)
#define	XBARA_CTRL1_STS2(x)
#define	XBARA_CTRL1_DEN3_MASK   (0x100U)
#define	XBARA_CTRL1_DEN3_SHIFT   (8U)
#define	XBARA_CTRL1_DEN3(x)
#define	XBARA_CTRL1_IEN3_MASK   (0x200U)
#define	XBARA_CTRL1_IEN3_SHIFT   (9U)
#define	XBARA_CTRL1_IEN3(x)
#define	XBARA_CTRL1_EDGE3_MASK   (0xC00U)
#define	XBARA_CTRL1_EDGE3_SHIFT   (10U)
#define	XBARA_CTRL1_EDGE3(x)
#define	XBARA_CTRL1_STS3_MASK   (0x1000U)
#define	XBARA_CTRL1_STS3_SHIFT   (12U)
#define	XBARA_CTRL1_STS3(x)
SEL0 - Crossbar B Select Register 0
#define	XBARB_SEL0_SEL0_MASK   (0x7FU)
#define	XBARB_SEL0_SEL0_SHIFT   (0U)
#define	XBARB_SEL0_SEL0(x)
#define	XBARB_SEL0_SEL1_MASK   (0x7F00U)
#define	XBARB_SEL0_SEL1_SHIFT   (8U)
#define	XBARB_SEL0_SEL1(x)
SEL1 - Crossbar B Select Register 1
#define	XBARB_SEL1_SEL2_MASK   (0x7FU)
#define	XBARB_SEL1_SEL2_SHIFT   (0U)
#define	XBARB_SEL1_SEL2(x)
#define	XBARB_SEL1_SEL3_MASK   (0x7F00U)
#define	XBARB_SEL1_SEL3_SHIFT   (8U)
#define	XBARB_SEL1_SEL3(x)
SEL2 - Crossbar B Select Register 2
#define	XBARB_SEL2_SEL4_MASK   (0x7FU)
#define	XBARB_SEL2_SEL4_SHIFT   (0U)
#define	XBARB_SEL2_SEL4(x)
#define	XBARB_SEL2_SEL5_MASK   (0x7F00U)
#define	XBARB_SEL2_SEL5_SHIFT   (8U)
#define	XBARB_SEL2_SEL5(x)
SEL3 - Crossbar B Select Register 3
#define	XBARB_SEL3_SEL6_MASK   (0x7FU)
#define	XBARB_SEL3_SEL6_SHIFT   (0U)
#define	XBARB_SEL3_SEL6(x)
#define	XBARB_SEL3_SEL7_MASK   (0x7F00U)
#define	XBARB_SEL3_SEL7_SHIFT   (8U)
#define	XBARB_SEL3_SEL7(x)
SEL4 - Crossbar B Select Register 4
#define	XBARB_SEL4_SEL8_MASK   (0x7FU)
#define	XBARB_SEL4_SEL8_SHIFT   (0U)
#define	XBARB_SEL4_SEL8(x)
#define	XBARB_SEL4_SEL9_MASK   (0x7F00U)
#define	XBARB_SEL4_SEL9_SHIFT   (8U)
#define	XBARB_SEL4_SEL9(x)
SEL5 - Crossbar B Select Register 5
#define	XBARB_SEL5_SEL10_MASK   (0x7FU)
#define	XBARB_SEL5_SEL10_SHIFT   (0U)
#define	XBARB_SEL5_SEL10(x)
#define	XBARB_SEL5_SEL11_MASK   (0x7F00U)
#define	XBARB_SEL5_SEL11_SHIFT   (8U)
#define	XBARB_SEL5_SEL11(x)
SEL6 - Crossbar B Select Register 6
#define	XBARB_SEL6_SEL12_MASK   (0x7FU)
#define	XBARB_SEL6_SEL12_SHIFT   (0U)
#define	XBARB_SEL6_SEL12(x)
#define	XBARB_SEL6_SEL13_MASK   (0x7F00U)
#define	XBARB_SEL6_SEL13_SHIFT   (8U)
#define	XBARB_SEL6_SEL13(x)
SEL7 - Crossbar B Select Register 7
#define	XBARB_SEL7_SEL14_MASK   (0x7FU)
#define	XBARB_SEL7_SEL14_SHIFT   (0U)
#define	XBARB_SEL7_SEL14(x)
#define	XBARB_SEL7_SEL15_MASK   (0x7F00U)
#define	XBARB_SEL7_SEL15_SHIFT   (8U)
#define	XBARB_SEL7_SEL15(x)
ECC_CTRL - ECC Control Register
#define	XECC_ECC_CTRL_ECC_EN_MASK   (0x1U)
#define	XECC_ECC_CTRL_ECC_EN_SHIFT   (0U)
#define	XECC_ECC_CTRL_ECC_EN(x)
#define	XECC_ECC_CTRL_WECC_EN_MASK   (0x2U)
#define	XECC_ECC_CTRL_WECC_EN_SHIFT   (1U)
#define	XECC_ECC_CTRL_WECC_EN(x)
#define	XECC_ECC_CTRL_RECC_EN_MASK   (0x4U)
#define	XECC_ECC_CTRL_RECC_EN_SHIFT   (2U)
#define	XECC_ECC_CTRL_RECC_EN(x)
#define	XECC_ECC_CTRL_SWAP_EN_MASK   (0x8U)
#define	XECC_ECC_CTRL_SWAP_EN_SHIFT   (3U)
#define	XECC_ECC_CTRL_SWAP_EN(x)
ERR_DATA_INJ - Error Injection On Write Data
#define	XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK   (0xFFFFFFFFU)
#define	XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT   (0U)
#define	XECC_ERR_DATA_INJ_ERR_DATA_INJ(x)
ERR_ECC_INJ - Error Injection On ECC Code of Write Data
#define	XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK   (0xFFFFFFFFU)
#define	XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT   (0U)
#define	XECC_ERR_ECC_INJ_ERR_ECC_INJ(x)
SINGLE_ERR_ADDR - Single Error Address
#define	XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK   (0xFFFFFFFFU)
#define	XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT   (0U)
#define	XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x)
SINGLE_ERR_DATA - Single Error Read Data
#define	XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT   (0U)
#define	XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x)
SINGLE_ERR_ECC - Single Error ECC Code
#define	XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK   (0xFFFFFFFFU)
#define	XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT   (0U)
#define	XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x)
SINGLE_ERR_POS - Single Error Bit Position
#define	XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK   (0xFFFFFFFFU)
#define	XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT   (0U)
#define	XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x)
SINGLE_ERR_BIT_FIELD - Single Error Bit Field
#define	XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK   (0xFFU)
#define	XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT   (0U)
#define	XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x)
#define	XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK   (0xFFFFFF00U)
#define	XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT   (8U)
#define	XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x)
MULTI_ERR_ADDR - Multiple Error Address
#define	XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK   (0xFFFFFFFFU)
#define	XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT   (0U)
#define	XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x)
MULTI_ERR_DATA - Multiple Error Read Data
#define	XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK   (0xFFFFFFFFU)
#define	XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT   (0U)
#define	XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x)
MULTI_ERR_ECC - Multiple Error ECC code
#define	XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK   (0xFFFFFFFFU)
#define	XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT   (0U)
#define	XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x)
MULTI_ERR_BIT_FIELD - Multiple Error Bit Field
#define	XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK   (0xFFU)
#define	XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT   (0U)
#define	XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x)
#define	XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK   (0xFFFFFF00U)
#define	XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT   (8U)
#define	XECC_MULTI_ERR_BIT_FIELD_Reserved1(x)
ECC_BASE_ADDR0 - ECC Region 0 Base Address
#define	XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT   (0U)
#define	XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x)
ECC_END_ADDR0 - ECC Region 0 End Address
#define	XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT   (0U)
#define	XECC_ECC_END_ADDR0_ECC_END_ADDR0(x)
ECC_BASE_ADDR1 - ECC Region 1 Base Address
#define	XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT   (0U)
#define	XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x)
ECC_END_ADDR1 - ECC Region 1 End Address
#define	XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT   (0U)
#define	XECC_ECC_END_ADDR1_ECC_END_ADDR1(x)
ECC_BASE_ADDR2 - ECC Region 2 Base Address
#define	XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT   (0U)
#define	XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x)
ECC_END_ADDR2 - ECC Region 2 End Address
#define	XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT   (0U)
#define	XECC_ECC_END_ADDR2_ECC_END_ADDR2(x)
ECC_BASE_ADDR3 - ECC Region 3 Base Address
#define	XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT   (0U)
#define	XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x)
ECC_END_ADDR3 - ECC Region 3 End Address
#define	XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK   (0xFFFFFFFFU)
#define	XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT   (0U)
#define	XECC_ECC_END_ADDR3_ECC_END_ADDR3(x)
MSC_MSAC_W0 - Memory Slot Access Control
#define	XRDC2_MSC_MSAC_W0_D0ACP_MASK   (0x7U)
#define	XRDC2_MSC_MSAC_W0_D0ACP_SHIFT   (0U)
#define	XRDC2_MSC_MSAC_W0_D0ACP(x)
#define	XRDC2_MSC_MSAC_W0_D1ACP_MASK   (0x38U)
#define	XRDC2_MSC_MSAC_W0_D1ACP_SHIFT   (3U)
#define	XRDC2_MSC_MSAC_W0_D1ACP(x)
#define	XRDC2_MSC_MSAC_W0_D2ACP_MASK   (0x1C0U)
#define	XRDC2_MSC_MSAC_W0_D2ACP_SHIFT   (6U)
#define	XRDC2_MSC_MSAC_W0_D2ACP(x)
#define	XRDC2_MSC_MSAC_W0_D3ACP_MASK   (0xE00U)
#define	XRDC2_MSC_MSAC_W0_D3ACP_SHIFT   (9U)
#define	XRDC2_MSC_MSAC_W0_D3ACP(x)
#define	XRDC2_MSC_MSAC_W0_D4ACP_MASK   (0x7000U)
#define	XRDC2_MSC_MSAC_W0_D4ACP_SHIFT   (12U)
#define	XRDC2_MSC_MSAC_W0_D4ACP(x)
#define	XRDC2_MSC_MSAC_W0_D5ACP_MASK   (0x38000U)
#define	XRDC2_MSC_MSAC_W0_D5ACP_SHIFT   (15U)
#define	XRDC2_MSC_MSAC_W0_D5ACP(x)
#define	XRDC2_MSC_MSAC_W0_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_MSC_MSAC_W0_D6ACP_SHIFT   (18U)
#define	XRDC2_MSC_MSAC_W0_D6ACP(x)
#define	XRDC2_MSC_MSAC_W0_D7ACP_MASK   (0xE00000U)
#define	XRDC2_MSC_MSAC_W0_D7ACP_SHIFT   (21U)
#define	XRDC2_MSC_MSAC_W0_D7ACP(x)
#define	XRDC2_MSC_MSAC_W0_EALO_MASK   (0xF000000U)
#define	XRDC2_MSC_MSAC_W0_EALO_SHIFT   (24U)
#define	XRDC2_MSC_MSAC_W0_EALO(x)
MSC_MSAC_W1 - Memory Slot Access Control
#define	XRDC2_MSC_MSAC_W1_D8ACP_MASK   (0x7U)
#define	XRDC2_MSC_MSAC_W1_D8ACP_SHIFT   (0U)
#define	XRDC2_MSC_MSAC_W1_D8ACP(x)
#define	XRDC2_MSC_MSAC_W1_D9ACP_MASK   (0x38U)
#define	XRDC2_MSC_MSAC_W1_D9ACP_SHIFT   (3U)
#define	XRDC2_MSC_MSAC_W1_D9ACP(x)
#define	XRDC2_MSC_MSAC_W1_D10ACP_MASK   (0x1C0U)
#define	XRDC2_MSC_MSAC_W1_D10ACP_SHIFT   (6U)
#define	XRDC2_MSC_MSAC_W1_D10ACP(x)
#define	XRDC2_MSC_MSAC_W1_D11ACP_MASK   (0xE00U)
#define	XRDC2_MSC_MSAC_W1_D11ACP_SHIFT   (9U)
#define	XRDC2_MSC_MSAC_W1_D11ACP(x)
#define	XRDC2_MSC_MSAC_W1_D12ACP_MASK   (0x7000U)
#define	XRDC2_MSC_MSAC_W1_D12ACP_SHIFT   (12U)
#define	XRDC2_MSC_MSAC_W1_D12ACP(x)
#define	XRDC2_MSC_MSAC_W1_D13ACP_MASK   (0x38000U)
#define	XRDC2_MSC_MSAC_W1_D13ACP_SHIFT   (15U)
#define	XRDC2_MSC_MSAC_W1_D13ACP(x)
#define	XRDC2_MSC_MSAC_W1_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_MSC_MSAC_W1_D14ACP_SHIFT   (18U)
#define	XRDC2_MSC_MSAC_W1_D14ACP(x)
#define	XRDC2_MSC_MSAC_W1_D15ACP_MASK   (0xE00000U)
#define	XRDC2_MSC_MSAC_W1_D15ACP_SHIFT   (21U)
#define	XRDC2_MSC_MSAC_W1_D15ACP(x)
#define	XRDC2_MSC_MSAC_W1_EAL_MASK   (0x3000000U)
#define	XRDC2_MSC_MSAC_W1_EAL_SHIFT   (24U)
#define	XRDC2_MSC_MSAC_W1_EAL(x)
#define	XRDC2_MSC_MSAC_W1_DL2_MASK   (0x60000000U)
#define	XRDC2_MSC_MSAC_W1_DL2_SHIFT   (29U)
#define	XRDC2_MSC_MSAC_W1_DL2(x)
#define	XRDC2_MSC_MSAC_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_MSC_MSAC_W1_VLD_SHIFT   (31U)
#define	XRDC2_MSC_MSAC_W1_VLD(x)
MDAC_MDA_W0 - Master Domain Assignment
#define	XRDC2_MDAC_MDA_W0_MASK_MASK   (0xFFFFU)
#define	XRDC2_MDAC_MDA_W0_MASK_SHIFT   (0U)
#define	XRDC2_MDAC_MDA_W0_MASK(x)
#define	XRDC2_MDAC_MDA_W0_MATCH_MASK   (0xFFFF0000U)
#define	XRDC2_MDAC_MDA_W0_MATCH_SHIFT   (16U)
#define	XRDC2_MDAC_MDA_W0_MATCH(x)
MDAC_MDA_W1 - Master Domain Assignment
#define	XRDC2_MDAC_MDA_W1_DID_MASK   (0xF0000U)
#define	XRDC2_MDAC_MDA_W1_DID_SHIFT   (16U)
#define	XRDC2_MDAC_MDA_W1_DID(x)
#define	XRDC2_MDAC_MDA_W1_PA_MASK   (0x3000000U)
#define	XRDC2_MDAC_MDA_W1_PA_SHIFT   (24U)
#define	XRDC2_MDAC_MDA_W1_PA(x)
#define	XRDC2_MDAC_MDA_W1_SA_MASK   (0xC000000U)
#define	XRDC2_MDAC_MDA_W1_SA_SHIFT   (26U)
#define	XRDC2_MDAC_MDA_W1_SA(x)
#define	XRDC2_MDAC_MDA_W1_DL_MASK   (0x40000000U)
#define	XRDC2_MDAC_MDA_W1_DL_SHIFT   (30U)
#define	XRDC2_MDAC_MDA_W1_DL(x)
#define	XRDC2_MDAC_MDA_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_MDAC_MDA_W1_VLD_SHIFT   (31U)
#define	XRDC2_MDAC_MDA_W1_VLD(x)
PAC_PDAC_W0 - Peripheral Domain Access Control
#define	XRDC2_PAC_PDAC_W0_D0ACP_MASK   (0x7U)
#define	XRDC2_PAC_PDAC_W0_D0ACP_SHIFT   (0U)
#define	XRDC2_PAC_PDAC_W0_D0ACP(x)
#define	XRDC2_PAC_PDAC_W0_D1ACP_MASK   (0x38U)
#define	XRDC2_PAC_PDAC_W0_D1ACP_SHIFT   (3U)
#define	XRDC2_PAC_PDAC_W0_D1ACP(x)
#define	XRDC2_PAC_PDAC_W0_D2ACP_MASK   (0x1C0U)
#define	XRDC2_PAC_PDAC_W0_D2ACP_SHIFT   (6U)
#define	XRDC2_PAC_PDAC_W0_D2ACP(x)
#define	XRDC2_PAC_PDAC_W0_D3ACP_MASK   (0xE00U)
#define	XRDC2_PAC_PDAC_W0_D3ACP_SHIFT   (9U)
#define	XRDC2_PAC_PDAC_W0_D3ACP(x)
#define	XRDC2_PAC_PDAC_W0_D4ACP_MASK   (0x7000U)
#define	XRDC2_PAC_PDAC_W0_D4ACP_SHIFT   (12U)
#define	XRDC2_PAC_PDAC_W0_D4ACP(x)
#define	XRDC2_PAC_PDAC_W0_D5ACP_MASK   (0x38000U)
#define	XRDC2_PAC_PDAC_W0_D5ACP_SHIFT   (15U)
#define	XRDC2_PAC_PDAC_W0_D5ACP(x)
#define	XRDC2_PAC_PDAC_W0_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_PAC_PDAC_W0_D6ACP_SHIFT   (18U)
#define	XRDC2_PAC_PDAC_W0_D6ACP(x)
#define	XRDC2_PAC_PDAC_W0_D7ACP_MASK   (0xE00000U)
#define	XRDC2_PAC_PDAC_W0_D7ACP_SHIFT   (21U)
#define	XRDC2_PAC_PDAC_W0_D7ACP(x)
#define	XRDC2_PAC_PDAC_W0_EALO_MASK   (0xF000000U)
#define	XRDC2_PAC_PDAC_W0_EALO_SHIFT   (24U)
#define	XRDC2_PAC_PDAC_W0_EALO(x)
PAC_PDAC_W1 - Peripheral Domain Access Control
#define	XRDC2_PAC_PDAC_W1_D8ACP_MASK   (0x7U)
#define	XRDC2_PAC_PDAC_W1_D8ACP_SHIFT   (0U)
#define	XRDC2_PAC_PDAC_W1_D8ACP(x)
#define	XRDC2_PAC_PDAC_W1_D9ACP_MASK   (0x38U)
#define	XRDC2_PAC_PDAC_W1_D9ACP_SHIFT   (3U)
#define	XRDC2_PAC_PDAC_W1_D9ACP(x)
#define	XRDC2_PAC_PDAC_W1_D10ACP_MASK   (0x1C0U)
#define	XRDC2_PAC_PDAC_W1_D10ACP_SHIFT   (6U)
#define	XRDC2_PAC_PDAC_W1_D10ACP(x)
#define	XRDC2_PAC_PDAC_W1_D11ACP_MASK   (0xE00U)
#define	XRDC2_PAC_PDAC_W1_D11ACP_SHIFT   (9U)
#define	XRDC2_PAC_PDAC_W1_D11ACP(x)
#define	XRDC2_PAC_PDAC_W1_D12ACP_MASK   (0x7000U)
#define	XRDC2_PAC_PDAC_W1_D12ACP_SHIFT   (12U)
#define	XRDC2_PAC_PDAC_W1_D12ACP(x)
#define	XRDC2_PAC_PDAC_W1_D13ACP_MASK   (0x38000U)
#define	XRDC2_PAC_PDAC_W1_D13ACP_SHIFT   (15U)
#define	XRDC2_PAC_PDAC_W1_D13ACP(x)
#define	XRDC2_PAC_PDAC_W1_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_PAC_PDAC_W1_D14ACP_SHIFT   (18U)
#define	XRDC2_PAC_PDAC_W1_D14ACP(x)
#define	XRDC2_PAC_PDAC_W1_D15ACP_MASK   (0xE00000U)
#define	XRDC2_PAC_PDAC_W1_D15ACP_SHIFT   (21U)
#define	XRDC2_PAC_PDAC_W1_D15ACP(x)
#define	XRDC2_PAC_PDAC_W1_EAL_MASK   (0x3000000U)
#define	XRDC2_PAC_PDAC_W1_EAL_SHIFT   (24U)
#define	XRDC2_PAC_PDAC_W1_EAL(x)
#define	XRDC2_PAC_PDAC_W1_DL2_MASK   (0x60000000U)
#define	XRDC2_PAC_PDAC_W1_DL2_SHIFT   (29U)
#define	XRDC2_PAC_PDAC_W1_DL2(x)
#define	XRDC2_PAC_PDAC_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_PAC_PDAC_W1_VLD_SHIFT   (31U)
#define	XRDC2_PAC_PDAC_W1_VLD(x)
MRC_MRGD_W0 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W0_SRTADDR_MASK   (0xFFFFF000U)
#define	XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W0_SRTADDR(x)
MRC_MRGD_W1 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W1_SRTADDR_MASK   (0xFU)
#define	XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W1_SRTADDR(x)
MRC_MRGD_W2 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W2_ENDADDR_MASK   (0xFFFFF000U)
#define	XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W2_ENDADDR(x)
MRC_MRGD_W3 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W3_ENDADDR_MASK   (0xFU)
#define	XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W3_ENDADDR(x)
MRC_MRGD_W5 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W5_D0ACP_MASK   (0x7U)
#define	XRDC2_MRC_MRGD_W5_D0ACP_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W5_D0ACP(x)
#define	XRDC2_MRC_MRGD_W5_D1ACP_MASK   (0x38U)
#define	XRDC2_MRC_MRGD_W5_D1ACP_SHIFT   (3U)
#define	XRDC2_MRC_MRGD_W5_D1ACP(x)
#define	XRDC2_MRC_MRGD_W5_D2ACP_MASK   (0x1C0U)
#define	XRDC2_MRC_MRGD_W5_D2ACP_SHIFT   (6U)
#define	XRDC2_MRC_MRGD_W5_D2ACP(x)
#define	XRDC2_MRC_MRGD_W5_D3ACP_MASK   (0xE00U)
#define	XRDC2_MRC_MRGD_W5_D3ACP_SHIFT   (9U)
#define	XRDC2_MRC_MRGD_W5_D3ACP(x)
#define	XRDC2_MRC_MRGD_W5_D4ACP_MASK   (0x7000U)
#define	XRDC2_MRC_MRGD_W5_D4ACP_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W5_D4ACP(x)
#define	XRDC2_MRC_MRGD_W5_D5ACP_MASK   (0x38000U)
#define	XRDC2_MRC_MRGD_W5_D5ACP_SHIFT   (15U)
#define	XRDC2_MRC_MRGD_W5_D5ACP(x)
#define	XRDC2_MRC_MRGD_W5_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_MRC_MRGD_W5_D6ACP_SHIFT   (18U)
#define	XRDC2_MRC_MRGD_W5_D6ACP(x)
#define	XRDC2_MRC_MRGD_W5_D7ACP_MASK   (0xE00000U)
#define	XRDC2_MRC_MRGD_W5_D7ACP_SHIFT   (21U)
#define	XRDC2_MRC_MRGD_W5_D7ACP(x)
#define	XRDC2_MRC_MRGD_W5_EALO_MASK   (0xF000000U)
#define	XRDC2_MRC_MRGD_W5_EALO_SHIFT   (24U)
#define	XRDC2_MRC_MRGD_W5_EALO(x)
MRC_MRGD_W6 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W6_D8ACP_MASK   (0x7U)
#define	XRDC2_MRC_MRGD_W6_D8ACP_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W6_D8ACP(x)
#define	XRDC2_MRC_MRGD_W6_D9ACP_MASK   (0x38U)
#define	XRDC2_MRC_MRGD_W6_D9ACP_SHIFT   (3U)
#define	XRDC2_MRC_MRGD_W6_D9ACP(x)
#define	XRDC2_MRC_MRGD_W6_D10ACP_MASK   (0x1C0U)
#define	XRDC2_MRC_MRGD_W6_D10ACP_SHIFT   (6U)
#define	XRDC2_MRC_MRGD_W6_D10ACP(x)
#define	XRDC2_MRC_MRGD_W6_D11ACP_MASK   (0xE00U)
#define	XRDC2_MRC_MRGD_W6_D11ACP_SHIFT   (9U)
#define	XRDC2_MRC_MRGD_W6_D11ACP(x)
#define	XRDC2_MRC_MRGD_W6_D12ACP_MASK   (0x7000U)
#define	XRDC2_MRC_MRGD_W6_D12ACP_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W6_D12ACP(x)
#define	XRDC2_MRC_MRGD_W6_D13ACP_MASK   (0x38000U)
#define	XRDC2_MRC_MRGD_W6_D13ACP_SHIFT   (15U)
#define	XRDC2_MRC_MRGD_W6_D13ACP(x)
#define	XRDC2_MRC_MRGD_W6_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_MRC_MRGD_W6_D14ACP_SHIFT   (18U)
#define	XRDC2_MRC_MRGD_W6_D14ACP(x)
#define	XRDC2_MRC_MRGD_W6_D15ACP_MASK   (0xE00000U)
#define	XRDC2_MRC_MRGD_W6_D15ACP_SHIFT   (21U)
#define	XRDC2_MRC_MRGD_W6_D15ACP(x)
#define	XRDC2_MRC_MRGD_W6_EAL_MASK   (0x3000000U)
#define	XRDC2_MRC_MRGD_W6_EAL_SHIFT   (24U)
#define	XRDC2_MRC_MRGD_W6_EAL(x)
#define	XRDC2_MRC_MRGD_W6_DL2_MASK   (0x60000000U)
#define	XRDC2_MRC_MRGD_W6_DL2_SHIFT   (29U)
#define	XRDC2_MRC_MRGD_W6_DL2(x)
#define	XRDC2_MRC_MRGD_W6_VLD_MASK   (0x80000000U)
#define	XRDC2_MRC_MRGD_W6_VLD_SHIFT   (31U)
#define	XRDC2_MRC_MRGD_W6_VLD(x)

Typedefs
typedef enum IRQn	IRQn_Type
typedef enum _rdc_master	rdc_master_t
	Structure for the RDC mapping.
typedef enum _rdc_mem	rdc_mem_t
typedef enum _rdc_periph	rdc_periph_t
typedef enum _xbar_input_signal	xbar_input_signal_t
typedef enum _xbar_output_signal	xbar_output_signal_t
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _iomuxc_lpsr_sw_mux_ctl_pad	iomuxc_lpsr_sw_mux_ctl_pad_t
	Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.
typedef enum _iomuxc_lpsr_sw_pad_ctl_pad	iomuxc_lpsr_sw_pad_ctl_pad_t
	Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.
typedef enum _iomuxc_lpsr_select_input	iomuxc_lpsr_select_input_t
	Enumeration for the IOMUXC_LPSR select input.
typedef enum _ssarc_power_domain_name	ssarc_power_domain_name_t
	Structure for the SSARC mapping.
typedef enum _ssarc_cpu_domain_name	ssarc_cpu_domain_name_t
typedef enum _xrdc2_master	xrdc2_master_t
	Structure for the XRDC2 mapping.
typedef enum _xrdc2_mem	xrdc2_mem_t
typedef enum _xrdc2_mem_slot	xrdc2_mem_slot_t
typedef enum _xrdc2_periph	xrdc2_periph_t
typedef enum _asrc_clock_source	asrc_clock_source_t
	The ASRC clock source.
typedef enum _iomuxc_sw_mux_ctl_pad	iomuxc_sw_mux_ctl_pad_t
	Enumeration for the IOMUXC SW_MUX_CTL_PAD.
typedef enum _iomuxc_sw_pad_ctl_pad	iomuxc_sw_pad_ctl_pad_t
	Enumeration for the IOMUXC SW_PAD_CTL_PAD.
typedef enum _iomuxc_select_input	iomuxc_select_input_t
	Enumeration for the IOMUXC select input.

Enumerations
enum	IRQn {   NotAvail_IRQn = -128 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 ,   BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 ,   PendSV_IRQn = -2 , SysTick_IRQn = -1 , DMA0_DMA16_IRQn = 0 , DMA1_DMA17_IRQn = 1 ,   DMA2_DMA18_IRQn = 2 , DMA3_DMA19_IRQn = 3 , DMA4_DMA20_IRQn = 4 , DMA5_DMA21_IRQn = 5 ,   DMA6_DMA22_IRQn = 6 , DMA7_DMA23_IRQn = 7 , DMA8_DMA24_IRQn = 8 , DMA9_DMA25_IRQn = 9 ,   DMA10_DMA26_IRQn = 10 , DMA11_DMA27_IRQn = 11 , DMA12_DMA28_IRQn = 12 , DMA13_DMA29_IRQn = 13 ,   DMA14_DMA30_IRQn = 14 , DMA15_DMA31_IRQn = 15 , DMA_ERROR_IRQn = 16 , Reserved33_IRQn = 17 ,   Reserved34_IRQn = 18 , CORE_IRQn = 19 , LPUART1_IRQn = 20 , LPUART2_IRQn = 21 ,   LPUART3_IRQn = 22 , LPUART4_IRQn = 23 , LPUART5_IRQn = 24 , LPUART6_IRQn = 25 ,   LPUART7_IRQn = 26 , LPUART8_IRQn = 27 , LPUART9_IRQn = 28 , LPUART10_IRQn = 29 ,   LPUART11_IRQn = 30 , LPUART12_IRQn = 31 , LPI2C1_IRQn = 32 , LPI2C2_IRQn = 33 ,   LPI2C3_IRQn = 34 , LPI2C4_IRQn = 35 , LPI2C5_IRQn = 36 , LPI2C6_IRQn = 37 ,   LPSPI1_IRQn = 38 , LPSPI2_IRQn = 39 , LPSPI3_IRQn = 40 , LPSPI4_IRQn = 41 ,   LPSPI5_IRQn = 42 , LPSPI6_IRQn = 43 , CAN1_IRQn = 44 , CAN1_ERROR_IRQn = 45 ,   CAN2_IRQn = 46 , CAN2_ERROR_IRQn = 47 , CAN3_IRQn = 48 , CAN3_ERROR_IRQn = 49 ,   Reserved66_IRQn = 50 , KPP_IRQn = 51 , Reserved68_IRQn = 52 , GPR_IRQ_IRQn = 53 ,   eLCDIF_IRQn = 54 , LCDIFv2_IRQn = 55 , CSI_IRQn = 56 , PXP_IRQn = 57 ,   MIPI_CSI_IRQn = 58 , MIPI_DSI_IRQn = 59 , GPU2D_IRQn = 60 , GPIO12_Combined_0_15_IRQn = 61 ,   GPIO12_Combined_16_31_IRQn = 62 , DAC_IRQn = 63 , KEY_MANAGER_IRQn = 64 , WDOG2_IRQn = 65 ,   SNVS_HP_NON_TZ_IRQn = 66 , SNVS_HP_TZ_IRQn = 67 , SNVS_PULSE_EVENT_IRQn = 68 , CAAM_IRQ0_IRQn = 69 ,   CAAM_IRQ1_IRQn = 70 , CAAM_IRQ2_IRQn = 71 , CAAM_IRQ3_IRQn = 72 , CAAM_RECORVE_ERRPR_IRQn = 73 ,   CAAM_RTIC_IRQn = 74 , CDOG_IRQn = 75 , SAI1_IRQn = 76 , SAI2_IRQn = 77 ,   SAI3_RX_IRQn = 78 , SAI3_TX_IRQn = 79 , SAI4_RX_IRQn = 80 , SAI4_TX_IRQn = 81 ,   SPDIF_IRQn = 82 , TMPSNS_INT_IRQn = 83 , TMPSNS_LOW_HIGH_IRQn = 84 , TMPSNS_PANIC_IRQn = 85 ,   LPSR_LP8_BROWNOUT_IRQn = 86 , LPSR_LP0_BROWNOUT_IRQn = 87 , ADC1_IRQn = 88 , ADC2_IRQn = 89 ,   USBPHY1_IRQn = 90 , USBPHY2_IRQn = 91 , RDC_IRQn = 92 , GPIO13_Combined_0_31_IRQn = 93 ,   Reserved110_IRQn = 94 , DCIC1_IRQn = 95 , DCIC2_IRQn = 96 , ASRC_IRQn = 97 ,   FLEXRAM_ECC_IRQn = 98 , GPIO7_8_9_10_11_IRQn = 99 , GPIO1_Combined_0_15_IRQn = 100 , GPIO1_Combined_16_31_IRQn = 101 ,   GPIO2_Combined_0_15_IRQn = 102 , GPIO2_Combined_16_31_IRQn = 103 , GPIO3_Combined_0_15_IRQn = 104 , GPIO3_Combined_16_31_IRQn = 105 ,   GPIO4_Combined_0_15_IRQn = 106 , GPIO4_Combined_16_31_IRQn = 107 , GPIO5_Combined_0_15_IRQn = 108 , GPIO5_Combined_16_31_IRQn = 109 ,   FLEXIO1_IRQn = 110 , FLEXIO2_IRQn = 111 , WDOG1_IRQn = 112 , RTWDOG4_IRQn = 113 ,   EWM_IRQn = 114 , OCOTP_READ_FUSE_ERROR_IRQn = 115 , OCOTP_READ_DONE_ERROR_IRQn = 116 , GPC_IRQn = 117 ,   MUB_IRQn = 118 , GPT1_IRQn = 119 , GPT2_IRQn = 120 , GPT3_IRQn = 121 ,   GPT4_IRQn = 122 , GPT5_IRQn = 123 , GPT6_IRQn = 124 , PWM1_0_IRQn = 125 ,   PWM1_1_IRQn = 126 , PWM1_2_IRQn = 127 , PWM1_3_IRQn = 128 , PWM1_FAULT_IRQn = 129 ,   FLEXSPI1_IRQn = 130 , FLEXSPI2_IRQn = 131 , SEMC_IRQn = 132 , USDHC1_IRQn = 133 ,   USDHC2_IRQn = 134 , USB_OTG2_IRQn = 135 , USB_OTG1_IRQn = 136 , ENET_IRQn = 137 ,   ENET_1588_Timer_IRQn = 138 , ENET_1G_MAC0_Tx_Rx_1_IRQn = 139 , ENET_1G_MAC0_Tx_Rx_2_IRQn = 140 , ENET_1G_IRQn = 141 ,   ENET_1G_1588_Timer_IRQn = 142 , XBAR1_IRQ_0_1_IRQn = 143 , XBAR1_IRQ_2_3_IRQn = 144 , ADC_ETC_IRQ0_IRQn = 145 ,   ADC_ETC_IRQ1_IRQn = 146 , ADC_ETC_IRQ2_IRQn = 147 , ADC_ETC_IRQ3_IRQn = 148 , ADC_ETC_ERROR_IRQ_IRQn = 149 ,   Reserved166_IRQn = 150 , Reserved167_IRQn = 151 , Reserved168_IRQn = 152 , Reserved169_IRQn = 153 ,   Reserved170_IRQn = 154 , PIT1_IRQn = 155 , PIT2_IRQn = 156 , ACMP1_IRQn = 157 ,   ACMP2_IRQn = 158 , ACMP3_IRQn = 159 , ACMP4_IRQn = 160 , Reserved177_IRQn = 161 ,   Reserved178_IRQn = 162 , Reserved179_IRQn = 163 , Reserved180_IRQn = 164 , ENC1_IRQn = 165 ,   ENC2_IRQn = 166 , ENC3_IRQn = 167 , ENC4_IRQn = 168 , Reserved185_IRQn = 169 ,   Reserved186_IRQn = 170 , TMR1_IRQn = 171 , TMR2_IRQn = 172 , TMR3_IRQn = 173 ,   TMR4_IRQn = 174 , SEMA4_CP0_IRQn = 175 , SEMA4_CP1_IRQn = 176 , PWM2_0_IRQn = 177 ,   PWM2_1_IRQn = 178 , PWM2_2_IRQn = 179 , PWM2_3_IRQn = 180 , PWM2_FAULT_IRQn = 181 ,   PWM3_0_IRQn = 182 , PWM3_1_IRQn = 183 , PWM3_2_IRQn = 184 , PWM3_3_IRQn = 185 ,   PWM3_FAULT_IRQn = 186 , PWM4_0_IRQn = 187 , PWM4_1_IRQn = 188 , PWM4_2_IRQn = 189 ,   PWM4_3_IRQn = 190 , PWM4_FAULT_IRQn = 191 , Reserved208_IRQn = 192 , Reserved209_IRQn = 193 ,   Reserved210_IRQn = 194 , Reserved211_IRQn = 195 , Reserved212_IRQn = 196 , Reserved213_IRQn = 197 ,   Reserved214_IRQn = 198 , Reserved215_IRQn = 199 , PDM_HWVAD_EVENT_IRQn = 200 , PDM_HWVAD_ERROR_IRQn = 201 ,   PDM_EVENT_IRQn = 202 , PDM_ERROR_IRQn = 203 , EMVSIM1_IRQn = 204 , EMVSIM2_IRQn = 205 ,   MECC1_INT_IRQn = 206 , MECC1_FATAL_INT_IRQn = 207 , MECC2_INT_IRQn = 208 , MECC2_FATAL_INT_IRQn = 209 ,   XECC_FLEXSPI1_INT_IRQn = 210 , XECC_FLEXSPI1_FATAL_INT_IRQn = 211 , XECC_FLEXSPI2_INT_IRQn = 212 , XECC_FLEXSPI2_FATAL_INT_IRQn = 213 ,   XECC_SEMC_INT_IRQn = 214 , XECC_SEMC_FATAL_INT_IRQn = 215 , Reserved232_IRQn = 216 , Reserved233_IRQn = 217 }
enum	_rdc_master {   kRDC_Master_ENET_1G_TX = 1U , kRDC_Master_ENET_1G_RX = 2U , kRDC_Master_ENET = 3U , kRDC_Master_ENET_QOS = 4U ,   kRDC_Master_USDHC1 = 5U , kRDC_Master_USDHC2 = 6U , kRDC_Master_USB = 7U , kRDC_Master_GPU = 8U ,   kRDC_Master_PXP = 9U , kRDC_Master_LCDIF = 10U , kRDC_Master_CSI = 11U }
	Structure for the RDC mapping. More...
enum	_rdc_mem {   kRDC_Mem_MRC0_0 = 0U , kRDC_Mem_MRC0_1 = 1U , kRDC_Mem_MRC0_2 = 2U , kRDC_Mem_MRC0_3 = 3U ,   kRDC_Mem_MRC0_4 = 4U , kRDC_Mem_MRC0_5 = 5U , kRDC_Mem_MRC0_6 = 6U , kRDC_Mem_MRC0_7 = 7U ,   kRDC_Mem_MRC1_0 = 8U , kRDC_Mem_MRC1_1 = 9U , kRDC_Mem_MRC1_2 = 10U , kRDC_Mem_MRC1_3 = 11U ,   kRDC_Mem_MRC1_4 = 12U , kRDC_Mem_MRC1_5 = 13U , kRDC_Mem_MRC1_6 = 14U , kRDC_Mem_MRC1_7 = 15U ,   kRDC_Mem_MRC2_0 = 16U , kRDC_Mem_MRC2_1 = 17U , kRDC_Mem_MRC2_2 = 18U , kRDC_Mem_MRC2_3 = 19U ,   kRDC_Mem_MRC2_4 = 20U , kRDC_Mem_MRC2_5 = 21U , kRDC_Mem_MRC2_6 = 22U , kRDC_Mem_MRC2_7 = 23U ,   kRDC_Mem_MRC3_0 = 24U , kRDC_Mem_MRC3_1 = 25U , kRDC_Mem_MRC3_2 = 26U , kRDC_Mem_MRC3_3 = 27U ,   kRDC_Mem_MRC3_4 = 28U , kRDC_Mem_MRC3_5 = 29U , kRDC_Mem_MRC3_6 = 30U , kRDC_Mem_MRC3_7 = 31U ,   kRDC_Mem_MRC4_0 = 32U , kRDC_Mem_MRC4_1 = 33U , kRDC_Mem_MRC4_2 = 34U , kRDC_Mem_MRC4_3 = 35U ,   kRDC_Mem_MRC4_4 = 36U , kRDC_Mem_MRC4_5 = 37U , kRDC_Mem_MRC4_6 = 38U , kRDC_Mem_MRC4_7 = 39U ,   kRDC_Mem_MRC5_0 = 40U , kRDC_Mem_MRC5_1 = 41U , kRDC_Mem_MRC5_2 = 42U , kRDC_Mem_MRC5_3 = 43U ,   kRDC_Mem_MRC6_0 = 44U , kRDC_Mem_MRC6_1 = 45U , kRDC_Mem_MRC6_2 = 46U , kRDC_Mem_MRC6_3 = 47U ,   kRDC_Mem_MRC7_0 = 48U , kRDC_Mem_MRC7_1 = 49U , kRDC_Mem_MRC7_2 = 50U , kRDC_Mem_MRC7_3 = 51U ,   kRDC_Mem_MRC7_4 = 52U , kRDC_Mem_MRC7_5 = 53U , kRDC_Mem_MRC7_6 = 54U , kRDC_Mem_MRC7_7 = 55U ,   kRDC_Mem_MRC8_0 = 56U , kRDC_Mem_MRC8_1 = 57U , kRDC_Mem_MRC8_2 = 58U }
enum	_rdc_periph {   kRDC_Periph_MTR = 0U , kRDC_Periph_MECC1 = 1U , kRDC_Periph_MECC2 = 2U , kRDC_Periph_FLEXSPI1 = 3U ,   kRDC_Periph_FLEXSPI2 = 4U , kRDC_Periph_SEMC = 5U , kRDC_Periph_CM7_IMXRT = 6U , kRDC_Periph_EWM = 7U ,   kRDC_Periph_WDOG1 = 8U , kRDC_Periph_WDOG2 = 9U , kRDC_Periph_WDOG3 = 10U , kRDC_Periph_AOI_XBAR = 11U ,   kRDC_Periph_ADC_ETC = 12U , kRDC_Periph_CAAM_1 = 13U , kRDC_Periph_ADC1 = 14U , kRDC_Periph_ADC2 = 15U ,   kRDC_Periph_TSC_DIG = 16U , kRDC_Periph_DAC = 17U , kRDC_Periph_IEE = 18U , kRDC_Periph_DMAMUX = 19U ,   kRDC_Periph_EDMA = 19U , kRDC_Periph_LPUART1 = 20U , kRDC_Periph_LPUART2 = 21U , kRDC_Periph_LPUART3 = 22U ,   kRDC_Periph_LPUART4 = 23U , kRDC_Periph_LPUART5 = 24U , kRDC_Periph_LPUART6 = 25U , kRDC_Periph_LPUART7 = 26U ,   kRDC_Periph_LPUART8 = 27U , kRDC_Periph_LPUART9 = 28U , kRDC_Periph_LPUART10 = 29U , kRDC_Periph_FLEXIO1 = 30U ,   kRDC_Periph_FLEXIO2 = 31U , kRDC_Periph_CAN1 = 32U , kRDC_Periph_CAN2 = 33U , kRDC_Periph_PIT1 = 34U ,   kRDC_Periph_KPP = 35U , kRDC_Periph_IOMUXC_GPR = 36U , kRDC_Periph_IOMUXC = 37U , kRDC_Periph_GPT1 = 38U ,   kRDC_Periph_GPT2 = 39U , kRDC_Periph_GPT3 = 40U , kRDC_Periph_GPT4 = 41U , kRDC_Periph_GPT5 = 42U ,   kRDC_Periph_GPT6 = 43U , kRDC_Periph_LPI2C1 = 44U , kRDC_Periph_LPI2C2 = 45U , kRDC_Periph_LPI2C3 = 46U ,   kRDC_Periph_LPI2C4 = 47U , kRDC_Periph_LPSPI1 = 48U , kRDC_Periph_LPSPI2 = 49U , kRDC_Periph_LPSPI3 = 50U ,   kRDC_Periph_LPSPI4 = 51U , kRDC_Periph_GPIO_1_6 = 52U , kRDC_Periph_CCM_OBS = 53U , kRDC_Periph_SIM1 = 54U ,   kRDC_Periph_SIM2 = 55U , kRDC_Periph_QTIMER1 = 56U , kRDC_Periph_QTIMER2 = 57U , kRDC_Periph_QTIMER3 = 58U ,   kRDC_Periph_QTIMER4 = 59U , kRDC_Periph_ENC1 = 60U , kRDC_Periph_ENC2 = 61U , kRDC_Periph_ENC3 = 62U ,   kRDC_Periph_ENC4 = 63U , kRDC_Periph_FLEXPWM1 = 64U , kRDC_Periph_FLEXPWM2 = 65U , kRDC_Periph_FLEXPWM3 = 66U ,   kRDC_Periph_FLEXPWM4 = 67U , kRDC_Periph_CAAM_2 = 68U , kRDC_Periph_CAAM_3 = 69U , kRDC_Periph_ACMP1 = 70U ,   kRDC_Periph_ACMP2 = 71U , kRDC_Periph_ACMP3 = 72U , kRDC_Periph_ACMP4 = 73U , kRDC_Periph_CAAM = 74U ,   kRDC_Periph_SPDIF = 75U , kRDC_Periph_SAI1 = 76U , kRDC_Periph_SAI2 = 77U , kRDC_Periph_SAI3 = 78U ,   kRDC_Periph_ASRC = 79U , kRDC_Periph_USDHC1 = 80U , kRDC_Periph_USDHC2 = 81U , kRDC_Periph_ENET_1G = 82U ,   kRDC_Periph_ENET = 83U , kRDC_Periph_USB_PL301 = 84U , kRDC_Periph_USBPHY2 = 85U , kRDC_Periph_USB_OTG2 = 85U ,   kRDC_Periph_USBPHY1 = 86U , kRDC_Periph_USB_OTG1 = 86U , kRDC_Periph_ENET_QOS = 87U , kRDC_Periph_CAAM_5 = 88U ,   kRDC_Periph_CSI = 89U , kRDC_Periph_LCDIF1 = 90U , kRDC_Periph_LCDIF2 = 91U , kRDC_Periph_MIPI_DSI = 92U ,   kRDC_Periph_MIPI_CSI = 93U , kRDC_Periph_PXP = 94U , kRDC_Periph_VIDEO_MUX = 95U , kRDC_Periph_PGMC_SRC_GPC = 96U ,   kRDC_Periph_IOMUXC_LPSR = 97U , kRDC_Periph_IOMUXC_LPSR_GPR = 98U , kRDC_Periph_WDOG4 = 99U , kRDC_Periph_DMAMUX_LPSR = 100U ,   kRDC_Periph_EDMA_LPSR = 100U , kRDC_Periph_Reserved = 101U , kRDC_Periph_MIC = 102U , kRDC_Periph_LPUART11 = 103U ,   kRDC_Periph_LPUART12 = 104U , kRDC_Periph_LPSPI5 = 105U , kRDC_Periph_LPSPI6 = 106U , kRDC_Periph_LPI2C5 = 107U ,   kRDC_Periph_LPI2C6 = 108U , kRDC_Periph_CAN3 = 109U , kRDC_Periph_SAI4 = 110U , kRDC_Periph_SEMA1 = 111U ,   kRDC_Periph_GPIO_7_12 = 112U , kRDC_Periph_KEY_MANAGER = 113U , kRDC_Periph_ANATOP = 114U , kRDC_Periph_SNVS_HP_WRAPPER = 115U ,   kRDC_Periph_IOMUXC_SNVS = 116U , kRDC_Periph_IOMUXC_SNVS_GPR = 117U , kRDC_Periph_SNVS_SRAM = 118U , kRDC_Periph_GPIO13 = 119U ,   kRDC_Periph_ROMCP = 120U , kRDC_Periph_DCDC = 121U , kRDC_Periph_OCOTP_CTRL_WRAPPER = 122U , kRDC_Periph_PIT2 = 123U ,   kRDC_Periph_SSARC = 124U , kRDC_Periph_CCM = 125U , kRDC_Periph_CAAM_6 = 126U , kRDC_Periph_CAAM_7 = 127U }
enum	_xbar_input_signal {   kXBARA1_InputLogicLow = 0|0x100U , kXBARA1_InputLogicHigh = 1|0x100U , kXBARA1_InputRESERVED2 = 2|0x100U , kXBARA1_InputRESERVED3 = 3|0x100U ,   kXBARA1_InputIomuxXbarInout04 = 4|0x100U , kXBARA1_InputIomuxXbarInout05 = 5|0x100U , kXBARA1_InputIomuxXbarInout06 = 6|0x100U , kXBARA1_InputIomuxXbarInout07 = 7|0x100U ,   kXBARA1_InputIomuxXbarInout08 = 8|0x100U , kXBARA1_InputIomuxXbarInout09 = 9|0x100U , kXBARA1_InputIomuxXbarInout10 = 10|0x100U , kXBARA1_InputIomuxXbarInout11 = 11|0x100U ,   kXBARA1_InputIomuxXbarInout12 = 12|0x100U , kXBARA1_InputIomuxXbarInout13 = 13|0x100U , kXBARA1_InputIomuxXbarInout14 = 14|0x100U , kXBARA1_InputIomuxXbarInout15 = 15|0x100U ,   kXBARA1_InputIomuxXbarInout16 = 16|0x100U , kXBARA1_InputIomuxXbarInout17 = 17|0x100U , kXBARA1_InputIomuxXbarInout18 = 18|0x100U , kXBARA1_InputIomuxXbarInout19 = 19|0x100U ,   kXBARA1_InputIomuxXbarInout20 = 20|0x100U , kXBARA1_InputIomuxXbarInout21 = 21|0x100U , kXBARA1_InputIomuxXbarInout22 = 22|0x100U , kXBARA1_InputIomuxXbarInout23 = 23|0x100U ,   kXBARA1_InputIomuxXbarInout24 = 24|0x100U , kXBARA1_InputIomuxXbarInout25 = 25|0x100U , kXBARA1_InputIomuxXbarInout26 = 26|0x100U , kXBARA1_InputIomuxXbarInout27 = 27|0x100U ,   kXBARA1_InputIomuxXbarInout28 = 28|0x100U , kXBARA1_InputIomuxXbarInout29 = 29|0x100U , kXBARA1_InputIomuxXbarInout30 = 30|0x100U , kXBARA1_InputIomuxXbarInout31 = 31|0x100U ,   kXBARA1_InputIomuxXbarInout32 = 32|0x100U , kXBARA1_InputIomuxXbarInout33 = 33|0x100U , kXBARA1_InputIomuxXbarInout34 = 34|0x100U , kXBARA1_InputIomuxXbarInout35 = 35|0x100U ,   kXBARA1_InputIomuxXbarInout36 = 36|0x100U , kXBARA1_InputIomuxXbarInout37 = 37|0x100U , kXBARA1_InputIomuxXbarInout38 = 38|0x100U , kXBARA1_InputIomuxXbarInout39 = 39|0x100U ,   kXBARA1_InputIomuxXbarInout40 = 40|0x100U , kXBARA1_InputRESERVED41 = 41|0x100U , kXBARA1_InputAcmp1Out = 42|0x100U , kXBARA1_InputAcmp2Out = 43|0x100U ,   kXBARA1_InputAcmp3Out = 44|0x100U , kXBARA1_InputAcmp4Out = 45|0x100U , kXBARA1_InputRESERVED46 = 46|0x100U , kXBARA1_InputRESERVED47 = 47|0x100U ,   kXBARA1_InputRESERVED48 = 48|0x100U , kXBARA1_InputRESERVED49 = 49|0x100U , kXBARA1_InputQtimer1Timer0 = 50|0x100U , kXBARA1_InputQtimer1Timer1 = 51|0x100U ,   kXBARA1_InputQtimer1Timer2 = 52|0x100U , kXBARA1_InputQtimer1Timer3 = 53|0x100U , kXBARA1_InputQtimer2Timer0 = 54|0x100U , kXBARA1_InputQtimer2Timer1 = 55|0x100U ,   kXBARA1_InputQtimer2Timer2 = 56|0x100U , kXBARA1_InputQtimer2Timer3 = 57|0x100U , kXBARA1_InputQtimer3Timer0 = 58|0x100U , kXBARA1_InputQtimer3Timer1 = 59|0x100U ,   kXBARA1_InputQtimer3Timer2 = 60|0x100U , kXBARA1_InputQtimer3Timer3 = 61|0x100U , kXBARA1_InputQtimer4Timer0 = 62|0x100U , kXBARA1_InputQtimer4Timer1 = 63|0x100U ,   kXBARA1_InputQtimer4Timer2 = 64|0x100U , kXBARA1_InputQtimer4Timer3 = 65|0x100U , kXBARA1_InputRESERVED66 = 66|0x100U , kXBARA1_InputRESERVED67 = 67|0x100U ,   kXBARA1_InputRESERVED68 = 68|0x100U , kXBARA1_InputRESERVED69 = 69|0x100U , kXBARA1_InputRESERVED70 = 70|0x100U , kXBARA1_InputRESERVED71 = 71|0x100U ,   kXBARA1_InputRESERVED72 = 72|0x100U , kXBARA1_InputRESERVED73 = 73|0x100U , kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U , kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U ,   kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U , kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U ,   kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U , kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U , kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U , kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U ,   kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U , kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U , kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U , kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U ,   kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U , kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U , kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U , kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U ,   kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U , kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U , kXBARA1_InputRESERVED94 = 94|0x100U , kXBARA1_InputRESERVED95 = 95|0x100U ,   kXBARA1_InputRESERVED96 = 96|0x100U , kXBARA1_InputRESERVED97 = 97|0x100U , kXBARA1_InputRESERVED98 = 98|0x100U , kXBARA1_InputRESERVED99 = 99|0x100U ,   kXBARA1_InputRESERVED100 = 100|0x100U , kXBARA1_InputRESERVED101 = 101|0x100U , kXBARA1_InputPit1Trigger0 = 102|0x100U , kXBARA1_InputPit1Trigger1 = 103|0x100U ,   kXBARA1_InputPit1Trigger2 = 104|0x100U , kXBARA1_InputPit1Trigger3 = 105|0x100U , kXBARA1_InputDec1PosMatch = 106|0x100U , kXBARA1_InputDec2PosMatch = 107|0x100U ,   kXBARA1_InputDec3PosMatch = 108|0x100U , kXBARA1_InputDec4PosMatch = 109|0x100U , kXBARA1_InputRESERVED110 = 110|0x100U , kXBARA1_InputRESERVED111 = 111|0x100U ,   kXBARA1_InputDmaDone0 = 112|0x100U , kXBARA1_InputDmaDone1 = 113|0x100U , kXBARA1_InputDmaDone2 = 114|0x100U , kXBARA1_InputDmaDone3 = 115|0x100U ,   kXBARA1_InputDmaDone4 = 116|0x100U , kXBARA1_InputDmaDone5 = 117|0x100U , kXBARA1_InputDmaDone6 = 118|0x100U , kXBARA1_InputDmaDone7 = 119|0x100U ,   kXBARA1_InputDmaLpsrDone0 = 120|0x100U , kXBARA1_InputDmaLpsrDone1 = 121|0x100U , kXBARA1_InputDmaLpsrDone2 = 122|0x100U , kXBARA1_InputDmaLpsrDone3 = 123|0x100U ,   kXBARA1_InputDmaLpsrDone4 = 124|0x100U , kXBARA1_InputDmaLpsrDone5 = 125|0x100U , kXBARA1_InputDmaLpsrDone6 = 126|0x100U , kXBARA1_InputDmaLpsrDone7 = 127|0x100U ,   kXBARA1_InputAoi1Out0 = 128|0x100U , kXBARA1_InputAoi1Out1 = 129|0x100U , kXBARA1_InputAoi1Out2 = 130|0x100U , kXBARA1_InputAoi1Out3 = 131|0x100U ,   kXBARA1_InputAoi2Out0 = 132|0x100U , kXBARA1_InputAoi2Out1 = 133|0x100U , kXBARA1_InputAoi2Out2 = 134|0x100U , kXBARA1_InputAoi2Out3 = 135|0x100U ,   kXBARA1_InputAdcEtc0Coco0 = 136|0x100U , kXBARA1_InputAdcEtc0Coco1 = 137|0x100U , kXBARA1_InputAdcEtc0Coco2 = 138|0x100U , kXBARA1_InputAdcEtc0Coco3 = 139|0x100U ,   kXBARA1_InputAdcEtc1Coco0 = 140|0x100U , kXBARA1_InputAdcEtc1Coco1 = 141|0x100U , kXBARA1_InputAdcEtc1Coco2 = 142|0x100U , kXBARA1_InputAdcEtc1Coco3 = 143|0x100U ,   kXBARB2_InputLogicLow = 0|0x200U , kXBARB2_InputLogicHigh = 1|0x200U , kXBARB2_InputAcmp1Out = 2|0x200U , kXBARB2_InputAcmp2Out = 3|0x200U ,   kXBARB2_InputAcmp3Out = 4|0x200U , kXBARB2_InputAcmp4Out = 5|0x200U , kXBARB2_InputRESERVED6 = 6|0x200U , kXBARB2_InputRESERVED7 = 7|0x200U ,   kXBARB2_InputRESERVED8 = 8|0x200U , kXBARB2_InputRESERVED9 = 9|0x200U , kXBARB2_InputQtimer1Timer0 = 10|0x200U , kXBARB2_InputQtimer1Timer1 = 11|0x200U ,   kXBARB2_InputQtimer1Timer2 = 12|0x200U , kXBARB2_InputQtimer1Timer3 = 13|0x200U , kXBARB2_InputQtimer2Timer0 = 14|0x200U , kXBARB2_InputQtimer2Timer1 = 15|0x200U ,   kXBARB2_InputQtimer2Timer2 = 16|0x200U , kXBARB2_InputQtimer2Timer3 = 17|0x200U , kXBARB2_InputQtimer3Timer0 = 18|0x200U , kXBARB2_InputQtimer3Timer1 = 19|0x200U ,   kXBARB2_InputQtimer3Timer2 = 20|0x200U , kXBARB2_InputQtimer3Timer3 = 21|0x200U , kXBARB2_InputQtimer4Timer0 = 22|0x200U , kXBARB2_InputQtimer4Timer1 = 23|0x200U ,   kXBARB2_InputQtimer4Timer2 = 24|0x200U , kXBARB2_InputQtimer4Timer3 = 25|0x200U , kXBARB2_InputRESERVED26 = 26|0x200U , kXBARB2_InputRESERVED27 = 27|0x200U ,   kXBARB2_InputRESERVED28 = 28|0x200U , kXBARB2_InputRESERVED29 = 29|0x200U , kXBARB2_InputRESERVED30 = 30|0x200U , kXBARB2_InputRESERVED31 = 31|0x200U ,   kXBARB2_InputRESERVED32 = 32|0x200U , kXBARB2_InputRESERVED33 = 33|0x200U , kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U , kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U ,   kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U , kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U , kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U , kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U ,   kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U , kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U , kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U , kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U ,   kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U , kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U , kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U , kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U ,   kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U , kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U , kXBARB2_InputRESERVED50 = 50|0x200U , kXBARB2_InputRESERVED51 = 51|0x200U ,   kXBARB2_InputRESERVED52 = 52|0x200U , kXBARB2_InputRESERVED53 = 53|0x200U , kXBARB2_InputRESERVED54 = 54|0x200U , kXBARB2_InputRESERVED55 = 55|0x200U ,   kXBARB2_InputRESERVED56 = 56|0x200U , kXBARB2_InputRESERVED57 = 57|0x200U , kXBARB2_InputPit1Trigger0 = 58|0x200U , kXBARB2_InputPit1Trigger1 = 59|0x200U ,   kXBARB2_InputAdcEtc0Coco0 = 60|0x200U , kXBARB2_InputAdcEtc0Coco1 = 61|0x200U , kXBARB2_InputAdcEtc0Coco2 = 62|0x200U , kXBARB2_InputAdcEtc0Coco3 = 63|0x200U ,   kXBARB2_InputAdcEtc1Coco0 = 64|0x200U , kXBARB2_InputAdcEtc1Coco1 = 65|0x200U , kXBARB2_InputAdcEtc1Coco2 = 66|0x200U , kXBARB2_InputAdcEtc1Coco3 = 67|0x200U ,   kXBARB2_InputRESERVED68 = 68|0x200U , kXBARB2_InputRESERVED69 = 69|0x200U , kXBARB2_InputRESERVED70 = 70|0x200U , kXBARB2_InputRESERVED71 = 71|0x200U ,   kXBARB2_InputRESERVED72 = 72|0x200U , kXBARB2_InputRESERVED73 = 73|0x200U , kXBARB2_InputRESERVED74 = 74|0x200U , kXBARB2_InputRESERVED75 = 75|0x200U ,   kXBARB2_InputDec1PosMatch = 76|0x200U , kXBARB2_InputDec2PosMatch = 77|0x200U , kXBARB2_InputDec3PosMatch = 78|0x200U , kXBARB2_InputDec4PosMatch = 79|0x200U ,   kXBARB2_InputRESERVED80 = 80|0x200U , kXBARB2_InputRESERVED81 = 81|0x200U , kXBARB2_InputDmaDone0 = 82|0x200U , kXBARB2_InputDmaDone1 = 83|0x200U ,   kXBARB2_InputDmaDone2 = 84|0x200U , kXBARB2_InputDmaDone3 = 85|0x200U , kXBARB2_InputDmaDone4 = 86|0x200U , kXBARB2_InputDmaDone5 = 87|0x200U ,   kXBARB2_InputDmaDone6 = 88|0x200U , kXBARB2_InputDmaDone7 = 89|0x200U , kXBARB2_InputDmaLpsrDone0 = 90|0x200U , kXBARB2_InputDmaLpsrDone1 = 91|0x200U ,   kXBARB2_InputDmaLpsrDone2 = 92|0x200U , kXBARB2_InputDmaLpsrDone3 = 93|0x200U , kXBARB2_InputDmaLpsrDone4 = 94|0x200U , kXBARB2_InputDmaLpsrDone5 = 95|0x200U ,   kXBARB2_InputDmaLpsrDone6 = 96|0x200U , kXBARB2_InputDmaLpsrDone7 = 97|0x200U , kXBARB3_InputLogicLow = 0|0x300U , kXBARB3_InputLogicHigh = 1|0x300U ,   kXBARB3_InputAcmp1Out = 2|0x300U , kXBARB3_InputAcmp2Out = 3|0x300U , kXBARB3_InputAcmp3Out = 4|0x300U , kXBARB3_InputAcmp4Out = 5|0x300U ,   kXBARB3_InputRESERVED6 = 6|0x300U , kXBARB3_InputRESERVED7 = 7|0x300U , kXBARB3_InputRESERVED8 = 8|0x300U , kXBARB3_InputRESERVED9 = 9|0x300U ,   kXBARB3_InputQtimer1Timer0 = 10|0x300U , kXBARB3_InputQtimer1Timer1 = 11|0x300U , kXBARB3_InputQtimer1Timer2 = 12|0x300U , kXBARB3_InputQtimer1Timer3 = 13|0x300U ,   kXBARB3_InputQtimer2Timer0 = 14|0x300U , kXBARB3_InputQtimer2Timer1 = 15|0x300U , kXBARB3_InputQtimer2Timer2 = 16|0x300U , kXBARB3_InputQtimer2Timer3 = 17|0x300U ,   kXBARB3_InputQtimer3Timer0 = 18|0x300U , kXBARB3_InputQtimer3Timer1 = 19|0x300U , kXBARB3_InputQtimer3Timer2 = 20|0x300U , kXBARB3_InputQtimer3Timer3 = 21|0x300U ,   kXBARB3_InputQtimer4Timer0 = 22|0x300U , kXBARB3_InputQtimer4Timer1 = 23|0x300U , kXBARB3_InputQtimer4Timer2 = 24|0x300U , kXBARB3_InputQtimer4Timer3 = 25|0x300U ,   kXBARB3_InputRESERVED26 = 26|0x300U , kXBARB3_InputRESERVED27 = 27|0x300U , kXBARB3_InputRESERVED28 = 28|0x300U , kXBARB3_InputRESERVED29 = 29|0x300U ,   kXBARB3_InputRESERVED30 = 30|0x300U , kXBARB3_InputRESERVED31 = 31|0x300U , kXBARB3_InputRESERVED32 = 32|0x300U , kXBARB3_InputRESERVED33 = 33|0x300U ,   kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U , kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U , kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U , kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U ,   kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U , kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U , kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U , kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U ,   kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U , kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U , kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U , kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U ,   kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U , kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U , kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U , kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U ,   kXBARB3_InputRESERVED50 = 50|0x300U , kXBARB3_InputRESERVED51 = 51|0x300U , kXBARB3_InputRESERVED52 = 52|0x300U , kXBARB3_InputRESERVED53 = 53|0x300U ,   kXBARB3_InputRESERVED54 = 54|0x300U , kXBARB3_InputRESERVED55 = 55|0x300U , kXBARB3_InputRESERVED56 = 56|0x300U , kXBARB3_InputRESERVED57 = 57|0x300U ,   kXBARB3_InputPit1Trigger0 = 58|0x300U , kXBARB3_InputPit1Trigger1 = 59|0x300U , kXBARB3_InputAdcEtc0Coco0 = 60|0x300U , kXBARB3_InputAdcEtc0Coco1 = 61|0x300U ,   kXBARB3_InputAdcEtc0Coco2 = 62|0x300U , kXBARB3_InputAdcEtc0Coco3 = 63|0x300U , kXBARB3_InputAdcEtc1Coco0 = 64|0x300U , kXBARB3_InputAdcEtc1Coco1 = 65|0x300U ,   kXBARB3_InputAdcEtc1Coco2 = 66|0x300U , kXBARB3_InputAdcEtc1Coco3 = 67|0x300U , kXBARB3_InputRESERVED68 = 68|0x300U , kXBARB3_InputRESERVED69 = 69|0x300U ,   kXBARB3_InputRESERVED70 = 70|0x300U , kXBARB3_InputRESERVED71 = 71|0x300U , kXBARB3_InputRESERVED72 = 72|0x300U , kXBARB3_InputRESERVED73 = 73|0x300U ,   kXBARB3_InputRESERVED74 = 74|0x300U , kXBARB3_InputRESERVED75 = 75|0x300U , kXBARB3_InputDec1PosMatch = 76|0x300U , kXBARB3_InputDec2PosMatch = 77|0x300U ,   kXBARB3_InputDec3PosMatch = 78|0x300U , kXBARB3_InputDec4PosMatch = 79|0x300U , kXBARB3_InputRESERVED80 = 80|0x300U , kXBARB3_InputRESERVED81 = 81|0x300U ,   kXBARB3_InputDmaDone0 = 82|0x300U , kXBARB3_InputDmaDone1 = 83|0x300U , kXBARB3_InputDmaDone2 = 84|0x300U , kXBARB3_InputDmaDone3 = 85|0x300U ,   kXBARB3_InputDmaDone4 = 86|0x300U , kXBARB3_InputDmaDone5 = 87|0x300U , kXBARB3_InputDmaDone6 = 88|0x300U , kXBARB3_InputDmaDone7 = 89|0x300U ,   kXBARB3_InputDmaLpsrDone0 = 90|0x300U , kXBARB3_InputDmaLpsrDone1 = 91|0x300U , kXBARB3_InputDmaLpsrDone2 = 92|0x300U , kXBARB3_InputDmaLpsrDone3 = 93|0x300U ,   kXBARB3_InputDmaLpsrDone4 = 94|0x300U , kXBARB3_InputDmaLpsrDone5 = 95|0x300U , kXBARB3_InputDmaLpsrDone6 = 96|0x300U , kXBARB3_InputDmaLpsrDone7 = 97|0x300U }
enum	_xbar_output_signal {   kXBARA1_OutputDmaChMuxReq81 = 0|0x100U , kXBARA1_OutputDmaChMuxReq82 = 1|0x100U , kXBARA1_OutputDmaChMuxReq83 = 2|0x100U , kXBARA1_OutputDmaChMuxReq84 = 3|0x100U ,   kXBARA1_OutputIomuxXbarInout04 = 4|0x100U , kXBARA1_OutputIomuxXbarInout05 = 5|0x100U , kXBARA1_OutputIomuxXbarInout06 = 6|0x100U , kXBARA1_OutputIomuxXbarInout07 = 7|0x100U ,   kXBARA1_OutputIomuxXbarInout08 = 8|0x100U , kXBARA1_OutputIomuxXbarInout09 = 9|0x100U , kXBARA1_OutputIomuxXbarInout10 = 10|0x100U , kXBARA1_OutputIomuxXbarInout11 = 11|0x100U ,   kXBARA1_OutputIomuxXbarInout12 = 12|0x100U , kXBARA1_OutputIomuxXbarInout13 = 13|0x100U , kXBARA1_OutputIomuxXbarInout14 = 14|0x100U , kXBARA1_OutputIomuxXbarInout15 = 15|0x100U ,   kXBARA1_OutputIomuxXbarInout16 = 16|0x100U , kXBARA1_OutputIomuxXbarInout17 = 17|0x100U , kXBARA1_OutputIomuxXbarInout18 = 18|0x100U , kXBARA1_OutputIomuxXbarInout19 = 19|0x100U ,   kXBARA1_OutputIomuxXbarInout20 = 20|0x100U , kXBARA1_OutputIomuxXbarInout21 = 21|0x100U , kXBARA1_OutputIomuxXbarInout22 = 22|0x100U , kXBARA1_OutputIomuxXbarInout23 = 23|0x100U ,   kXBARA1_OutputIomuxXbarInout24 = 24|0x100U , kXBARA1_OutputIomuxXbarInout25 = 25|0x100U , kXBARA1_OutputIomuxXbarInout26 = 26|0x100U , kXBARA1_OutputIomuxXbarInout27 = 27|0x100U ,   kXBARA1_OutputIomuxXbarInout28 = 28|0x100U , kXBARA1_OutputIomuxXbarInout29 = 29|0x100U , kXBARA1_OutputIomuxXbarInout30 = 30|0x100U , kXBARA1_OutputIomuxXbarInout31 = 31|0x100U ,   kXBARA1_OutputIomuxXbarInout32 = 32|0x100U , kXBARA1_OutputIomuxXbarInout33 = 33|0x100U , kXBARA1_OutputIomuxXbarInout34 = 34|0x100U , kXBARA1_OutputIomuxXbarInout35 = 35|0x100U ,   kXBARA1_OutputIomuxXbarInout36 = 36|0x100U , kXBARA1_OutputIomuxXbarInout37 = 37|0x100U , kXBARA1_OutputIomuxXbarInout38 = 38|0x100U , kXBARA1_OutputIomuxXbarInout39 = 39|0x100U ,   kXBARA1_OutputIomuxXbarInout40 = 40|0x100U , kXBARA1_OutputAcmp1Sample = 41|0x100U , kXBARA1_OutputAcmp2Sample = 42|0x100U , kXBARA1_OutputAcmp3Sample = 43|0x100U ,   kXBARA1_OutputAcmp4Sample = 44|0x100U , kXBARA1_OutputRESERVED45 = 45|0x100U , kXBARA1_OutputRESERVED46 = 46|0x100U , kXBARA1_OutputRESERVED47 = 47|0x100U ,   kXBARA1_OutputRESERVED48 = 48|0x100U , kXBARA1_OutputFlexpwm1Pwm0Exta = 49|0x100U , kXBARA1_OutputFlexpwm1Pwm1Exta = 50|0x100U , kXBARA1_OutputFlexpwm1Pwm2Exta = 51|0x100U ,   kXBARA1_OutputFlexpwm1Pwm3Exta = 52|0x100U , kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U , kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U , kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U ,   kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U , kXBARA1_OutputFlexpwm1ExtClk = 57|0x100U , kXBARA1_OutputFlexpwm1Fault0 = 58|0x100U , kXBARA1_OutputFlexpwm1Fault1 = 59|0x100U ,   kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U , kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U , kXBARA1_OutputFlexpwm1ExtForce = 62|0x100U , kXBARA1_OutputFlexpwm2Pwm0Exta = 63|0x100U ,   kXBARA1_OutputFlexpwm2Pwm1Exta = 64|0x100U , kXBARA1_OutputFlexpwm2Pwm2Exta = 65|0x100U , kXBARA1_OutputFlexpwm2Pwm3Exta = 66|0x100U , kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U ,   kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U , kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U , kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U , kXBARA1_OutputFlexpwm2ExtClk = 71|0x100U ,   kXBARA1_OutputFlexpwm2Fault0 = 72|0x100U , kXBARA1_OutputFlexpwm2Fault1 = 73|0x100U , kXBARA1_OutputFlexpwm2ExtForce = 74|0x100U , kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U ,   kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U , kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U , kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U , kXBARA1_OutputFlexpwm34ExtClk = 79|0x100U ,   kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U , kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U , kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U , kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U ,   kXBARA1_OutputFlexpwm3Fault0 = 84|0x100U , kXBARA1_OutputFlexpwm3Fault1 = 85|0x100U , kXBARA1_OutputFlexpwm3ExtForce = 86|0x100U , kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U ,   kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U , kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U , kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U , kXBARA1_OutputFlexpwm4Fault0 = 91|0x100U ,   kXBARA1_OutputFlexpwm4Fault1 = 92|0x100U , kXBARA1_OutputFlexpwm4ExtForce = 93|0x100U , kXBARA1_OutputRESERVED94 = 94|0x100U , kXBARA1_OutputRESERVED95 = 95|0x100U ,   kXBARA1_OutputRESERVED96 = 96|0x100U , kXBARA1_OutputRESERVED97 = 97|0x100U , kXBARA1_OutputRESERVED98 = 98|0x100U , kXBARA1_OutputRESERVED99 = 99|0x100U ,   kXBARA1_OutputRESERVED100 = 100|0x100U , kXBARA1_OutputRESERVED101 = 101|0x100U , kXBARA1_OutputRESERVED102 = 102|0x100U , kXBARA1_OutputRESERVED103 = 103|0x100U ,   kXBARA1_OutputRESERVED104 = 104|0x100U , kXBARA1_OutputRESERVED105 = 105|0x100U , kXBARA1_OutputRESERVED106 = 106|0x100U , kXBARA1_OutputRESERVED107 = 107|0x100U ,   kXBARA1_OutputDec1Phasea = 108|0x100U , kXBARA1_OutputDec1Phaseb = 109|0x100U , kXBARA1_OutputDec1Index = 110|0x100U , kXBARA1_OutputDec1Home = 111|0x100U ,   kXBARA1_OutputDec1Trigger = 112|0x100U , kXBARA1_OutputDec2Phasea = 113|0x100U , kXBARA1_OutputDec2Phaseb = 114|0x100U , kXBARA1_OutputDec2Index = 115|0x100U ,   kXBARA1_OutputDec2Home = 116|0x100U , kXBARA1_OutputDec2Trigger = 117|0x100U , kXBARA1_OutputDec3Phasea = 118|0x100U , kXBARA1_OutputDec3Phaseb = 119|0x100U ,   kXBARA1_OutputDec3Index = 120|0x100U , kXBARA1_OutputDec3Home = 121|0x100U , kXBARA1_OutputDec3Trigger = 122|0x100U , kXBARA1_OutputDec4Phasea = 123|0x100U ,   kXBARA1_OutputDec4Phaseb = 124|0x100U , kXBARA1_OutputDec4Index = 125|0x100U , kXBARA1_OutputDec4Home = 126|0x100U , kXBARA1_OutputDec4Trigger = 127|0x100U ,   kXBARA1_OutputRESERVED128 = 128|0x100U , kXBARA1_OutputRESERVED129 = 129|0x100U , kXBARA1_OutputRESERVED130 = 130|0x100U , kXBARA1_OutputRESERVED131 = 131|0x100U ,   kXBARA1_OutputCan1 = 132|0x100U , kXBARA1_OutputCan2 = 133|0x100U , kXBARA1_OutputRESERVED134 = 134|0x100U , kXBARA1_OutputRESERVED135 = 135|0x100U ,   kXBARA1_OutputRESERVED136 = 136|0x100U , kXBARA1_OutputRESERVED137 = 137|0x100U , kXBARA1_OutputQtimer1Timer0 = 138|0x100U , kXBARA1_OutputQtimer1Timer1 = 139|0x100U ,   kXBARA1_OutputQtimer1Timer2 = 140|0x100U , kXBARA1_OutputQtimer1Timer3 = 141|0x100U , kXBARA1_OutputQtimer2Timer0 = 142|0x100U , kXBARA1_OutputQtimer2Timer1 = 143|0x100U ,   kXBARA1_OutputQtimer2Timer2 = 144|0x100U , kXBARA1_OutputQtimer2Timer3 = 145|0x100U , kXBARA1_OutputQtimer3Timer0 = 146|0x100U , kXBARA1_OutputQtimer3Timer1 = 147|0x100U ,   kXBARA1_OutputQtimer3Timer2 = 148|0x100U , kXBARA1_OutputQtimer3Timer3 = 149|0x100U , kXBARA1_OutputQtimer4Timer0 = 150|0x100U , kXBARA1_OutputQtimer4Timer1 = 151|0x100U ,   kXBARA1_OutputQtimer4Timer2 = 152|0x100U , kXBARA1_OutputQtimer4Timer3 = 153|0x100U , kXBARA1_OutputEwmEwmIn = 154|0x100U , kXBARA1_OutputAdcEtc0Coco0 = 155|0x100U ,   kXBARA1_OutputAdcEtc0Coco1 = 156|0x100U , kXBARA1_OutputAdcEtc0Coco2 = 157|0x100U , kXBARA1_OutputAdcEtc0Coco3 = 158|0x100U , kXBARA1_OutputAdcEtc1Coco0 = 159|0x100U ,   kXBARA1_OutputAdcEtc1Coco1 = 160|0x100U , kXBARA1_OutputAdcEtc1Coco2 = 161|0x100U , kXBARA1_OutputAdcEtc1Coco3 = 162|0x100U , kXBARA1_OutputRESERVED163 = 163|0x100U ,   kXBARA1_OutputRESERVED164 = 164|0x100U , kXBARA1_OutputRESERVED165 = 165|0x100U , kXBARA1_OutputRESERVED166 = 166|0x100U , kXBARA1_OutputRESERVED167 = 167|0x100U ,   kXBARA1_OutputRESERVED168 = 168|0x100U , kXBARA1_OutputRESERVED169 = 169|0x100U , kXBARA1_OutputRESERVED170 = 170|0x100U , kXBARA1_OutputFlexio1TrigIn0 = 171|0x100U ,   kXBARA1_OutputFlexio1TrigIn1 = 172|0x100U , kXBARA1_OutputFlexio2TrigIn0 = 173|0x100U , kXBARA1_OutputFlexio2TrigIn1 = 174|0x100U , kXBARB2_OutputAoi1In00 = 0|0x200U ,   kXBARB2_OutputAoi1In01 = 1|0x200U , kXBARB2_OutputAoi1In02 = 2|0x200U , kXBARB2_OutputAoi1In03 = 3|0x200U , kXBARB2_OutputAoi1In04 = 4|0x200U ,   kXBARB2_OutputAoi1In05 = 5|0x200U , kXBARB2_OutputAoi1In06 = 6|0x200U , kXBARB2_OutputAoi1In07 = 7|0x200U , kXBARB2_OutputAoi1In08 = 8|0x200U ,   kXBARB2_OutputAoi1In09 = 9|0x200U , kXBARB2_OutputAoi1In10 = 10|0x200U , kXBARB2_OutputAoi1In11 = 11|0x200U , kXBARB2_OutputAoi1In12 = 12|0x200U ,   kXBARB2_OutputAoi1In13 = 13|0x200U , kXBARB2_OutputAoi1In14 = 14|0x200U , kXBARB2_OutputAoi1In15 = 15|0x200U , kXBARB3_OutputAoi2In00 = 0|0x300U ,   kXBARB3_OutputAoi2In01 = 1|0x300U , kXBARB3_OutputAoi2In02 = 2|0x300U , kXBARB3_OutputAoi2In03 = 3|0x300U , kXBARB3_OutputAoi2In04 = 4|0x300U ,   kXBARB3_OutputAoi2In05 = 5|0x300U , kXBARB3_OutputAoi2In06 = 6|0x300U , kXBARB3_OutputAoi2In07 = 7|0x300U , kXBARB3_OutputAoi2In08 = 8|0x300U ,   kXBARB3_OutputAoi2In09 = 9|0x300U , kXBARB3_OutputAoi2In10 = 10|0x300U , kXBARB3_OutputAoi2In11 = 11|0x300U , kXBARB3_OutputAoi2In12 = 12|0x300U ,   kXBARB3_OutputAoi2In13 = 13|0x300U , kXBARB3_OutputAoi2In14 = 14|0x300U , kXBARB3_OutputAoi2In15 = 15|0x300U }
enum	_dma_request_source {   kDmaRequestMuxFlexIO1Request2Request3 = 1|0x100U , kDmaRequestMuxFlexIO1Request4Request5 = 2|0x100U , kDmaRequestMuxFlexIO1Request6Request7 = 3|0x100U , kDmaRequestMuxFlexIO2Request0Request1 = 4|0x100U ,   kDmaRequestMuxFlexIO2Request2Request3 = 5|0x100U , kDmaRequestMuxFlexIO2Request4Request5 = 6|0x100U , kDmaRequestMuxFlexIO2Request6Request7 = 7|0x100U , kDmaRequestMuxLPUART1Tx = 8|0x100U ,   kDmaRequestMuxLPUART1Rx = 9|0x100U , kDmaRequestMuxLPUART2Tx = 10|0x100U , kDmaRequestMuxLPUART2Rx = 11|0x100U , kDmaRequestMuxLPUART3Tx = 12|0x100U ,   kDmaRequestMuxLPUART3Rx = 13|0x100U , kDmaRequestMuxLPUART4Tx = 14|0x100U , kDmaRequestMuxLPUART4Rx = 15|0x100U , kDmaRequestMuxLPUART5Tx = 16|0x100U ,   kDmaRequestMuxLPUART5Rx = 17|0x100U , kDmaRequestMuxLPUART6Tx = 18|0x100U , kDmaRequestMuxLPUART6Rx = 19|0x100U , kDmaRequestMuxLPUART7Tx = 20|0x100U ,   kDmaRequestMuxLPUART7Rx = 21|0x100U , kDmaRequestMuxLPUART8Tx = 22|0x100U , kDmaRequestMuxLPUART8Rx = 23|0x100U , kDmaRequestMuxLPUART9Tx = 24|0x100U ,   kDmaRequestMuxLPUART9Rx = 25|0x100U , kDmaRequestMuxLPUART10Tx = 26|0x100U , kDmaRequestMuxLPUART10Rx = 27|0x100U , kDmaRequestMuxLPUART11Tx = 28|0x100U ,   kDmaRequestMuxLPUART11Rx = 29|0x100U , kDmaRequestMuxLPUART12Tx = 30|0x100U , kDmaRequestMuxLPUART12Rx = 31|0x100U , kDmaRequestMuxCSI = 32|0x100U ,   kDmaRequestMuxPxp = 33|0x100U , kDmaRequestMuxeLCDIF = 34|0x100U , kDmaRequestMuxLCDIFv2 = 35|0x100U , kDmaRequestMuxLPSPI1Rx = 36|0x100U ,   kDmaRequestMuxLPSPI1Tx = 37|0x100U , kDmaRequestMuxLPSPI2Rx = 38|0x100U , kDmaRequestMuxLPSPI2Tx = 39|0x100U , kDmaRequestMuxLPSPI3Rx = 40|0x100U ,   kDmaRequestMuxLPSPI3Tx = 41|0x100U , kDmaRequestMuxLPSPI4Rx = 42|0x100U , kDmaRequestMuxLPSPI4Tx = 43|0x100U , kDmaRequestMuxLPSPI5Rx = 44|0x100U ,   kDmaRequestMuxLPSPI5Tx = 45|0x100U , kDmaRequestMuxLPSPI6Rx = 46|0x100U , kDmaRequestMuxLPSPI6Tx = 47|0x100U , kDmaRequestMuxLPI2C1 = 48|0x100U ,   kDmaRequestMuxLPI2C2 = 49|0x100U , kDmaRequestMuxLPI2C3 = 50|0x100U , kDmaRequestMuxLPI2C4 = 51|0x100U , kDmaRequestMuxLPI2C5 = 52|0x100U ,   kDmaRequestMuxLPI2C6 = 53|0x100U , kDmaRequestMuxSai1Rx = 54|0x100U , kDmaRequestMuxSai1Tx = 55|0x100U , kDmaRequestMuxSai2Rx = 56|0x100U ,   kDmaRequestMuxSai2Tx = 57|0x100U , kDmaRequestMuxSai3Rx = 58|0x100U , kDmaRequestMuxSai3Tx = 59|0x100U , kDmaRequestMuxSai4Rx = 60|0x100U ,   kDmaRequestMuxSai4Tx = 61|0x100U , kDmaRequestMuxSpdifRx = 62|0x100U , kDmaRequestMuxSpdifTx = 63|0x100U , kDmaRequestMuxADC_ETC = 64|0x100U ,   kDmaRequestMuxFlexIO1Request0Request1 = 65|0x100U , kDmaRequestMuxADC1 = 66|0x100U , kDmaRequestMuxADC2 = 67|0x100U , kDmaRequestMuxACMP1 = 69|0x100U ,   kDmaRequestMuxACMP2 = 70|0x100U , kDmaRequestMuxACMP3 = 71|0x100U , kDmaRequestMuxACMP4 = 72|0x100U , kDmaRequestMuxFlexSPI1Rx = 77|0x100U ,   kDmaRequestMuxFlexSPI1Tx = 78|0x100U , kDmaRequestMuxFlexSPI2Rx = 79|0x100U , kDmaRequestMuxFlexSPI2Tx = 80|0x100U , kDmaRequestMuxXBAR1Request0 = 81|0x100U ,   kDmaRequestMuxXBAR1Request1 = 82|0x100U , kDmaRequestMuxXBAR1Request2 = 83|0x100U , kDmaRequestMuxXBAR1Request3 = 84|0x100U , kDmaRequestMuxFlexPWM1CaptureSub0 = 85|0x100U ,   kDmaRequestMuxFlexPWM1CaptureSub1 = 86|0x100U , kDmaRequestMuxFlexPWM1CaptureSub2 = 87|0x100U , kDmaRequestMuxFlexPWM1CaptureSub3 = 88|0x100U , kDmaRequestMuxFlexPWM1ValueSub0 = 89|0x100U ,   kDmaRequestMuxFlexPWM1ValueSub1 = 90|0x100U , kDmaRequestMuxFlexPWM1ValueSub2 = 91|0x100U , kDmaRequestMuxFlexPWM1ValueSub3 = 92|0x100U , kDmaRequestMuxFlexPWM2CaptureSub0 = 93|0x100U ,   kDmaRequestMuxFlexPWM2CaptureSub1 = 94|0x100U , kDmaRequestMuxFlexPWM2CaptureSub2 = 95|0x100U , kDmaRequestMuxFlexPWM2CaptureSub3 = 96|0x100U , kDmaRequestMuxFlexPWM2ValueSub0 = 97|0x100U ,   kDmaRequestMuxFlexPWM2ValueSub1 = 98|0x100U , kDmaRequestMuxFlexPWM2ValueSub2 = 99|0x100U , kDmaRequestMuxFlexPWM2ValueSub3 = 100|0x100U , kDmaRequestMuxFlexPWM3CaptureSub0 = 101|0x100U ,   kDmaRequestMuxFlexPWM3CaptureSub1 = 102|0x100U , kDmaRequestMuxFlexPWM3CaptureSub2 = 103|0x100U , kDmaRequestMuxFlexPWM3CaptureSub3 = 104|0x100U , kDmaRequestMuxFlexPWM3ValueSub0 = 105|0x100U ,   kDmaRequestMuxFlexPWM3ValueSub1 = 106|0x100U , kDmaRequestMuxFlexPWM3ValueSub2 = 107|0x100U , kDmaRequestMuxFlexPWM3ValueSub3 = 108|0x100U , kDmaRequestMuxFlexPWM4CaptureSub0 = 109|0x100U ,   kDmaRequestMuxFlexPWM4CaptureSub1 = 110|0x100U , kDmaRequestMuxFlexPWM4CaptureSub2 = 111|0x100U , kDmaRequestMuxFlexPWM4CaptureSub3 = 112|0x100U , kDmaRequestMuxFlexPWM4ValueSub0 = 113|0x100U ,   kDmaRequestMuxFlexPWM4ValueSub1 = 114|0x100U , kDmaRequestMuxFlexPWM4ValueSub2 = 115|0x100U , kDmaRequestMuxFlexPWM4ValueSub3 = 116|0x100U , kDmaRequestMuxQTIMER1CaptTimer0 = 133|0x100U ,   kDmaRequestMuxQTIMER1CaptTimer1 = 134|0x100U , kDmaRequestMuxQTIMER1CaptTimer2 = 135|0x100U , kDmaRequestMuxQTIMER1CaptTimer3 = 136|0x100U , kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 137|0x100U ,   kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 138|0x100U , kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 139|0x100U , kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 140|0x100U , kDmaRequestMuxQTIMER2CaptTimer0 = 141|0x100U ,   kDmaRequestMuxQTIMER2CaptTimer1 = 142|0x100U , kDmaRequestMuxQTIMER2CaptTimer2 = 143|0x100U , kDmaRequestMuxQTIMER2CaptTimer3 = 144|0x100U , kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 145|0x100U ,   kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 146|0x100U , kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 147|0x100U , kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 148|0x100U , kDmaRequestMuxQTIMER3CaptTimer0 = 149|0x100U ,   kDmaRequestMuxQTIMER3CaptTimer1 = 150|0x100U , kDmaRequestMuxQTIMER3CaptTimer2 = 151|0x100U , kDmaRequestMuxQTIMER3CaptTimer3 = 152|0x100U , kDmaRequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1 = 153|0x100U ,   kDmaRequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0 = 154|0x100U , kDmaRequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3 = 155|0x100U , kDmaRequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2 = 156|0x100U , kDmaRequestMuxQTIMER4CaptTimer0 = 157|0x100U ,   kDmaRequestMuxQTIMER4CaptTimer1 = 158|0x100U , kDmaRequestMuxQTIMER4CaptTimer2 = 159|0x100U , kDmaRequestMuxQTIMER4CaptTimer3 = 160|0x100U , kDmaRequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1 = 161|0x100U ,   kDmaRequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0 = 162|0x100U , kDmaRequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3 = 163|0x100U , kDmaRequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2 = 164|0x100U , kDmaRequestMuxPdm = 181|0x100U ,   kDmaRequestMuxEnetTimer0 = 182|0x100U , kDmaRequestMuxEnetTimer1 = 183|0x100U , kDmaRequestMuxEnet1GTimer0 = 184|0x100U , kDmaRequestMuxEnet1GTimer1 = 185|0x100U ,   kDmaRequestMuxCAN1 = 186|0x100U , kDmaRequestMuxCAN2 = 187|0x100U , kDmaRequestMuxCAN3 = 188|0x100U , kDmaRequestMuxDAC = 189|0x100U ,   kDmaRequestMuxASRCRequest1 = 191|0x100U , kDmaRequestMuxASRCRequest2 = 192|0x100U , kDmaRequestMuxASRCRequest3 = 193|0x100U , kDmaRequestMuxASRCRequest4 = 194|0x100U ,   kDmaRequestMuxASRCRequest5 = 195|0x100U , kDmaRequestMuxASRCRequest6 = 196|0x100U , kDmaRequestMuxEmvsim1Tx = 197|0x100U , kDmaRequestMuxEmvsim1Rx = 198|0x100U ,   kDmaRequestMuxEmvsim2Tx = 199|0x100U , kDmaRequestMuxEmvsim2Rx = 200|0x100U }
	Structure for the DMA hardware request. More...
enum	_iomuxc_lpsr_sw_mux_ctl_pad {   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U }
	Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD. More...
enum	_iomuxc_lpsr_sw_pad_ctl_pad {   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U }
	Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD. More...
enum	_iomuxc_lpsr_select_input {   kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U , kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U ,   kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U ,   kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U , kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U ,   kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U ,   kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U , kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U , kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U ,   kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U }
	Enumeration for the IOMUXC_LPSR select input. More...
enum	_ssarc_power_domain_name {   kSSARC_MEGAMIXPowerDomain = 0U , kSSARC_DISPLAYMIXPowerDomain = 1U , kSSARC_WAKEUPMIXPowerDomain = 2U , kSSARC_LPSRMIXPowerDomain = 3U ,   kSSARC_PowerDomain4 = 4U , kSSARC_PowerDomain5 = 5U , kSSARC_PowerDomain6 = 6U , kSSARC_PowerDomain7 = 7U }
	Structure for the SSARC mapping. More...
enum	_ssarc_cpu_domain_name { kSSARC_CM7Core = 0U , kSSARC_CM4Core = 1U }
enum	_xrdc2_master {   kXRDC2_Master_M7_AHB = 0U , kXRDC2_Master_M4_AHBC = 0U , kXRDC2_Master_M7_AXI = 1U , kXRDC2_Master_M4_AHBS = 1U ,   kXRDC2_Master_CAAM = 2U , kXRDC2_Master_CSI = 3U , kXRDC2_Master_M7_EDMA = 4U , kXRDC2_Master_M4_EDMA = 4U ,   kXRDC2_Master_ENET = 5U , kXRDC2_Master_ENET_1G_RX = 6U , kXRDC2_Master_ENET_1G_TX = 7U , kXRDC2_Master_ENET_QOS = 8U ,   kXRDC2_Master_GPU = 9U , kXRDC2_Master_LCDIF = 10U , kXRDC2_Master_LCDIFV2 = 11U , kXRDC2_Master_PXP = 12U ,   kXRDC2_Master_SSARC = 14U , kXRDC2_Master_USB = 15U , kXRDC2_Master_USDHC1 = 16U , kXRDC2_Master_USDHC2 = 17U }
	Structure for the XRDC2 mapping. More...
enum	_xrdc2_mem {   kXRDC2_Mem_CAAM_Region0 = XRDC2_MAKE_MEM(0, 0) , kXRDC2_Mem_CAAM_Region1 = XRDC2_MAKE_MEM(0, 1) , kXRDC2_Mem_CAAM_Region2 = XRDC2_MAKE_MEM(0, 2) , kXRDC2_Mem_CAAM_Region3 = XRDC2_MAKE_MEM(0, 3) ,   kXRDC2_Mem_CAAM_Region4 = XRDC2_MAKE_MEM(0, 4) , kXRDC2_Mem_CAAM_Region5 = XRDC2_MAKE_MEM(0, 5) , kXRDC2_Mem_CAAM_Region6 = XRDC2_MAKE_MEM(0, 6) , kXRDC2_Mem_CAAM_Region7 = XRDC2_MAKE_MEM(0, 7) ,   kXRDC2_Mem_CAAM_Region8 = XRDC2_MAKE_MEM(0, 8) , kXRDC2_Mem_CAAM_Region9 = XRDC2_MAKE_MEM(0, 9) , kXRDC2_Mem_CAAM_Region10 = XRDC2_MAKE_MEM(0, 10) , kXRDC2_Mem_CAAM_Region11 = XRDC2_MAKE_MEM(0, 11) ,   kXRDC2_Mem_CAAM_Region12 = XRDC2_MAKE_MEM(0, 12) , kXRDC2_Mem_CAAM_Region13 = XRDC2_MAKE_MEM(0, 13) , kXRDC2_Mem_CAAM_Region14 = XRDC2_MAKE_MEM(0, 14) , kXRDC2_Mem_CAAM_Region15 = XRDC2_MAKE_MEM(0, 15) ,   kXRDC2_Mem_FLEXSPI1_Region0 = XRDC2_MAKE_MEM(1, 0) , kXRDC2_Mem_FLEXSPI1_Region1 = XRDC2_MAKE_MEM(1, 1) , kXRDC2_Mem_FLEXSPI1_Region2 = XRDC2_MAKE_MEM(1, 2) , kXRDC2_Mem_FLEXSPI1_Region3 = XRDC2_MAKE_MEM(1, 3) ,   kXRDC2_Mem_FLEXSPI1_Region4 = XRDC2_MAKE_MEM(1, 4) , kXRDC2_Mem_FLEXSPI1_Region5 = XRDC2_MAKE_MEM(1, 5) , kXRDC2_Mem_FLEXSPI1_Region6 = XRDC2_MAKE_MEM(1, 6) , kXRDC2_Mem_FLEXSPI1_Region7 = XRDC2_MAKE_MEM(1, 7) ,   kXRDC2_Mem_FLEXSPI1_Region8 = XRDC2_MAKE_MEM(1, 8) , kXRDC2_Mem_FLEXSPI1_Region9 = XRDC2_MAKE_MEM(1, 9) , kXRDC2_Mem_FLEXSPI1_Region10 = XRDC2_MAKE_MEM(1, 10) , kXRDC2_Mem_FLEXSPI1_Region11 = XRDC2_MAKE_MEM(1, 11) ,   kXRDC2_Mem_FLEXSPI1_Region12 = XRDC2_MAKE_MEM(1, 12) , kXRDC2_Mem_FLEXSPI1_Region13 = XRDC2_MAKE_MEM(1, 13) , kXRDC2_Mem_FLEXSPI1_Region14 = XRDC2_MAKE_MEM(1, 14) , kXRDC2_Mem_FLEXSPI1_Region15 = XRDC2_MAKE_MEM(1, 15) ,   kXRDC2_Mem_FLEXSPI2_Region0 = XRDC2_MAKE_MEM(2, 0) , kXRDC2_Mem_FLEXSPI2_Region1 = XRDC2_MAKE_MEM(2, 1) , kXRDC2_Mem_FLEXSPI2_Region2 = XRDC2_MAKE_MEM(2, 2) , kXRDC2_Mem_FLEXSPI2_Region3 = XRDC2_MAKE_MEM(2, 3) ,   kXRDC2_Mem_FLEXSPI2_Region4 = XRDC2_MAKE_MEM(2, 4) , kXRDC2_Mem_FLEXSPI2_Region5 = XRDC2_MAKE_MEM(2, 5) , kXRDC2_Mem_FLEXSPI2_Region6 = XRDC2_MAKE_MEM(2, 6) , kXRDC2_Mem_FLEXSPI2_Region7 = XRDC2_MAKE_MEM(2, 7) ,   kXRDC2_Mem_FLEXSPI2_Region8 = XRDC2_MAKE_MEM(2, 8) , kXRDC2_Mem_FLEXSPI2_Region9 = XRDC2_MAKE_MEM(2, 9) , kXRDC2_Mem_FLEXSPI2_Region10 = XRDC2_MAKE_MEM(2, 10) , kXRDC2_Mem_FLEXSPI2_Region11 = XRDC2_MAKE_MEM(2, 11) ,   kXRDC2_Mem_FLEXSPI2_Region12 = XRDC2_MAKE_MEM(2, 12) , kXRDC2_Mem_FLEXSPI2_Region13 = XRDC2_MAKE_MEM(2, 13) , kXRDC2_Mem_FLEXSPI2_Region14 = XRDC2_MAKE_MEM(2, 14) , kXRDC2_Mem_FLEXSPI2_Region15 = XRDC2_MAKE_MEM(2, 15) ,   kXRDC2_Mem_M4LMEM_Region0 = XRDC2_MAKE_MEM(3, 0) , kXRDC2_Mem_M4LMEM_Region1 = XRDC2_MAKE_MEM(3, 1) , kXRDC2_Mem_M4LMEM_Region2 = XRDC2_MAKE_MEM(3, 2) , kXRDC2_Mem_M4LMEM_Region3 = XRDC2_MAKE_MEM(3, 3) ,   kXRDC2_Mem_M4LMEM_Region4 = XRDC2_MAKE_MEM(3, 4) , kXRDC2_Mem_M4LMEM_Region5 = XRDC2_MAKE_MEM(3, 5) , kXRDC2_Mem_M4LMEM_Region6 = XRDC2_MAKE_MEM(3, 6) , kXRDC2_Mem_M4LMEM_Region7 = XRDC2_MAKE_MEM(3, 7) ,   kXRDC2_Mem_M4LMEM_Region8 = XRDC2_MAKE_MEM(3, 8) , kXRDC2_Mem_M4LMEM_Region9 = XRDC2_MAKE_MEM(3, 9) , kXRDC2_Mem_M4LMEM_Region10 = XRDC2_MAKE_MEM(3, 10) , kXRDC2_Mem_M4LMEM_Region11 = XRDC2_MAKE_MEM(3, 11) ,   kXRDC2_Mem_M4LMEM_Region12 = XRDC2_MAKE_MEM(3, 12) , kXRDC2_Mem_M4LMEM_Region13 = XRDC2_MAKE_MEM(3, 13) , kXRDC2_Mem_M4LMEM_Region14 = XRDC2_MAKE_MEM(3, 14) , kXRDC2_Mem_M4LMEM_Region15 = XRDC2_MAKE_MEM(3, 15) ,   kXRDC2_Mem_M7OC_Region0 = XRDC2_MAKE_MEM(4, 0) , kXRDC2_Mem_M7OC_Region1 = XRDC2_MAKE_MEM(4, 1) , kXRDC2_Mem_M7OC_Region2 = XRDC2_MAKE_MEM(4, 2) , kXRDC2_Mem_M7OC_Region3 = XRDC2_MAKE_MEM(4, 3) ,   kXRDC2_Mem_M7OC_Region4 = XRDC2_MAKE_MEM(4, 4) , kXRDC2_Mem_M7OC_Region5 = XRDC2_MAKE_MEM(4, 5) , kXRDC2_Mem_M7OC_Region6 = XRDC2_MAKE_MEM(4, 6) , kXRDC2_Mem_M7OC_Region7 = XRDC2_MAKE_MEM(4, 7) ,   kXRDC2_Mem_M7OC_Region8 = XRDC2_MAKE_MEM(4, 8) , kXRDC2_Mem_M7OC_Region9 = XRDC2_MAKE_MEM(4, 9) , kXRDC2_Mem_M7OC_Region10 = XRDC2_MAKE_MEM(4, 10) , kXRDC2_Mem_M7OC_Region11 = XRDC2_MAKE_MEM(4, 11) ,   kXRDC2_Mem_M7OC_Region12 = XRDC2_MAKE_MEM(4, 12) , kXRDC2_Mem_M7OC_Region13 = XRDC2_MAKE_MEM(4, 13) , kXRDC2_Mem_M7OC_Region14 = XRDC2_MAKE_MEM(4, 14) , kXRDC2_Mem_M7OC_Region15 = XRDC2_MAKE_MEM(4, 15) ,   kXRDC2_Mem_MECC1_Region0 = XRDC2_MAKE_MEM(5, 0) , kXRDC2_Mem_MECC1_Region1 = XRDC2_MAKE_MEM(5, 1) , kXRDC2_Mem_MECC1_Region2 = XRDC2_MAKE_MEM(5, 2) , kXRDC2_Mem_MECC1_Region3 = XRDC2_MAKE_MEM(5, 3) ,   kXRDC2_Mem_MECC1_Region4 = XRDC2_MAKE_MEM(5, 4) , kXRDC2_Mem_MECC1_Region5 = XRDC2_MAKE_MEM(5, 5) , kXRDC2_Mem_MECC1_Region6 = XRDC2_MAKE_MEM(5, 6) , kXRDC2_Mem_MECC1_Region7 = XRDC2_MAKE_MEM(5, 7) ,   kXRDC2_Mem_MECC1_Region8 = XRDC2_MAKE_MEM(5, 8) , kXRDC2_Mem_MECC1_Region9 = XRDC2_MAKE_MEM(5, 9) , kXRDC2_Mem_MECC1_Region10 = XRDC2_MAKE_MEM(5, 10) , kXRDC2_Mem_MECC1_Region11 = XRDC2_MAKE_MEM(5, 11) ,   kXRDC2_Mem_MECC1_Region12 = XRDC2_MAKE_MEM(5, 12) , kXRDC2_Mem_MECC1_Region13 = XRDC2_MAKE_MEM(5, 13) , kXRDC2_Mem_MECC1_Region14 = XRDC2_MAKE_MEM(5, 14) , kXRDC2_Mem_MECC1_Region15 = XRDC2_MAKE_MEM(5, 15) ,   kXRDC2_Mem_MECC2_Region0 = XRDC2_MAKE_MEM(6, 0) , kXRDC2_Mem_MECC2_Region1 = XRDC2_MAKE_MEM(6, 1) , kXRDC2_Mem_MECC2_Region2 = XRDC2_MAKE_MEM(6, 2) , kXRDC2_Mem_MECC2_Region3 = XRDC2_MAKE_MEM(6, 3) ,   kXRDC2_Mem_MECC2_Region4 = XRDC2_MAKE_MEM(6, 4) , kXRDC2_Mem_MECC2_Region5 = XRDC2_MAKE_MEM(6, 5) , kXRDC2_Mem_MECC2_Region6 = XRDC2_MAKE_MEM(6, 6) , kXRDC2_Mem_MECC2_Region7 = XRDC2_MAKE_MEM(6, 7) ,   kXRDC2_Mem_MECC2_Region8 = XRDC2_MAKE_MEM(6, 8) , kXRDC2_Mem_MECC2_Region9 = XRDC2_MAKE_MEM(6, 9) , kXRDC2_Mem_MECC2_Region10 = XRDC2_MAKE_MEM(6, 10) , kXRDC2_Mem_MECC2_Region11 = XRDC2_MAKE_MEM(6, 11) ,   kXRDC2_Mem_MECC2_Region12 = XRDC2_MAKE_MEM(6, 12) , kXRDC2_Mem_MECC2_Region13 = XRDC2_MAKE_MEM(6, 13) , kXRDC2_Mem_MECC2_Region14 = XRDC2_MAKE_MEM(6, 14) , kXRDC2_Mem_MECC2_Region15 = XRDC2_MAKE_MEM(6, 15) ,   kXRDC2_Mem_SEMC_Region0 = XRDC2_MAKE_MEM(7, 0) , kXRDC2_Mem_SEMC_Region1 = XRDC2_MAKE_MEM(7, 1) , kXRDC2_Mem_SEMC_Region2 = XRDC2_MAKE_MEM(7, 2) , kXRDC2_Mem_SEMC_Region3 = XRDC2_MAKE_MEM(7, 3) ,   kXRDC2_Mem_SEMC_Region4 = XRDC2_MAKE_MEM(7, 4) , kXRDC2_Mem_SEMC_Region5 = XRDC2_MAKE_MEM(7, 5) , kXRDC2_Mem_SEMC_Region6 = XRDC2_MAKE_MEM(7, 6) , kXRDC2_Mem_SEMC_Region7 = XRDC2_MAKE_MEM(7, 7) ,   kXRDC2_Mem_SEMC_Region8 = XRDC2_MAKE_MEM(7, 8) , kXRDC2_Mem_SEMC_Region9 = XRDC2_MAKE_MEM(7, 9) , kXRDC2_Mem_SEMC_Region10 = XRDC2_MAKE_MEM(7, 10) , kXRDC2_Mem_SEMC_Region11 = XRDC2_MAKE_MEM(7, 11) ,   kXRDC2_Mem_SEMC_Region12 = XRDC2_MAKE_MEM(7, 12) , kXRDC2_Mem_SEMC_Region13 = XRDC2_MAKE_MEM(7, 13) , kXRDC2_Mem_SEMC_Region14 = XRDC2_MAKE_MEM(7, 14) , kXRDC2_Mem_SEMC_Region15 = XRDC2_MAKE_MEM(7, 15) }
enum	_xrdc2_mem_slot { kXRDC2_MemSlot_GPV0 = 0U , kXRDC2_MemSlot_GPV1 = 1U , kXRDC2_MemSlot_GPV2 = 2U , kXRDC2_MemSlot_ROMCP = 3U }
enum	_xrdc2_periph {   kXRDC2_Periph_ACMP4 = XRDC2_MAKE_PERIPH(0, 108) , kXRDC2_Periph_ACMP3 = XRDC2_MAKE_PERIPH(0, 107) , kXRDC2_Periph_ACMP2 = XRDC2_MAKE_PERIPH(0, 106) , kXRDC2_Periph_ACMP1 = XRDC2_MAKE_PERIPH(0, 105) ,   kXRDC2_Periph_FLEXPWM4 = XRDC2_MAKE_PERIPH(0, 102) , kXRDC2_Periph_FLEXPWM3 = XRDC2_MAKE_PERIPH(0, 101) , kXRDC2_Periph_FLEXPWM2 = XRDC2_MAKE_PERIPH(0, 100) , kXRDC2_Periph_FLEXPWM1 = XRDC2_MAKE_PERIPH(0, 99 ) ,   kXRDC2_Periph_ENC4 = XRDC2_MAKE_PERIPH(0, 96 ) , kXRDC2_Periph_ENC3 = XRDC2_MAKE_PERIPH(0, 95 ) , kXRDC2_Periph_ENC2 = XRDC2_MAKE_PERIPH(0, 94 ) , kXRDC2_Periph_ENC1 = XRDC2_MAKE_PERIPH(0, 93 ) ,   kXRDC2_Periph_QTIMER4 = XRDC2_MAKE_PERIPH(0, 90 ) , kXRDC2_Periph_QTIMER3 = XRDC2_MAKE_PERIPH(0, 89 ) , kXRDC2_Periph_QTIMER2 = XRDC2_MAKE_PERIPH(0, 88 ) , kXRDC2_Periph_QTIMER1 = XRDC2_MAKE_PERIPH(0, 87 ) ,   kXRDC2_Periph_SIM2 = XRDC2_MAKE_PERIPH(0, 86 ) , kXRDC2_Periph_SIM1 = XRDC2_MAKE_PERIPH(0, 85 ) , kXRDC2_Periph_CCM_OBS = XRDC2_MAKE_PERIPH(0, 84 ) , kXRDC2_Periph_GPIO6 = XRDC2_MAKE_PERIPH(0, 80 ) ,   kXRDC2_Periph_GPIO5 = XRDC2_MAKE_PERIPH(0, 79 ) , kXRDC2_Periph_GPIO4 = XRDC2_MAKE_PERIPH(0, 78 ) , kXRDC2_Periph_GPIO3 = XRDC2_MAKE_PERIPH(0, 77 ) , kXRDC2_Periph_GPIO2 = XRDC2_MAKE_PERIPH(0, 76 ) ,   kXRDC2_Periph_GPIO1 = XRDC2_MAKE_PERIPH(0, 75 ) , kXRDC2_Periph_LPSPI4 = XRDC2_MAKE_PERIPH(0, 72 ) , kXRDC2_Periph_LPSPI3 = XRDC2_MAKE_PERIPH(0, 71 ) , kXRDC2_Periph_LPSPI2 = XRDC2_MAKE_PERIPH(0, 70 ) ,   kXRDC2_Periph_LPSPI1 = XRDC2_MAKE_PERIPH(0, 69 ) , kXRDC2_Periph_LPI2C4 = XRDC2_MAKE_PERIPH(0, 68 ) , kXRDC2_Periph_LPI2C3 = XRDC2_MAKE_PERIPH(0, 67 ) , kXRDC2_Periph_LPI2C2 = XRDC2_MAKE_PERIPH(0, 66 ) ,   kXRDC2_Periph_LPI2C1 = XRDC2_MAKE_PERIPH(0, 65 ) , kXRDC2_Periph_GPT6 = XRDC2_MAKE_PERIPH(0, 64 ) , kXRDC2_Periph_GPT5 = XRDC2_MAKE_PERIPH(0, 63 ) , kXRDC2_Periph_GPT4 = XRDC2_MAKE_PERIPH(0, 62 ) ,   kXRDC2_Periph_GPT3 = XRDC2_MAKE_PERIPH(0, 61 ) , kXRDC2_Periph_GPT2 = XRDC2_MAKE_PERIPH(0, 60 ) , kXRDC2_Periph_GPT1 = XRDC2_MAKE_PERIPH(0, 59 ) , kXRDC2_Periph_IOMUXC = XRDC2_MAKE_PERIPH(0, 58 ) ,   kXRDC2_Periph_IOMUXC_GPR = XRDC2_MAKE_PERIPH(0, 57 ) , kXRDC2_Periph_KPP = XRDC2_MAKE_PERIPH(0, 56 ) , kXRDC2_Periph_PIT1 = XRDC2_MAKE_PERIPH(0, 54 ) , kXRDC2_Periph_SEMC = XRDC2_MAKE_PERIPH(0, 53 ) ,   kXRDC2_Periph_FLEXSPI2 = XRDC2_MAKE_PERIPH(0, 52 ) , kXRDC2_Periph_FLEXSPI1 = XRDC2_MAKE_PERIPH(0, 51 ) , kXRDC2_Periph_CAN2 = XRDC2_MAKE_PERIPH(0, 50 ) , kXRDC2_Periph_CAN1 = XRDC2_MAKE_PERIPH(0, 49 ) ,   kXRDC2_Periph_AOI2 = XRDC2_MAKE_PERIPH(0, 47 ) , kXRDC2_Periph_AOI1 = XRDC2_MAKE_PERIPH(0, 46 ) , kXRDC2_Periph_FLEXIO2 = XRDC2_MAKE_PERIPH(0, 44 ) , kXRDC2_Periph_FLEXIO1 = XRDC2_MAKE_PERIPH(0, 43 ) ,   kXRDC2_Periph_LPUART10 = XRDC2_MAKE_PERIPH(0, 40 ) , kXRDC2_Periph_LPUART9 = XRDC2_MAKE_PERIPH(0, 39 ) , kXRDC2_Periph_LPUART8 = XRDC2_MAKE_PERIPH(0, 38 ) , kXRDC2_Periph_LPUART7 = XRDC2_MAKE_PERIPH(0, 37 ) ,   kXRDC2_Periph_LPUART6 = XRDC2_MAKE_PERIPH(0, 36 ) , kXRDC2_Periph_LPUART5 = XRDC2_MAKE_PERIPH(0, 35 ) , kXRDC2_Periph_LPUART4 = XRDC2_MAKE_PERIPH(0, 34 ) , kXRDC2_Periph_LPUART3 = XRDC2_MAKE_PERIPH(0, 33 ) ,   kXRDC2_Periph_LPUART2 = XRDC2_MAKE_PERIPH(0, 32 ) , kXRDC2_Periph_LPUART1 = XRDC2_MAKE_PERIPH(0, 31 ) , kXRDC2_Periph_DMA_CH_MUX = XRDC2_MAKE_PERIPH(0, 29 ) , kXRDC2_Periph_EDMA = XRDC2_MAKE_PERIPH(0, 28 ) ,   kXRDC2_Periph_IEE = XRDC2_MAKE_PERIPH(0, 27 ) , kXRDC2_Periph_DAC = XRDC2_MAKE_PERIPH(0, 25 ) , kXRDC2_Periph_TSC_DIG = XRDC2_MAKE_PERIPH(0, 23 ) , kXRDC2_Periph_ADC2 = XRDC2_MAKE_PERIPH(0, 21 ) ,   kXRDC2_Periph_ADC1 = XRDC2_MAKE_PERIPH(0, 20 ) , kXRDC2_Periph_ADC_ETC = XRDC2_MAKE_PERIPH(0, 18 ) , kXRDC2_Periph_XBAR3 = XRDC2_MAKE_PERIPH(0, 17 ) , kXRDC2_Periph_XBAR2 = XRDC2_MAKE_PERIPH(0, 16 ) ,   kXRDC2_Periph_XBAR1 = XRDC2_MAKE_PERIPH(0, 15 ) , kXRDC2_Periph_WDOG3 = XRDC2_MAKE_PERIPH(0, 14 ) , kXRDC2_Periph_WDOG2 = XRDC2_MAKE_PERIPH(0, 13 ) , kXRDC2_Periph_WDOG1 = XRDC2_MAKE_PERIPH(0, 12 ) ,   kXRDC2_Periph_EWM = XRDC2_MAKE_PERIPH(0, 11 ) , kXRDC2_Periph_FLEXRAM = XRDC2_MAKE_PERIPH(0, 10 ) , kXRDC2_Periph_XECC_SEMC = XRDC2_MAKE_PERIPH(0, 9 ) , kXRDC2_Periph_XECC_FLEXSPI2 = XRDC2_MAKE_PERIPH(0, 8 ) ,   kXRDC2_Periph_XECC_FLEXSPI1 = XRDC2_MAKE_PERIPH(0, 7 ) , kXRDC2_Periph_MECC2 = XRDC2_MAKE_PERIPH(0, 6 ) , kXRDC2_Periph_MECC1 = XRDC2_MAKE_PERIPH(0, 5 ) , kXRDC2_Periph_MTR = XRDC2_MAKE_PERIPH(0, 4 ) ,   kXRDC2_Periph_SFA = XRDC2_MAKE_PERIPH(0, 3 ) , kXRDC2_Periph_CAAM_DEBUG_3 = XRDC2_MAKE_PERIPH(1, 51 ) , kXRDC2_Periph_CAAM_DEBUG_2 = XRDC2_MAKE_PERIPH(1, 50 ) , kXRDC2_Periph_CAAM_DEBUG_1 = XRDC2_MAKE_PERIPH(1, 49 ) ,   kXRDC2_Periph_CAAM_DEBUG_0 = XRDC2_MAKE_PERIPH(1, 48 ) , kXRDC2_Periph_CAAM_RTIC_3 = XRDC2_MAKE_PERIPH(1, 43 ) , kXRDC2_Periph_CAAM_RTIC_2 = XRDC2_MAKE_PERIPH(1, 42 ) , kXRDC2_Periph_CAAM_RTIC_1 = XRDC2_MAKE_PERIPH(1, 41 ) ,   kXRDC2_Periph_CAAM_RTIC_0 = XRDC2_MAKE_PERIPH(1, 40 ) , kXRDC2_Periph_CAAM_JR3_3 = XRDC2_MAKE_PERIPH(1, 35 ) , kXRDC2_Periph_CAAM_JR3_2 = XRDC2_MAKE_PERIPH(1, 34 ) , kXRDC2_Periph_CAAM_JR3_1 = XRDC2_MAKE_PERIPH(1, 33 ) ,   kXRDC2_Periph_CAAM_JR3_0 = XRDC2_MAKE_PERIPH(1, 32 ) , kXRDC2_Periph_CAAM_JR2_3 = XRDC2_MAKE_PERIPH(1, 31 ) , kXRDC2_Periph_CAAM_JR2_2 = XRDC2_MAKE_PERIPH(1, 30 ) , kXRDC2_Periph_CAAM_JR2_1 = XRDC2_MAKE_PERIPH(1, 29 ) ,   kXRDC2_Periph_CAAM_JR2_0 = XRDC2_MAKE_PERIPH(1, 28 ) , kXRDC2_Periph_CAAM_JR1_3 = XRDC2_MAKE_PERIPH(1, 27 ) , kXRDC2_Periph_CAAM_JR1_2 = XRDC2_MAKE_PERIPH(1, 26 ) , kXRDC2_Periph_CAAM_JR1_1 = XRDC2_MAKE_PERIPH(1, 25 ) ,   kXRDC2_Periph_CAAM_JR1_0 = XRDC2_MAKE_PERIPH(1, 24 ) , kXRDC2_Periph_CAAM_JR0_3 = XRDC2_MAKE_PERIPH(1, 23 ) , kXRDC2_Periph_CAAM_JR0_2 = XRDC2_MAKE_PERIPH(1, 22 ) , kXRDC2_Periph_CAAM_JR0_1 = XRDC2_MAKE_PERIPH(1, 21 ) ,   kXRDC2_Periph_CAAM_JR0_0 = XRDC2_MAKE_PERIPH(1, 20 ) , kXRDC2_Periph_CAAM_GENERAL_3 = XRDC2_MAKE_PERIPH(1, 19 ) , kXRDC2_Periph_CAAM_GENERAL_2 = XRDC2_MAKE_PERIPH(1, 18 ) , kXRDC2_Periph_CAAM_GENERAL_1 = XRDC2_MAKE_PERIPH(1, 17 ) ,   kXRDC2_Periph_CAAM_GENERAL_0 = XRDC2_MAKE_PERIPH(1, 16 ) , kXRDC2_Periph_ENET_QOS = XRDC2_MAKE_PERIPH(1, 15 ) , kXRDC2_Periph_USBPHY2 = XRDC2_MAKE_PERIPH(1, 14 ) , kXRDC2_Periph_USBPHY1 = XRDC2_MAKE_PERIPH(1, 13 ) ,   kXRDC2_Periph_USB_OTG = XRDC2_MAKE_PERIPH(1, 12 ) , kXRDC2_Periph_USB_OTG2 = XRDC2_MAKE_PERIPH(1, 11 ) , kXRDC2_Periph_USB_PL301 = XRDC2_MAKE_PERIPH(1, 10 ) , kXRDC2_Periph_ENET = XRDC2_MAKE_PERIPH(1, 9 ) ,   kXRDC2_Periph_ENET_1G = XRDC2_MAKE_PERIPH(1, 8 ) , kXRDC2_Periph_USDHC2 = XRDC2_MAKE_PERIPH(1, 7 ) , kXRDC2_Periph_USDHC1 = XRDC2_MAKE_PERIPH(1, 6 ) , kXRDC2_Periph_ASRC = XRDC2_MAKE_PERIPH(1, 5 ) ,   kXRDC2_Periph_SAI3 = XRDC2_MAKE_PERIPH(1, 3 ) , kXRDC2_Periph_SAI2 = XRDC2_MAKE_PERIPH(1, 2 ) , kXRDC2_Periph_SAI1 = XRDC2_MAKE_PERIPH(1, 1 ) , kXRDC2_Periph_SPDIF = XRDC2_MAKE_PERIPH(1, 0 ) ,   kXRDC2_Periph_VIDEO_MUX = XRDC2_MAKE_PERIPH(2, 6 ) , kXRDC2_Periph_PXP = XRDC2_MAKE_PERIPH(2, 5 ) , kXRDC2_Periph_MIPI_CSI = XRDC2_MAKE_PERIPH(2, 4 ) , kXRDC2_Periph_MIPI_DSI = XRDC2_MAKE_PERIPH(2, 3 ) ,   kXRDC2_Periph_LCDIFV2 = XRDC2_MAKE_PERIPH(2, 2 ) , kXRDC2_Periph_LCDIF = XRDC2_MAKE_PERIPH(2, 1 ) , kXRDC2_Periph_CSI = XRDC2_MAKE_PERIPH(2, 0 ) , kXRDC2_Periph_XRDC2_MGR_M7_3 = XRDC2_MAKE_PERIPH(3, 59 ) ,   kXRDC2_Periph_XRDC2_MGR_M7_2 = XRDC2_MAKE_PERIPH(3, 58 ) , kXRDC2_Periph_XRDC2_MGR_M7_1 = XRDC2_MAKE_PERIPH(3, 57 ) , kXRDC2_Periph_XRDC2_MGR_M7_0 = XRDC2_MAKE_PERIPH(3, 56 ) , kXRDC2_Periph_XRDC2_MGR_M4_3 = XRDC2_MAKE_PERIPH(3, 55 ) ,   kXRDC2_Periph_XRDC2_MGR_M4_2 = XRDC2_MAKE_PERIPH(3, 54 ) , kXRDC2_Periph_XRDC2_MGR_M4_1 = XRDC2_MAKE_PERIPH(3, 53 ) , kXRDC2_Periph_XRDC2_MGR_M4_0 = XRDC2_MAKE_PERIPH(3, 52 ) , kXRDC2_Periph_SEMA2 = XRDC2_MAKE_PERIPH(3, 51 ) ,   kXRDC2_Periph_SEMA_HS = XRDC2_MAKE_PERIPH(3, 50 ) , kXRDC2_Periph_CCM_1 = XRDC2_MAKE_PERIPH(3, 49 ) , kXRDC2_Periph_CCM_0 = XRDC2_MAKE_PERIPH(3, 48 ) , kXRDC2_Periph_SSARC_LP = XRDC2_MAKE_PERIPH(3, 46 ) ,   kXRDC2_Periph_SSARC_HP = XRDC2_MAKE_PERIPH(3, 45 ) , kXRDC2_Periph_PIT2 = XRDC2_MAKE_PERIPH(3, 44 ) , kXRDC2_Periph_OCOTP_CTRL_WRAPPER = XRDC2_MAKE_PERIPH(3, 43 ) , kXRDC2_Periph_DCDC = XRDC2_MAKE_PERIPH(3, 42 ) ,   kXRDC2_Periph_ROMCP = XRDC2_MAKE_PERIPH(3, 41 ) , kXRDC2_Periph_GPIO13 = XRDC2_MAKE_PERIPH(3, 40 ) , kXRDC2_Periph_SNVS_SRAM = XRDC2_MAKE_PERIPH(3, 39 ) , kXRDC2_Periph_IOMUXC_SNVS_GPR = XRDC2_MAKE_PERIPH(3, 38 ) ,   kXRDC2_Periph_IOMUXC_SNVS = XRDC2_MAKE_PERIPH(3, 37 ) , kXRDC2_Periph_SNVS_HP_WRAPPER = XRDC2_MAKE_PERIPH(3, 36 ) , kXRDC2_Periph_PGMC = XRDC2_MAKE_PERIPH(3, 34 ) , kXRDC2_Periph_ANATOP = XRDC2_MAKE_PERIPH(3, 33 ) ,   kXRDC2_Periph_KEY_MANAGER = XRDC2_MAKE_PERIPH(3, 32 ) , kXRDC2_Periph_RDC = XRDC2_MAKE_PERIPH(3, 30 ) , kXRDC2_Periph_GPIO12 = XRDC2_MAKE_PERIPH(3, 28 ) , kXRDC2_Periph_GPIO11 = XRDC2_MAKE_PERIPH(3, 27 ) ,   kXRDC2_Periph_GPIO10 = XRDC2_MAKE_PERIPH(3, 26 ) , kXRDC2_Periph_GPIO9 = XRDC2_MAKE_PERIPH(3, 25 ) , kXRDC2_Periph_GPIO8 = XRDC2_MAKE_PERIPH(3, 24 ) , kXRDC2_Periph_GPIO7 = XRDC2_MAKE_PERIPH(3, 23 ) ,   kXRDC2_Periph_MU_B = XRDC2_MAKE_PERIPH(3, 19 ) , kXRDC2_Periph_MU_A = XRDC2_MAKE_PERIPH(3, 18 ) , kXRDC2_Periph_SEMA1 = XRDC2_MAKE_PERIPH(3, 17 ) , kXRDC2_Periph_SAI4 = XRDC2_MAKE_PERIPH(3, 16 ) ,   kXRDC2_Periph_CAN3 = XRDC2_MAKE_PERIPH(3, 15 ) , kXRDC2_Periph_LPI2C6 = XRDC2_MAKE_PERIPH(3, 14 ) , kXRDC2_Periph_LPI2C5 = XRDC2_MAKE_PERIPH(3, 13 ) , kXRDC2_Periph_LPSPI6 = XRDC2_MAKE_PERIPH(3, 12 ) ,   kXRDC2_Periph_LPSPI5 = XRDC2_MAKE_PERIPH(3, 11 ) , kXRDC2_Periph_LPUART12 = XRDC2_MAKE_PERIPH(3, 10 ) , kXRDC2_Periph_LPUART11 = XRDC2_MAKE_PERIPH(3, 9 ) , kXRDC2_Periph_MIC = XRDC2_MAKE_PERIPH(3, 8 ) ,   kXRDC2_Periph_DMA_CH_MUX_LPSR = XRDC2_MAKE_PERIPH(3, 6 ) , kXRDC2_Periph_EDMA_LPSR = XRDC2_MAKE_PERIPH(3, 5 ) , kXRDC2_Periph_WDOG4 = XRDC2_MAKE_PERIPH(3, 4 ) , kXRDC2_Periph_IOMUXC_LPSR_GPR = XRDC2_MAKE_PERIPH(3, 3 ) ,   kXRDC2_Periph_IOMUXC_LPSR = XRDC2_MAKE_PERIPH(3, 2 ) , kXRDC2_Periph_SRC = XRDC2_MAKE_PERIPH(3, 1 ) , kXRDC2_Periph_GPC = XRDC2_MAKE_PERIPH(3, 0 ) , kXRDC2_Periph_GPU = XRDC2_MAKE_PERIPH(4, 0 ) }
enum	_asrc_clock_source {   kASRC_ClockSourceNotAvalible = -1U , kASRC_ClockSourceBitClock0_SAI1_TX = 0U , kASRC_ClockSourceBitClock1_SAI1_RX = 1U , kASRC_ClockSourceBitClock2_SAI2_TX = 2U ,   kASRC_ClockSourceBitClock3_SAI2_RX = 3U , kASRC_ClockSourceBitClock4_SAI3_TX = 4U , kASRC_ClockSourceBitClock5_SAI3_RX = 5U , kASRC_ClockSourceBitClock6_SAI4_TX = 6U ,   kASRC_ClockSourceBitClock7_SAI4_RX = 7U , kASRC_ClockSourceBitClock8_SPDIF_TX = 8U , kASRC_ClockSourceBitClock9_SPDIF_RX = 9U , kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U ,   kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U , kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U , kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U , kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U }
	The ASRC clock source. More...
enum	_iomuxc_sw_mux_ctl_pad {   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U ,   kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U }
	Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
enum	_iomuxc_sw_pad_ctl_pad {   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U ,   kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U }
	Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
enum	_iomuxc_select_input {   kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U , kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U ,   kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U , kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U , kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U ,   kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U , kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U , kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U ,   kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U , kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U , kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U ,   kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U , kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U ,   kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U ,   kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U ,   kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U ,   kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U ,   kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U , kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U ,   kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U ,   kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U ,   kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U ,   kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U , kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U , kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U ,   kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U , kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U , kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U ,   kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U , kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U , kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U ,   kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U , kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U , kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U ,   kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U , kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U , kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U ,   kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U ,   kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U , kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U ,   kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U , kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U ,   kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U , kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U , kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U ,   kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U , kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U , kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U ,   kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U , kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U , kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U ,   kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U , kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U , kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U ,   kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U , kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U , kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U ,   kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U , kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U , kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U ,   kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U , kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U , kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U ,   kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U , kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U , kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U ,   kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U , kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U , kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U ,   kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U , kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U ,   kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U , kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U , kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U ,   kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U , kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U , kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U ,   kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U , kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U , kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U ,   kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U , kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U , kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U ,   kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U , kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U , kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U ,   kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U , kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U }
	Enumeration for the IOMUXC select input. More...

Detailed Description

CMSIS Peripheral Access Layer for MIMXRT1166_cm4.

Version

0.1

Date

2020-12-29

CMSIS Peripheral Access Layer for MIMXRT1166_cm4

Macro Definition Documentation

_MIMXRT1166_CM4_H_

#define _MIMXRT1166_CM4_H_

Symbol preventing repeated inclusion

MCU_MEM_MAP_VERSION

#define MCU_MEM_MAP_VERSION   0x0000U

Memory map major version (memory maps with equal major version number are compatible)

MCU_MEM_MAP_VERSION_MINOR

#define MCU_MEM_MAP_VERSION_MINOR   0x0001U

Memory map minor version

XRDC2_GET_MRC

#define XRDC2_GET_MRC

(

mem

)

Value:

((mem) >> 5U)

XRDC2_GET_MRGD

#define XRDC2_GET_MRGD

(

mem

)

Value:

((mem) & 31U)

XRDC2_GET_PAC

#define XRDC2_GET_PAC

(

periph

)

Value:

((periph) >> 8U)

XRDC2_GET_PDAC

#define XRDC2_GET_PDAC

(

periph

)

Value:

((periph) & 255U)

XRDC2_MAKE_MEM

#define XRDC2_MAKE_MEM	(		mrc,
			mrgd )

Value:

(((mrc) << 5U) | (mrgd))

XRDC2_MAKE_PERIPH

#define XRDC2_MAKE_PERIPH	(		pac,
			pdac )

Value:

(((pac) << 8U) | (pdac))