 |
RTEMS 6.3
|
|
RTEMS 6.3
|
Macros | |
| #define | FLEXIO_SHIFTCTL_COUNT (4U) |
| #define | FLEXIO_SHIFTCFG_COUNT (4U) |
| #define | FLEXIO_SHIFTBUF_COUNT (4U) |
| #define | FLEXIO_SHIFTBUFBIS_COUNT (4U) |
| #define | FLEXIO_SHIFTBUFBYS_COUNT (4U) |
| #define | FLEXIO_SHIFTBUFBBS_COUNT (4U) |
| #define | FLEXIO_TIMCTL_COUNT (4U) |
| #define | FLEXIO_TIMCFG_COUNT (4U) |
| #define | FLEXIO_TIMCMP_COUNT (4U) |
| #define | FLEXIO_SHIFTBUFNBS_COUNT (4U) |
| #define | FLEXIO_SHIFTBUFHWS_COUNT (4U) |
| #define | FLEXIO_SHIFTBUFNIS_COUNT (4U) |
| #define | FLEXIO_SHIFTCTL_COUNT (8U) |
| #define | FLEXIO_SHIFTCFG_COUNT (8U) |
| #define | FLEXIO_SHIFTBUF_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFBIS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFBYS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFBBS_COUNT (8U) |
| #define | FLEXIO_TIMCTL_COUNT (8U) |
| #define | FLEXIO_TIMCFG_COUNT (8U) |
| #define | FLEXIO_TIMCMP_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFNBS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFHWS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFNIS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFOES_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFEOS_COUNT (8U) |
| #define | FLEXIO_SHIFTCTL_COUNT (8U) |
| #define | FLEXIO_SHIFTCFG_COUNT (8U) |
| #define | FLEXIO_SHIFTBUF_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFBIS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFBYS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFBBS_COUNT (8U) |
| #define | FLEXIO_TIMCTL_COUNT (8U) |
| #define | FLEXIO_TIMCFG_COUNT (8U) |
| #define | FLEXIO_TIMCMP_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFNBS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFHWS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFNIS_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFOES_COUNT (8U) |
| #define | FLEXIO_SHIFTBUFEOS_COUNT (8U) |
| #define | LPUART_VERID_FEATURE_MASK (0xFFFFU) |
| #define | LPUART_VERID_FEATURE_SHIFT (0U) |
| #define | LPUART_VERID_FEATURE(x) |
| #define | LPUART_VERID_MINOR_MASK (0xFF0000U) |
| #define | LPUART_VERID_MINOR_SHIFT (16U) |
| #define | LPUART_VERID_MINOR(x) |
| #define | LPUART_VERID_MAJOR_MASK (0xFF000000U) |
| #define | LPUART_VERID_MAJOR_SHIFT (24U) |
| #define | LPUART_VERID_MAJOR(x) |
| #define | LPUART_PARAM_TXFIFO_MASK (0xFFU) |
| #define | LPUART_PARAM_TXFIFO_SHIFT (0U) |
| #define | LPUART_PARAM_TXFIFO(x) |
| #define | LPUART_PARAM_RXFIFO_MASK (0xFF00U) |
| #define | LPUART_PARAM_RXFIFO_SHIFT (8U) |
| #define | LPUART_PARAM_RXFIFO(x) |
| #define | LPUART_VERID_FEATURE_MASK (0xFFFFU) |
| #define | LPUART_VERID_FEATURE_SHIFT (0U) |
| #define | LPUART_VERID_FEATURE(x) |
| #define | LPUART_VERID_MINOR_MASK (0xFF0000U) |
| #define | LPUART_VERID_MINOR_SHIFT (16U) |
| #define | LPUART_VERID_MINOR(x) |
| #define | LPUART_VERID_MAJOR_MASK (0xFF000000U) |
| #define | LPUART_VERID_MAJOR_SHIFT (24U) |
| #define | LPUART_VERID_MAJOR(x) |
| #define | LPUART_PARAM_TXFIFO_MASK (0xFFU) |
| #define | LPUART_PARAM_TXFIFO_SHIFT (0U) |
| #define | LPUART_PARAM_TXFIFO(x) |
| #define | LPUART_PARAM_RXFIFO_MASK (0xFF00U) |
| #define | LPUART_PARAM_RXFIFO_SHIFT (8U) |
| #define | LPUART_PARAM_RXFIFO(x) |
VERID - Version ID Register | |
| #define | FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
| #define | FLEXIO_VERID_FEATURE_SHIFT (0U) |
| #define | FLEXIO_VERID_FEATURE(x) |
| #define | FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
| #define | FLEXIO_VERID_MINOR_SHIFT (16U) |
| #define | FLEXIO_VERID_MINOR(x) |
| #define | FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
| #define | FLEXIO_VERID_MAJOR_SHIFT (24U) |
| #define | FLEXIO_VERID_MAJOR(x) |
| #define | FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
| #define | FLEXIO_VERID_FEATURE_SHIFT (0U) |
| #define | FLEXIO_VERID_FEATURE(x) |
| #define | FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
| #define | FLEXIO_VERID_MINOR_SHIFT (16U) |
| #define | FLEXIO_VERID_MINOR(x) |
| #define | FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
| #define | FLEXIO_VERID_MAJOR_SHIFT (24U) |
| #define | FLEXIO_VERID_MAJOR(x) |
| #define | FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
| #define | FLEXIO_VERID_FEATURE_SHIFT (0U) |
| #define | FLEXIO_VERID_FEATURE(x) |
| #define | FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
| #define | FLEXIO_VERID_MINOR_SHIFT (16U) |
| #define | FLEXIO_VERID_MINOR(x) |
| #define | FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
| #define | FLEXIO_VERID_MAJOR_SHIFT (24U) |
| #define | FLEXIO_VERID_MAJOR(x) |
| #define | LPUART_VERID_FEATURE_MASK (0xFFFFU) |
| #define | LPUART_VERID_FEATURE_SHIFT (0U) |
| #define | LPUART_VERID_FEATURE(x) |
| #define | LPUART_VERID_MINOR_MASK (0xFF0000U) |
| #define | LPUART_VERID_MINOR_SHIFT (16U) |
| #define | LPUART_VERID_MINOR(x) |
| #define | LPUART_VERID_MAJOR_MASK (0xFF000000U) |
| #define | LPUART_VERID_MAJOR_SHIFT (24U) |
| #define | LPUART_VERID_MAJOR(x) |
PARAM - Parameter Register | |
| #define | FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
| #define | FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
| #define | FLEXIO_PARAM_SHIFTER(x) |
| #define | FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
| #define | FLEXIO_PARAM_TIMER_SHIFT (8U) |
| #define | FLEXIO_PARAM_TIMER(x) |
| #define | FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
| #define | FLEXIO_PARAM_PIN_SHIFT (16U) |
| #define | FLEXIO_PARAM_PIN(x) |
| #define | FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
| #define | FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
| #define | FLEXIO_PARAM_TRIGGER(x) |
| #define | FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
| #define | FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
| #define | FLEXIO_PARAM_SHIFTER(x) |
| #define | FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
| #define | FLEXIO_PARAM_TIMER_SHIFT (8U) |
| #define | FLEXIO_PARAM_TIMER(x) |
| #define | FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
| #define | FLEXIO_PARAM_PIN_SHIFT (16U) |
| #define | FLEXIO_PARAM_PIN(x) |
| #define | FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
| #define | FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
| #define | FLEXIO_PARAM_TRIGGER(x) |
| #define | FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
| #define | FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
| #define | FLEXIO_PARAM_SHIFTER(x) |
| #define | FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
| #define | FLEXIO_PARAM_TIMER_SHIFT (8U) |
| #define | FLEXIO_PARAM_TIMER(x) |
| #define | FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
| #define | FLEXIO_PARAM_PIN_SHIFT (16U) |
| #define | FLEXIO_PARAM_PIN(x) |
| #define | FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
| #define | FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
| #define | FLEXIO_PARAM_TRIGGER(x) |
| #define | LPUART_PARAM_TXFIFO_MASK (0xFFU) |
| #define | LPUART_PARAM_TXFIFO_SHIFT (0U) |
| #define | LPUART_PARAM_TXFIFO(x) |
| #define | LPUART_PARAM_RXFIFO_MASK (0xFF00U) |
| #define | LPUART_PARAM_RXFIFO_SHIFT (8U) |
| #define | LPUART_PARAM_RXFIFO(x) |
CTRL - FlexIO Control Register | |
| #define | FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
| #define | FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
| #define | FLEXIO_CTRL_FLEXEN(x) |
| #define | FLEXIO_CTRL_SWRST_MASK (0x2U) |
| #define | FLEXIO_CTRL_SWRST_SHIFT (1U) |
| #define | FLEXIO_CTRL_SWRST(x) |
| #define | FLEXIO_CTRL_FASTACC_MASK (0x4U) |
| #define | FLEXIO_CTRL_FASTACC_SHIFT (2U) |
| #define | FLEXIO_CTRL_FASTACC(x) |
| #define | FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
| #define | FLEXIO_CTRL_DBGE_SHIFT (30U) |
| #define | FLEXIO_CTRL_DBGE(x) |
| #define | FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
| #define | FLEXIO_CTRL_DOZEN_SHIFT (31U) |
| #define | FLEXIO_CTRL_DOZEN(x) |
| #define | FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
| #define | FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
| #define | FLEXIO_CTRL_FLEXEN(x) |
| #define | FLEXIO_CTRL_SWRST_MASK (0x2U) |
| #define | FLEXIO_CTRL_SWRST_SHIFT (1U) |
| #define | FLEXIO_CTRL_SWRST(x) |
| #define | FLEXIO_CTRL_FASTACC_MASK (0x4U) |
| #define | FLEXIO_CTRL_FASTACC_SHIFT (2U) |
| #define | FLEXIO_CTRL_FASTACC(x) |
| #define | FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
| #define | FLEXIO_CTRL_DBGE_SHIFT (30U) |
| #define | FLEXIO_CTRL_DBGE(x) |
| #define | FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
| #define | FLEXIO_CTRL_DOZEN_SHIFT (31U) |
| #define | FLEXIO_CTRL_DOZEN(x) |
| #define | FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
| #define | FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
| #define | FLEXIO_CTRL_FLEXEN(x) |
| #define | FLEXIO_CTRL_SWRST_MASK (0x2U) |
| #define | FLEXIO_CTRL_SWRST_SHIFT (1U) |
| #define | FLEXIO_CTRL_SWRST(x) |
| #define | FLEXIO_CTRL_FASTACC_MASK (0x4U) |
| #define | FLEXIO_CTRL_FASTACC_SHIFT (2U) |
| #define | FLEXIO_CTRL_FASTACC(x) |
| #define | FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
| #define | FLEXIO_CTRL_DBGE_SHIFT (30U) |
| #define | FLEXIO_CTRL_DBGE(x) |
| #define | FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
| #define | FLEXIO_CTRL_DOZEN_SHIFT (31U) |
| #define | FLEXIO_CTRL_DOZEN(x) |
PIN - Pin State Register | |
| #define | FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_PIN_PDI_SHIFT (0U) |
| #define | FLEXIO_PIN_PDI(x) |
| #define | FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_PIN_PDI_SHIFT (0U) |
| #define | FLEXIO_PIN_PDI(x) |
| #define | FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_PIN_PDI_SHIFT (0U) |
| #define | FLEXIO_PIN_PDI(x) |
SHIFTSTAT - Shifter Status Register | |
| #define | FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) |
| #define | FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
| #define | FLEXIO_SHIFTSTAT_SSF(x) |
| #define | FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) |
| #define | FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
| #define | FLEXIO_SHIFTSTAT_SSF(x) |
| #define | FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) |
| #define | FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
| #define | FLEXIO_SHIFTSTAT_SSF(x) |
SHIFTERR - Shifter Error Register | |
| #define | FLEXIO_SHIFTERR_SEF_MASK (0xFU) |
| #define | FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
| #define | FLEXIO_SHIFTERR_SEF(x) |
| #define | FLEXIO_SHIFTERR_SEF_MASK (0xFFU) |
| #define | FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
| #define | FLEXIO_SHIFTERR_SEF(x) |
| #define | FLEXIO_SHIFTERR_SEF_MASK (0xFFU) |
| #define | FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
| #define | FLEXIO_SHIFTERR_SEF(x) |
TIMSTAT - Timer Status Register | |
| #define | FLEXIO_TIMSTAT_TSF_MASK (0xFU) |
| #define | FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
| #define | FLEXIO_TIMSTAT_TSF(x) |
| #define | FLEXIO_TIMSTAT_TSF_MASK (0xFFU) |
| #define | FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
| #define | FLEXIO_TIMSTAT_TSF(x) |
| #define | FLEXIO_TIMSTAT_TSF_MASK (0xFFU) |
| #define | FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
| #define | FLEXIO_TIMSTAT_TSF(x) |
SHIFTSIEN - Shifter Status Interrupt Enable | |
| #define | FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) |
| #define | FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSIEN_SSIE(x) |
| #define | FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) |
| #define | FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSIEN_SSIE(x) |
| #define | FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) |
| #define | FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSIEN_SSIE(x) |
SHIFTEIEN - Shifter Error Interrupt Enable | |
| #define | FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) |
| #define | FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
| #define | FLEXIO_SHIFTEIEN_SEIE(x) |
| #define | FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) |
| #define | FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
| #define | FLEXIO_SHIFTEIEN_SEIE(x) |
| #define | FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) |
| #define | FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
| #define | FLEXIO_SHIFTEIEN_SEIE(x) |
TIMIEN - Timer Interrupt Enable Register | |
| #define | FLEXIO_TIMIEN_TEIE_MASK (0xFU) |
| #define | FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
| #define | FLEXIO_TIMIEN_TEIE(x) |
| #define | FLEXIO_TIMIEN_TEIE_MASK (0xFFU) |
| #define | FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
| #define | FLEXIO_TIMIEN_TEIE(x) |
| #define | FLEXIO_TIMIEN_TEIE_MASK (0xFFU) |
| #define | FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
| #define | FLEXIO_TIMIEN_TEIE(x) |
SHIFTSDEN - Shifter Status DMA Enable | |
| #define | FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) |
| #define | FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSDEN_SSDE(x) |
| #define | FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) |
| #define | FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSDEN_SSDE(x) |
| #define | FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) |
| #define | FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSDEN_SSDE(x) |
SHIFTSTATE - Shifter State Register | |
| #define | FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) |
| #define | FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSTATE_STATE(x) |
| #define | FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) |
| #define | FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSTATE_STATE(x) |
| #define | FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) |
| #define | FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) |
| #define | FLEXIO_SHIFTSTATE_STATE(x) |
SHIFTCTL - Shifter Control N Register | |
| #define | FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
| #define | FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
| #define | FLEXIO_SHIFTCTL_SMOD(x) |
| #define | FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
| #define | FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
| #define | FLEXIO_SHIFTCTL_PINPOL(x) |
| #define | FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) |
| #define | FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
| #define | FLEXIO_SHIFTCTL_PINSEL(x) |
| #define | FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
| #define | FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
| #define | FLEXIO_SHIFTCTL_PINCFG(x) |
| #define | FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
| #define | FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
| #define | FLEXIO_SHIFTCTL_TIMPOL(x) |
| #define | FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) |
| #define | FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
| #define | FLEXIO_SHIFTCTL_TIMSEL(x) |
| #define | FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
| #define | FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
| #define | FLEXIO_SHIFTCTL_SMOD(x) |
| #define | FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
| #define | FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
| #define | FLEXIO_SHIFTCTL_PINPOL(x) |
| #define | FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) |
| #define | FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
| #define | FLEXIO_SHIFTCTL_PINSEL(x) |
| #define | FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
| #define | FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
| #define | FLEXIO_SHIFTCTL_PINCFG(x) |
| #define | FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
| #define | FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
| #define | FLEXIO_SHIFTCTL_TIMPOL(x) |
| #define | FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) |
| #define | FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
| #define | FLEXIO_SHIFTCTL_TIMSEL(x) |
| #define | FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
| #define | FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
| #define | FLEXIO_SHIFTCTL_SMOD(x) |
| #define | FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
| #define | FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
| #define | FLEXIO_SHIFTCTL_PINPOL(x) |
| #define | FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) |
| #define | FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
| #define | FLEXIO_SHIFTCTL_PINSEL(x) |
| #define | FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
| #define | FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
| #define | FLEXIO_SHIFTCTL_PINCFG(x) |
| #define | FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
| #define | FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
| #define | FLEXIO_SHIFTCTL_TIMPOL(x) |
| #define | FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) |
| #define | FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
| #define | FLEXIO_SHIFTCTL_TIMSEL(x) |
SHIFTCFG - Shifter Configuration N Register | |
| #define | FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
| #define | FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
| #define | FLEXIO_SHIFTCFG_SSTART(x) |
| #define | FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
| #define | FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
| #define | FLEXIO_SHIFTCFG_SSTOP(x) |
| #define | FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
| #define | FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
| #define | FLEXIO_SHIFTCFG_INSRC(x) |
| #define | FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) |
| #define | FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) |
| #define | FLEXIO_SHIFTCFG_PWIDTH(x) |
| #define | FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
| #define | FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
| #define | FLEXIO_SHIFTCFG_SSTART(x) |
| #define | FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
| #define | FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
| #define | FLEXIO_SHIFTCFG_SSTOP(x) |
| #define | FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
| #define | FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
| #define | FLEXIO_SHIFTCFG_INSRC(x) |
| #define | FLEXIO_SHIFTCFG_LATST_MASK (0x200U) |
| #define | FLEXIO_SHIFTCFG_LATST_SHIFT (9U) |
| #define | FLEXIO_SHIFTCFG_LATST(x) |
| #define | FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) |
| #define | FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) |
| #define | FLEXIO_SHIFTCFG_PWIDTH(x) |
| #define | FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
| #define | FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
| #define | FLEXIO_SHIFTCFG_SSTART(x) |
| #define | FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
| #define | FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
| #define | FLEXIO_SHIFTCFG_SSTOP(x) |
| #define | FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
| #define | FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
| #define | FLEXIO_SHIFTCFG_INSRC(x) |
| #define | FLEXIO_SHIFTCFG_LATST_MASK (0x200U) |
| #define | FLEXIO_SHIFTCFG_LATST_SHIFT (9U) |
| #define | FLEXIO_SHIFTCFG_LATST(x) |
| #define | FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) |
| #define | FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) |
| #define | FLEXIO_SHIFTCFG_PWIDTH(x) |
SHIFTBUF - Shifter Buffer N Register | |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF(x) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF(x) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUF_SHIFTBUF(x) |
SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register | |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) |
SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register | |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) |
SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register | |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) |
TIMCTL - Timer Control N Register | |
| #define | FLEXIO_TIMCTL_TIMOD_MASK (0x3U) |
| #define | FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
| #define | FLEXIO_TIMCTL_TIMOD(x) |
| #define | FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
| #define | FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
| #define | FLEXIO_TIMCTL_PINPOL(x) |
| #define | FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) |
| #define | FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
| #define | FLEXIO_TIMCTL_PINSEL(x) |
| #define | FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
| #define | FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
| #define | FLEXIO_TIMCTL_PINCFG(x) |
| #define | FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
| #define | FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
| #define | FLEXIO_TIMCTL_TRGSRC(x) |
| #define | FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
| #define | FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
| #define | FLEXIO_TIMCTL_TRGPOL(x) |
| #define | FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) |
| #define | FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
| #define | FLEXIO_TIMCTL_TRGSEL(x) |
| #define | FLEXIO_TIMCTL_TIMOD_MASK (0x7U) |
| #define | FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
| #define | FLEXIO_TIMCTL_TIMOD(x) |
| #define | FLEXIO_TIMCTL_ONETIM_MASK (0x20U) |
| #define | FLEXIO_TIMCTL_ONETIM_SHIFT (5U) |
| #define | FLEXIO_TIMCTL_ONETIM(x) |
| #define | FLEXIO_TIMCTL_PININS_MASK (0x40U) |
| #define | FLEXIO_TIMCTL_PININS_SHIFT (6U) |
| #define | FLEXIO_TIMCTL_PININS(x) |
| #define | FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
| #define | FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
| #define | FLEXIO_TIMCTL_PINPOL(x) |
| #define | FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) |
| #define | FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
| #define | FLEXIO_TIMCTL_PINSEL(x) |
| #define | FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
| #define | FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
| #define | FLEXIO_TIMCTL_PINCFG(x) |
| #define | FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
| #define | FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
| #define | FLEXIO_TIMCTL_TRGSRC(x) |
| #define | FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
| #define | FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
| #define | FLEXIO_TIMCTL_TRGPOL(x) |
| #define | FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) |
| #define | FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
| #define | FLEXIO_TIMCTL_TRGSEL(x) |
| #define | FLEXIO_TIMCTL_TIMOD_MASK (0x7U) |
| #define | FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
| #define | FLEXIO_TIMCTL_TIMOD(x) |
| #define | FLEXIO_TIMCTL_ONETIM_MASK (0x20U) |
| #define | FLEXIO_TIMCTL_ONETIM_SHIFT (5U) |
| #define | FLEXIO_TIMCTL_ONETIM(x) |
| #define | FLEXIO_TIMCTL_PININS_MASK (0x40U) |
| #define | FLEXIO_TIMCTL_PININS_SHIFT (6U) |
| #define | FLEXIO_TIMCTL_PININS(x) |
| #define | FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
| #define | FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
| #define | FLEXIO_TIMCTL_PINPOL(x) |
| #define | FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) |
| #define | FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
| #define | FLEXIO_TIMCTL_PINSEL(x) |
| #define | FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
| #define | FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
| #define | FLEXIO_TIMCTL_PINCFG(x) |
| #define | FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
| #define | FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
| #define | FLEXIO_TIMCTL_TRGSRC(x) |
| #define | FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
| #define | FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
| #define | FLEXIO_TIMCTL_TRGPOL(x) |
| #define | FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) |
| #define | FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
| #define | FLEXIO_TIMCTL_TRGSEL(x) |
TIMCFG - Timer Configuration N Register | |
| #define | FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
| #define | FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
| #define | FLEXIO_TIMCFG_TSTART(x) |
| #define | FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
| #define | FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
| #define | FLEXIO_TIMCFG_TSTOP(x) |
| #define | FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
| #define | FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
| #define | FLEXIO_TIMCFG_TIMENA(x) |
| #define | FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
| #define | FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
| #define | FLEXIO_TIMCFG_TIMDIS(x) |
| #define | FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
| #define | FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
| #define | FLEXIO_TIMCFG_TIMRST(x) |
| #define | FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) |
| #define | FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
| #define | FLEXIO_TIMCFG_TIMDEC(x) |
| #define | FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
| #define | FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
| #define | FLEXIO_TIMCFG_TIMOUT(x) |
| #define | FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
| #define | FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
| #define | FLEXIO_TIMCFG_TSTART(x) |
| #define | FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
| #define | FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
| #define | FLEXIO_TIMCFG_TSTOP(x) |
| #define | FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
| #define | FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
| #define | FLEXIO_TIMCFG_TIMENA(x) |
| #define | FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
| #define | FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
| #define | FLEXIO_TIMCFG_TIMDIS(x) |
| #define | FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
| #define | FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
| #define | FLEXIO_TIMCFG_TIMRST(x) |
| #define | FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) |
| #define | FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
| #define | FLEXIO_TIMCFG_TIMDEC(x) |
| #define | FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
| #define | FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
| #define | FLEXIO_TIMCFG_TIMOUT(x) |
| #define | FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
| #define | FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
| #define | FLEXIO_TIMCFG_TSTART(x) |
| #define | FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
| #define | FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
| #define | FLEXIO_TIMCFG_TSTOP(x) |
| #define | FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
| #define | FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
| #define | FLEXIO_TIMCFG_TIMENA(x) |
| #define | FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
| #define | FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
| #define | FLEXIO_TIMCFG_TIMDIS(x) |
| #define | FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
| #define | FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
| #define | FLEXIO_TIMCFG_TIMRST(x) |
| #define | FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) |
| #define | FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
| #define | FLEXIO_TIMCFG_TIMDEC(x) |
| #define | FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
| #define | FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
| #define | FLEXIO_TIMCFG_TIMOUT(x) |
TIMCMP - Timer Compare N Register | |
| #define | FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
| #define | FLEXIO_TIMCMP_CMP_SHIFT (0U) |
| #define | FLEXIO_TIMCMP_CMP(x) |
| #define | FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
| #define | FLEXIO_TIMCMP_CMP_SHIFT (0U) |
| #define | FLEXIO_TIMCMP_CMP(x) |
| #define | FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
| #define | FLEXIO_TIMCMP_CMP_SHIFT (0U) |
| #define | FLEXIO_TIMCMP_CMP(x) |
SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register | |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) |
SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register | |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) |
SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register | |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) |
TIMERSDEN - Timer Status DMA Enable | |
| #define | FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) |
| #define | FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) |
| #define | FLEXIO_TIMERSDEN_TSDE(x) |
| #define | FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) |
| #define | FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) |
| #define | FLEXIO_TIMERSDEN_TSDE(x) |
SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register | |
| #define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) |
| #define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) |
SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register | |
| #define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) |
| #define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) |
| #define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) |
| #define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) |
| #define FLEXIO_CTRL_DBGE | ( | x | ) |
DBGE - Debug Enable 0b0..FlexIO is disabled in debug modes. 0b1..FlexIO is enabled in debug modes
| #define FLEXIO_CTRL_DBGE | ( | x | ) |
DBGE - Debug Enable 0b0..FlexIO is disabled in debug modes. 0b1..FlexIO is enabled in debug modes
| #define FLEXIO_CTRL_DBGE | ( | x | ) |
DBGE - Debug Enable 0b0..FlexIO is disabled in debug modes. 0b1..FlexIO is enabled in debug modes
| #define FLEXIO_CTRL_DOZEN | ( | x | ) |
DOZEN - Doze Enable 0b0..FlexIO enabled in Doze modes. 0b1..FlexIO disabled in Doze modes.
| #define FLEXIO_CTRL_DOZEN | ( | x | ) |
DOZEN - Doze Enable 0b0..FlexIO enabled in Doze modes. 0b1..FlexIO disabled in Doze modes.
| #define FLEXIO_CTRL_DOZEN | ( | x | ) |
DOZEN - Doze Enable 0b0..FlexIO enabled in Doze modes. 0b1..FlexIO disabled in Doze modes.
| #define FLEXIO_CTRL_FASTACC | ( | x | ) |
FASTACC - Fast Access 0b0..Configures for normal register accesses to FlexIO 0b1..Configures for fast register accesses to FlexIO
| #define FLEXIO_CTRL_FASTACC | ( | x | ) |
FASTACC - Fast Access 0b0..Configures for normal register accesses to FlexIO 0b1..Configures for fast register accesses to FlexIO
| #define FLEXIO_CTRL_FASTACC | ( | x | ) |
FASTACC - Fast Access 0b0..Configures for normal register accesses to FlexIO 0b1..Configures for fast register accesses to FlexIO
| #define FLEXIO_CTRL_FLEXEN | ( | x | ) |
FLEXEN - FlexIO Enable 0b0..FlexIO module is disabled. 0b1..FlexIO module is enabled.
| #define FLEXIO_CTRL_FLEXEN | ( | x | ) |
FLEXEN - FlexIO Enable 0b0..FlexIO module is disabled. 0b1..FlexIO module is enabled.
| #define FLEXIO_CTRL_FLEXEN | ( | x | ) |
FLEXEN - FlexIO Enable 0b0..FlexIO module is disabled. 0b1..FlexIO module is enabled.
| #define FLEXIO_CTRL_SWRST | ( | x | ) |
SWRST - Software Reset 0b0..Software reset is disabled 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
| #define FLEXIO_CTRL_SWRST | ( | x | ) |
SWRST - Software Reset 0b0..Software reset is disabled 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
| #define FLEXIO_CTRL_SWRST | ( | x | ) |
SWRST - Software Reset 0b0..Software reset is disabled 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
| #define FLEXIO_PARAM_PIN | ( | x | ) |
PIN - Pin Number
| #define FLEXIO_PARAM_PIN | ( | x | ) |
PIN - Pin Number
| #define FLEXIO_PARAM_PIN | ( | x | ) |
PIN - Pin Number
| #define FLEXIO_PARAM_SHIFTER | ( | x | ) |
SHIFTER - Shifter Number
| #define FLEXIO_PARAM_SHIFTER | ( | x | ) |
SHIFTER - Shifter Number
| #define FLEXIO_PARAM_SHIFTER | ( | x | ) |
SHIFTER - Shifter Number
| #define FLEXIO_PARAM_TIMER | ( | x | ) |
TIMER - Timer Number
| #define FLEXIO_PARAM_TIMER | ( | x | ) |
TIMER - Timer Number
| #define FLEXIO_PARAM_TIMER | ( | x | ) |
TIMER - Timer Number
| #define FLEXIO_PARAM_TRIGGER | ( | x | ) |
TRIGGER - Trigger Number
| #define FLEXIO_PARAM_TRIGGER | ( | x | ) |
TRIGGER - Trigger Number
| #define FLEXIO_PARAM_TRIGGER | ( | x | ) |
TRIGGER - Trigger Number
| #define FLEXIO_PIN_PDI | ( | x | ) |
PDI - Pin Data Input
| #define FLEXIO_PIN_PDI | ( | x | ) |
PDI - Pin Data Input
| #define FLEXIO_PIN_PDI | ( | x | ) |
PDI - Pin Data Input
| #define FLEXIO_SHIFTBUF_SHIFTBUF | ( | x | ) |
SHIFTBUF - Shift Buffer
| #define FLEXIO_SHIFTBUF_SHIFTBUF | ( | x | ) |
SHIFTBUF - Shift Buffer
| #define FLEXIO_SHIFTBUF_SHIFTBUF | ( | x | ) |
SHIFTBUF - Shift Buffer
| #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS | ( | x | ) |
SHIFTBUFBBS - Shift Buffer
| #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS | ( | x | ) |
SHIFTBUFBBS - Shift Buffer
| #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS | ( | x | ) |
SHIFTBUFBBS - Shift Buffer
| #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS | ( | x | ) |
SHIFTBUFBIS - Shift Buffer
| #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS | ( | x | ) |
SHIFTBUFBIS - Shift Buffer
| #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS | ( | x | ) |
SHIFTBUFBIS - Shift Buffer
| #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS | ( | x | ) |
SHIFTBUFBYS - Shift Buffer
| #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS | ( | x | ) |
SHIFTBUFBYS - Shift Buffer
| #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS | ( | x | ) |
SHIFTBUFBYS - Shift Buffer
| #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS | ( | x | ) |
SHIFTBUFEOS - Shift Buffer
| #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS | ( | x | ) |
SHIFTBUFEOS - Shift Buffer
| #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS | ( | x | ) |
SHIFTBUFHWS - Shift Buffer
| #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS | ( | x | ) |
SHIFTBUFHWS - Shift Buffer
| #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS | ( | x | ) |
SHIFTBUFHWS - Shift Buffer
| #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS | ( | x | ) |
SHIFTBUFNBS - Shift Buffer
| #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS | ( | x | ) |
SHIFTBUFNBS - Shift Buffer
| #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS | ( | x | ) |
SHIFTBUFNBS - Shift Buffer
| #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS | ( | x | ) |
SHIFTBUFNIS - Shift Buffer
| #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS | ( | x | ) |
SHIFTBUFNIS - Shift Buffer
| #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS | ( | x | ) |
SHIFTBUFNIS - Shift Buffer
| #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES | ( | x | ) |
SHIFTBUFOES - Shift Buffer
| #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES | ( | x | ) |
SHIFTBUFOES - Shift Buffer
| #define FLEXIO_SHIFTCFG_INSRC | ( | x | ) |
INSRC - Input Source 0b0..Pin 0b1..Shifter N+1 Output
| #define FLEXIO_SHIFTCFG_INSRC | ( | x | ) |
INSRC - Input Source 0b0..Pin 0b1..Shifter N+1 Output
| #define FLEXIO_SHIFTCFG_INSRC | ( | x | ) |
INSRC - Input Source 0b0..Pin 0b1..Shifter N+1 Output
| #define FLEXIO_SHIFTCFG_LATST | ( | x | ) |
LATST - Late Store 0b0..Shift register stores the pre-shift register state. 0b1..Shift register stores the post-shift register state.
| #define FLEXIO_SHIFTCFG_LATST | ( | x | ) |
LATST - Late Store 0b0..Shift register stores the pre-shift register state. 0b1..Shift register stores the post-shift register state.
| #define FLEXIO_SHIFTCFG_PWIDTH | ( | x | ) |
PWIDTH - Parallel Width
| #define FLEXIO_SHIFTCFG_PWIDTH | ( | x | ) |
PWIDTH - Parallel Width
| #define FLEXIO_SHIFTCFG_PWIDTH | ( | x | ) |
PWIDTH - Parallel Width
| #define FLEXIO_SHIFTCFG_SSTART | ( | x | ) |
SSTART - Shifter Start bit 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
| #define FLEXIO_SHIFTCFG_SSTART | ( | x | ) |
SSTART - Shifter Start bit 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
| #define FLEXIO_SHIFTCFG_SSTART | ( | x | ) |
SSTART - Shifter Start bit 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
| #define FLEXIO_SHIFTCFG_SSTOP | ( | x | ) |
SSTOP - Shifter Stop bit 0b00..Stop bit disabled for transmitter/receiver/match store 0b01..Reserved for transmitter/receiver/match store 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
| #define FLEXIO_SHIFTCFG_SSTOP | ( | x | ) |
SSTOP - Shifter Stop bit 0b00..Stop bit disabled for transmitter/receiver/match store 0b01..Reserved for transmitter/receiver/match store 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
| #define FLEXIO_SHIFTCFG_SSTOP | ( | x | ) |
SSTOP - Shifter Stop bit 0b00..Stop bit disabled for transmitter/receiver/match store 0b01..Reserved for transmitter/receiver/match store 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
| #define FLEXIO_SHIFTCTL_PINCFG | ( | x | ) |
PINCFG - Shifter Pin Configuration 0b00..Shifter pin output disabled 0b01..Shifter pin open drain or bidirectional output enable 0b10..Shifter pin bidirectional output data 0b11..Shifter pin output
| #define FLEXIO_SHIFTCTL_PINCFG | ( | x | ) |
PINCFG - Shifter Pin Configuration 0b00..Shifter pin output disabled 0b01..Shifter pin open drain or bidirectional output enable 0b10..Shifter pin bidirectional output data 0b11..Shifter pin output
| #define FLEXIO_SHIFTCTL_PINCFG | ( | x | ) |
PINCFG - Shifter Pin Configuration 0b00..Shifter pin output disabled 0b01..Shifter pin open drain or bidirectional output enable 0b10..Shifter pin bidirectional output data 0b11..Shifter pin output
| #define FLEXIO_SHIFTCTL_PINPOL | ( | x | ) |
PINPOL - Shifter Pin Polarity 0b0..Pin is active high 0b1..Pin is active low
| #define FLEXIO_SHIFTCTL_PINPOL | ( | x | ) |
PINPOL - Shifter Pin Polarity 0b0..Pin is active high 0b1..Pin is active low
| #define FLEXIO_SHIFTCTL_PINPOL | ( | x | ) |
PINPOL - Shifter Pin Polarity 0b0..Pin is active high 0b1..Pin is active low
| #define FLEXIO_SHIFTCTL_PINSEL | ( | x | ) |
PINSEL - Shifter Pin Select
| #define FLEXIO_SHIFTCTL_PINSEL | ( | x | ) |
PINSEL - Shifter Pin Select
| #define FLEXIO_SHIFTCTL_PINSEL | ( | x | ) |
PINSEL - Shifter Pin Select
| #define FLEXIO_SHIFTCTL_SMOD | ( | x | ) |
SMOD - Shifter Mode 0b000..Disabled. 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0b011..Reserved. 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
| #define FLEXIO_SHIFTCTL_SMOD | ( | x | ) |
SMOD - Shifter Mode 0b000..Disabled. 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0b011..Reserved. 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
| #define FLEXIO_SHIFTCTL_SMOD | ( | x | ) |
SMOD - Shifter Mode 0b000..Disabled. 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0b011..Reserved. 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
| #define FLEXIO_SHIFTCTL_TIMPOL | ( | x | ) |
TIMPOL - Timer Polarity 0b0..Shift on posedge of Shift clock 0b1..Shift on negedge of Shift clock
| #define FLEXIO_SHIFTCTL_TIMPOL | ( | x | ) |
TIMPOL - Timer Polarity 0b0..Shift on posedge of Shift clock 0b1..Shift on negedge of Shift clock
| #define FLEXIO_SHIFTCTL_TIMPOL | ( | x | ) |
TIMPOL - Timer Polarity 0b0..Shift on posedge of Shift clock 0b1..Shift on negedge of Shift clock
| #define FLEXIO_SHIFTCTL_TIMSEL | ( | x | ) |
TIMSEL - Timer Select
| #define FLEXIO_SHIFTCTL_TIMSEL | ( | x | ) |
TIMSEL - Timer Select
| #define FLEXIO_SHIFTCTL_TIMSEL | ( | x | ) |
TIMSEL - Timer Select
| #define FLEXIO_SHIFTEIEN_SEIE | ( | x | ) |
SEIE - Shifter Error Interrupt Enable
| #define FLEXIO_SHIFTEIEN_SEIE | ( | x | ) |
SEIE - Shifter Error Interrupt Enable
| #define FLEXIO_SHIFTEIEN_SEIE | ( | x | ) |
SEIE - Shifter Error Interrupt Enable
| #define FLEXIO_SHIFTERR_SEF | ( | x | ) |
SEF - Shifter Error Flags
| #define FLEXIO_SHIFTERR_SEF | ( | x | ) |
SEF - Shifter Error Flags
| #define FLEXIO_SHIFTERR_SEF | ( | x | ) |
SEF - Shifter Error Flags
| #define FLEXIO_SHIFTSDEN_SSDE | ( | x | ) |
SSDE - Shifter Status DMA Enable
| #define FLEXIO_SHIFTSDEN_SSDE | ( | x | ) |
SSDE - Shifter Status DMA Enable
| #define FLEXIO_SHIFTSDEN_SSDE | ( | x | ) |
SSDE - Shifter Status DMA Enable
| #define FLEXIO_SHIFTSIEN_SSIE | ( | x | ) |
SSIE - Shifter Status Interrupt Enable
| #define FLEXIO_SHIFTSIEN_SSIE | ( | x | ) |
SSIE - Shifter Status Interrupt Enable
| #define FLEXIO_SHIFTSIEN_SSIE | ( | x | ) |
SSIE - Shifter Status Interrupt Enable
| #define FLEXIO_SHIFTSTAT_SSF | ( | x | ) |
SSF - Shifter Status Flag
| #define FLEXIO_SHIFTSTAT_SSF | ( | x | ) |
SSF - Shifter Status Flag
| #define FLEXIO_SHIFTSTAT_SSF | ( | x | ) |
SSF - Shifter Status Flag
| #define FLEXIO_SHIFTSTATE_STATE | ( | x | ) |
STATE - Current State Pointer
| #define FLEXIO_SHIFTSTATE_STATE | ( | x | ) |
STATE - Current State Pointer
| #define FLEXIO_SHIFTSTATE_STATE | ( | x | ) |
STATE - Current State Pointer
| #define FLEXIO_TIMCFG_TIMDEC | ( | x | ) |
TIMDEC - Timer Decrement 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
TIMDEC - Timer Decrement 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input. 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
| #define FLEXIO_TIMCFG_TIMDEC | ( | x | ) |
TIMDEC - Timer Decrement 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input. 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
| #define FLEXIO_TIMCFG_TIMDEC | ( | x | ) |
TIMDEC - Timer Decrement 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input. 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
| #define FLEXIO_TIMCFG_TIMDIS | ( | x | ) |
TIMDIS - Timer Disable 0b000..Timer never disabled 0b001..Timer disabled on Timer N-1 disable 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0b100..Timer disabled on Pin rising or falling edge 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 0b110..Timer disabled on Trigger falling edge 0b111..Reserved
| #define FLEXIO_TIMCFG_TIMDIS | ( | x | ) |
TIMDIS - Timer Disable 0b000..Timer never disabled 0b001..Timer disabled on Timer N-1 disable 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0b100..Timer disabled on Pin rising or falling edge 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 0b110..Timer disabled on Trigger falling edge 0b111..Reserved
| #define FLEXIO_TIMCFG_TIMDIS | ( | x | ) |
TIMDIS - Timer Disable 0b000..Timer never disabled 0b001..Timer disabled on Timer N-1 disable 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0b100..Timer disabled on Pin rising or falling edge 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 0b110..Timer disabled on Trigger falling edge 0b111..Reserved
| #define FLEXIO_TIMCFG_TIMENA | ( | x | ) |
TIMENA - Timer Enable 0b000..Timer always enabled 0b001..Timer enabled on Timer N-1 enable 0b010..Timer enabled on Trigger high 0b011..Timer enabled on Trigger high and Pin high 0b100..Timer enabled on Pin rising edge 0b101..Timer enabled on Pin rising edge and Trigger high 0b110..Timer enabled on Trigger rising edge 0b111..Timer enabled on Trigger rising or falling edge
| #define FLEXIO_TIMCFG_TIMENA | ( | x | ) |
TIMENA - Timer Enable 0b000..Timer always enabled 0b001..Timer enabled on Timer N-1 enable 0b010..Timer enabled on Trigger high 0b011..Timer enabled on Trigger high and Pin high 0b100..Timer enabled on Pin rising edge 0b101..Timer enabled on Pin rising edge and Trigger high 0b110..Timer enabled on Trigger rising edge 0b111..Timer enabled on Trigger rising or falling edge
| #define FLEXIO_TIMCFG_TIMENA | ( | x | ) |
TIMENA - Timer Enable 0b000..Timer always enabled 0b001..Timer enabled on Timer N-1 enable 0b010..Timer enabled on Trigger high 0b011..Timer enabled on Trigger high and Pin high 0b100..Timer enabled on Pin rising edge 0b101..Timer enabled on Pin rising edge and Trigger high 0b110..Timer enabled on Trigger rising edge 0b111..Timer enabled on Trigger rising or falling edge
| #define FLEXIO_TIMCFG_TIMOUT | ( | x | ) |
TIMOUT - Timer Output 0b00..Timer output is logic one when enabled and is not affected by timer reset 0b01..Timer output is logic zero when enabled and is not affected by timer reset 0b10..Timer output is logic one when enabled and on timer reset 0b11..Timer output is logic zero when enabled and on timer reset
| #define FLEXIO_TIMCFG_TIMOUT | ( | x | ) |
TIMOUT - Timer Output 0b00..Timer output is logic one when enabled and is not affected by timer reset 0b01..Timer output is logic zero when enabled and is not affected by timer reset 0b10..Timer output is logic one when enabled and on timer reset 0b11..Timer output is logic zero when enabled and on timer reset
| #define FLEXIO_TIMCFG_TIMOUT | ( | x | ) |
TIMOUT - Timer Output 0b00..Timer output is logic one when enabled and is not affected by timer reset 0b01..Timer output is logic zero when enabled and is not affected by timer reset 0b10..Timer output is logic one when enabled and on timer reset 0b11..Timer output is logic zero when enabled and on timer reset
| #define FLEXIO_TIMCFG_TIMRST | ( | x | ) |
TIMRST - Timer Reset 0b000..Timer never reset 0b001..Reserved 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge
TIMRST - Timer Reset 0b000..Timer never reset 0b001..Timer reset on Timer Output high. 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge
| #define FLEXIO_TIMCFG_TIMRST | ( | x | ) |
TIMRST - Timer Reset 0b000..Timer never reset 0b001..Timer reset on Timer Output high. 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge
| #define FLEXIO_TIMCFG_TIMRST | ( | x | ) |
TIMRST - Timer Reset 0b000..Timer never reset 0b001..Timer reset on Timer Output high. 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge
| #define FLEXIO_TIMCFG_TSTART | ( | x | ) |
TSTART - Timer Start Bit 0b0..Start bit disabled 0b1..Start bit enabled
| #define FLEXIO_TIMCFG_TSTART | ( | x | ) |
TSTART - Timer Start Bit 0b0..Start bit disabled 0b1..Start bit enabled
| #define FLEXIO_TIMCFG_TSTART | ( | x | ) |
TSTART - Timer Start Bit 0b0..Start bit disabled 0b1..Start bit enabled
| #define FLEXIO_TIMCFG_TSTOP | ( | x | ) |
TSTOP - Timer Stop Bit 0b00..Stop bit disabled 0b01..Stop bit is enabled on timer compare 0b10..Stop bit is enabled on timer disable 0b11..Stop bit is enabled on timer compare and timer disable
| #define FLEXIO_TIMCFG_TSTOP | ( | x | ) |
TSTOP - Timer Stop Bit 0b00..Stop bit disabled 0b01..Stop bit is enabled on timer compare 0b10..Stop bit is enabled on timer disable 0b11..Stop bit is enabled on timer compare and timer disable
| #define FLEXIO_TIMCFG_TSTOP | ( | x | ) |
TSTOP - Timer Stop Bit 0b00..Stop bit disabled 0b01..Stop bit is enabled on timer compare 0b10..Stop bit is enabled on timer disable 0b11..Stop bit is enabled on timer compare and timer disable
| #define FLEXIO_TIMCMP_CMP | ( | x | ) |
CMP - Timer Compare Value
| #define FLEXIO_TIMCMP_CMP | ( | x | ) |
CMP - Timer Compare Value
| #define FLEXIO_TIMCMP_CMP | ( | x | ) |
CMP - Timer Compare Value
| #define FLEXIO_TIMCTL_ONETIM | ( | x | ) |
ONETIM - Timer One Time Operation 0b0..The timer enable event is generated as normal. 0b1..The timer enable event is blocked unless timer status flag is clear.
| #define FLEXIO_TIMCTL_ONETIM | ( | x | ) |
ONETIM - Timer One Time Operation 0b0..The timer enable event is generated as normal. 0b1..The timer enable event is blocked unless timer status flag is clear.
| #define FLEXIO_TIMCTL_PINCFG | ( | x | ) |
PINCFG - Timer Pin Configuration 0b00..Timer pin output disabled 0b01..Timer pin open drain or bidirectional output enable 0b10..Timer pin bidirectional output data 0b11..Timer pin output
| #define FLEXIO_TIMCTL_PINCFG | ( | x | ) |
PINCFG - Timer Pin Configuration 0b00..Timer pin output disabled 0b01..Timer pin open drain or bidirectional output enable 0b10..Timer pin bidirectional output data 0b11..Timer pin output
| #define FLEXIO_TIMCTL_PINCFG | ( | x | ) |
PINCFG - Timer Pin Configuration 0b00..Timer pin output disabled 0b01..Timer pin open drain or bidirectional output enable 0b10..Timer pin bidirectional output data 0b11..Timer pin output
| #define FLEXIO_TIMCTL_PININS | ( | x | ) |
PININS - Timer Pin Input Select 0b0..Timer pin input and output are selected by PINSEL. 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
| #define FLEXIO_TIMCTL_PININS | ( | x | ) |
PININS - Timer Pin Input Select 0b0..Timer pin input and output are selected by PINSEL. 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
| #define FLEXIO_TIMCTL_PINPOL | ( | x | ) |
PINPOL - Timer Pin Polarity 0b0..Pin is active high 0b1..Pin is active low
| #define FLEXIO_TIMCTL_PINPOL | ( | x | ) |
PINPOL - Timer Pin Polarity 0b0..Pin is active high 0b1..Pin is active low
| #define FLEXIO_TIMCTL_PINPOL | ( | x | ) |
PINPOL - Timer Pin Polarity 0b0..Pin is active high 0b1..Pin is active low
| #define FLEXIO_TIMCTL_PINSEL | ( | x | ) |
PINSEL - Timer Pin Select
| #define FLEXIO_TIMCTL_PINSEL | ( | x | ) |
PINSEL - Timer Pin Select
| #define FLEXIO_TIMCTL_PINSEL | ( | x | ) |
PINSEL - Timer Pin Select
| #define FLEXIO_TIMCTL_TIMOD | ( | x | ) |
TIMOD - Timer Mode 0b00..Timer Disabled. 0b01..Dual 8-bit counters baud mode. 0b10..Dual 8-bit counters PWM high mode. 0b11..Single 16-bit counter mode.
TIMOD - Timer Mode 0b000..Timer Disabled. 0b001..Dual 8-bit counters baud mode. 0b010..Dual 8-bit counters PWM high mode. 0b011..Single 16-bit counter mode. 0b100..Single 16-bit counter disable mode. 0b101..Dual 8-bit counters word mode. 0b110..Dual 8-bit counters PWM low mode. 0b111..Single 16-bit input capture mode.
| #define FLEXIO_TIMCTL_TIMOD | ( | x | ) |
TIMOD - Timer Mode 0b000..Timer Disabled. 0b001..Dual 8-bit counters baud mode. 0b010..Dual 8-bit counters PWM high mode. 0b011..Single 16-bit counter mode. 0b100..Single 16-bit counter disable mode. 0b101..Dual 8-bit counters word mode. 0b110..Dual 8-bit counters PWM low mode. 0b111..Single 16-bit input capture mode.
| #define FLEXIO_TIMCTL_TIMOD | ( | x | ) |
TIMOD - Timer Mode 0b000..Timer Disabled. 0b001..Dual 8-bit counters baud mode. 0b010..Dual 8-bit counters PWM high mode. 0b011..Single 16-bit counter mode. 0b100..Single 16-bit counter disable mode. 0b101..Dual 8-bit counters word mode. 0b110..Dual 8-bit counters PWM low mode. 0b111..Single 16-bit input capture mode.
| #define FLEXIO_TIMCTL_TRGPOL | ( | x | ) |
TRGPOL - Trigger Polarity 0b0..Trigger active high 0b1..Trigger active low
| #define FLEXIO_TIMCTL_TRGPOL | ( | x | ) |
TRGPOL - Trigger Polarity 0b0..Trigger active high 0b1..Trigger active low
| #define FLEXIO_TIMCTL_TRGPOL | ( | x | ) |
TRGPOL - Trigger Polarity 0b0..Trigger active high 0b1..Trigger active low
| #define FLEXIO_TIMCTL_TRGSEL | ( | x | ) |
TRGSEL - Trigger Select
| #define FLEXIO_TIMCTL_TRGSEL | ( | x | ) |
TRGSEL - Trigger Select
| #define FLEXIO_TIMCTL_TRGSEL | ( | x | ) |
TRGSEL - Trigger Select
| #define FLEXIO_TIMCTL_TRGSRC | ( | x | ) |
TRGSRC - Trigger Source 0b0..External trigger selected 0b1..Internal trigger selected
| #define FLEXIO_TIMCTL_TRGSRC | ( | x | ) |
TRGSRC - Trigger Source 0b0..External trigger selected 0b1..Internal trigger selected
| #define FLEXIO_TIMCTL_TRGSRC | ( | x | ) |
TRGSRC - Trigger Source 0b0..External trigger selected 0b1..Internal trigger selected
| #define FLEXIO_TIMERSDEN_TSDE | ( | x | ) |
TSDE - Timer Status DMA Enable
| #define FLEXIO_TIMERSDEN_TSDE | ( | x | ) |
TSDE - Timer Status DMA Enable
| #define FLEXIO_TIMIEN_TEIE | ( | x | ) |
TEIE - Timer Status Interrupt Enable
| #define FLEXIO_TIMIEN_TEIE | ( | x | ) |
TEIE - Timer Status Interrupt Enable
| #define FLEXIO_TIMIEN_TEIE | ( | x | ) |
TEIE - Timer Status Interrupt Enable
| #define FLEXIO_TIMSTAT_TSF | ( | x | ) |
TSF - Timer Status Flags
| #define FLEXIO_TIMSTAT_TSF | ( | x | ) |
TSF - Timer Status Flags
| #define FLEXIO_TIMSTAT_TSF | ( | x | ) |
TSF - Timer Status Flags
| #define FLEXIO_VERID_FEATURE | ( | x | ) |
FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes.
FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
| #define FLEXIO_VERID_FEATURE | ( | x | ) |
FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
| #define FLEXIO_VERID_FEATURE | ( | x | ) |
FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
| #define FLEXIO_VERID_MAJOR | ( | x | ) |
MAJOR - Major Version Number
| #define FLEXIO_VERID_MAJOR | ( | x | ) |
MAJOR - Major Version Number
| #define FLEXIO_VERID_MAJOR | ( | x | ) |
MAJOR - Major Version Number
| #define FLEXIO_VERID_MINOR | ( | x | ) |
MINOR - Minor Version Number
| #define FLEXIO_VERID_MINOR | ( | x | ) |
MINOR - Minor Version Number
| #define FLEXIO_VERID_MINOR | ( | x | ) |
MINOR - Minor Version Number
| #define LPUART_PARAM_RXFIFO | ( | x | ) |
RXFIFO - Receive FIFO Size
| #define LPUART_PARAM_RXFIFO | ( | x | ) |
RXFIFO - Receive FIFO Size
| #define LPUART_PARAM_RXFIFO | ( | x | ) |
RXFIFO - Receive FIFO Size
| #define LPUART_PARAM_TXFIFO | ( | x | ) |
TXFIFO - Transmit FIFO Size
| #define LPUART_PARAM_TXFIFO | ( | x | ) |
TXFIFO - Transmit FIFO Size
| #define LPUART_PARAM_TXFIFO | ( | x | ) |
TXFIFO - Transmit FIFO Size
| #define LPUART_VERID_FEATURE | ( | x | ) |
FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.
| #define LPUART_VERID_FEATURE | ( | x | ) |
FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.
| #define LPUART_VERID_FEATURE | ( | x | ) |
FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.
| #define LPUART_VERID_MAJOR | ( | x | ) |
MAJOR - Major Version Number
| #define LPUART_VERID_MAJOR | ( | x | ) |
MAJOR - Major Version Number
| #define LPUART_VERID_MAJOR | ( | x | ) |
MAJOR - Major Version Number
| #define LPUART_VERID_MINOR | ( | x | ) |
MINOR - Minor Version Number
| #define LPUART_VERID_MINOR | ( | x | ) |
MINOR - Minor Version Number
| #define LPUART_VERID_MINOR | ( | x | ) |
MINOR - Minor Version Number
1.18.0