ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK (0xFFU)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK (0x2000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT (13U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK (0x4000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK (0x20000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT (17U)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK (0xFFU)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
#define	ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK (0x2000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT (13U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK (0x4000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
#define	ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK (0x20000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT (17U)
#define	ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x)

SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK (0x10000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK (0x200000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT (21U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK (0x10000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK (0x200000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT (21U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x)

SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x)

SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK (0x3FU)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK (0x3F00U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK (0x3F0000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK (0x3F000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT (24U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK (0x3FU)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK (0x3F00U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK (0x3F0000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK (0x3F000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT (24U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x)

SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK (0x10000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK (0x800000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT (23U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK (0x10000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK (0x800000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT (23U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x)

SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x)

SYS_PLL2_SS - SYS_PLL2_SS_REGISTER
#define	ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP(x)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP(x)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL2_SS_STEP(x)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL2_SS_STOP(x)

SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK (0x3FU)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK (0x3F00U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK (0x3F0000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK (0x3F000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT (24U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK (0x3FU)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK (0x3F00U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT (8U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK (0x3F0000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK (0x3F000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT (24U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x)

SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD(x)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL2_MFD_MFD(x)

SYS_PLL1_SS - SYS_PLL1_SS_REGISTER
#define	ANADIG_PLL_SYS_PLL1_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP(x)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP(x)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_SS_STEP(x)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_SYS_PLL1_SS_ENABLE(x)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_SYS_PLL1_SS_STOP(x)

SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x)

SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x)

SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x)

SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x)

PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x)

PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STEP(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_PLL_AUDIO_SS_STOP(x)

PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x)

PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x)

PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x)

PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
#define	ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x)

PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK (0x7FFFU)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STEP(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK (0x8000U)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT (15U)
#define	ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK (0xFFFF0000U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT (16U)
#define	ANADIG_PLL_PLL_VIDEO_SS_STOP(x)

PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x)

PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x)

PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
#define	ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x)

Detailed Description

Macro Definition Documentation

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)

ARM_PLL_CONTROL_MODE - pll_arm_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)

ARM_PLL_CONTROL_MODE - pll_arm_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)

ARM_PLL_GATE - ARM_PLL_GATE 0b1..Clock is gated 0b0..Clock is not gated

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)

ARM_PLL_GATE - ARM_PLL_GATE 0b1..Clock is gated 0b0..Clock is not gated

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)

ARM_PLL_STABLE - ARM_PLL_STABLE 0b1..ARM PLL is stable 0b0..ARM PLL is not stable

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)

ARM_PLL_STABLE - ARM_PLL_STABLE 0b1..ARM PLL is stable 0b0..ARM PLL is not stable

◆ ANADIG_PLL_ARM_PLL_CTRL_BYPASS [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)

BYPASS - Bypass the pll. 0b1..Bypass Mode 0b0..Function mode

◆ ANADIG_PLL_ARM_PLL_CTRL_BYPASS [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)

BYPASS - Bypass the pll. 0b1..Bypass Mode 0b0..Function mode

◆ ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)

DIV_SELECT - DIV_SELECT

◆ ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)

DIV_SELECT - DIV_SELECT

◆ ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - Enable the clock output. 0b0..Disable the clock 0b1..Enable the clock

◆ ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - Enable the clock output. 0b0..Disable the clock 0b1..Enable the clock

◆ ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)

HOLD_RING_OFF - PLL Start up initialization 0b0..Normal operation 0b1..Initialize PLL start up

◆ ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)

HOLD_RING_OFF - PLL Start up initialization 0b0..Normal operation 0b1..Initialize PLL start up

◆ ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)

POST_DIV_SEL - POST_DIV_SEL 0b00..Divide by 2 0b01..Divide by 4 0b10..Divide by 8 0b11..Divide by 1

◆ ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)

POST_DIV_SEL - POST_DIV_SEL 0b00..Divide by 2 0b01..Divide by 4 0b10..Divide by 8 0b11..Divide by 1

◆ ANADIG_PLL_ARM_PLL_CTRL_POWERUP [1/2]

#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)

POWERUP - Powers up the PLL. 0b1..Power Up the PLL 0b0..Power down the PLL

◆ ANADIG_PLL_ARM_PLL_CTRL_POWERUP [2/2]

#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)

POWERUP - Powers up the PLL. 0b1..Power Up the PLL 0b0..Power down the PLL

◆ ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK [1/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - ENABLE_CLK

◆ ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK [2/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - ENABLE_CLK

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY [1/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)

PLL_AUDIO_AI_BUSY - pll_audio_ai_busy

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY [2/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)

PLL_AUDIO_AI_BUSY - pll_audio_ai_busy

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE [1/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)

PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE [2/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)

PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE [1/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)

PLL_AUDIO_GATE - PLL_AUDIO_GATE 0b1..Gate the output 0b0..No gate

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE [2/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)

PLL_AUDIO_GATE - PLL_AUDIO_GATE 0b1..Gate the output 0b0..No gate

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE [1/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)

PLL_AUDIO_STABLE - PLL_AUDIO_STABLE

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE [2/2]

#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)

PLL_AUDIO_STABLE - PLL_AUDIO_STABLE

◆ ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM [1/2]

#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)

DENOM - DENOM

◆ ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM [2/2]

#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)

DENOM - DENOM

◆ ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT [1/2]

#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)

PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT

◆ ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT [2/2]

#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)

PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT

◆ ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM [1/2]

#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)

NUM - NUM

◆ ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM [2/2]

#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)

NUM - NUM

◆ ANADIG_PLL_PLL_AUDIO_SS_ENABLE [1/2]

#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_PLL_AUDIO_SS_ENABLE [2/2]

#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_PLL_AUDIO_SS_STEP [1/2]

#define ANADIG_PLL_PLL_AUDIO_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_PLL_AUDIO_SS_STEP [2/2]

#define ANADIG_PLL_PLL_AUDIO_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_PLL_AUDIO_SS_STOP [1/2]

#define ANADIG_PLL_PLL_AUDIO_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_PLL_AUDIO_SS_STOP [2/2]

#define ANADIG_PLL_PLL_AUDIO_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK [1/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - ENABLE_CLK

◆ ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK [2/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - ENABLE_CLK

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY [1/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)

PLL_VIDEO_AI_BUSY - pll_video_ai_busy

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY [2/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)

PLL_VIDEO_AI_BUSY - pll_video_ai_busy

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE [1/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)

PLL_VIDEO_CONTROL_MODE - pll_video_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE [2/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)

PLL_VIDEO_CONTROL_MODE - pll_video_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR [1/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)

PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR [2/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)

PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE [1/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)

PLL_VIDEO_GATE - PLL_VIDEO_GATE 0b1..Gate the output 0b0..No gate

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE [2/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)

PLL_VIDEO_GATE - PLL_VIDEO_GATE 0b1..Gate the output 0b0..No gate

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE [1/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)

PLL_VIDEO_STABLE - PLL_VIDEO_STABLE

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE [2/2]

#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)

PLL_VIDEO_STABLE - PLL_VIDEO_STABLE

◆ ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM [1/2]

#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)

DENOM - DENOM

◆ ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM [2/2]

#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)

DENOM - DENOM

◆ ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT [1/2]

#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK)

DIV_SELECT - DIV_SELECT

◆ ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT [2/2]

#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK)

DIV_SELECT - DIV_SELECT

◆ ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM [1/2]

#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)

NUM - NUM

◆ ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM [2/2]

#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)

NUM - NUM

◆ ANADIG_PLL_PLL_VIDEO_SS_ENABLE [1/2]

#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_PLL_VIDEO_SS_ENABLE [2/2]

#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_PLL_VIDEO_SS_STEP [1/2]

#define ANADIG_PLL_PLL_VIDEO_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_PLL_VIDEO_SS_STEP [2/2]

#define ANADIG_PLL_PLL_VIDEO_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_PLL_VIDEO_SS_STOP [1/2]

#define ANADIG_PLL_PLL_VIDEO_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_PLL_VIDEO_SS_STOP [2/2]

#define ANADIG_PLL_PLL_VIDEO_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - ENABLE_CLK

◆ ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - ENABLE_CLK

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)

SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)

SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)

SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)

SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2 [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)

SYS_PLL1_DIV2 - SYS_PLL1_DIV2

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2 [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)

SYS_PLL1_DIV2 - SYS_PLL1_DIV2

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)

SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)

SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5 [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)

SYS_PLL1_DIV5 - SYS_PLL1_DIV5

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5 [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)

SYS_PLL1_DIV5 - SYS_PLL1_DIV5

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)

SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)

SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)

SYS_PLL1_GATE - SYS_PLL1_GATE 0b1..Gate the output 0b0..No gate

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)

SYS_PLL1_GATE - SYS_PLL1_GATE 0b1..Gate the output 0b0..No gate

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)

SYS_PLL1_STABLE - SYS_PLL1_STABLE

◆ ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)

SYS_PLL1_STABLE - SYS_PLL1_STABLE

◆ ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM [1/2]

#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)

DENOM - DENOM

◆ ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM [2/2]

#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)

DENOM - DENOM

◆ ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT [1/2]

#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)

DIV_SELECT - DIV_SELECT

◆ ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT [2/2]

#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)

DIV_SELECT - DIV_SELECT

◆ ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM [1/2]

#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)

NUM - NUM

◆ ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM [2/2]

#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)

NUM - NUM

◆ ANADIG_PLL_SYS_PLL1_SS_ENABLE [1/2]

#define ANADIG_PLL_SYS_PLL1_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_SYS_PLL1_SS_ENABLE [2/2]

#define ANADIG_PLL_SYS_PLL1_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_SYS_PLL1_SS_STEP [1/2]

#define ANADIG_PLL_SYS_PLL1_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_SYS_PLL1_SS_STEP [2/2]

#define ANADIG_PLL_SYS_PLL1_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_SYS_PLL1_SS_STOP [1/2]

#define ANADIG_PLL_SYS_PLL1_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_SYS_PLL1_SS_STOP [2/2]

#define ANADIG_PLL_SYS_PLL1_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_SYS_PLL2_CTRL_BYPASS [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)

BYPASS - Bypass the pll. 0b1..Bypass Mode 0b0..Function mode

◆ ANADIG_PLL_SYS_PLL2_CTRL_BYPASS [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)

BYPASS - Bypass the pll. 0b1..Bypass Mode 0b0..Function mode

◆ ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)

DITHER_ENABLE - DITHER_ENABLE 0b0..Disable Dither 0b1..Enable Dither

◆ ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)

DITHER_ENABLE - DITHER_ENABLE 0b0..Disable Dither 0b1..Enable Dither

◆ ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - Enable the clock output. 0b0..Disable the clock 0b1..Enable the clock

◆ ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - Enable the clock output. 0b0..Disable the clock 0b1..Enable the clock

◆ ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)

HOLD_RING_OFF - PLL Start up initialization 0b0..Normal operation 0b1..Initialize PLL start up

◆ ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)

HOLD_RING_OFF - PLL Start up initialization 0b0..Normal operation 0b1..Initialize PLL start up

◆ ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)

PFD_OFFSET_EN - PFD_OFFSET_EN

◆ ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)

PFD_OFFSET_EN - PFD_OFFSET_EN

◆ ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)

PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE

◆ ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)

PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE

◆ ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)

PLL_REG_EN - Enable Internal PLL Regulator

◆ ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)

PLL_REG_EN - Enable Internal PLL Regulator

◆ ANADIG_PLL_SYS_PLL2_CTRL_POWERUP [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)

POWERUP - Powers up the PLL. 0b1..Power Up the PLL 0b0..Power down the PLL

◆ ANADIG_PLL_SYS_PLL2_CTRL_POWERUP [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)

POWERUP - Powers up the PLL. 0b1..Power Up the PLL 0b0..Power down the PLL

◆ ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)

SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)

SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)

SYS_PLL2_GATE - SYS_PLL2_GATE 0b1..Clock is gated 0b0..Clock is not gated

◆ ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)

SYS_PLL2_GATE - SYS_PLL2_GATE 0b1..Clock is gated 0b0..Clock is not gated

◆ ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)

SYS_PLL2_STABLE - SYS_PLL2_STABLE

◆ ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)

SYS_PLL2_STABLE - SYS_PLL2_STABLE

◆ ANADIG_PLL_SYS_PLL2_MFD_MFD [1/2]

#define ANADIG_PLL_SYS_PLL2_MFD_MFD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)

MFD - Denominator

◆ ANADIG_PLL_SYS_PLL2_MFD_MFD [2/2]

#define ANADIG_PLL_SYS_PLL2_MFD_MFD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)

MFD - Denominator

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)

PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)

PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)

PFD0_FRAC - PFD0_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)

PFD0_FRAC - PFD0_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)

PFD0_STABLE - PFD0_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)

PFD0_STABLE - PFD0_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)

PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)

PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)

PFD1_FRAC - PFD1_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)

PFD1_FRAC - PFD1_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)

PFD1_STABLE - PFD1_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)

PFD1_STABLE - PFD1_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)

PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)

PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)

PFD2_FRAC - PFD2_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)

PFD2_FRAC - PFD2_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)

PFD2_STABLE - PFD2_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)

PFD2_STABLE - PFD2_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)

PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)

PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)

PFD3_FRAC - PFD3_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)

PFD3_FRAC - PFD3_FRAC

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)

PFD3_STABLE - PFD3_STABLE

◆ ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)

PFD3_STABLE - PFD3_STABLE

◆ ANADIG_PLL_SYS_PLL2_SS_ENABLE [1/2]

#define ANADIG_PLL_SYS_PLL2_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_SYS_PLL2_SS_ENABLE [2/2]

#define ANADIG_PLL_SYS_PLL2_SS_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)

ENABLE - ENABLE 0b1..Enable Spread Spectrum 0b0..Disable Spread Spectrum

◆ ANADIG_PLL_SYS_PLL2_SS_STEP [1/2]

#define ANADIG_PLL_SYS_PLL2_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_SYS_PLL2_SS_STEP [2/2]

#define ANADIG_PLL_SYS_PLL2_SS_STEP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)

STEP - STEP

◆ ANADIG_PLL_SYS_PLL2_SS_STOP [1/2]

#define ANADIG_PLL_SYS_PLL2_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_SYS_PLL2_SS_STOP [2/2]

#define ANADIG_PLL_SYS_PLL2_SS_STOP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)

STOP - STOP

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)

PFD0_CONTROL_MODE - pfd0_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)

PFD0_CONTROL_MODE - pfd0_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)

PFD0_UPDATE - PFD0_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)

PFD0_UPDATE - PFD0_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)

PFD1_CONTROL_MODE - pfd1_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)

PFD1_CONTROL_MODE - pfd1_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)

PFD1_UPDATE - PFD1_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)

PFD1_UPDATE - PFD1_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)

PFD2_CONTROL_MODE - pfd2_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)

PFD2_CONTROL_MODE - pfd2_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)

PFD2_UPDATE - PFD2_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)

PFD2_UPDATE - PFD2_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)

PFD3_CONTROL_MODE - pfd3_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)

PFD3_CONTROL_MODE - pfd3_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)

PFD3_UPDATE - PFD3_UPDATE

◆ ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)

PFD3_UPDATE - PFD3_UPDATE

◆ ANADIG_PLL_SYS_PLL3_CTRL_BYPASS [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)

BYPASS - BYPASS 0b1..Bypass Mode 0b0..Function mode

◆ ANADIG_PLL_SYS_PLL3_CTRL_BYPASS [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)

BYPASS - BYPASS 0b1..Bypass Mode 0b0..Function mode

◆ ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - Enable the clock output. 0b0..Disable the clock 0b1..Enable the clock

◆ ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)

ENABLE_CLK - Enable the clock output. 0b0..Disable the clock 0b1..Enable the clock

◆ ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)

HOLD_RING_OFF - PLL Start up initialization 0b0..Normal operation 0b1..Initialize PLL start up

◆ ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)

HOLD_RING_OFF - PLL Start up initialization 0b0..Normal operation 0b1..Initialize PLL start up

◆ ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)

PLL_REG_EN - Enable Internal PLL Regulator

◆ ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)

PLL_REG_EN - Enable Internal PLL Regulator

◆ ANADIG_PLL_SYS_PLL3_CTRL_POWERUP [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)

POWERUP - Powers up the PLL. 0b1..Power Up the PLL 0b0..Power down the PLL

◆ ANADIG_PLL_SYS_PLL3_CTRL_POWERUP [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)

POWERUP - Powers up the PLL. 0b1..Power Up the PLL 0b0..Power down the PLL

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)

SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)

SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2 [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)

SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2 [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)

SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)

SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)

SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)

SYS_PLL3_GATE - SYS_PLL3_GATE 0b1..Clock is gated 0b0..Clock is not gated

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)

SYS_PLL3_GATE - SYS_PLL3_GATE 0b1..Clock is gated 0b0..Clock is not gated

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)

SYS_PLL3_STABLE - SYS_PLL3_STABLE

◆ ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)

SYS_PLL3_STABLE - SYS_PLL3_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)

PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd0) is off (power savings 0b0..ref_pfd0 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)

PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd0) is off (power savings 0b0..ref_pfd0 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)

PFD0_FRAC - PFD0_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)

PFD0_FRAC - PFD0_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)

PFD0_STABLE - PFD0_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)

PFD0_STABLE - PFD0_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)

PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd1) is off (power savings) 0b0..ref_pfd1 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)

PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd1) is off (power savings) 0b0..ref_pfd1 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)

PFD1_FRAC - PFD1_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)

PFD1_FRAC - PFD1_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)

PFD1_STABLE - PFD1_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)

PFD1_STABLE - PFD1_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)

PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd2) is off (power savings) 0b0..ref_pfd2 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)

PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd2) is off (power savings) 0b0..ref_pfd2 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)

PFD2_FRAC - PFD2_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)

PFD2_FRAC - PFD2_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)

PFD2_STABLE - PFD2_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)

PFD2_STABLE - PFD2_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)

PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd3) is off (power savings) 0b0..ref_pfd3 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)

PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE 0b1..Fractional divider clock (reference ref_pfd3) is off (power savings) 0b0..ref_pfd3 fractional divider clock is enabled

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)

PFD3_FRAC - PFD3_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)

PFD3_FRAC - PFD3_FRAC

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE [1/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)

PFD3_STABLE - PFD3_STABLE

◆ ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE [2/2]

#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)

PFD3_STABLE - PFD3_STABLE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)

PDF2_CONTROL_MODE - pdf2_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)

PDF2_CONTROL_MODE - pdf2_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)

PFD0_CONTROL_MODE - pfd0_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)

PFD0_CONTROL_MODE - pfd0_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)

PFD0_UPDATE - PFD0_OVERRIDE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)

PFD0_UPDATE - PFD0_OVERRIDE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)

PFD1_CONTROL_MODE - pfd1_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)

PFD1_CONTROL_MODE - pfd1_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)

PFD1_UPDATE - PFD1_OVERRIDE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)

PFD1_UPDATE - PFD1_OVERRIDE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)

PFD2_UPDATE - PFD2_OVERRIDE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)

PFD2_UPDATE - PFD2_OVERRIDE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)

PFD3_CONTROL_MODE - pfd3_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)

PFD3_CONTROL_MODE - pfd3_control_mode 0b0..Software Mode (Default) 0b1..GPC Mode

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE [1/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)

PFD3_UPDATE - PFD3_UPDATE

◆ ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE [2/2]

#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)

PFD3_UPDATE - PFD3_UPDATE

ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER

SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER

SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER

SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER

SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER

SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER

SYS_PLL2_SS - SYS_PLL2_SS_REGISTER

SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER

SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER

SYS_PLL1_SS - SYS_PLL1_SS_REGISTER

SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER

SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER

SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER

SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER

PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER

PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER

PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER

PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER

PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER

PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER

PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER

PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER

PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER

PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER

Detailed Description

Macro Definition Documentation

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_BYPASS [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_BYPASS [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL [2/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_POWERUP [1/2]

◆ ANADIG_PLL_ARM_PLL_CTRL_POWERUP [2/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK [1/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK [2/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY [1/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY [2/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE [1/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE [2/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE [1/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE [2/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE [1/2]

◆ ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE [2/2]

◆ ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM [1/2]

◆ ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM [2/2]

◆ ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT [1/2]

◆ ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT [2/2]

◆ ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM [1/2]

◆ ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM [2/2]

◆ ANADIG_PLL_PLL_AUDIO_SS_ENABLE [1/2]

◆ ANADIG_PLL_PLL_AUDIO_SS_ENABLE [2/2]

◆ ANADIG_PLL_PLL_AUDIO_SS_STEP [1/2]

◆ ANADIG_PLL_PLL_AUDIO_SS_STEP [2/2]

◆ ANADIG_PLL_PLL_AUDIO_SS_STOP [1/2]

◆ ANADIG_PLL_PLL_AUDIO_SS_STOP [2/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK [1/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK [2/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY [1/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY [2/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE [1/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE [2/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR [1/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR [2/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE [1/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE [2/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE [1/2]

◆ ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE [2/2]

◆ ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM [1/2]

◆ ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM [2/2]