 |
RTEMS 6.3
|
|
RTEMS 6.3
|
PMU_LDO_PLL - PMU_LDO_PLL_REGISTER | |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U) |
| #define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) |
PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER | |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) |
PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER | |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK (0x1000000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT (24U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK (0x4000000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT (26U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK (0x1000000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT (24U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK (0x4000000U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT (26U) |
| #define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x) |
PMU_REF_CTRL - PMU_REF_CTRL_REGISTER | |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK (0x4U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK (0x4U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) |
| #define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U) |
| #define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) |
PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER | |
| #define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U) |
| #define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U) |
| #define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) |
| #define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U) |
| #define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U) |
| #define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) |
LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) |
LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) |
LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) |
LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) |
LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) |
LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) |
LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) |
LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) |
LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) |
LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) |
LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) |
LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) |
LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) |
LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER | |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER | |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) |
RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER | |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) |
RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER | |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) |
BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER | |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER | |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER | |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER | |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
| #define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) |
RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER | |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) |
RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER | |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) |
| #define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) |
REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER | |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U) |
| #define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) |
LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER | |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U) |
| #define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) |
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - STBY_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0 | ( | x | ) |
BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0 | ( | x | ) |
BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1 | ( | x | ) |
BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1 | ( | x | ) |
BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10 | ( | x | ) |
BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10 | ( | x | ) |
BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11 | ( | x | ) |
BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11 | ( | x | ) |
BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12 | ( | x | ) |
BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12 | ( | x | ) |
BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13 | ( | x | ) |
BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13 | ( | x | ) |
BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14 | ( | x | ) |
BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14 | ( | x | ) |
BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15 | ( | x | ) |
BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15 | ( | x | ) |
BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2 | ( | x | ) |
BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2 | ( | x | ) |
BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3 | ( | x | ) |
BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3 | ( | x | ) |
BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4 | ( | x | ) |
BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4 | ( | x | ) |
BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5 | ( | x | ) |
BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5 | ( | x | ) |
BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6 | ( | x | ) |
BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6 | ( | x | ) |
BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7 | ( | x | ) |
BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7 | ( | x | ) |
BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8 | ( | x | ) |
BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8 | ( | x | ) |
BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9 | ( | x | ) |
BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9 | ( | x | ) |
BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0 | ( | x | ) |
LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0 | ( | x | ) |
LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1 | ( | x | ) |
LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1 | ( | x | ) |
LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10 | ( | x | ) |
LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10 | ( | x | ) |
LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11 | ( | x | ) |
LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11 | ( | x | ) |
LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12 | ( | x | ) |
LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12 | ( | x | ) |
LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13 | ( | x | ) |
LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13 | ( | x | ) |
LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14 | ( | x | ) |
LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14 | ( | x | ) |
LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15 | ( | x | ) |
LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15 | ( | x | ) |
LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2 | ( | x | ) |
LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2 | ( | x | ) |
LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3 | ( | x | ) |
LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3 | ( | x | ) |
LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4 | ( | x | ) |
LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4 | ( | x | ) |
LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5 | ( | x | ) |
LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5 | ( | x | ) |
LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6 | ( | x | ) |
LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6 | ( | x | ) |
LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7 | ( | x | ) |
LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7 | ( | x | ) |
LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8 | ( | x | ) |
LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8 | ( | x | ) |
LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9 | ( | x | ) |
LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9 | ( | x | ) |
LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0 | ( | x | ) |
TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0 | ( | x | ) |
TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1 | ( | x | ) |
TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1 | ( | x | ) |
TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10 | ( | x | ) |
TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10 | ( | x | ) |
TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11 | ( | x | ) |
TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11 | ( | x | ) |
TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12 | ( | x | ) |
TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12 | ( | x | ) |
TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13 | ( | x | ) |
TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13 | ( | x | ) |
TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14 | ( | x | ) |
TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14 | ( | x | ) |
TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15 | ( | x | ) |
TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15 | ( | x | ) |
TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2 | ( | x | ) |
TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2 | ( | x | ) |
TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3 | ( | x | ) |
TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3 | ( | x | ) |
TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4 | ( | x | ) |
TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4 | ( | x | ) |
TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5 | ( | x | ) |
TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5 | ( | x | ) |
TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6 | ( | x | ) |
TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6 | ( | x | ) |
TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7 | ( | x | ) |
TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7 | ( | x | ) |
TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8 | ( | x | ) |
TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8 | ( | x | ) |
TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9 | ( | x | ) |
TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9 | ( | x | ) |
TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0 | ( | x | ) |
BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0 | ( | x | ) |
BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1 | ( | x | ) |
BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1 | ( | x | ) |
BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10 | ( | x | ) |
BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10 | ( | x | ) |
BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11 | ( | x | ) |
BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11 | ( | x | ) |
BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12 | ( | x | ) |
BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12 | ( | x | ) |
BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13 | ( | x | ) |
BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13 | ( | x | ) |
BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14 | ( | x | ) |
BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14 | ( | x | ) |
BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15 | ( | x | ) |
BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15 | ( | x | ) |
BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2 | ( | x | ) |
BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2 | ( | x | ) |
BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3 | ( | x | ) |
BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3 | ( | x | ) |
BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4 | ( | x | ) |
BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4 | ( | x | ) |
BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5 | ( | x | ) |
BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5 | ( | x | ) |
BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6 | ( | x | ) |
BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6 | ( | x | ) |
BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7 | ( | x | ) |
BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7 | ( | x | ) |
BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8 | ( | x | ) |
BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8 | ( | x | ) |
BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9 | ( | x | ) |
BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9 | ( | x | ) |
BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0 | ( | x | ) |
LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0 | ( | x | ) |
LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1 | ( | x | ) |
LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1 | ( | x | ) |
LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10 | ( | x | ) |
LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10 | ( | x | ) |
LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11 | ( | x | ) |
LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11 | ( | x | ) |
LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12 | ( | x | ) |
LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12 | ( | x | ) |
LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13 | ( | x | ) |
LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13 | ( | x | ) |
LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14 | ( | x | ) |
LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14 | ( | x | ) |
LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15 | ( | x | ) |
LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15 | ( | x | ) |
LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2 | ( | x | ) |
LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2 | ( | x | ) |
LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3 | ( | x | ) |
LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3 | ( | x | ) |
LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4 | ( | x | ) |
LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4 | ( | x | ) |
LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5 | ( | x | ) |
LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5 | ( | x | ) |
LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6 | ( | x | ) |
LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6 | ( | x | ) |
LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7 | ( | x | ) |
LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7 | ( | x | ) |
LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8 | ( | x | ) |
LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8 | ( | x | ) |
LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9 | ( | x | ) |
LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9 | ( | x | ) |
LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9 0b0..LP 0b1..HP
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0 | ( | x | ) |
TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0 | ( | x | ) |
TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1 | ( | x | ) |
TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1 | ( | x | ) |
TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10 | ( | x | ) |
TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10 | ( | x | ) |
TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11 | ( | x | ) |
TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11 | ( | x | ) |
TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12 | ( | x | ) |
TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12 | ( | x | ) |
TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13 | ( | x | ) |
TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13 | ( | x | ) |
TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14 | ( | x | ) |
TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14 | ( | x | ) |
TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15 | ( | x | ) |
TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15 | ( | x | ) |
TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2 | ( | x | ) |
TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2 | ( | x | ) |
TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3 | ( | x | ) |
TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3 | ( | x | ) |
TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4 | ( | x | ) |
TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4 | ( | x | ) |
TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5 | ( | x | ) |
TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5 | ( | x | ) |
TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6 | ( | x | ) |
TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6 | ( | x | ) |
TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7 | ( | x | ) |
TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7 | ( | x | ) |
TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8 | ( | x | ) |
TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8 | ( | x | ) |
TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9 | ( | x | ) |
TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9 | ( | x | ) |
TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0 | ( | x | ) |
VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0 | ( | x | ) |
VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1 | ( | x | ) |
VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1 | ( | x | ) |
VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2 | ( | x | ) |
VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2 | ( | x | ) |
VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3 | ( | x | ) |
VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3 | ( | x | ) |
VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4 | ( | x | ) |
VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4 | ( | x | ) |
VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5 | ( | x | ) |
VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5 | ( | x | ) |
VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6 | ( | x | ) |
VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6 | ( | x | ) |
VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7 | ( | x | ) |
VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7 | ( | x | ) |
VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10 | ( | x | ) |
VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10 | ( | x | ) |
VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11 | ( | x | ) |
VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11 | ( | x | ) |
VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8 | ( | x | ) |
VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8 | ( | x | ) |
VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9 | ( | x | ) |
VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9 | ( | x | ) |
VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12 | ( | x | ) |
VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12 | ( | x | ) |
VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13 | ( | x | ) |
VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13 | ( | x | ) |
VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14 | ( | x | ) |
VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14 | ( | x | ) |
VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15 | ( | x | ) |
VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15
| #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15 | ( | x | ) |
VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM | ( | x | ) |
LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM
| #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM | ( | x | ) |
LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM
| #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN | ( | x | ) |
LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN
| #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN | ( | x | ) |
LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE | ( | x | ) |
RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE | ( | x | ) |
RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE | ( | x | ) |
RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE | ( | x | ) |
RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8 | ( | x | ) |
WB_ADJ_1P8 - wb_adj_1p8 0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF 0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF 0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF 0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF 0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF 0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF 0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF 0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF 0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF 0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF 0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF 0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF 0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF 0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF 0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF 0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8 | ( | x | ) |
WB_ADJ_1P8 - wb_adj_1p8 0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF 0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF 0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF 0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF 0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF 0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF 0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF 0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF 0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF 0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF 0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF 0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF 0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF 0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF 0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF 0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN | ( | x | ) |
WB_EN - wb_en
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN | ( | x | ) |
WB_EN - wb_en
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK | ( | x | ) |
WB_OK - Digital Output pin.
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK | ( | x | ) |
WB_OK - Digital Output pin.
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8 | ( | x | ) |
WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8 0b010..BB 0b100..BB
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8 | ( | x | ) |
WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8 0b010..BB 0b100..BB
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT | ( | x | ) |
WB_TST_DIG_OUT - Digital output
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT | ( | x | ) |
WB_TST_DIG_OUT - Digital output
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD | ( | x | ) |
WB_TST_MD - TMOD_wb_tst_md_1p8
| #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD | ( | x | ) |
WB_TST_MD - TMOD_wb_tst_md_1p8
| #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8 | ( | x | ) |
WB_CFG_1P8 - wb_cfg_1p8
| #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8 | ( | x | ) |
WB_CFG_1P8 - wb_cfg_1p8
| #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8 | ( | x | ) |
WB_VDD_SEL_1P8 - wb_vdd_sel_1p8 0b0..VDD_LV1 0b1..VDD_LV2
| #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8 | ( | x | ) |
WB_VDD_SEL_1P8 - wb_vdd_sel_1p8 0b0..VDD_LV1 0b1..VDD_LV2
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY | ( | x | ) |
LDO_PLL_AI_BUSY - ldo_pll_busy
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY | ( | x | ) |
LDO_PLL_AI_BUSY - ldo_pll_busy
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE | ( | x | ) |
LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE | ( | x | ) |
LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE | ( | x | ) |
LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE | ( | x | ) |
LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE | ( | x | ) |
LDO_PLL_ENABLE - LDO_PLL_ENABLE
| #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE | ( | x | ) |
LDO_PLL_ENABLE - LDO_PLL_ENABLE
| #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0 | ( | x | ) |
CKGB_LPSR1P0 - ckgb_lpsr1p0
| #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0 | ( | x | ) |
CKGB_LPSR1P0 - ckgb_lpsr1p0
| #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER | ( | x | ) |
EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer
| #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER | ( | x | ) |
EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer
| #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY | ( | x | ) |
REF_AI_BUSY - ref_ai_busy
| #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY | ( | x | ) |
REF_AI_BUSY - ref_ai_busy
| #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE | ( | x | ) |
REF_AI_TOGGLE - ref_ai_toggle
| #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE | ( | x | ) |
REF_AI_TOGGLE - ref_ai_toggle
| #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE | ( | x | ) |
REF_CONTROL_MODE - REF_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE | ( | x | ) |
REF_CONTROL_MODE - REF_CONTROL_MODE 0b0..SW Control 0b1..HW Control
| #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE | ( | x | ) |
REF_ENABLE - REF_ENABLE
| #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE | ( | x | ) |
REF_ENABLE - REF_ENABLE
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS | ( | x | ) |
OSCILLATOR_BITS - oscillator_bits
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS | ( | x | ) |
OSCILLATOR_BITS - oscillator_bits
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH | ( | x | ) |
REGULATOR_STRENGTH - regulator_strength
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH | ( | x | ) |
REGULATOR_STRENGTH - regulator_strength
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW | ( | x | ) |
WB_CFG_NW - wb_cfg_nw
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW | ( | x | ) |
WB_CFG_NW - wb_cfg_nw
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW | ( | x | ) |
WB_CFG_PW - wb_cfg_pw
| #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW | ( | x | ) |
WB_CFG_PW - wb_cfg_pw
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS | ( | x | ) |
OSCILLATOR_BITS - oscillator_bits
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS | ( | x | ) |
OSCILLATOR_BITS - oscillator_bits
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH | ( | x | ) |
REGULATOR_STRENGTH - regulator_strength
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH | ( | x | ) |
REGULATOR_STRENGTH - regulator_strength
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW | ( | x | ) |
WB_CFG_NW - wb_cfg_nw
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW | ( | x | ) |
WB_CFG_NW - wb_cfg_nw
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW | ( | x | ) |
WB_CFG_PW - wb_cfg_pw
| #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW | ( | x | ) |
WB_CFG_PW - wb_cfg_pw
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0 | ( | x | ) |
ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1 | ( | x | ) |
ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10 | ( | x | ) |
ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11 | ( | x | ) |
ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12 | ( | x | ) |
ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13 | ( | x | ) |
ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14 | ( | x | ) |
ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15 | ( | x | ) |
ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2 | ( | x | ) |
ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3 | ( | x | ) |
ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4 | ( | x | ) |
ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5 | ( | x | ) |
ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6 | ( | x | ) |
ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7 | ( | x | ) |
ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8 | ( | x | ) |
ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9 | ( | x | ) |
ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 0b0..ON 0b1..OFF
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0 | ( | x | ) |
STBY_EN_SETPOINT0 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1 | ( | x | ) |
STBY_EN_SETPOINT1 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10 | ( | x | ) |
STBY_EN_SETPOINT10 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11 | ( | x | ) |
STBY_EN_SETPOINT11 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12 | ( | x | ) |
STBY_EN_SETPOINT12 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13 | ( | x | ) |
STBY_EN_SETPOINT13 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14 | ( | x | ) |
STBY_EN_SETPOINT14 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15 | ( | x | ) |
STBY_EN_SETPOINT15 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2 | ( | x | ) |
STBY_EN_SETPOINT2 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3 | ( | x | ) |
STBY_EN_SETPOINT3 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4 | ( | x | ) |
STBY_EN_SETPOINT4 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5 | ( | x | ) |
STBY_EN_SETPOINT5 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6 | ( | x | ) |
STBY_EN_SETPOINT6 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7 | ( | x | ) |
STBY_EN_SETPOINT7 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8 | ( | x | ) |
STBY_EN_SETPOINT8 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9 | ( | x | ) |
STBY_EN_SETPOINT9 - Standby mode 0b0..Disabled 0b1..Enabled
| #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ | ( | x | ) |
REFTOP_IBZTCADJ - REFTOP_IBZTCADJ
| #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ | ( | x | ) |
REFTOP_IBZTCADJ - REFTOP_IBZTCADJ
| #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN | ( | x | ) |
REFTOP_TRIM_EN - REFTOP_TRIM_EN
| #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN | ( | x | ) |
REFTOP_TRIM_EN - REFTOP_TRIM_EN
| #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ | ( | x | ) |
REFTOP_VBGADJ - REFTOP_VBGADJ
| #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ | ( | x | ) |
REFTOP_VBGADJ - REFTOP_VBGADJ
1.18.0