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RTEMS 6.3
|
Topics | |
| ENET Register Masks | |
Data Structures | |
| struct | ENET_Type |
| struct | ENET_Type::[struct].CHANNEL |
Macros | |
| #define | ENET_BASE (0x402D8000u) |
| #define | ENET ((ENET_Type *)ENET_BASE) |
| #define | ENET_BASE_ADDRS { ENET_BASE } |
| #define | ENET_BASE_PTRS { ENET } |
| #define | ENET_Transmit_IRQS { ENET_IRQn } |
| #define | ENET_Receive_IRQS { ENET_IRQn } |
| #define | ENET_Error_IRQS { ENET_IRQn } |
| #define | ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } |
| #define | ENET_Ts_IRQS { ENET_IRQn } |
| #define | ENET_BUFF_ALIGNMENT (64U) |
| #define | ENET_BASE (0x40424000u) |
| #define | ENET ((ENET_Type *)ENET_BASE) |
| #define | ENET_1G_BASE (0x40420000u) |
| #define | ENET_1G ((ENET_Type *)ENET_1G_BASE) |
| #define | ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE } |
| #define | ENET_BASE_PTRS { ENET, ENET_1G } |
| #define | ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_Receive_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_Error_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn } |
| #define | ENET_Ts_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_BUFF_ALIGNMENT (64U) |
| #define | ENET_BASE (0x40424000u) |
| #define | ENET ((ENET_Type *)ENET_BASE) |
| #define | ENET_1G_BASE (0x40420000u) |
| #define | ENET_1G ((ENET_Type *)ENET_1G_BASE) |
| #define | ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE } |
| #define | ENET_BASE_PTRS { ENET, ENET_1G } |
| #define | ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_Receive_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_Error_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn } |
| #define | ENET_Ts_IRQS { ENET_IRQn, ENET_1G_IRQn } |
| #define | ENET_BUFF_ALIGNMENT (64U) |
| #define ENET_1G ((ENET_Type *)ENET_1G_BASE) |
Peripheral ENET_1G base pointer
| #define ENET_1G ((ENET_Type *)ENET_1G_BASE) |
Peripheral ENET_1G base pointer
| #define ENET_1G_BASE (0x40420000u) |
Peripheral ENET_1G base address
| #define ENET_1G_BASE (0x40420000u) |
Peripheral ENET_1G base address
| #define ENET_BASE (0x402D8000u) |
Peripheral ENET base address
| #define ENET_BASE (0x40424000u) |
Peripheral ENET base address
| #define ENET_BASE (0x40424000u) |
Peripheral ENET base address
| #define ENET_BASE_ADDRS { ENET_BASE } |
Array initializer of ENET peripheral base addresses
| #define ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE } |
Array initializer of ENET peripheral base addresses
| #define ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE } |
Array initializer of ENET peripheral base addresses
| #define ENET_BASE_PTRS { ENET } |
Array initializer of ENET peripheral base pointers
| #define ENET_Transmit_IRQS { ENET_IRQn } |
Interrupt vectors for the ENET peripheral type
| #define ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn } |
Interrupt vectors for the ENET peripheral type
| #define ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn } |
Interrupt vectors for the ENET peripheral type