19 #ifndef _RTEMS_SCORE_CPU_H 20 #define _RTEMS_SCORE_CPU_H 31 #if defined(RTEMS_PARAVIRT) 32 #include <rtems/score/paravirt.h> 59 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE 67 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 75 #define CPU_HARDWARE_FP TRUE 76 #define CPU_SOFTWARE_FP FALSE 78 #define CPU_ALL_TASKS_ARE_FP TRUE 79 #define CPU_IDLE_TASK_IS_FP TRUE 80 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 83 #if ( I386_HAS_FPU == 1 ) 84 #define CPU_HARDWARE_FP TRUE 86 #define CPU_HARDWARE_FP FALSE 88 #define CPU_SOFTWARE_FP FALSE 90 #define CPU_ALL_TASKS_ARE_FP FALSE 91 #define CPU_IDLE_TASK_IS_FP FALSE 92 #if defined(RTEMS_SMP) 93 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 95 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 99 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 101 #define CPU_STACK_GROWS_UP FALSE 104 #define CPU_CACHE_LINE_BYTES 64 106 #define CPU_STRUCTURE_ALIGNMENT 108 #define CPU_MAXIMUM_PROCESSORS 32 110 #define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 111 #define I386_CONTEXT_CONTROL_ESP_OFFSET 4 112 #define I386_CONTEXT_CONTROL_EBP_OFFSET 8 113 #define I386_CONTEXT_CONTROL_EBX_OFFSET 12 114 #define I386_CONTEXT_CONTROL_ESI_OFFSET 16 115 #define I386_CONTEXT_CONTROL_EDI_OFFSET 20 116 #define I386_CONTEXT_CONTROL_GS_0_OFFSET 24 117 #define I386_CONTEXT_CONTROL_GS_1_OFFSET 28 118 #define I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32 121 #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 36 139 segment_descriptors gs;
142 volatile bool is_executing;
146 #define _CPU_Context_Get_SP( _context ) \ 150 static inline bool _CPU_Context_Get_is_executing(
157 static inline void _CPU_Context_Set_is_executing(
162 context->is_executing = is_executing;
195 uint8_t fp_save_area[108];
256 uint8_t xmmregs[8][16];
264 extern cpuExcHandlerType _currentExcHandler;
265 extern void rtems_exception_init_mngt(
void);
274 uint32_t reserved[3];
291 I386_EXCEPTION_DIVIDE_BY_ZERO = 0,
292 I386_EXCEPTION_DEBUG = 1,
293 I386_EXCEPTION_NMI = 2,
294 I386_EXCEPTION_BREAKPOINT = 3,
295 I386_EXCEPTION_OVERFLOW = 4,
296 I386_EXCEPTION_BOUND = 5,
297 I386_EXCEPTION_ILLEGAL_INSTR = 6,
298 I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
299 I386_EXCEPTION_DOUBLE_FAULT = 8,
300 I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
301 I386_EXCEPTION_INVALID_TSS = 10,
302 I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
303 I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
304 I386_EXCEPTION_GENERAL_PROT_ERR = 13,
305 I386_EXCEPTION_PAGE_FAULT = 14,
306 I386_EXCEPTION_INTEL_RES15 = 15,
307 I386_EXCEPTION_FLOAT_ERROR = 16,
308 I386_EXCEPTION_ALIGN_CHECK = 17,
309 I386_EXCEPTION_MACHINE_CHECK = 18,
310 I386_EXCEPTION_ENTER_RDBG = 50
312 } Intel_symbolic_exception_name;
321 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 336 #define CPU_MODES_INTERRUPT_MASK 0x00000001 342 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 349 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 355 #define CPU_STACK_MINIMUM_SIZE 4096 357 #define CPU_SIZEOF_POINTER 4 363 #define CPU_ALIGNMENT 4 364 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 375 #define CPU_STACK_ALIGNMENT 16 377 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 393 #if !defined(I386_DISABLE_INLINE_ISR_DISABLE_ENABLE) 394 #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) 396 #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) 398 #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) 400 #define _CPU_ISR_Set_level( _new_level ) \ 402 if ( _new_level ) __asm__ volatile ( "cli" ); \ 403 else __asm__ volatile ( "sti" ); \ 406 #define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts() 407 #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) 408 #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) 409 #define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) 414 return ( level & EFLAGS_INTR_ENABLE ) != 0;
424 #define _CPU_Interrupt_stack_setup( _lo, _hi ) \ 426 _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ 443 #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 444 #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 450 void *stack_area_begin,
451 size_t stack_area_size,
453 void (*entry_point)(
void ),
458 #define _CPU_Context_Restart_self( _the_context ) \ 459 _CPU_Context_restore( (_the_context) ); 461 #if defined(RTEMS_SMP) 462 uint32_t _CPU_SMP_Initialize(
void );
464 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
466 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
468 void _CPU_SMP_Prepare_start_multitasking(
void );
470 uint32_t _CPU_SMP_Get_current_processor(
void );
472 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
474 static inline void _CPU_SMP_Processor_event_broadcast(
void )
476 __asm__ volatile (
"" : : :
"memory" );
479 static inline void _CPU_SMP_Processor_event_receive(
void )
481 __asm__ volatile (
"" : : :
"memory" );
485 #define _CPU_Context_Initialize_fp( _fp_area ) \ 487 memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ 513 #define CPU_USE_GENERIC_BITFIELD_CODE FALSE 515 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 517 uint16_t __value_in_register = ( _value ); \ 518 uint16_t __output = 0; \ 519 __asm__ volatile ( "bsfw %0,%1 " \ 520 : "=r" ( __value_in_register ), "=r" ( __output ) \ 521 : "0" ( __value_in_register ), "1" ( __output ) \ 523 ( _output ) = __output; \ 538 #define _CPU_Priority_Mask( _bit_number ) \ 539 ( 1 << (_bit_number) ) 541 #define _CPU_Priority_bits_index( _priority ) \ 555 typedef void ( *CPU_ISR_handler )( void );
559 CPU_ISR_handler new_handler,
560 CPU_ISR_handler *old_handler
594 #define _CPU_Context_save_fp(fp_context_pp) \ 596 __asm__ __volatile__( \ 598 :"=m"((*(fp_context_pp))->fpucw) \ 600 __asm__ __volatile__( \ 602 :"=m"((*(fp_context_pp))->mxcsr) \ 617 #define _CPU_Context_restore_fp(fp_context_pp) \ 619 __asm__ __volatile__( \ 621 ::"m"((*(fp_context_pp))->fpucw) \ 624 __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ 633 #define _CPU_Context_Initialization_at_thread_begin() \ 635 __asm__ __volatile__( \ 639 :"st","st(1)","st(2)","st(3)", \ 640 "st(4)","st(5)","st(6)","st(7)", \ 643 if ( _Thread_Executing->fp_context ) { \ 644 _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ 657 static inline CPU_Counter_ticks _CPU_Counter_difference(
658 CPU_Counter_ticks second,
659 CPU_Counter_ticks first
662 return second - first;
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:194
uint32_t isr_dispatch_disable
Definition: cpu.h:140
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
Interrupt stack frame (ISF).
Definition: cpu.h:191
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
Intel I386 CPU Dependent Source.
void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN
Definition: bsp_fatal_halt.c:12
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
typedef __attribute__
Disable IRQ Interrupts.
Definition: cmsis_gcc.h:69
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
lpc176x_can_isr_vector isr_vector
Vector of isr for the can_driver .
Definition: can.c:37
SPARC basic context.
Definition: cpu.h:194
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
Definition: sse_test.c:126
unsigned context
Definition: tlb.h:108
Context_Control_fp _CPU_Null_fp_context
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:493
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66