cpu.h File Reference

NO_CPU Department Source. More...

#include <rtems/score/basedefs.h>
#include <rtems/score/no_cpu.h>

Go to the source code of this file.

Data Structures
struct	Context_Control
	Thread register context. More...
struct	Context_Control_fp
	SPARC basic context. More...
struct	CPU_Interrupt_frame
	Interrupt stack frame (ISF). More...
struct	CPU_Exception_frame
	The set of registers that specifies the complete processor state. More...

Macros
#define	CPU_SIMPLE_VECTORED_INTERRUPTS   TRUE
#define	CPU_ISR_PASSES_FRAME_POINTER   FALSE
#define	CPU_HARDWARE_FP   FALSE
#define	CPU_SOFTWARE_FP   FALSE
#define	CPU_ALL_TASKS_ARE_FP   TRUE
#define	CPU_IDLE_TASK_IS_FP   FALSE
#define	CPU_USE_DEFERRED_FP_SWITCH   TRUE
#define	CPU_ENABLE_ROBUST_THREAD_DISPATCH   FALSE
	Enables a robust thread dispatch if set to TRUE. More...
#define	CPU_STACK_GROWS_UP   TRUE
#define	CPU_CACHE_LINE_BYTES   32
#define	CPU_STRUCTURE_ALIGNMENT   RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
#define	CPU_MODES_INTERRUPT_MASK   0x00000001
#define	CPU_MAXIMUM_PROCESSORS   32
	Maximum number of processors of all systems supported by this CPU port.
#define	_CPU_Context_Get_SP(_context)   (_context)->stack_pointer
#define	CPU_CONTEXT_FP_SIZE   sizeof( Context_Control_fp )
#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   0
#define	CPU_INTERRUPT_NUMBER_OF_VECTORS   32
#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER   (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
#define	CPU_STACK_MINIMUM_SIZE   (1024*4)
#define	CPU_SIZEOF_POINTER   4
#define	CPU_ALIGNMENT   8
#define	CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
#define	CPU_STACK_ALIGNMENT   0
#define	CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
#define	_CPU_Initialize_vectors()
#define	_CPU_ISR_Disable(_isr_cookie)
#define	_CPU_ISR_Enable(_isr_cookie)
#define	_CPU_ISR_Flash(_isr_cookie)
#define	_CPU_ISR_Set_level(new_level)
#define	_CPU_Context_Destroy(_the_thread, _the_context)
#define	_CPU_Context_Initialize(_the_context, _stack_base, _size, _isr, _entry_point, _is_fp, _tls_area)
#define	_CPU_Context_Restart_self(_the_context)   _CPU_Context_restore( (_the_context) );
#define	_CPU_Context_Initialize_fp(_destination)
#define	_CPU_Fatal_halt(_source, _error)
#define	CPU_USE_GENERIC_BITFIELD_CODE   TRUE
#define	_CPU_Bitfield_Find_first_bit(_value, _output)
#define	_CPU_Priority_Mask(_bit_number)   ( 1 << (_bit_number) )
#define	_CPU_Priority_bits_index(_priority)   (_priority)
#define	CPU_swap_u16(value)   (((value&0xff) << 8) | ((value >> 8)&0xff))

Typedefs
typedef void(*	CPU_ISR_raw_handler) (void)
typedef void(*	CPU_ISR_handler) (uint32_t)
typedef uint32_t	CPU_Counter_ticks
	Unsigned integer type for CPU counter values.

Functions
RTEMS_INLINE_ROUTINE bool	_CPU_ISR_Is_enabled (uint32_t level)
	Returns true if interrupts are enabled in the specified ISR level, otherwise returns false. More...
uint32_t	_CPU_ISR_Get_level (void)
	Returns the interrupt level of the executing thread. More...
void	_CPU_Initialize (void)
	CPU initialization. More...
void	_CPU_ISR_install_raw_handler (uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
void	_CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
void *	_CPU_Thread_Idle_body (uintptr_t ignored)
void	_CPU_Context_switch (Context_Control *run, Context_Control *heir)
	CPU switch context. More...
void	_CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
void	_CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
void	_CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)
	Prints the exception frame via printk(). More...
uint32_t	_CPU_Counter_frequency (void)
	Returns the current CPU counter frequency in Hz. More...
CPU_Counter_ticks	_CPU_Counter_read (void)
	Returns the current CPU counter value. More...

Variables
Context_Control_fp	_CPU_Null_fp_context

Detailed Description

NO_CPU Department Source.

This include file contains information pertaining to the NO_CPU processor.

Macro Definition Documentation

_CPU_Context_Destroy

#define _CPU_Context_Destroy	(		_the_thread,
			_the_context
	)

Value:

{ \
  }

_CPU_Context_Initialize

#define _CPU_Context_Initialize	(		_the_context,
			_stack_base,
			_size,
			_isr,
			_entry_point,
			_is_fp,
			_tls_area
	)

Value:

{ \
  }

_CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp

(

_destination

)

Value:

{ \
   *(*(_destination)) = _CPU_Null_fp_context; \
  }

This routine initializes the FP context area passed to it to. There are a few standard ways in which to initialize the floating point context. The code included for this macro assumes that this is a CPU in which a "initial" FP context was saved into _CPU_Null_fp_context and it simply copies it to the destination context passed to it.

Other floating point context save/restore models include:

1. not doing anything, and
2. putting a "null FP status word" in the correct place in the FP context.

Parameters

[in]

_destination

is the floating point context area

Port Specific Information:

XXX document implementation including references if appropriate

_CPU_Context_Restart_self

#define _CPU_Context_Restart_self

(

_the_context

)

_CPU_Context_restore( (_the_context) );

This routine is responsible for somehow restarting the currently executing task. If you are lucky, then all that is necessary is restoring the context. Otherwise, there will need to be a special assembly routine which does something special in this case. For many ports, simply adding a label to the restore path of _CPU_Context_switch will work. On other ports, it may be possibly to load a few arguments and jump to the restore path. It will not work if restarting self conflicts with the stack frame assumptions of restoring a context.

Port Specific Information:

XXX document implementation including references if appropriate

_CPU_Fatal_halt

#define _CPU_Fatal_halt	(		_source,
			_error
	)

Value:

{ \
  }

This routine copies _error into a known place – typically a stack location or a register, optionally disables interrupts, and halts/stops the CPU.

Port Specific Information:

XXX document implementation including references if appropriate

_CPU_ISR_Disable

#define _CPU_ISR_Disable

(

_isr_cookie

)

Value:

{ \
    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
  }

_CPU_ISR_Enable

#define _CPU_ISR_Enable

(

_isr_cookie

)

Value:

{ \
  }

_CPU_ISR_Flash

#define _CPU_ISR_Flash

(

_isr_cookie

)

Value:

{ \
  }

_CPU_ISR_Set_level

#define _CPU_ISR_Set_level

(

new_level

)

Value:

{ \
  }

_CPU_Priority_Mask

#define _CPU_Priority_Mask

(

_bit_number

)

( 1 << (_bit_number) )

This routine builds the mask which corresponds to the bit fields as searched by _CPU_Bitfield_Find_first_bit. See the discussion for that routine.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_ALIGNMENT

#define CPU_ALIGNMENT   8

CPU's worst alignment requirement for data types on a byte boundary. This alignment does not take into account the requirements for the stack. It must be a power of two greater than or equal to two. The power of two requirement makes it possible to align values easily using simple bit operations.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_ALL_TASKS_ARE_FP

#define CPU_ALL_TASKS_ARE_FP   TRUE

Are all tasks RTEMS_FLOATING_POINT tasks implicitly?

If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.

So far, the only CPUs in which this option has been used are the HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and gcc both implicitly used the floating point registers to perform integer multiplies. Similarly, the PowerPC port of gcc has been seen to allocate floating point local variables and touch the FPU even when the flow through a subroutine (like vfprintf()) might not use floating point formats.

If a function which you would not think utilize the FP unit DOES, then one can not easily predict which tasks will use the FP hardware. In this case, this option should be TRUE.

If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_CACHE_LINE_BYTES

#define CPU_CACHE_LINE_BYTES   32

The maximum cache line size in bytes.

The actual processor may use no cache or a smaller cache line size.

CPU_ENABLE_ROBUST_THREAD_DISPATCH

#define CPU_ENABLE_ROBUST_THREAD_DISPATCH   FALSE

Enables a robust thread dispatch if set to TRUE.

In general, it is an application bug to call blocking operating system services with interrupts disabled. In most situations this only increases the interrupt latency. However, on SMP configurations or on some CPU port like ARM Cortex-M it leads to undefined system behaviour. It order to ease the application development, this error condition is checked at run-time in case this CPU port option is defined to TRUE.

CPU_HARDWARE_FP

#define CPU_HARDWARE_FP   FALSE

Does the CPU have hardware floating point?

If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.

If there is a FP coprocessor such as the i387 or mc68881, then the answer is TRUE.

The macro name "NO_CPU_HAS_FPU" should be made CPU specific. It indicates whether or not this CPU model has FP support. For example, it would be possible to have an i386_nofp CPU model which set this to false to indicate that you have an i386 without an i387 and wish to leave floating point support out of RTEMS.

CPU_HEAP_ALIGNMENT

#define CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT

This number corresponds to the byte alignment requirement for the heap handler. This alignment requirement may be stricter than that for the data types alignment specified by CPU_ALIGNMENT. It is common for the heap to follow the same alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, then this should be set to CPU_ALIGNMENT.

NOTE: It must be a power of two greater than or equal to two. The requirement to be a multiple of two is because the heap uses the least significant field of the front and back flags to indicate that a block is in use or free. So you do not want any odd length blocks really putting length data in that bit.

On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will have to be greater or equal to than CPU_ALIGNMENT to ensure that elements allocated from the heap meet all restrictions.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_IDLE_TASK_IS_FP

#define CPU_IDLE_TASK_IS_FP   FALSE

Should the IDLE task have a floating point context?

If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task and it has a floating point context which is switched in and out. If FALSE, then the IDLE task does not have a floating point context.

Setting this to TRUE negatively impacts the time required to preempt the IDLE task from an interrupt because the floating point context must be saved as part of the preemption.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_INTERRUPT_STACK_ALIGNMENT

#define CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES

The alignment of the interrupt stack in bytes.

The alignment should take the stack ABI and the cache line size into account.

CPU_ISR_PASSES_FRAME_POINTER

#define CPU_ISR_PASSES_FRAME_POINTER   FALSE

Does the RTEMS invoke the user's ISR with the vector number and a pointer to the saved interrupt frame (1) or just the vector number (0)?

Port Specific Information:

XXX document implementation including references if appropriate

CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread. Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_SIMPLE_VECTORED_INTERRUPTS

#define CPU_SIMPLE_VECTORED_INTERRUPTS   TRUE

Does the CPU follow the simple vectored interrupt model?

If TRUE, then RTEMS allocates the vector table it internally manages. If FALSE, then the BSP is assumed to allocate and manage the vector table

Port Specific Information:

XXX document implementation including references if appropriate

CPU_SIZEOF_POINTER

#define CPU_SIZEOF_POINTER   4

Size of a pointer.

This must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code.

CPU_SOFTWARE_FP

#define CPU_SOFTWARE_FP   FALSE

Does the CPU have no hardware floating point and GCC provides a software floating point implementation which must be context switched?

This feature conditional is used to indicate whether or not there is software implemented floating point that must be context switched. The determination of whether or not this applies is very tool specific and the state saved/restored is also compiler specific.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_STACK_ALIGNMENT

#define CPU_STACK_ALIGNMENT   0

This number corresponds to the byte alignment requirement for the stack. This alignment requirement may be stricter than that for the data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the stack, then this should be set to 0.

NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_STACK_GROWS_UP

#define CPU_STACK_GROWS_UP   TRUE

Does the stack grow up (toward higher addresses) or down (toward lower addresses)?

If TRUE, then the grows upward. If FALSE, then the grows toward smaller addresses.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_STRUCTURE_ALIGNMENT

#define CPU_STRUCTURE_ALIGNMENT   RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )

The following is the variable attribute used to force alignment of critical RTEMS structures. On some processors it may make sense to have these aligned on tighter boundaries than the minimum requirements of the compiler in order to have as much of the critical data area as possible in a cache line.

Port Specific Information:

XXX document implementation including references if appropriate

CPU_USE_DEFERRED_FP_SWITCH

#define CPU_USE_DEFERRED_FP_SWITCH   TRUE

Should the saving of the floating point registers be deferred until a context switch is made to another different floating point task?

If TRUE, then the floating point context will not be stored until necessary. It will remain in the floating point registers and not disturned until another floating point task is switched to.

If FALSE, then the floating point context is saved when a floating point task is switched out and restored when the next floating point task is restored. The state of the floating point registers between those two operations is not specified.

If the floating point context does NOT have to be saved as part of interrupt dispatching, then it should be safe to set this to TRUE.

Setting this flag to TRUE results in using a different algorithm for deciding when to save and restore the floating point context. The deferred FP switch algorithm minimizes the number of times the FP context is saved and restored. The FP context is not saved until a context switch is made to another, different FP task. Thus in a system with only one FP task, the FP context will never be saved or restored.

Port Specific Information:

XXX document implementation including references if appropriate

Variable Documentation

_CPU_Null_fp_context

Context_Control_fp _CPU_Null_fp_context

This variable is optional. It is used on CPUs on which it is difficult to generate an "uninitialized" FP context. It is filled in by _CPU_Initialize and copied into the task's FP context area during _CPU_Context_Initialize.

Port Specific Information:

XXX document implementation including references if appropriate