RTEMS  5.1
Modules | Files | Data Structures | Macros | Typedefs | Functions

ARM Architecture Support. More...

Modules

 ARM Assembler Support
 ARM Assembler Support.
 
 ARM Co-Processor 15 Support
 ARM co-processor 15 (CP15) support.
 
 ARM Paravirtualization Support
 

Files

file  cpu.c
 ARM architecture support implementation.
 
file  cpu_asm.h
 ARM Assembler Support API.
 

Data Structures

struct  Context_Control
 Thread register context. More...
 
struct  ARM_VFP_context
 
struct  CPU_Exception_frame
 The set of registers that specifies the complete processor state. More...
 

Macros

#define CPU_MODEL_NAME   "ARMv4"
 
#define ARM_MULTILIB_ARCH_V4
 
#define CPU_NAME   "ARM"
 
#define CPU_SIMPLE_VECTORED_INTERRUPTS   FALSE
 
#define CPU_ISR_PASSES_FRAME_POINTER   FALSE
 
#define CPU_HARDWARE_FP   FALSE
 
#define CPU_SOFTWARE_FP   FALSE
 
#define CPU_ALL_TASKS_ARE_FP   FALSE
 
#define CPU_IDLE_TASK_IS_FP   FALSE
 
#define CPU_USE_DEFERRED_FP_SWITCH   FALSE
 
#define CPU_ENABLE_ROBUST_THREAD_DISPATCH   TRUE
 
#define CPU_STACK_GROWS_UP   FALSE
 
#define CPU_CACHE_LINE_BYTES   32
 
#define CPU_STRUCTURE_ALIGNMENT   RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
 
#define CPU_MODES_INTERRUPT_MASK   0x1
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   0
 
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
 
#define CPU_STACK_MINIMUM_SIZE   (1024 * 4)
 
#define CPU_SIZEOF_POINTER   4
 
#define CPU_ALIGNMENT   8
 
#define CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
 
#define CPU_STACK_ALIGNMENT   8
 
#define CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
 
#define CPU_USE_GENERIC_BITFIELD_CODE   TRUE
 
#define CPU_MAXIMUM_PROCESSORS   32
 
#define ARM_EXCEPTION_FRAME_SIZE   80
 
#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET   52
 
#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET   72
 
#define ARM_VFP_CONTEXT_SIZE   264
 
#define _CPU_ISR_Disable(_isr_cookie)
 
#define _CPU_ISR_Enable(_isr_cookie)   arm_interrupt_enable( _isr_cookie )
 
#define _CPU_ISR_Flash(_isr_cookie)   arm_interrupt_flash( _isr_cookie )
 
#define _CPU_Context_Get_SP(_context)   (_context)->register_sp
 
#define _CPU_Context_Restart_self(_the_context)   _CPU_Context_restore( (_the_context) );
 
#define _CPU_Context_Initialize_fp(_destination)
 
#define _CPU_Fatal_halt(_source, _err)
 
#define CPU_PER_CPU_CONTROL_SIZE   0
 

Typedefs

typedef void(* CPU_ISR_handler) (void)
 
typedef uint32_t CPU_Counter_ticks
 
typedef uintptr_t CPU_Uint32ptr
 

Functions

RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled (uint32_t level)
 
void _CPU_ISR_Set_level (uint32_t level)
 Sets the hardware interrupt level by the level value. More...
 
uint32_t _CPU_ISR_Get_level (void)
 
void _CPU_Context_Initialize (Context_Control *the_context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
 
void _CPU_Initialize (void)
 CPU initialization. More...
 
void _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
 
void _CPU_Context_switch (Context_Control *run, Context_Control *heir)
 CPU switch context.
 
void _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
 
uint32_t _CPU_Counter_frequency (void)
 
CPU_Counter_ticks _CPU_Counter_read (void)
 
void * _CPU_Thread_Idle_body (uintptr_t ignored)
 
void _CPU_Exception_frame_print (const CPU_Exception_frame *frame)
 
void _ARM_Exception_default (CPU_Exception_frame *frame)
 
void _CPU_Context_volatile_clobber (uintptr_t pattern)
 
void _CPU_Context_validate (uintptr_t pattern)
 
RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal (void)
 
RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation (void)
 

Detailed Description

ARM Architecture Support.

Macro Definition Documentation

◆ _CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp (   _destination)
Value:
do { \
*(*(_destination)) = _CPU_Null_fp_context; \
} while (0)
Context_Control_fp _CPU_Null_fp_context

◆ _CPU_Fatal_halt

#define _CPU_Fatal_halt (   _source,
  _err 
)
Value:
do { \
uint32_t _level; \
uint32_t _error = _err; \
_CPU_ISR_Disable( _level ); \
(void) _level; \
__asm__ volatile ("mov r0, %0\n" \
: "=r" (_error) \
: "0" (_error) \
: "r0" ); \
while (1); \
} while (0);

◆ _CPU_ISR_Disable

#define _CPU_ISR_Disable (   _isr_cookie)
Value:
do { \
_isr_cookie = arm_interrupt_disable(); \
} while (0)

Typedef Documentation

◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.

Function Documentation

◆ _CPU_Initialize()

void _CPU_Initialize ( void  )

CPU initialization.

CPU initialization.

◆ _CPU_ISR_Set_level()

void _CPU_ISR_Set_level ( uint32_t  level)

Sets the hardware interrupt level by the level value.

Parameters
[in]levelfor or1k can only range over two values: 0 (enable interrupts) and 1 (disable interrupts). In future implementations if fast context switch is implemented, the level can range from 0 to 15.
See also
OpenRISC architecture manual.