This header file defines the DSU4 register block interface. More...

#include <stdint.h>

Data Structures
struct	dsu4
	This structure defines the DSU4 register block memory map. More...

Macros
#define	DSU4_CTRL_PW 0x800U

#define	DSU4_CTRL_HL 0x400U

#define	DSU4_CTRL_PE 0x200U

#define	DSU4_CTRL_EB 0x100U

#define	DSU4_CTRL_EE 0x80U

#define	DSU4_CTRL_DM 0x40U

#define	DSU4_CTRL_BZ 0x20U

#define	DSU4_CTRL_BX 0x10U

#define	DSU4_CTRL_BS 0x8U

#define	DSU4_CTRL_BW 0x4U

#define	DSU4_CTRL_BE 0x2U

#define	DSU4_CTRL_TE 0x1U

#define	DSU4_DTTC_TIMETAG_SHIFT 0

#define	DSU4_DTTC_TIMETAG_MASK 0xffffffffU

#define	DSU4_DTTC_TIMETAG_GET(_reg)

#define	DSU4_DTTC_TIMETAG_SET(_reg, _val)

#define	DSU4_DTTC_TIMETAG(_val)

#define	DSU4_BRSS_SS_3_0_SHIFT 16

#define	DSU4_BRSS_SS_3_0_MASK 0xf0000U

#define	DSU4_BRSS_SS_3_0_GET(_reg)

#define	DSU4_BRSS_SS_3_0_SET(_reg, _val)

#define	DSU4_BRSS_SS_3_0(_val)

#define	DSU4_BRSS_BN_3_0_SHIFT 0

#define	DSU4_BRSS_BN_3_0_MASK 0xfU

#define	DSU4_BRSS_BN_3_0_GET(_reg)

#define	DSU4_BRSS_BN_3_0_SET(_reg, _val)

#define	DSU4_BRSS_BN_3_0(_val)

#define	DSU4_DBGM_DM_3_0_SHIFT 16

#define	DSU4_DBGM_DM_3_0_MASK 0xf0000U

#define	DSU4_DBGM_DM_3_0_GET(_reg)

#define	DSU4_DBGM_DM_3_0_SET(_reg, _val)

#define	DSU4_DBGM_DM_3_0(_val)

#define	DSU4_DBGM_ED_3_0_SHIFT 0

#define	DSU4_DBGM_ED_3_0_MASK 0xfU

#define	DSU4_DBGM_ED_3_0_GET(_reg)

#define	DSU4_DBGM_ED_3_0_SET(_reg, _val)

#define	DSU4_DBGM_ED_3_0(_val)

#define	DSU4_DTR_EM 0x1000U

#define	DSU4_DTR_TRAPTYPE_SHIFT 4

#define	DSU4_DTR_TRAPTYPE_MASK 0xff0U

#define	DSU4_DTR_TRAPTYPE_GET(_reg)

#define	DSU4_DTR_TRAPTYPE_SET(_reg, _val)

#define	DSU4_DTR_TRAPTYPE(_val)

#define	DSU4_DASI_ASI_SHIFT 0

#define	DSU4_DASI_ASI_MASK 0xffU

#define	DSU4_DASI_ASI_GET(_reg)

#define	DSU4_DASI_ASI_SET(_reg, _val)

#define	DSU4_DASI_ASI(_val)

#define	DSU4_ATBC_DCNT_SHIFT 16

#define	DSU4_ATBC_DCNT_MASK 0xff0000U

#define	DSU4_ATBC_DCNT_GET(_reg)

#define	DSU4_ATBC_DCNT_SET(_reg, _val)

#define	DSU4_ATBC_DCNT(_val)

#define	DSU4_ATBC_DF 0x100U

#define	DSU4_ATBC_SF 0x80U

#define	DSU4_ATBC_TE 0x40U

#define	DSU4_ATBC_TF 0x20U

#define	DSU4_ATBC_BW_SHIFT 3

#define	DSU4_ATBC_BW_MASK 0x18U

#define	DSU4_ATBC_BW_GET(_reg)

#define	DSU4_ATBC_BW_SET(_reg, _val)

#define	DSU4_ATBC_BW(_val)

#define	DSU4_ATBC_BR 0x4U

#define	DSU4_ATBC_DM 0x2U

#define	DSU4_ATBC_EN 0x1U

#define	DSU4_ATBI_INDEX_SHIFT 4

#define	DSU4_ATBI_INDEX_MASK 0xff0U

#define	DSU4_ATBI_INDEX_GET(_reg)

#define	DSU4_ATBI_INDEX_SET(_reg, _val)

#define	DSU4_ATBI_INDEX(_val)

#define	DSU4_ATBFC_WPF_SHIFT 12

#define	DSU4_ATBFC_WPF_MASK 0x3000U

#define	DSU4_ATBFC_WPF_GET(_reg)

#define	DSU4_ATBFC_WPF_SET(_reg, _val)

#define	DSU4_ATBFC_WPF(_val)

#define	DSU4_ATBFC_BPF_SHIFT 8

#define	DSU4_ATBFC_BPF_MASK 0x300U

#define	DSU4_ATBFC_BPF_GET(_reg)

#define	DSU4_ATBFC_BPF_SET(_reg, _val)

#define	DSU4_ATBFC_BPF(_val)

#define	DSU4_ATBFC_PF 0x8U

#define	DSU4_ATBFC_AF 0x4U

#define	DSU4_ATBFC_FR 0x2U

#define	DSU4_ATBFC_FW 0x1U

#define	DSU4_ATBFM_SMASK_15_0_SHIFT 16

#define	DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U

#define	DSU4_ATBFM_SMASK_15_0_GET(_reg)

#define	DSU4_ATBFM_SMASK_15_0_SET(_reg, _val)

#define	DSU4_ATBFM_SMASK_15_0(_val)

#define	DSU4_ATBFM_MMASK_15_0_SHIFT 0

#define	DSU4_ATBFM_MMASK_15_0_MASK 0xffffU

#define	DSU4_ATBFM_MMASK_15_0_GET(_reg)

#define	DSU4_ATBFM_MMASK_15_0_SET(_reg, _val)

#define	DSU4_ATBFM_MMASK_15_0(_val)

#define	DSU4_ATBBA_BADDR_31_2_SHIFT 2

#define	DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU

#define	DSU4_ATBBA_BADDR_31_2_GET(_reg)

#define	DSU4_ATBBA_BADDR_31_2_SET(_reg, _val)

#define	DSU4_ATBBA_BADDR_31_2(_val)

#define	DSU4_ATBBM_BMASK_31_2_SHIFT 2

#define	DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU

#define	DSU4_ATBBM_BMASK_31_2_GET(_reg)

#define	DSU4_ATBBM_BMASK_31_2_SET(_reg, _val)

#define	DSU4_ATBBM_BMASK_31_2(_val)

#define	DSU4_ATBBM_LD 0x2U

#define	DSU4_ATBBM_ST 0x1U

#define	DSU4_ICNT_CE 0x80000000U

#define	DSU4_ICNT_IC 0x40000000U

#define	DSU4_ICNT_PE 0x20000000U

#define	DSU4_ICNT_ICOUNT_28_0_SHIFT 0

#define	DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU

#define	DSU4_ICNT_ICOUNT_28_0_GET(_reg)

#define	DSU4_ICNT_ICOUNT_28_0_SET(_reg, _val)

#define	DSU4_ICNT_ICOUNT_28_0(_val)

#define	DSU4_AHBWPC_IN 0x40U

#define	DSU4_AHBWPC_CP 0x20U

#define	DSU4_AHBWPC_EN 0x10U

#define	DSU4_AHBWPC_IN 0x4U

#define	DSU4_AHBWPC_CP 0x2U

#define	DSU4_AHBWPC_EN 0x1U

#define	DSU4_AHBWPD_DATA_SHIFT 0

#define	DSU4_AHBWPD_DATA_MASK 0xffffffffU

#define	DSU4_AHBWPD_DATA_GET(_reg)

#define	DSU4_AHBWPD_DATA_SET(_reg, _val)

#define	DSU4_AHBWPD_DATA(_val)

#define	DSU4_AHBWPM_MASK_SHIFT 0

#define	DSU4_AHBWPM_MASK_MASK 0xffffffffU

#define	DSU4_AHBWPM_MASK_GET(_reg)

#define	DSU4_AHBWPM_MASK_SET(_reg, _val)

#define	DSU4_AHBWPM_MASK(_val)

#define	DSU4_ITBC0_TFILT_SHIFT 28

#define	DSU4_ITBC0_TFILT_MASK 0xf0000000U

#define	DSU4_ITBC0_TFILT_GET(_reg)

#define	DSU4_ITBC0_TFILT_SET(_reg, _val)

#define	DSU4_ITBC0_TFILT(_val)

#define	DSU4_ITBC0_ITPOINTER_SHIFT 0

#define	DSU4_ITBC0_ITPOINTER_MASK 0xffffU

#define	DSU4_ITBC0_ITPOINTER_GET(_reg)

#define	DSU4_ITBC0_ITPOINTER_SET(_reg, _val)

#define	DSU4_ITBC0_ITPOINTER(_val)

#define	DSU4_ITBC1_WO 0x8000000U

#define	DSU4_ITBC1_TLIM_SHIFT 24

#define	DSU4_ITBC1_TLIM_MASK 0x7000000U

#define	DSU4_ITBC1_TLIM_GET(_reg)

#define	DSU4_ITBC1_TLIM_SET(_reg, _val)

#define	DSU4_ITBC1_TLIM(_val)

#define	DSU4_ITBC1_TOV 0x800000U

Typedefs
typedef struct dsu4	dsu4
	This structure defines the DSU4 register block memory map.

Detailed Description

This header file defines the DSU4 register block interface.

Data Structures

Macros

Typedefs

Detailed Description