AHB trace buffer control register (ATBC)

This group contains register bit definitions. More...

Macros
#define	DSU4_ATBC_DCNT_SHIFT   16
#define	DSU4_ATBC_DCNT_MASK   0xff0000U
#define	DSU4_ATBC_DCNT_GET(_reg)
#define	DSU4_ATBC_DCNT_SET(_reg, _val)
#define	DSU4_ATBC_DCNT(_val)
#define	DSU4_ATBC_DF   0x100U
#define	DSU4_ATBC_SF   0x80U
#define	DSU4_ATBC_TE   0x40U
#define	DSU4_ATBC_TF   0x20U
#define	DSU4_ATBC_BW_SHIFT   3
#define	DSU4_ATBC_BW_MASK   0x18U
#define	DSU4_ATBC_BW_GET(_reg)
#define	DSU4_ATBC_BW_SET(_reg, _val)
#define	DSU4_ATBC_BW(_val)
#define	DSU4_ATBC_BR   0x4U
#define	DSU4_ATBC_DM   0x2U
#define	DSU4_ATBC_EN   0x1U

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

DSU4_ATBC_BW

#define DSU4_ATBC_BW

(

_val

)

Value:

  ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \
    DSU4_ATBC_BW_MASK )

DSU4_ATBC_BW_GET

#define DSU4_ATBC_BW_GET

(

_reg

)

Value:

  ( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> \
    DSU4_ATBC_BW_SHIFT )

DSU4_ATBC_BW_SET

#define DSU4_ATBC_BW_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~DSU4_ATBC_BW_MASK ) | \
    ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \
      DSU4_ATBC_BW_MASK ) )

DSU4_ATBC_DCNT

#define DSU4_ATBC_DCNT

(

_val

)

Value:

  ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \
    DSU4_ATBC_DCNT_MASK )

DSU4_ATBC_DCNT_GET

#define DSU4_ATBC_DCNT_GET

(

_reg

)

Value:

  ( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> \
    DSU4_ATBC_DCNT_SHIFT )

DSU4_ATBC_DCNT_SET

#define DSU4_ATBC_DCNT_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~DSU4_ATBC_DCNT_MASK ) | \
    ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \
      DSU4_ATBC_DCNT_MASK ) )