Instruction trace buffer control register 1 (ITBC1)

This group contains register bit definitions. More...

Macros
#define	DSU4_ITBC1_WO   0x8000000U
#define	DSU4_ITBC1_TLIM_SHIFT   24
#define	DSU4_ITBC1_TLIM_MASK   0x7000000U
#define	DSU4_ITBC1_TLIM_GET(_reg)
#define	DSU4_ITBC1_TLIM_SET(_reg, _val)
#define	DSU4_ITBC1_TLIM(_val)
#define	DSU4_ITBC1_TOV   0x800000U

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

DSU4_ITBC1_TLIM

#define DSU4_ITBC1_TLIM

(

_val

)

Value:

  ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \
    DSU4_ITBC1_TLIM_MASK )

DSU4_ITBC1_TLIM_GET

#define DSU4_ITBC1_TLIM_GET

(

_reg

)

Value:

  ( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> \
    DSU4_ITBC1_TLIM_SHIFT )

DSU4_ITBC1_TLIM_SET

#define DSU4_ITBC1_TLIM_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~DSU4_ITBC1_TLIM_MASK ) | \
    ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \
      DSU4_ITBC1_TLIM_MASK ) )