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ARM Co-Processor 15 Support
Internal » SuperCore » CPU Architecture Support » ARM

ARM co-processor 15 (CP15) support. More...

Files

file  arm-cp15.h
 ARM co-processor 15 (CP15) API.
 

Macros

#define ARM_CORTEX_A9_ACTL_FW   (1U << 0)
 
#define ARM_CORTEX_A9_ACTL_L2_PREFETCH_HINT_ENABLE   (1U << 1)
 
#define ARM_CORTEX_A9_ACTL_L1_PREFETCH_ENABLE   (1U << 2)
 
#define ARM_CORTEX_A9_ACTL_WRITE_FULL_LINE_OF_ZEROS_MODE   (1U << 3)
 
#define ARM_CORTEX_A9_ACTL_SMP   (1U << 6)
 
#define ARM_CORTEX_A9_ACTL_EXCL   (1U << 7)
 
#define ARM_CORTEX_A9_ACTL_ALLOC_IN_ONE_WAY   (1U << 8)
 
#define ARM_CORTEX_A9_ACTL_PARITY_ON   (1U << 9)
 
#define ARM_CP15_PMCLRSET_CYCLE_COUNTER   0x80000000
 
#define ARM_CP15_PMCR_IMP(x)   ((x) << 24)
 
#define ARM_CP15_PMCR_IDCODE(x)   ((x) << 16)
 
#define ARM_CP15_PMCR_N(x)   ((x) << 11)
 
#define ARM_CP15_PMCR_DP   (1U << 5)
 
#define ARM_CP15_PMCR_X   (1U << 4)
 
#define ARM_CP15_PMCR_D   (1U << 3)
 
#define ARM_CP15_PMCR_C   (1U << 2)
 
#define ARM_CP15_PMCR_P   (1U << 1)
 
#define ARM_CP15_PMCR_E   (1U << 0)
 

Functions

uint32_t arm_cp15_set_translation_table_entries (const void *begin, const void *end, uint32_t section_flags)
 Sets the section_flags for the address range [begin, end). More...
 
void * arm_cp15_set_exception_handler (Arm_symbolic_exception_name exception, void(*handler)(void))
 Sets the exception handler in the vector table. More...
 

MMU Defines

See section B3.8.2, "Short-descriptor format memory region attributes, without TEX remap" in the "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition".

#define ARM_MMU_SECT_BASE_SHIFT   20
 
#define ARM_MMU_SECT_BASE_MASK   (0xfffU << ARM_MMU_SECT_BASE_SHIFT)
 
#define ARM_MMU_SECT_NS   (1U << 19)
 
#define ARM_MMU_SECT_NG   (1U << 17)
 
#define ARM_MMU_SECT_S   (1U << 16)
 
#define ARM_MMU_SECT_AP_2   (1U << 15)
 
#define ARM_MMU_SECT_TEX_2   (1U << 14)
 
#define ARM_MMU_SECT_TEX_1   (1U << 13)
 
#define ARM_MMU_SECT_TEX_0   (1U << 12)
 
#define ARM_MMU_SECT_TEX_SHIFT   12
 
#define ARM_MMU_SECT_TEX_MASK   (0x3U << ARM_MMU_SECT_TEX_SHIFT)
 
#define ARM_MMU_SECT_AP_1   (1U << 11)
 
#define ARM_MMU_SECT_AP_0   (1U << 10)
 
#define ARM_MMU_SECT_AP_SHIFT   10
 
#define ARM_MMU_SECT_AP_MASK   (0x23U << ARM_MMU_SECT_AP_SHIFT)
 
#define ARM_MMU_SECT_DOMAIN_SHIFT   5
 
#define ARM_MMU_SECT_DOMAIN_MASK   (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT)
 
#define ARM_MMU_SECT_XN   (1U << 4)
 
#define ARM_MMU_SECT_C   (1U << 3)
 
#define ARM_MMU_SECT_B   (1U << 2)
 
#define ARM_MMU_SECT_PXN   (1U << 0)
 
#define ARM_MMU_SECT_DEFAULT   0x2U
 
#define ARM_MMU_SECT_GET_INDEX(mva)   (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT)
 
#define ARM_MMU_SECT_MVA_ALIGN_UP(mva)
 
#define ARM_MMU_PAGE_TABLE_BASE_SHIFT   10
 
#define ARM_MMU_PAGE_TABLE_BASE_MASK   (0x3fffffU << ARM_MMU_PAGE_TABLE_BASE_SHIFT)
 
#define ARM_MMU_PAGE_TABLE_DOMAIN_SHIFT   5
 
#define ARM_MMU_PAGE_TABLE_DOMAIN_MASK   (0xfU << ARM_MMU_PAGE_TABLE_DOMAIN_SHIFT)
 
#define ARM_MMU_PAGE_TABLE_NS   (1U << 3)
 
#define ARM_MMU_PAGE_TABLE_PXN   (1U << 2)
 
#define ARM_MMU_PAGE_TABLE_DEFAULT   0x1U
 
#define ARM_MMU_SMALL_PAGE_BASE_SHIFT   12
 
#define ARM_MMU_SMALL_PAGE_BASE_MASK   (0xfffffU << ARM_MMU_SMALL_PAGE_BASE_SHIFT)
 
#define ARM_MMU_SMALL_PAGE_NG   (1U << 11)
 
#define ARM_MMU_SMALL_PAGE_S   (1U << 10)
 
#define ARM_MMU_SMALL_PAGE_AP_2   (1U << 9)
 
#define ARM_MMU_SMALL_PAGE_TEX_2   (1U << 8)
 
#define ARM_MMU_SMALL_PAGE_TEX_1   (1U << 7)
 
#define ARM_MMU_SMALL_PAGE_TEX_0   (1U << 6)
 
#define ARM_MMU_SMALL_PAGE_TEX_SHIFT   6
 
#define ARM_MMU_SMALL_PAGE_TEX_MASK   (0x3U << ARM_MMU_SMALL_PAGE_TEX_SHIFT)
 
#define ARM_MMU_SMALL_PAGE_AP_1   (1U << 5)
 
#define ARM_MMU_SMALL_PAGE_AP_0   (1U << 4)
 
#define ARM_MMU_SMALL_PAGE_AP_SHIFT   4
 
#define ARM_MMU_SMALL_PAGE_AP_MASK   (0x23U << ARM_MMU_SMALL_PAGE_AP_SHIFT)
 
#define ARM_MMU_SMALL_PAGE_C   (1U << 3)
 
#define ARM_MMU_SMALL_PAGE_B   (1U << 2)
 
#define ARM_MMU_SMALL_PAGE_XN   (1U << 0)
 
#define ARM_MMU_SMALL_PAGE_DEFAULT   0x2U
 
#define ARM_MMU_SMALL_PAGE_GET_INDEX(mva)   (((uint32_t) (mva)) >> ARM_MMU_SMALL_PAGE_BASE_SHIFT)
 
#define ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP(mva)
 
#define ARM_MMU_SECT_FLAGS_TO_PAGE_TABLE(flags)
 
#define ARM_MMU_PAGE_TABLE_FLAGS_TO_SECT(flags)
 
#define ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE(flags)
 
#define ARM_MMU_SMALL_PAGE_FLAGS_TO_SECT(flags)
 
#define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE   4U
 
#define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT   4096U
 
#define ARM_MMU_SMALL_PAGE_TABLE_ENTRY_SIZE   4U
 
#define ARM_MMU_SMALL_PAGE_TABLE_ENTRY_COUNT   256U
 
#define ARM_MMU_DEFAULT_CLIENT_DOMAIN   15U
 
#define ARMV7_MMU_READ_ONLY
 
#define ARMV7_MMU_READ_ONLY_CACHED   (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
 
#define ARMV7_MMU_READ_WRITE
 
#define ARMV7_MMU_READ_WRITE_CACHED
 
#define ARMV7_MMU_DATA_READ_ONLY   (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0)
 
#define ARMV7_MMU_DATA_READ_ONLY_CACHED   ARMV7_MMU_READ_ONLY_CACHED
 
#define ARMV7_MMU_DATA_READ_WRITE   (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_TEX_0)
 
#define ARMV7_MMU_DATA_READ_WRITE_CACHED   ARMV7_MMU_READ_WRITE_CACHED
 
#define ARMV7_MMU_CODE   (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0)
 
#define ARMV7_MMU_CODE_CACHED   ARMV7_MMU_READ_ONLY_CACHED
 
#define ARMV7_MMU_DEVICE   (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_B)
 

Control Register Defines

#define ARM_CP15_CTRL_TE   (1U << 30)
 
#define ARM_CP15_CTRL_AFE   (1U << 29)
 
#define ARM_CP15_CTRL_TRE   (1U << 28)
 
#define ARM_CP15_CTRL_NMFI   (1U << 27)
 
#define ARM_CP15_CTRL_EE   (1U << 25)
 
#define ARM_CP15_CTRL_VE   (1U << 24)
 
#define ARM_CP15_CTRL_XP   (1U << 23)
 
#define ARM_CP15_CTRL_U   (1U << 22)
 
#define ARM_CP15_CTRL_FI   (1U << 21)
 
#define ARM_CP15_CTRL_UWXN   (1U << 20)
 
#define ARM_CP15_CTRL_WXN   (1U << 19)
 
#define ARM_CP15_CTRL_HA   (1U << 17)
 
#define ARM_CP15_CTRL_L4   (1U << 15)
 
#define ARM_CP15_CTRL_RR   (1U << 14)
 
#define ARM_CP15_CTRL_V   (1U << 13)
 
#define ARM_CP15_CTRL_I   (1U << 12)
 
#define ARM_CP15_CTRL_Z   (1U << 11)
 
#define ARM_CP15_CTRL_SW   (1U << 10)
 
#define ARM_CP15_CTRL_R   (1U << 9)
 
#define ARM_CP15_CTRL_S   (1U << 8)
 
#define ARM_CP15_CTRL_B   (1U << 7)
 
#define ARM_CP15_CTRL_CP15BEN   (1U << 5)
 
#define ARM_CP15_CTRL_C   (1U << 2)
 
#define ARM_CP15_CTRL_A   (1U << 1)
 
#define ARM_CP15_CTRL_M   (1U << 0)
 

Domain Access Control Defines

#define ARM_CP15_DAC_NO_ACCESS   0x0U
 
#define ARM_CP15_DAC_CLIENT   0x1U
 
#define ARM_CP15_DAC_MANAGER   0x3U
 
#define ARM_CP15_DAC_DOMAIN(index, val)   ((val) << (2 * index))
 

Fault Status Register Defines

#define ARM_CP15_FAULT_STATUS_MASK   0x040F
 
#define ARM_CP15_FSR_ALIGNMENT_FAULT   0x00000001
 
#define ARM_CP15_FSR_BACKGROUND_FAULT   0x0000
 
#define ARM_CP15_FSR_ACCESS_PERMISSION_FAULT   0x000D
 
#define ARM_CP15_FSR_PRECISE_EXTERNAL_ABORT_FAULT   0x0008
 
#define ARM_CP15_FSR_IMPRECISE_EXTERNAL_ABORT_FAULT   0x0406
 
#define ARM_CP15_FSR_PRECISE_PARITY_ERROR_EXCEPTION   0x0006
 
#define ARM_CP15_FSR_IMPRECISE_PARITY_ERROR_EXCEPTION   0x0408
 
#define ARM_CP15_FSR_DEBUG_EVENT   0x0002
 

CTR, Cache Type Register Defines

The format can be obtained from CP15 by call arm_cp15_cache_type_get_format(arm_cp15_get_cache_type());

#define ARM_CP15_CACHE_TYPE_FORMAT_ARMV6   0
 
#define ARM_CP15_CACHE_TYPE_FORMAT_ARMV7   4
 

CCSIDR, Cache Size ID Register Defines

#define ARM_CP15_CACHE_CSS_ID_DATA   0
 
#define ARM_CP15_CACHE_CSS_ID_INSTRUCTION   1
 
#define ARM_CP15_CACHE_CSS_LEVEL(level)   ((level) << 1)
 

Detailed Description

ARM co-processor 15 (CP15) support.

Macro Definition Documentation

◆ ARM_MMU_PAGE_TABLE_FLAGS_TO_SECT

#define ARM_MMU_PAGE_TABLE_FLAGS_TO_SECT (   flags)
Value:
(ARM_MMU_SECT_DEFAULT \
| ((flags) & ARM_MMU_PAGE_TABLE_DOMAIN_MASK) \
| (((flags) & ARM_MMU_PAGE_TABLE_NS) << 16) \
| (((flags) & ARM_MMU_PAGE_TABLE_PXN) >> 2))

◆ ARM_MMU_SECT_FLAGS_TO_PAGE_TABLE

#define ARM_MMU_SECT_FLAGS_TO_PAGE_TABLE (   flags)
Value:
(ARM_MMU_PAGE_TABLE_DEFAULT \
| ((flags) & ARM_MMU_SECT_DOMAIN_MASK) \
| (((flags) & ARM_MMU_SECT_NS) >> 16) \
| (((flags) & ARM_MMU_SECT_PXN) << 2))

◆ ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE

#define ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE (   flags)
Value:
((((flags) & 0x3fc00) >> 6) \
| ((flags) & (ARM_MMU_SECT_C | ARM_MMU_SECT_B | 0x2)) \
| (((flags) & ARM_MMU_SECT_XN) >> 4))

◆ ARM_MMU_SECT_MVA_ALIGN_UP

#define ARM_MMU_SECT_MVA_ALIGN_UP (   mva)
Value:
((1U << ARM_MMU_SECT_BASE_SHIFT) \
+ ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U)))

◆ ARM_MMU_SMALL_PAGE_FLAGS_TO_SECT

#define ARM_MMU_SMALL_PAGE_FLAGS_TO_SECT (   flags)
Value:
((((flags) & 0xff0) << 6) \
| ((flags) & (ARM_MMU_SMALL_PAGE_C | ARM_MMU_SMALL_PAGE_B | 0x2)) \
| (((flags) & ARM_MMU_SMALL_PAGE_XN) << 4))

◆ ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP

#define ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP (   mva)
Value:
((1U << ARM_MMU_SMALL_PAGE_BASE_SHIFT) \
+ ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SMALL_PAGE_BASE_SHIFT) - 1U)))

◆ ARMV7_MMU_READ_ONLY

#define ARMV7_MMU_READ_ONLY
Value:
((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
| ARM_MMU_SECT_AP_0 \
| ARM_MMU_SECT_AP_2 \
| ARM_MMU_SECT_DEFAULT)

◆ ARMV7_MMU_READ_WRITE

#define ARMV7_MMU_READ_WRITE
Value:
((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
| ARM_MMU_SECT_AP_0 \
| ARM_MMU_SECT_DEFAULT)

◆ ARMV7_MMU_READ_WRITE_CACHED

#define ARMV7_MMU_READ_WRITE_CACHED
Value:
(ARMV7_MMU_READ_WRITE \
| ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B)

Function Documentation

◆ arm_cp15_set_exception_handler()

void* arm_cp15_set_exception_handler ( Arm_symbolic_exception_name  exception,
void(*)(void)  handler 
)

Sets the exception handler in the vector table.

Returns
Previous handler.

◆ arm_cp15_set_translation_table_entries()

uint32_t arm_cp15_set_translation_table_entries ( const void *  begin,
const void *  end,
uint32_t  section_flags 
)

Sets the section_flags for the address range [begin, end).

Returns
Previous section flags of the first modified entry.
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