RTEMS
5.1
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Blackfin CPU Department Source. More...
Go to the source code of this file.
Data Structures | |
struct | Context_Control |
Thread register context. More... | |
struct | CPU_Interrupt_frame |
Interrupt stack frame (ISF). More... | |
Macros | |
#define | CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
#define | CPU_ISR_PASSES_FRAME_POINTER TRUE |
#define | CPU_HARDWARE_FP FALSE |
#define | CPU_SOFTWARE_FP FALSE |
#define | CPU_ALL_TASKS_ARE_FP FALSE |
#define | CPU_IDLE_TASK_IS_FP FALSE |
#define | CPU_USE_DEFERRED_FP_SWITCH FALSE |
#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
#define | CPU_STACK_GROWS_UP FALSE |
#define | CPU_CACHE_LINE_BYTES 32 |
#define | CPU_STRUCTURE_ALIGNMENT |
#define | CPU_MODES_INTERRUPT_MASK 0x00000001 |
#define | CPU_MAXIMUM_PROCESSORS 32 |
#define | _CPU_Context_Get_SP(_context) (_context)->register_sp |
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
#define | CPU_INTERRUPT_NUMBER_OF_VECTORS 16 |
#define | CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
#define | CPU_STACK_MINIMUM_SIZE (1024*8) |
#define | CPU_SIZEOF_POINTER 4 |
#define | CPU_ALIGNMENT 8 |
#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
#define | CPU_STACK_ALIGNMENT 8 |
#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
#define | _CPU_Initialize_vectors() |
#define | _CPU_ISR_Disable(_level) |
#define | _CPU_ISR_Enable(_level) |
#define | _CPU_ISR_Flash(_level) |
#define | _CPU_ISR_Set_level(_new_level) |
#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
#define | _CPU_Fatal_halt(_source, _error) |
#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
Typedefs | |
typedef void(* | CPU_ISR_raw_handler) (void) |
typedef void(* | CPU_ISR_handler) (uint32_t) |
typedef CPU_Interrupt_frame | CPU_Exception_frame |
typedef uint32_t | CPU_Counter_ticks |
typedef uintptr_t | CPU_Uint32ptr |
Functions | |
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level) |
uint32_t | _CPU_ISR_Get_level (void) |
void | _CPU_Context_Initialize (Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area) |
void | _CPU_Initialize (void) |
CPU initialize. This routine performs CPU dependent initialization. More... | |
void | _CPU_ISR_install_raw_handler (uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler) |
void | _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler) |
void * | _CPU_Thread_Idle_body (uintptr_t ignored) |
void | _CPU_Context_switch (Context_Control *run, Context_Control *heir) |
CPU switch context. More... | |
void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN |
void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame) |
uint32_t | _CPU_Counter_frequency (void) |
CPU_Counter_ticks | _CPU_Counter_read (void) |
Blackfin CPU Department Source.
This include file contains information pertaining to the Blackfin processor.
#define _CPU_Context_Restart_self | ( | _the_context | ) | _CPU_Context_restore( (_the_context) ); |
This routine is responsible for somehow restarting the currently executing task. If you are lucky, then all that is necessary is restoring the context. Otherwise, there will need to be a special assembly routine which does something special in this case. For many ports, simply adding a label to the restore path of _CPU_Context_switch will work. On other ports, it may be possibly to load a few arguments and jump to the restore path. It will not work if restarting self conflicts with the stack frame assumptions of restoring a context.
Port Specific Information:
XXX document implementation including references if appropriate
#define _CPU_Fatal_halt | ( | _source, | |
_error | |||
) |
This routine copies _error into a known place – typically a stack location or a register, optionally disables interrupts, and halts/stops the CPU.
Port Specific Information:
XXX document implementation including references if appropriate
#define CPU_ALIGNMENT 8 |
CPU's worst alignment requirement for data types on a byte boundary. This alignment does not take into account the requirements for the stack.
Port Specific Information:
XXX document implementation including references if appropriate
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
This number corresponds to the byte alignment requirement for the heap handler. This alignment requirement may be stricter than that for the data types alignment specified by CPU_ALIGNMENT. It is common for the heap to follow the same alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, then this should be set to CPU_ALIGNMENT.
On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will have to be greater or equal to than CPU_ALIGNMENT to ensure that elements allocated from the heap meet all restrictions.
Port Specific Information:
XXX document implementation including references if appropriate
#define CPU_ISR_PASSES_FRAME_POINTER TRUE |
Does the RTEMS invoke the user's ISR with the vector number and a pointer to the saved interrupt frame (1) or just the vector number (0)?
Port Specific Information:
XXX document implementation including references if appropriate
#define CPU_STACK_ALIGNMENT 8 |
This number corresponds to the byte alignment requirement for the stack. This alignment requirement may be stricter than that for the data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the stack, then this should be set to 0.
Port Specific Information:
XXX document implementation including references if appropriate
#define CPU_STACK_GROWS_UP FALSE |
Does the stack grow up (toward higher addresses) or down (toward lower addresses)?
If TRUE, then the grows upward. If FALSE, then the grows toward smaller addresses.
Port Specific Information:
XXX document implementation including references if appropriate
typedef uintptr_t CPU_Uint32ptr |
Type that can store a 32-bit integer or a pointer.