21 #ifndef _RTEMS_SCORE_CPU_H 22 #define _RTEMS_SCORE_CPU_H 44 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 55 #define CPU_ISR_PASSES_FRAME_POINTER TRUE 57 #define CPU_HARDWARE_FP FALSE 59 #define CPU_SOFTWARE_FP FALSE 61 #define CPU_ALL_TASKS_ARE_FP FALSE 63 #define CPU_IDLE_TASK_IS_FP FALSE 65 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 67 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 80 #define CPU_STACK_GROWS_UP FALSE 83 #define CPU_CACHE_LINE_BYTES 32 85 #define CPU_STRUCTURE_ALIGNMENT 97 #define CPU_MODES_INTERRUPT_MASK 0x00000001 99 #define CPU_MAXIMUM_PROCESSORS 32 167 uint32_t register_r4;
168 uint32_t register_r5;
169 uint32_t register_r6;
170 uint32_t register_r7;
172 uint32_t register_p3;
173 uint32_t register_p4;
174 uint32_t register_p5;
175 uint32_t register_fp;
176 uint32_t register_sp;
178 uint32_t register_rets;
183 #define _CPU_Context_Get_SP( _context ) \ 184 (_context)->register_sp 221 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 232 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 238 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 245 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 256 #define CPU_STACK_MINIMUM_SIZE (1024*8) 258 #define CPU_SIZEOF_POINTER 4 268 #define CPU_ALIGNMENT 8 293 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 308 #define CPU_STACK_ALIGNMENT 8 310 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 330 #define _CPU_Initialize_vectors() 342 #define _CPU_ISR_Disable( _level ) \ 344 __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ 359 #define _CPU_ISR_Enable( _level ) { \ 360 __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ 375 #define _CPU_ISR_Flash( _level ) { \ 376 __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ 377 : : "d"(_level) : "R0" ); \ 400 #define _CPU_ISR_Set_level( _new_level ) \ 402 __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ 457 uint32_t *stack_base,
480 #define _CPU_Context_Restart_self( _the_context ) \ 481 _CPU_Context_restore( (_the_context) ); 496 #define _CPU_Fatal_halt( _source, _error ) \ 498 __asm__ volatile ( "cli R1; \ 503 : : "r" (_error) ); \ 508 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 522 typedef void ( *CPU_ISR_raw_handler )( void );
526 CPU_ISR_raw_handler new_handler,
527 CPU_ISR_raw_handler *old_handler
530 typedef void ( *CPU_ISR_handler )( uint32_t );
534 CPU_ISR_handler new_handler,
535 CPU_ISR_handler *old_handler
621 static inline uint32_t CPU_swap_u32(
625 uint32_t byte1, byte2, byte3, byte4, swapped;
627 byte4 = (value >> 24) & 0xff;
628 byte3 = (value >> 16) & 0xff;
629 byte2 = (value >> 8) & 0xff;
630 byte1 = value & 0xff;
632 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
642 #define CPU_swap_u16( value ) \ 643 (((value&0xff) << 8) | ((value >> 8)&0xff)) 653 static inline CPU_Counter_ticks _CPU_Counter_difference(
654 CPU_Counter_ticks second,
655 CPU_Counter_ticks first
658 return second - first;
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:194
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
Blackfin Set up Basic CPU Dependency Settings Based on Compiler Settings.
Interrupt stack frame (ISF).
Definition: cpu.h:191
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:649
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
unsigned size
Definition: tte.h:74
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:493
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66