29 #ifndef _RTEMS_SCORE_CPU_H 30 #define _RTEMS_SCORE_CPU_H 33 #if defined(RTEMS_PARAVIRT) 34 #include <rtems/score/paravirt.h> 44 #if defined(ARM_MULTILIB_ARCH_V4) 46 #if defined(__thumb__) && !defined(__thumb2__) 47 #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg 48 #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" 49 #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" 50 #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) 51 #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT 53 #define ARM_SWITCH_REGISTERS 54 #define ARM_SWITCH_TO_ARM 55 #define ARM_SWITCH_BACK 56 #define ARM_SWITCH_OUTPUT 57 #define ARM_SWITCH_ADDITIONAL_OUTPUT 65 #define ARM_PSR_N (1 << 31) 66 #define ARM_PSR_Z (1 << 30) 67 #define ARM_PSR_C (1 << 29) 68 #define ARM_PSR_V (1 << 28) 69 #define ARM_PSR_Q (1 << 27) 70 #define ARM_PSR_J (1 << 24) 71 #define ARM_PSR_GE_SHIFT 16 72 #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) 73 #define ARM_PSR_E (1 << 9) 74 #define ARM_PSR_A (1 << 8) 75 #define ARM_PSR_I (1 << 7) 76 #define ARM_PSR_F (1 << 6) 77 #define ARM_PSR_T (1 << 5) 78 #define ARM_PSR_M_SHIFT 0 79 #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) 80 #define ARM_PSR_M_USR 0x10 81 #define ARM_PSR_M_FIQ 0x11 82 #define ARM_PSR_M_IRQ 0x12 83 #define ARM_PSR_M_SVC 0x13 84 #define ARM_PSR_M_ABT 0x17 85 #define ARM_PSR_M_HYP 0x1a 86 #define ARM_PSR_M_UND 0x1b 87 #define ARM_PSR_M_SYS 0x1f 96 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE 98 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 100 #define CPU_HARDWARE_FP FALSE 102 #define CPU_SOFTWARE_FP FALSE 104 #define CPU_ALL_TASKS_ARE_FP FALSE 106 #define CPU_IDLE_TASK_IS_FP FALSE 108 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 110 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE 112 #define CPU_STACK_GROWS_UP FALSE 114 #if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) 115 #define CPU_CACHE_LINE_BYTES 64 117 #define CPU_CACHE_LINE_BYTES 32 120 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) 122 #define CPU_MODES_INTERRUPT_MASK 0x1 124 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 126 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 128 #define CPU_STACK_MINIMUM_SIZE (1024 * 4) 131 #define CPU_SIZEOF_POINTER 4 134 #define CPU_ALIGNMENT 8 136 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 139 #define CPU_STACK_ALIGNMENT 8 141 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 154 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 156 #define CPU_MAXIMUM_PROCESSORS 32 158 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER 159 #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 162 #ifdef ARM_MULTILIB_VFP 163 #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 166 #ifdef ARM_MULTILIB_ARCH_V4 167 #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40 171 #if defined(ARM_MULTILIB_VFP) 172 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 173 #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER) 174 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 176 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44 180 #define ARM_EXCEPTION_FRAME_SIZE 80 182 #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 184 #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 186 #define ARM_VFP_CONTEXT_SIZE 264 195 #if defined(ARM_MULTILIB_ARCH_V4) 196 uint32_t register_r4;
197 uint32_t register_r5;
198 uint32_t register_r6;
199 uint32_t register_r7;
200 uint32_t register_r8;
201 uint32_t register_r9;
202 uint32_t register_r10;
203 uint32_t register_fp;
204 uint32_t register_sp;
205 uint32_t register_lr;
206 uint32_t isr_dispatch_disable;
207 #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) 208 uint32_t register_r4;
209 uint32_t register_r5;
210 uint32_t register_r6;
211 uint32_t register_r7;
212 uint32_t register_r8;
213 uint32_t register_r9;
214 uint32_t register_r10;
215 uint32_t register_r11;
218 uint32_t isr_nest_level;
222 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER 225 #ifdef ARM_MULTILIB_VFP 226 uint64_t register_d8;
227 uint64_t register_d9;
228 uint64_t register_d10;
229 uint64_t register_d11;
230 uint64_t register_d12;
231 uint64_t register_d13;
232 uint64_t register_d14;
233 uint64_t register_d15;
236 volatile bool is_executing;
240 static inline void _ARM_Data_memory_barrier(
void )
242 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 243 __asm__ volatile (
"dmb" : : :
"memory" );
249 static inline void _ARM_Data_synchronization_barrier(
void )
251 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 252 __asm__ volatile (
"dsb" : : :
"memory" );
258 static inline void _ARM_Instruction_synchronization_barrier(
void )
260 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 261 __asm__ volatile (
"isb" : : :
"memory" );
267 #if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE) 268 uint32_t arm_interrupt_disable(
void );
269 void arm_interrupt_enable( uint32_t level );
270 void arm_interrupt_flash( uint32_t level );
272 static inline uint32_t arm_interrupt_disable(
void )
276 #if defined(ARM_MULTILIB_ARCH_V4) 277 uint32_t arm_switch_reg;
295 "mrs %[level], cpsr\n" 296 "orr %[arm_switch_reg], %[level], #0x80\n" 297 "msr cpsr, %[arm_switch_reg]\n" 299 : [arm_switch_reg]
"=&r" (arm_switch_reg), [level]
"=&r" (level)
301 #elif defined(ARM_MULTILIB_ARCH_V7M) 302 uint32_t basepri = 0x80;
305 "mrs %[level], basepri\n" 306 "msr basepri_max, %[basepri]\n" 307 : [level]
"=&r" (level)
308 : [basepri]
"r" (basepri)
315 static inline void arm_interrupt_enable( uint32_t level )
317 #if defined(ARM_MULTILIB_ARCH_V4) 318 ARM_SWITCH_REGISTERS;
322 "msr cpsr, %[level]\n" 325 : [level]
"r" (level)
327 #elif defined(ARM_MULTILIB_ARCH_V7M) 329 "msr basepri, %[level]\n" 331 : [level]
"r" (level)
336 static inline void arm_interrupt_flash( uint32_t level )
338 #if defined(ARM_MULTILIB_ARCH_V4) 339 uint32_t arm_switch_reg;
343 "mrs %[arm_switch_reg], cpsr\n" 344 "msr cpsr, %[level]\n" 345 "msr cpsr, %[arm_switch_reg]\n" 347 : [arm_switch_reg]
"=&r" (arm_switch_reg)
348 : [level]
"r" (level)
350 #elif defined(ARM_MULTILIB_ARCH_V7M) 354 "mrs %[basepri], basepri\n" 355 "msr basepri, %[level]\n" 356 "msr basepri, %[basepri]\n" 357 : [basepri]
"=&r" (basepri)
358 : [level]
"r" (level)
364 #define _CPU_ISR_Disable( _isr_cookie ) \ 366 _isr_cookie = arm_interrupt_disable(); \ 369 #define _CPU_ISR_Enable( _isr_cookie ) \ 370 arm_interrupt_enable( _isr_cookie ) 372 #define _CPU_ISR_Flash( _isr_cookie ) \ 373 arm_interrupt_flash( _isr_cookie ) 377 #if defined(ARM_MULTILIB_ARCH_V4) 378 return ( level & 0x80 ) == 0;
379 #elif defined(ARM_MULTILIB_ARCH_V7M) 390 void *stack_area_begin,
391 size_t stack_area_size,
393 void (*entry_point)(
void ),
398 #define _CPU_Context_Get_SP( _context ) \ 399 (_context)->register_sp 402 static inline bool _CPU_Context_Get_is_executing(
409 static inline void _CPU_Context_Set_is_executing(
414 context->is_executing = is_executing;
418 #define _CPU_Context_Restart_self( _the_context ) \ 419 _CPU_Context_restore( (_the_context) ); 421 #define _CPU_Context_Initialize_fp( _destination ) \ 423 *(*(_destination)) = _CPU_Null_fp_context; \ 426 #define _CPU_Fatal_halt( _source, _err ) \ 429 uint32_t _error = _err; \ 430 _CPU_ISR_Disable( _level ); \ 432 __asm__ volatile ("mov r0, %0\n" \ 444 typedef void ( *CPU_ISR_handler )( void );
448 CPU_ISR_handler new_handler,
449 CPU_ISR_handler *old_handler
460 #if defined(ARM_MULTILIB_ARCH_V7M) 463 #define _CPU_Start_multitasking _ARMV7M_Start_multitasking 467 uint32_t _CPU_SMP_Initialize(
void );
469 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
471 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
473 void _CPU_SMP_Prepare_start_multitasking(
void );
475 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
481 "mrc p15, 0, %[mpidr], c0, c0, 5\n" 482 : [mpidr]
"=&r" (mpidr)
485 return mpidr & 0xffU;
488 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
490 static inline void _ARM_Send_event(
void )
492 __asm__ volatile (
"sev" : : :
"memory" );
495 static inline void _ARM_Wait_for_event(
void )
497 __asm__ volatile (
"wfe" : : :
"memory" );
500 static inline void _CPU_SMP_Processor_event_broadcast(
void )
502 _ARM_Data_synchronization_barrier();
506 static inline void _CPU_SMP_Processor_event_receive(
void )
508 _ARM_Wait_for_event();
509 _ARM_Data_memory_barrier();
514 static inline uint32_t CPU_swap_u32( uint32_t value )
516 #if defined(__thumb2__) 523 #elif defined(__thumb__) 524 uint32_t byte1, byte2, byte3, byte4, swapped;
526 byte4 = (value >> 24) & 0xff;
527 byte3 = (value >> 16) & 0xff;
528 byte2 = (value >> 8) & 0xff;
529 byte1 = value & 0xff;
531 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
534 uint32_t tmp = value;
535 __asm__ volatile (
"EOR %1, %0, %0, ROR #16\n" 536 "BIC %1, %1, #0xff0000\n" 537 "MOV %0, %0, ROR #8\n" 538 "EOR %0, %0, %1, LSR #8\n" 539 :
"=r" (value),
"=r" (tmp)
540 :
"0" (value),
"1" (tmp));
547 #if defined(__thumb2__) 555 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
565 static inline CPU_Counter_ticks _CPU_Counter_difference(
566 CPU_Counter_ticks second,
567 CPU_Counter_ticks first
570 return second - first;
575 #if defined(ARM_MULTILIB_ARCH_V4) 578 ARM_EXCEPTION_RESET = 0,
579 ARM_EXCEPTION_UNDEF = 1,
580 ARM_EXCEPTION_SWI = 2,
581 ARM_EXCEPTION_PREF_ABORT = 3,
582 ARM_EXCEPTION_DATA_ABORT = 4,
583 ARM_EXCEPTION_RESERVED = 5,
584 ARM_EXCEPTION_IRQ = 6,
585 ARM_EXCEPTION_FIQ = 7,
587 ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
588 } Arm_symbolic_exception_name;
593 uint32_t register_fpexc;
594 uint32_t register_fpscr;
595 uint64_t register_d0;
596 uint64_t register_d1;
597 uint64_t register_d2;
598 uint64_t register_d3;
599 uint64_t register_d4;
600 uint64_t register_d5;
601 uint64_t register_d6;
602 uint64_t register_d7;
603 uint64_t register_d8;
604 uint64_t register_d9;
605 uint64_t register_d10;
606 uint64_t register_d11;
607 uint64_t register_d12;
608 uint64_t register_d13;
609 uint64_t register_d14;
610 uint64_t register_d15;
611 uint64_t register_d16;
612 uint64_t register_d17;
613 uint64_t register_d18;
614 uint64_t register_d19;
615 uint64_t register_d20;
616 uint64_t register_d21;
617 uint64_t register_d22;
618 uint64_t register_d23;
619 uint64_t register_d24;
620 uint64_t register_d25;
621 uint64_t register_d26;
622 uint64_t register_d27;
623 uint64_t register_d28;
624 uint64_t register_d29;
625 uint64_t register_d30;
626 uint64_t register_d31;
630 uint32_t register_r0;
631 uint32_t register_r1;
632 uint32_t register_r2;
633 uint32_t register_r3;
634 uint32_t register_r4;
635 uint32_t register_r5;
636 uint32_t register_r6;
637 uint32_t register_r7;
638 uint32_t register_r8;
639 uint32_t register_r9;
640 uint32_t register_r10;
641 uint32_t register_r11;
642 uint32_t register_r12;
643 uint32_t register_sp;
646 #if defined(ARM_MULTILIB_ARCH_V4) 647 uint32_t register_cpsr;
648 Arm_symbolic_exception_name vector;
649 #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) 650 uint32_t register_xpsr;
654 uint32_t reserved_for_stack_alignment;
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:194
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
#define RTEMS_COMPILER_MEMORY_BARRIER()
Definition: basedefs.h:77
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
#define CPU_swap_u16(value)
Definition: cpu.h:642
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:493
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
ARM Assembler Support API.