cpu.h

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/*
 *  COPYRIGHT (c) 1989-2011.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.org/license/LICENSE.
 */

#ifndef _RTEMS_SCORE_CPU_H
#define _RTEMS_SCORE_CPU_H

#ifdef __cplusplus
extern "C" {
#endif

#include <rtems/score/basedefs.h>
#include <rtems/score/sparc.h>

/* conditional compilation parameters */

/*
 * The SPARC ABI is a bit special with respect to the floating point context.
 * The complete floating point context is volatile.  Thus, from an ABI point
 * of view nothing needs to be saved and restored during a context switch.
 * Instead the floating point context must be saved and restored during
 * interrupt processing.  Historically, the deferred floating point switch was
 * used for SPARC and the complete floating point context is saved and
 * restored during a context switch to the new floating point unit owner.
 * This is a bit dangerous since post-switch actions (e.g. signal handlers)
 * and context switch extensions may silently corrupt the floating point
 * context.
 *
 * The floating point unit is disabled for interrupt handlers.  Thus, in case
 * an interrupt handler uses the floating point unit then this will result in a
 * trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
 *
 * In uniprocessor configurations, a lazy floating point context switch is
 * used.  In case an active floating point thread is interrupted (PSR[EF] == 1)
 * and a thread dispatch is carried out, then this thread is registered as the
 * floating point owner.  When a floating point owner is present during a
 * context switch, the floating point unit is disabled for the heir thread
 * (PSR[EF] == 0).  The floating point disabled trap checks that the use of the
 * floating point unit is allowed and saves/restores the floating point context
 * on demand.
 *
 * In SMP configurations, the deferred floating point switch is not supported
 * in principle.  So, use here a synchronous floating point switching.
 * Synchronous means that the volatile floating point context is saved and
 * restored around a thread dispatch issued during interrupt processing.  Thus
 * post-switch actions and context switch extensions may safely use the
 * floating point unit.
 */
#if SPARC_HAS_FPU == 1
  #if defined(RTEMS_SMP)
    #define SPARC_USE_SYNCHRONOUS_FP_SWITCH
  #else
    #define SPARC_USE_LAZY_FP_SWITCH
  #endif
#endif

#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE

#define CPU_ISR_PASSES_FRAME_POINTER FALSE

#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
  #define CPU_HARDWARE_FP     TRUE
#else
  #define CPU_HARDWARE_FP     FALSE
#endif

#define CPU_SOFTWARE_FP     FALSE

#define CPU_ALL_TASKS_ARE_FP     FALSE

#define CPU_IDLE_TASK_IS_FP      FALSE

#define CPU_USE_DEFERRED_FP_SWITCH FALSE

#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE

#define CPU_STACK_GROWS_UP               FALSE

/* LEON3 systems may use a cache line size of 64 */
#define CPU_CACHE_LINE_BYTES 64

#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )

#define CPU_MODES_INTERRUPT_MASK   0x0000000F

#ifndef ASM

typedef struct {
  uint32_t    l0;
  uint32_t    l1;
  uint32_t    l2;
  uint32_t    l3;
  uint32_t    l4;
  uint32_t    l5;
  uint32_t    l6;
  uint32_t    l7;
  uint32_t    i0;
  uint32_t    i1;
  uint32_t    i2;
  uint32_t    i3;
  uint32_t    i4;
  uint32_t    i5;
  uint32_t    i6_fp;
  uint32_t    i7;
  void       *structure_return_address;

  /*
   * The following are for the callee to save the register arguments in
   * should this be necessary.
   */
  uint32_t    saved_arg0;
  uint32_t    saved_arg1;
  uint32_t    saved_arg2;
  uint32_t    saved_arg3;
  uint32_t    saved_arg4;
  uint32_t    saved_arg5;
  uint32_t    pad0;
} SPARC_Minimum_stack_frame;

#endif /* ASM */

#define CPU_STACK_FRAME_L0_OFFSET             0x00

#define CPU_STACK_FRAME_L1_OFFSET             0x04

#define CPU_STACK_FRAME_L2_OFFSET             0x08

#define CPU_STACK_FRAME_L3_OFFSET             0x0c

#define CPU_STACK_FRAME_L4_OFFSET             0x10

#define CPU_STACK_FRAME_L5_OFFSET             0x14

#define CPU_STACK_FRAME_L6_OFFSET             0x18

#define CPU_STACK_FRAME_L7_OFFSET             0x1c

#define CPU_STACK_FRAME_I0_OFFSET             0x20

#define CPU_STACK_FRAME_I1_OFFSET             0x24

#define CPU_STACK_FRAME_I2_OFFSET             0x28

#define CPU_STACK_FRAME_I3_OFFSET             0x2c

#define CPU_STACK_FRAME_I4_OFFSET             0x30

#define CPU_STACK_FRAME_I5_OFFSET             0x34

#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38

#define CPU_STACK_FRAME_I7_OFFSET             0x3c

#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40

#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44

#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48

#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c

#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50

#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54

#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58

#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c

#define CPU_MAXIMUM_PROCESSORS 32

#ifndef ASM
typedef struct Context_Control_fp Context_Control_fp;

typedef struct {
  uint32_t   g5;
  uint32_t   g7;

  double     l0_and_l1;
  uint32_t   l2;
  uint32_t   l3;
  uint32_t   l4;
  uint32_t   l5;
  uint32_t   l6;
  uint32_t   l7;

  uint32_t   i0;
  uint32_t   i1;
  uint32_t   i2;
  uint32_t   i3;
  uint32_t   i4;
  uint32_t   i5;
  uint32_t   i6_fp;
  uint32_t   i7;

  uint32_t   o6_sp;
  uint32_t   o7;

  uint32_t   psr;
  uint32_t   isr_dispatch_disable;

#if defined(SPARC_USE_LAZY_FP_SWITCH)
  Context_Control_fp *fp_context;
#endif

#if defined(RTEMS_SMP)
  volatile uint32_t is_executing;
#endif
} Context_Control;

#define _CPU_Context_Get_SP( _context ) \
  (_context)->o6_sp

#ifdef RTEMS_SMP
  static inline bool _CPU_Context_Get_is_executing(
    const Context_Control *context
  )
  {
    return context->is_executing;
  }

  static inline void _CPU_Context_Set_is_executing(
    Context_Control *context,
    bool is_executing
  )
  {
    context->is_executing = is_executing;
  }
#endif

#endif /* ASM */

/*
 *  Offsets of fields with Context_Control for assembly routines.
 */

#define G5_OFFSET    0x00

#define G7_OFFSET    0x04

#define L0_OFFSET    0x08

#define L1_OFFSET    0x0C

#define L2_OFFSET    0x10

#define L3_OFFSET    0x14

#define L4_OFFSET    0x18

#define L5_OFFSET    0x1C

#define L6_OFFSET    0x20

#define L7_OFFSET    0x24

#define I0_OFFSET    0x28

#define I1_OFFSET    0x2C

#define I2_OFFSET    0x30

#define I3_OFFSET    0x34

#define I4_OFFSET    0x38

#define I5_OFFSET    0x3C

#define I6_FP_OFFSET 0x40

#define I7_OFFSET    0x44

#define O6_SP_OFFSET 0x48

#define O7_OFFSET    0x4C

#define PSR_OFFSET   0x50

#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54

#if defined(RTEMS_SMP)
  #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
#endif

#ifndef ASM

struct Context_Control_fp {
  double      f0_f1;
  double      f2_f3;
  double      f4_f5;
  double      f6_f7;
  double      f8_f9;
  double      f10_f11;
  double      f12_f13;
  double      f14_f15;
  double      f16_f17;
  double      f18_f19;
  double      f20_f21;
  double      f22_f23;
  double      f24_f25;
  double      f26_f27;
  double      f28_f29;
  double      f30_f31;
  uint32_t    fsr;
};

#endif /* ASM */

/*
 *  Offsets of fields with Context_Control_fp for assembly routines.
 */

#define FO_F1_OFFSET     0x00

#define F2_F3_OFFSET     0x08

#define F4_F5_OFFSET     0x10

#define F6_F7_OFFSET     0x18

#define F8_F9_OFFSET     0x20

#define F1O_F11_OFFSET   0x28

#define F12_F13_OFFSET   0x30

#define F14_F15_OFFSET   0x38

#define F16_F17_OFFSET   0x40

#define F18_F19_OFFSET   0x48

#define F2O_F21_OFFSET   0x50

#define F22_F23_OFFSET   0x58

#define F24_F25_OFFSET   0x60

#define F26_F27_OFFSET   0x68

#define F28_F29_OFFSET   0x70

#define F3O_F31_OFFSET   0x78

#define FSR_OFFSET       0x80

#define CONTEXT_CONTROL_FP_SIZE 0x84

#ifndef ASM

typedef struct {
  SPARC_Minimum_stack_frame Stack_frame;
  uint32_t                 psr;
  uint32_t                 pc;
  uint32_t                 npc;
  uint32_t                 g1;
  uint32_t                 g2;
  uint32_t                 g3;
  uint32_t                 g4;
  uint32_t                 g5;
  uint32_t                 reserved_for_alignment;
  uint32_t                 g7;
  uint32_t                 i0;
  uint32_t                 i1;
  uint32_t                 i2;
  uint32_t                 i3;
  uint32_t                 i4;
  uint32_t                 i5;
  uint32_t                 i6_fp;
  uint32_t                 i7;
  uint32_t                 y;
  uint32_t                 tpc;
} CPU_Interrupt_frame;

#endif /* ASM */

#ifndef ASM

typedef struct {
  uint32_t     mov_psr_l0;
  uint32_t     sethi_of_handler_to_l4;
  uint32_t     jmp_to_low_of_handler_plus_l4;
  uint32_t     mov_vector_l3;
} CPU_Trap_table_entry;

extern const CPU_Trap_table_entry _CPU_Trap_slot_template;

#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

#endif

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024

#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256

#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511

#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100

#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)

#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )

#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

#define CPU_STACK_MINIMUM_SIZE  (1024*4)

#define CPU_SIZEOF_POINTER 4

#define CPU_ALIGNMENT      8

#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT

#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT

#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES

#ifndef ASM

/*
 *  ISR handler macros
 */

#define _CPU_Initialize_vectors()

#define _CPU_ISR_Disable( _level ) \
  (_level) = sparc_disable_interrupts()

#define _CPU_ISR_Enable( _level ) \
  sparc_enable_interrupts( _level )

#define _CPU_ISR_Flash( _level ) \
  sparc_flash_interrupts( _level )

#define _CPU_ISR_Is_enabled( _isr_cookie ) \
  sparc_interrupt_is_enabled( _isr_cookie )

RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
{
  return ( level & SPARC_PSR_PIL_MASK ) == 0;
}

#define _CPU_ISR_Set_level( _newlevel ) \
   sparc_enable_interrupts( _newlevel << 8)

uint32_t   _CPU_ISR_Get_level( void );

/* end of ISR handler macros */

/* Context handler macros */

void _CPU_Context_Initialize(
  Context_Control  *the_context,
  uint32_t         *stack_base,
  uint32_t          size,
  uint32_t          new_level,
  void             *entry_point,
  bool              is_fp,
  void             *tls_area
);

#define _CPU_Context_Initialization_at_thread_begin() \
  do { \
    __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
  } while (0)

#define _CPU_Context_Restart_self( _the_context ) \
   _CPU_Context_restore( (_the_context) );

#define _CPU_Context_Initialize_fp( _destination ) \
  do { } while ( 0 )

#define _CPU_Context_save_fp( _fp_context_ptr ) \
  do { } while ( 0 )

#define _CPU_Context_restore_fp( _fp_context_ptr ) \
  do { } while ( 0 )
/* end of Context handler macros */

/* Fatal Error manager macros */

extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
  RTEMS_NO_RETURN;

/* end of Fatal Error manager macros */

#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE

/* Bitfield handler macros */

#if ( SPARC_HAS_BITSCAN == 0 )

  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#else
  #error "scan instruction not currently supported by RTEMS!!"
#endif

/* end of Bitfield handler macros */

/* functions */

void _CPU_Initialize(void);

typedef void ( *CPU_ISR_raw_handler )( void );

void _CPU_ISR_install_raw_handler(
  uint32_t             vector,
  CPU_ISR_raw_handler  new_handler,
  CPU_ISR_raw_handler *old_handler
);

typedef void ( *CPU_ISR_handler )( uint32_t );

void _CPU_ISR_install_vector(
  uint32_t         vector,
  CPU_ISR_handler  new_handler,
  CPU_ISR_handler *old_handler
);

void *_CPU_Thread_Idle_body( uintptr_t ignored );

void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);

void _CPU_Context_restore(
  Context_Control *new_context
) RTEMS_NO_RETURN;

#if defined(RTEMS_SMP)
  uint32_t _CPU_SMP_Initialize( void );

  bool _CPU_SMP_Start_processor( uint32_t cpu_index );

  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );

  void _CPU_SMP_Prepare_start_multitasking( void );

  #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
    static inline uint32_t _CPU_SMP_Get_current_processor( void )
    {
      return _LEON3_Get_current_processor();
    }
  #else
    uint32_t _CPU_SMP_Get_current_processor( void );
  #endif

  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );

  static inline void _CPU_SMP_Processor_event_broadcast( void )
  {
    __asm__ volatile ( "" : : : "memory" );
  }

  static inline void _CPU_SMP_Processor_event_receive( void )
  {
    __asm__ volatile ( "" : : : "memory" );
  }
#endif

#if defined(SPARC_USE_LAZY_FP_SWITCH)
#define _CPU_Context_Destroy( _the_thread, _the_context ) \
  do { \
    Per_CPU_Control *cpu_self = _Per_CPU_Get(); \
    Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \
    if ( _fp_owner == _the_thread ) { \
      cpu_self->cpu_per_cpu.fp_owner = NULL; \
    } \
  } while ( 0 )
#endif

typedef struct {
  uint32_t trap;
  CPU_Interrupt_frame *isf;
} CPU_Exception_frame;

void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );

static inline uint32_t CPU_swap_u32(
  uint32_t value
)
{
  uint32_t   byte1, byte2, byte3, byte4, swapped;

  byte4 = (value >> 24) & 0xff;
  byte3 = (value >> 16) & 0xff;
  byte2 = (value >> 8)  & 0xff;
  byte1 =  value        & 0xff;

  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
  return( swapped );
}

#define CPU_swap_u16( value ) \
  (((value&0xff) << 8) | ((value >> 8)&0xff))

typedef uint32_t CPU_Counter_ticks;

uint32_t _CPU_Counter_frequency( void );

typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );

/*
 * The SPARC processors supported by RTEMS have no built-in CPU counter
 * support.  We have to use some hardware counter module for this purpose, for
 * example the GPTIMER instance used by the clock driver.  The BSP must provide
 * an implementation of the CPU counter read function.  This allows the use of
 * dynamic hardware enumeration.
 */
typedef struct {
  SPARC_Counter_read                read_isr_disabled;
  SPARC_Counter_read                read;
  volatile const CPU_Counter_ticks *counter_register;
  volatile const uint32_t          *pending_register;
  uint32_t                          pending_mask;
  CPU_Counter_ticks                 accumulated;
  CPU_Counter_ticks                 interval;
} SPARC_Counter;

extern const SPARC_Counter _SPARC_Counter;

static inline CPU_Counter_ticks _CPU_Counter_read( void )
{
  return ( *_SPARC_Counter.read )();
}

static inline CPU_Counter_ticks _CPU_Counter_difference(
  CPU_Counter_ticks second,
  CPU_Counter_ticks first
)
{
  return second - first;
}

typedef uintptr_t CPU_Uint32ptr;

#endif /* ASM */

#ifdef __cplusplus
}
#endif

#endif