RTEMS
cpu.h
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1 
10 /*
11  * COPYRIGHT (c) 1989-2011.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_CPU_H
20 #define _RTEMS_SCORE_CPU_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #include <rtems/score/basedefs.h>
27 #include <rtems/score/sparc.h>
28 
29 /* conditional compilation parameters */
30 
31 /*
32  * The SPARC ABI is a bit special with respect to the floating point context.
33  * The complete floating point context is volatile. Thus, from an ABI point
34  * of view nothing needs to be saved and restored during a context switch.
35  * Instead the floating point context must be saved and restored during
36  * interrupt processing. Historically, the deferred floating point switch was
37  * used for SPARC and the complete floating point context is saved and
38  * restored during a context switch to the new floating point unit owner.
39  * This is a bit dangerous since post-switch actions (e.g. signal handlers)
40  * and context switch extensions may silently corrupt the floating point
41  * context.
42  *
43  * The floating point unit is disabled for interrupt handlers. Thus, in case
44  * an interrupt handler uses the floating point unit then this will result in a
45  * trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
46  *
47  * In uniprocessor configurations, a lazy floating point context switch is
48  * used. In case an active floating point thread is interrupted (PSR[EF] == 1)
49  * and a thread dispatch is carried out, then this thread is registered as the
50  * floating point owner. When a floating point owner is present during a
51  * context switch, the floating point unit is disabled for the heir thread
52  * (PSR[EF] == 0). The floating point disabled trap checks that the use of the
53  * floating point unit is allowed and saves/restores the floating point context
54  * on demand.
55  *
56  * In SMP configurations, the deferred floating point switch is not supported
57  * in principle. So, use here a synchronous floating point switching.
58  * Synchronous means that the volatile floating point context is saved and
59  * restored around a thread dispatch issued during interrupt processing. Thus
60  * post-switch actions and context switch extensions may safely use the
61  * floating point unit.
62  */
63 #if SPARC_HAS_FPU == 1
64  #if defined(RTEMS_SMP)
65  #define SPARC_USE_SYNCHRONOUS_FP_SWITCH
66  #else
67  #define SPARC_USE_LAZY_FP_SWITCH
68  #endif
69 #endif
70 
81 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
82 
91 #define CPU_ISR_PASSES_FRAME_POINTER FALSE
92 
101 #if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
102  #define CPU_HARDWARE_FP TRUE
103 #else
104  #define CPU_HARDWARE_FP FALSE
105 #endif
106 
111 #define CPU_SOFTWARE_FP FALSE
112 
121 #define CPU_ALL_TASKS_ARE_FP FALSE
122 
132 #define CPU_IDLE_TASK_IS_FP FALSE
133 
134 #define CPU_USE_DEFERRED_FP_SWITCH FALSE
135 
136 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
137 
147 #define CPU_STACK_GROWS_UP FALSE
148 
149 /* LEON3 systems may use a cache line size of 64 */
150 #define CPU_CACHE_LINE_BYTES 64
151 
152 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
153 
161 #define CPU_MODES_INTERRUPT_MASK 0x0000000F
162 
163 #ifndef ASM
164 
170 typedef struct {
172  uint32_t l0;
174  uint32_t l1;
176  uint32_t l2;
178  uint32_t l3;
180  uint32_t l4;
182  uint32_t l5;
184  uint32_t l6;
186  uint32_t l7;
188  uint32_t i0;
190  uint32_t i1;
192  uint32_t i2;
194  uint32_t i3;
196  uint32_t i4;
198  uint32_t i5;
200  uint32_t i6_fp;
202  uint32_t i7;
205 
206  /*
207  * The following are for the callee to save the register arguments in
208  * should this be necessary.
209  */
211  uint32_t saved_arg0;
213  uint32_t saved_arg1;
215  uint32_t saved_arg2;
217  uint32_t saved_arg3;
219  uint32_t saved_arg4;
221  uint32_t saved_arg5;
223  uint32_t pad0;
225 
226 #endif /* ASM */
227 
229 #define CPU_STACK_FRAME_L0_OFFSET 0x00
230 
231 #define CPU_STACK_FRAME_L1_OFFSET 0x04
232 
233 #define CPU_STACK_FRAME_L2_OFFSET 0x08
234 
235 #define CPU_STACK_FRAME_L3_OFFSET 0x0c
236 
237 #define CPU_STACK_FRAME_L4_OFFSET 0x10
238 
239 #define CPU_STACK_FRAME_L5_OFFSET 0x14
240 
241 #define CPU_STACK_FRAME_L6_OFFSET 0x18
242 
243 #define CPU_STACK_FRAME_L7_OFFSET 0x1c
244 
245 #define CPU_STACK_FRAME_I0_OFFSET 0x20
246 
247 #define CPU_STACK_FRAME_I1_OFFSET 0x24
248 
249 #define CPU_STACK_FRAME_I2_OFFSET 0x28
250 
251 #define CPU_STACK_FRAME_I3_OFFSET 0x2c
252 
253 #define CPU_STACK_FRAME_I4_OFFSET 0x30
254 
255 #define CPU_STACK_FRAME_I5_OFFSET 0x34
256 
257 #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38
258 
259 #define CPU_STACK_FRAME_I7_OFFSET 0x3c
260 
261 #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40
262 
263 #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44
264 
265 #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48
266 
267 #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c
268 
269 #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50
270 
271 #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54
272 
273 #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58
274 
275 #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
276 
277 #define CPU_MAXIMUM_PROCESSORS 32
278 
300 #ifndef ASM
302 
318 typedef struct {
320  uint32_t g5;
322  uint32_t g7;
323 
331  double l0_and_l1;
333  uint32_t l2;
335  uint32_t l3;
337  uint32_t l4;
339  uint32_t l5;
341  uint32_t l6;
343  uint32_t l7;
344 
346  uint32_t i0;
348  uint32_t i1;
350  uint32_t i2;
352  uint32_t i3;
354  uint32_t i4;
356  uint32_t i5;
358  uint32_t i6_fp;
360  uint32_t i7;
361 
363  uint32_t o6_sp;
368  uint32_t o7;
369 
371  uint32_t psr;
378 
379 #if defined(SPARC_USE_LAZY_FP_SWITCH)
380  Context_Control_fp *fp_context;
381 #endif
382 
383 #if defined(RTEMS_SMP)
384  volatile uint32_t is_executing;
385 #endif
387 
393 #define _CPU_Context_Get_SP( _context ) \
394  (_context)->o6_sp
395 
396 #ifdef RTEMS_SMP
397  static inline bool _CPU_Context_Get_is_executing(
398  const Context_Control *context
399  )
400  {
401  return context->is_executing;
402  }
403 
404  static inline void _CPU_Context_Set_is_executing(
405  Context_Control *context,
406  bool is_executing
407  )
408  {
409  context->is_executing = is_executing;
410  }
411 #endif
412 
413 #endif /* ASM */
414 
415 /*
416  * Offsets of fields with Context_Control for assembly routines.
417  */
418 
420 #define G5_OFFSET 0x00
421 
422 #define G7_OFFSET 0x04
423 
425 #define L0_OFFSET 0x08
426 
427 #define L1_OFFSET 0x0C
428 
429 #define L2_OFFSET 0x10
430 
431 #define L3_OFFSET 0x14
432 
433 #define L4_OFFSET 0x18
434 
435 #define L5_OFFSET 0x1C
436 
437 #define L6_OFFSET 0x20
438 
439 #define L7_OFFSET 0x24
440 
442 #define I0_OFFSET 0x28
443 
444 #define I1_OFFSET 0x2C
445 
446 #define I2_OFFSET 0x30
447 
448 #define I3_OFFSET 0x34
449 
450 #define I4_OFFSET 0x38
451 
452 #define I5_OFFSET 0x3C
453 
454 #define I6_FP_OFFSET 0x40
455 
456 #define I7_OFFSET 0x44
457 
459 #define O6_SP_OFFSET 0x48
460 
461 #define O7_OFFSET 0x4C
462 
464 #define PSR_OFFSET 0x50
465 
466 #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54
467 
468 #if defined(RTEMS_SMP)
469  #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
470 #endif
471 
472 #ifndef ASM
473 
480  double f0_f1;
482  double f2_f3;
484  double f4_f5;
486  double f6_f7;
488  double f8_f9;
490  double f10_f11;
492  double f12_f13;
494  double f14_f15;
496  double f16_f17;
498  double f18_f19;
500  double f20_f21;
502  double f22_f23;
504  double f24_f25;
506  double f26_f27;
508  double f28_f29;
510  double f30_f31;
512  uint32_t fsr;
513 };
514 
515 #endif /* ASM */
516 
517 /*
518  * Offsets of fields with Context_Control_fp for assembly routines.
519  */
520 
522 #define FO_F1_OFFSET 0x00
523 
524 #define F2_F3_OFFSET 0x08
525 
526 #define F4_F5_OFFSET 0x10
527 
528 #define F6_F7_OFFSET 0x18
529 
530 #define F8_F9_OFFSET 0x20
531 
532 #define F1O_F11_OFFSET 0x28
533 
534 #define F12_F13_OFFSET 0x30
535 
536 #define F14_F15_OFFSET 0x38
537 
538 #define F16_F17_OFFSET 0x40
539 
540 #define F18_F19_OFFSET 0x48
541 
542 #define F2O_F21_OFFSET 0x50
543 
544 #define F22_F23_OFFSET 0x58
545 
546 #define F24_F25_OFFSET 0x60
547 
548 #define F26_F27_OFFSET 0x68
549 
550 #define F28_F29_OFFSET 0x70
551 
552 #define F3O_F31_OFFSET 0x78
553 
554 #define FSR_OFFSET 0x80
555 
557 #define CONTEXT_CONTROL_FP_SIZE 0x84
558 
559 #ifndef ASM
560 
571 typedef struct {
575  uint32_t psr;
577  uint32_t pc;
579  uint32_t npc;
581  uint32_t g1;
583  uint32_t g2;
585  uint32_t g3;
587  uint32_t g4;
589  uint32_t g5;
593  uint32_t g7;
595  uint32_t i0;
597  uint32_t i1;
599  uint32_t i2;
601  uint32_t i3;
603  uint32_t i4;
605  uint32_t i5;
607  uint32_t i6_fp;
609  uint32_t i7;
611  uint32_t y;
613  uint32_t tpc;
615 
616 #endif /* ASM */
617 
618 #ifndef ASM
619 
627 typedef struct {
629  uint32_t mov_psr_l0;
635  uint32_t mov_vector_l3;
637 
648 
652 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
653 
654 #endif
655 
661 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
662 
686 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
687 
692 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
693 
698 #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
699 
703 #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
704 
708 #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 )
709 
713 #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256)
714 
719 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
720 
729 #define CPU_STACK_MINIMUM_SIZE (1024*4)
730 
734 #define CPU_SIZEOF_POINTER 4
735 
742 #define CPU_ALIGNMENT 8
743 
755 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
756 
761 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
762 
763 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
764 
765 #ifndef ASM
766 
767 /*
768  * ISR handler macros
769  */
770 
774 #define _CPU_Initialize_vectors()
775 
780 #define _CPU_ISR_Disable( _level ) \
781  (_level) = sparc_disable_interrupts()
782 
788 #define _CPU_ISR_Enable( _level ) \
789  sparc_enable_interrupts( _level )
790 
797 #define _CPU_ISR_Flash( _level ) \
798  sparc_flash_interrupts( _level )
799 
800 #define _CPU_ISR_Is_enabled( _isr_cookie ) \
801  sparc_interrupt_is_enabled( _isr_cookie )
802 
803 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
804 {
805  return ( level & SPARC_PSR_PIL_MASK ) == 0;
806 }
807 
813 #define _CPU_ISR_Set_level( _newlevel ) \
814  sparc_enable_interrupts( _newlevel << 8)
815 
823 uint32_t _CPU_ISR_Get_level( void );
824 
825 /* end of ISR handler macros */
826 
827 /* Context handler macros */
828 
851  Context_Control *the_context,
852  uint32_t *stack_base,
853  uint32_t size,
854  uint32_t new_level,
855  void *entry_point,
856  bool is_fp,
857  void *tls_area
858 );
859 
873 #define _CPU_Context_Initialization_at_thread_begin() \
874  do { \
875  __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
876  } while (0)
877 
886 #define _CPU_Context_Restart_self( _the_context ) \
887  _CPU_Context_restore( (_the_context) );
888 
892 #define _CPU_Context_Initialize_fp( _destination ) \
893  do { } while ( 0 )
894 
898 #define _CPU_Context_save_fp( _fp_context_ptr ) \
899  do { } while ( 0 )
900 
904 #define _CPU_Context_restore_fp( _fp_context_ptr ) \
905  do { } while ( 0 )
906 /* end of Context handler macros */
907 
908 /* Fatal Error manager macros */
909 
915 extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
917 
918 /* end of Fatal Error manager macros */
919 
920 #define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
921 
922 /* Bitfield handler macros */
923 
924 #if ( SPARC_HAS_BITSCAN == 0 )
925 
929  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
930 #else
931  #error "scan instruction not currently supported by RTEMS!!"
932 #endif
933 
934 /* end of Bitfield handler macros */
935 
936 /* functions */
937 
943 void _CPU_Initialize(void);
944 
945 typedef void ( *CPU_ISR_raw_handler )( void );
946 
958  uint32_t vector,
959  CPU_ISR_raw_handler new_handler,
960  CPU_ISR_raw_handler *old_handler
961 );
962 
963 typedef void ( *CPU_ISR_handler )( uint32_t );
964 
976  uint32_t vector,
977  CPU_ISR_handler new_handler,
978  CPU_ISR_handler *old_handler
979 );
980 
981 void *_CPU_Thread_Idle_body( uintptr_t ignored );
982 
992  Context_Control *run,
993  Context_Control *heir
994 );
995 
1005  Context_Control *new_context
1006 ) RTEMS_NO_RETURN;
1007 
1008 #if defined(RTEMS_SMP)
1009  uint32_t _CPU_SMP_Initialize( void );
1010 
1011  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1012 
1013  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1014 
1015  void _CPU_SMP_Prepare_start_multitasking( void );
1016 
1017  #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
1018  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1019  {
1020  return _LEON3_Get_current_processor();
1021  }
1022  #else
1023  uint32_t _CPU_SMP_Get_current_processor( void );
1024  #endif
1025 
1026  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1027 
1028  static inline void _CPU_SMP_Processor_event_broadcast( void )
1029  {
1030  __asm__ volatile ( "" : : : "memory" );
1031  }
1032 
1033  static inline void _CPU_SMP_Processor_event_receive( void )
1034  {
1035  __asm__ volatile ( "" : : : "memory" );
1036  }
1037 #endif
1038 
1039 #if defined(SPARC_USE_LAZY_FP_SWITCH)
1040 #define _CPU_Context_Destroy( _the_thread, _the_context ) \
1041  do { \
1042  Per_CPU_Control *cpu_self = _Per_CPU_Get(); \
1043  Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \
1044  if ( _fp_owner == _the_thread ) { \
1045  cpu_self->cpu_per_cpu.fp_owner = NULL; \
1046  } \
1047  } while ( 0 )
1048 #endif
1049 
1050 typedef struct {
1051  uint32_t trap;
1052  CPU_Interrupt_frame *isf;
1054 
1055 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1056 
1077 static inline uint32_t CPU_swap_u32(
1078  uint32_t value
1079 )
1080 {
1081  uint32_t byte1, byte2, byte3, byte4, swapped;
1082 
1083  byte4 = (value >> 24) & 0xff;
1084  byte3 = (value >> 16) & 0xff;
1085  byte2 = (value >> 8) & 0xff;
1086  byte1 = value & 0xff;
1087 
1088  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1089  return( swapped );
1090 }
1091 
1099 #define CPU_swap_u16( value ) \
1100  (((value&0xff) << 8) | ((value >> 8)&0xff))
1101 
1102 typedef uint32_t CPU_Counter_ticks;
1103 
1104 uint32_t _CPU_Counter_frequency( void );
1105 
1106 typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );
1107 
1108 /*
1109  * The SPARC processors supported by RTEMS have no built-in CPU counter
1110  * support. We have to use some hardware counter module for this purpose, for
1111  * example the GPTIMER instance used by the clock driver. The BSP must provide
1112  * an implementation of the CPU counter read function. This allows the use of
1113  * dynamic hardware enumeration.
1114  */
1115 typedef struct {
1116  SPARC_Counter_read read_isr_disabled;
1117  SPARC_Counter_read read;
1118  volatile const CPU_Counter_ticks *counter_register;
1119  volatile const uint32_t *pending_register;
1120  uint32_t pending_mask;
1121  CPU_Counter_ticks accumulated;
1122  CPU_Counter_ticks interval;
1123 } SPARC_Counter;
1124 
1125 extern const SPARC_Counter _SPARC_Counter;
1126 
1127 static inline CPU_Counter_ticks _CPU_Counter_read( void )
1128 {
1129  return ( *_SPARC_Counter.read )();
1130 }
1131 
1132 static inline CPU_Counter_ticks _CPU_Counter_difference(
1133  CPU_Counter_ticks second,
1134  CPU_Counter_ticks first
1135 )
1136 {
1137  return second - first;
1138 }
1139 
1141 typedef uintptr_t CPU_Uint32ptr;
1142 
1143 #endif /* ASM */
1144 
1145 #ifdef __cplusplus
1146 }
1147 #endif
1148 
1149 #endif
uint32_t g5
Definition: cpu.h:320
uint32_t g7
Definition: cpu.h:593
double f0_f1
Definition: cpu.h:480
uint32_t fsr
Definition: cpu.h:512
Definition: cpu.h:627
uint32_t i0
Definition: cpu.h:346
uint32_t l3
Definition: cpu.h:335
uint32_t mov_vector_l3
Definition: cpu.h:635
uint32_t i5
Definition: cpu.h:605
void * structure_return_address
Definition: cpu.h:204
SPARC basic context.
Definition: cpu.h:318
uint32_t isr_dispatch_disable
Definition: cpu.h:377
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:237
uint32_t saved_arg4
Definition: cpu.h:219
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Definition: cpu.c:354
uint32_t l2
Definition: cpu.h:333
uint32_t reserved_for_alignment
Definition: cpu.h:591
uint32_t mov_psr_l0
Definition: cpu.h:629
double f8_f9
Definition: cpu.h:488
Interrupt stack frame (ISF).
Definition: cpu.h:571
uint32_t saved_arg0
Definition: cpu.h:211
uint32_t g7
Definition: cpu.h:322
uint32_t i6_fp
Definition: cpu.h:358
uint32_t g3
Definition: cpu.h:585
uint32_t sethi_of_handler_to_l4
Definition: cpu.h:631
uint32_t saved_arg5
Definition: cpu.h:221
double f10_f11
Definition: cpu.h:490
double l0_and_l1
Definition: cpu.h:331
uint32_t l6
Definition: cpu.h:341
uint32_t i5
Definition: cpu.h:356
double f22_f23
Definition: cpu.h:502
uint32_t i7
Definition: cpu.h:609
uint32_t tpc
Definition: cpu.h:613
uint32_t i0
Definition: cpu.h:595
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
SPARC specific context restore.
uint32_t i2
Definition: cpu.h:599
double f4_f5
Definition: cpu.h:484
uint32_t i4
Definition: cpu.h:354
uint32_t g2
Definition: cpu.h:583
uint32_t _CPU_ISR_Get_level(void)
Obtain the current interrupt disable level.
Definition: cpu.c:191
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
SPARC specific context switch.
uint32_t i2
Definition: cpu.h:350
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:207
uint32_t psr
Definition: cpu.h:371
SPARC_Minimum_stack_frame Stack_frame
Definition: cpu.h:573
static uint32_t CPU_swap_u32(uint32_t value)
SPARC specific method to endian swap an uint32_t.
Definition: cpu.h:1077
double f2_f3
Definition: cpu.h:482
uintptr_t CPU_Uint32ptr
Definition: cpu.h:1141
double f26_f27
Definition: cpu.h:506
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: cpu.c:156
uint32_t l5
Definition: cpu.h:339
uint32_t npc
Definition: cpu.h:579
SPARC basic context.
Definition: cpu.h:478
uint32_t jmp_to_low_of_handler_plus_l4
Definition: cpu.h:633
double f12_f13
Definition: cpu.h:492
double f18_f19
Definition: cpu.h:498
double f28_f29
Definition: cpu.h:508
uint32_t l4
Definition: cpu.h:337
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
double f30_f31
Definition: cpu.h:510
double f6_f7
Definition: cpu.h:486
uint32_t g1
Definition: cpu.h:581
uint32_t saved_arg3
Definition: cpu.h:217
uint32_t i1
Definition: cpu.h:597
void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN
void _CPU_Initialize(void)
SPARC specific initialization.
Definition: cpu.c:176
uint32_t o6_sp
Definition: cpu.h:363
uint32_t psr
Definition: cpu.h:575
uint32_t i3
Definition: cpu.h:352
This header file provides basic definitions used by the API and the implementation.
double f20_f21
Definition: cpu.h:500
#define SPARC_PSR_PIL_MASK
Definition: sparc.h:127
double f24_f25
Definition: cpu.h:504
uint32_t g4
Definition: cpu.h:587
#define RTEMS_INLINE_ROUTINE
Gives a hint to the compiler in a function declaration to inline this function.
Definition: basedefs.h:683
uint32_t g5
Definition: cpu.h:589
double f16_f17
Definition: cpu.h:496
double f14_f15
Definition: cpu.h:494
uint32_t i6_fp
Definition: cpu.h:607
uint32_t i4
Definition: cpu.h:603
uint32_t pc
Definition: cpu.h:577
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.c:318
uint32_t y
Definition: cpu.h:611
uint32_t i3
Definition: cpu.h:601
uint32_t saved_arg2
Definition: cpu.h:215
uint32_t l7
Definition: cpu.h:343
uint32_t o7
Definition: cpu.h:368
uint32_t saved_arg1
Definition: cpu.h:213
uint32_t i7
Definition: cpu.h:360
uint32_t i1
Definition: cpu.h:348