Information Required to Build RTEMS for a Particular Member of the SPARC Family. More...

#include <rtems/score/basedefs.h>

Macros
#define	SPARC_HAS_BITSCAN 0

#define	SPARC_NUMBER_OF_REGISTER_WINDOWS 8

#define	SPARC_LEON3FT_B2BST_NOP

#define	SPARC_HAS_FPU 1

#define	CPU_MODEL_NAME "w/FPU"

#define	CPU_NAME "SPARC"

#define	SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */

#define	SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */

#define	SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */

#define	SPARC_PSR_S_MASK 0x00000080 /* bit 7 */

#define	SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */

#define	SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */

#define	SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */

#define	SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */

#define	SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */

#define	SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */

#define	SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */

#define	SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */

#define	SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */

#define	SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */

#define	SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */

#define	SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */

#define	SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */

#define	SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */

#define	SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */

#define	SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */

#define	LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28

#define	SPARC_SWTRAP_SYSCALL 0

#define	SPARC_SWTRAP_IRQDIS 9

#define	SPARC_SWTRAP_IRQEN 10

#define	SPARC_SWTRAP_IRQDIS_FP 11

#define	nop()

#define	sparc_get_psr(_psr)
	Macro to obtain the PSR. More...

#define	sparc_set_psr(_psr)
	Macro to set the PSR. More...

#define	sparc_get_tbr(_tbr)
	Macro to obtain the TBR. More...

#define	sparc_set_tbr(_tbr)
	Macro to set the TBR. More...

#define	sparc_get_wim(_wim)
	Macro to obtain the WIM. More...

#define	sparc_set_wim(_wim)
	Macro to set the WIM. More...

#define	sparc_get_y(_y)
	Macro to obtain the Y register. More...

#define	sparc_set_y(_y)
	Macro to set the Y register. More...

#define	sparc_flash_interrupts(_psr)
	SPARC flash processor interrupts. More...

#define	sparc_get_interrupt_level(_level)
	SPARC obtain interrupt level. More...

Functions
static uint32_t	sparc_disable_interrupts (void)
	SPARC disable processor interrupts. More...

static void	sparc_enable_interrupts (uint32_t psr)
	SPARC enable processor interrupts. More...

void	sparc_syscall_exit (uint32_t exitcode1, uint32_t exitcode2) RTEMS_NO_RETURN
	SPARC exit through system call 1. More...

static uint32_t	_LEON3_Get_current_processor (void)

Detailed Description

Information Required to Build RTEMS for a Particular Member of the SPARC Family.

This file contains the information required to build RTEMS for a particular member of the SPARC family. It does this by setting variables to indicate which implementation dependent features are present in a particular member of the family.

Definition in file sparc.h.

Macro Definition Documentation

◆ CPU_MODEL_NAME

#define CPU_MODEL_NAME "w/FPU"

This macro contains a string describing the multilib variant being build.

Definition at line 91 of file sparc.h.

◆ CPU_NAME

#define CPU_NAME "SPARC"

Define the name of the CPU family.

Definition at line 99 of file sparc.h.

◆ nop

#define nop ( )

Value:

do { \
    __asm__ volatile ( "nop" ); \
  } while ( 0 )

This macro is a standard nop instruction.

Definition at line 175 of file sparc.h.

◆ sparc_flash_interrupts

#define sparc_flash_interrupts ( _psr )

Value:

do { \
    sparc_enable_interrupts( (_psr) ); \
    _psr = sparc_disable_interrupts(); \
  } while ( 0 )

SPARC flash processor interrupts.

This method is invoked to temporarily enable all maskable interrupts.

Parameters

[in] _psr is the PSR returned by sparc_disable_interrupts.

Definition at line 378 of file sparc.h.

◆ sparc_get_interrupt_level

#define sparc_get_interrupt_level ( _level )

Value:

do { \
    uint32_t _psr_level = 0; \
    \
    sparc_get_psr( _psr_level ); \
    (_level) = \
      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
  } while ( 0 )

SPARC obtain interrupt level.

This method is invoked to obtain the current interrupt disable level.

Parameters

[in] _level is the PSR returned by sparc_disable_interrupts.

Definition at line 391 of file sparc.h.

◆ sparc_get_psr

#define sparc_get_psr ( _psr )

Value:

do { \
     (_psr) = 0; \
     __asm__ volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
  } while ( 0 )

Macro to obtain the PSR.

This macro returns the current contents of the PSR register in _psr.

Definition at line 194 of file sparc.h.

◆ sparc_get_tbr

#define sparc_get_tbr ( _tbr )

Value:

do { \
     (_tbr) = 0; /* to avoid unitialized warnings */ \
     __asm__ volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
  } while ( 0 )

Macro to obtain the TBR.

This macro returns the current contents of the TBR register in _tbr.

Definition at line 240 of file sparc.h.

◆ sparc_get_wim

#define sparc_get_wim ( _wim )

Value:

do { \
    __asm__ volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
  } while ( 0 )

Macro to obtain the WIM.

This macro returns the current contents of the WIM field in _wim.

Definition at line 274 of file sparc.h.

◆ sparc_get_y

#define sparc_get_y ( _y )

Value:

do { \
    __asm__ volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
  } while ( 0 )

Macro to obtain the Y register.

This macro returns the current contents of the Y register in _y.

Definition at line 297 of file sparc.h.

◆ SPARC_HAS_BITSCAN

#define SPARC_HAS_BITSCAN 0

Some higher end SPARCs have a bitscan instructions. It would be nice to take advantage of them. Right now, there is no port to a CPU model with this feature and no (untested) code that is based on this feature flag.

Definition at line 55 of file sparc.h.

◆ SPARC_HAS_FPU

#define SPARC_HAS_FPU 1

This macro indicates whether this multilib variation has hardware floating point or not. We use the gcc cpp predefine _SOFT_FLOAT to determine that.

Definition at line 83 of file sparc.h.

◆ SPARC_LEON3FT_B2BST_NOP

#define SPARC_LEON3FT_B2BST_NOP

See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error"

Definition at line 72 of file sparc.h.

◆ SPARC_NUMBER_OF_REGISTER_WINDOWS

#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8

This should be OK until a port to a higher end SPARC processor is made that has more than 8 register windows. If this cannot be determined based on multilib settings (v7/v8/v9), then the cpu_asm.S code that depends on this will have to move to libcpu.

Definition at line 63 of file sparc.h.

◆ SPARC_PSR_CWP_BIT_POSITION

#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */

This constant is the starting bit position of the CWP in the PSR.

Definition at line 140 of file sparc.h.

◆ SPARC_PSR_CWP_MASK

#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */

PSR masks and starting bit positions

NOTE: Reserved bits are ignored.

Definition at line 111 of file sparc.h.

◆ SPARC_PSR_EC_BIT_POSITION

#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */

This constant is the starting bit position of the EC in the PSR.

Definition at line 152 of file sparc.h.

◆ SPARC_PSR_EC_MASK

#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */

This constant is a mask for the EC bits in the PSR.

Definition at line 131 of file sparc.h.

◆ SPARC_PSR_EF_BIT_POSITION

#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */

This constant is the starting bit position of the EF in the PSR.

Definition at line 150 of file sparc.h.

◆ SPARC_PSR_EF_MASK

#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */

This constant is a mask for the EF bits in the PSR.

Definition at line 129 of file sparc.h.

◆ SPARC_PSR_ET_BIT_POSITION

#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */

This constant is the starting bit position of the ET in the PSR.

Definition at line 142 of file sparc.h.

◆ SPARC_PSR_ET_MASK

#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */

This constant is a mask for the ET bits in the PSR.

Definition at line 121 of file sparc.h.

◆ SPARC_PSR_ICC_BIT_POSITION

#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */

This constant is the starting bit position of the ICC in the PSR.

Definition at line 154 of file sparc.h.

◆ SPARC_PSR_ICC_MASK

#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */

This constant is a mask for the ICC bits in the PSR.

Definition at line 133 of file sparc.h.

◆ SPARC_PSR_IMPL_BIT_POSITION

#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */

This constant is the starting bit position of the IMPL in the PSR.

Definition at line 158 of file sparc.h.

◆ SPARC_PSR_IMPL_MASK

#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */

This constant is a mask for the IMPL bits in the PSR.

Definition at line 137 of file sparc.h.

◆ SPARC_PSR_PIL_BIT_POSITION

#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */

This constant is the starting bit position of the PIL in the PSR.

Definition at line 148 of file sparc.h.

◆ SPARC_PSR_PIL_MASK

#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */

This constant is a mask for the PIL bits in the PSR.

Definition at line 127 of file sparc.h.

◆ SPARC_PSR_PS_BIT_POSITION

#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */

This constant is the starting bit position of the PS in the PSR.

Definition at line 144 of file sparc.h.

◆ SPARC_PSR_PS_MASK

#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */

This constant is a mask for the PS bits in the PSR.

Definition at line 123 of file sparc.h.

◆ SPARC_PSR_S_BIT_POSITION

#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */

This constant is the starting bit position of the S in the PSR.

Definition at line 146 of file sparc.h.

◆ SPARC_PSR_S_MASK

#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */

This constant is a mask for the S bits in the PSR.

Definition at line 125 of file sparc.h.

◆ SPARC_PSR_VER_BIT_POSITION

#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */

This constant is the starting bit position of the VER in the PSR.

Definition at line 156 of file sparc.h.

◆ SPARC_PSR_VER_MASK

#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */

This constant is a mask for the VER bits in the PSR.

Definition at line 135 of file sparc.h.

◆ sparc_set_psr

#define sparc_set_psr ( _psr )

Value:

do { \
    __asm__ volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
    nop(); \
    nop(); \
    nop(); \
  } while ( 0 )

Macro to set the PSR.

This macro sets the PSR register to the value in _psr.

Definition at line 216 of file sparc.h.

◆ sparc_set_tbr

#define sparc_set_tbr ( _tbr )

Value:

do { \
     __asm__ volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
  } while ( 0 )

Macro to set the TBR.

This macro sets the TBR register to the value in _tbr.

Definition at line 262 of file sparc.h.

◆ sparc_set_wim

#define sparc_set_wim ( _wim )

Value:

do { \
    __asm__ volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
    nop(); \
    nop(); \
    nop(); \
  } while ( 0 )

Macro to set the WIM.

This macro sets the WIM field to the value in _wim.

Definition at line 284 of file sparc.h.

◆ sparc_set_y

#define sparc_set_y ( _y )

Value:

do { \
    __asm__ volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
  } while ( 0 )

Macro to set the Y register.

This macro sets the Y register to the value in _y.

Definition at line 307 of file sparc.h.

Function Documentation

◆ sparc_disable_interrupts()

static uint32_t sparc_disable_interrupts ( void )

inlinestatic

SPARC disable processor interrupts.

This method is invoked to disable all maskable interrupts.

Returns: This method returns the entire PSR contents.

Definition at line 319 of file sparc.h.

◆ sparc_enable_interrupts()

static void sparc_enable_interrupts ( uint32_t psr )

inlinestatic

SPARC enable processor interrupts.

This method is invoked to enable all maskable interrupts.

Parameters

[in] psr is the PSR returned by sparc_disable_interrupts.

Definition at line 333 of file sparc.h.

◆ sparc_syscall_exit()

void sparc_syscall_exit	(	uint32_t	exitcode1,
		uint32_t	exitcode2
	)

SPARC exit through system call 1.

This method is invoked to go into system error halt. The optional arguments can be given to hypervisor, hardware debugger, simulator or similar.

System error mode is entered when taking a trap when traps have been disabled. What happens when error mode is entered depends on the motherboard. In a typical development systems the CPU relingish control to the debugger, simulator, hypervisor or similar. The following steps are taken:

Going into system error mode by Software Trap 0
g1=1 (syscall 1 - Exit)
g2=Primary exit code
g3=Secondary exit code. Dependends on g2 exit type.

This function never returns.

Parameters

[in]	exitcode1	Primary exit code stored in CPU g2 register after exit
[in]	exitcode2	Primary exit code stored in CPU g3 register after exit

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ CPU_MODEL_NAME

◆ CPU_NAME

◆ nop

◆ sparc_flash_interrupts

◆ sparc_get_interrupt_level

◆ sparc_get_psr

◆ sparc_get_tbr

◆ sparc_get_wim

◆ sparc_get_y

◆ SPARC_HAS_BITSCAN

◆ SPARC_HAS_FPU

◆ SPARC_LEON3FT_B2BST_NOP

◆ SPARC_NUMBER_OF_REGISTER_WINDOWS

◆ SPARC_PSR_CWP_BIT_POSITION

◆ SPARC_PSR_CWP_MASK

◆ SPARC_PSR_EC_BIT_POSITION

◆ SPARC_PSR_EC_MASK

◆ SPARC_PSR_EF_BIT_POSITION

◆ SPARC_PSR_EF_MASK

◆ SPARC_PSR_ET_BIT_POSITION

◆ SPARC_PSR_ET_MASK

◆ SPARC_PSR_ICC_BIT_POSITION

◆ SPARC_PSR_ICC_MASK

◆ SPARC_PSR_IMPL_BIT_POSITION

◆ SPARC_PSR_IMPL_MASK

◆ SPARC_PSR_PIL_BIT_POSITION

◆ SPARC_PSR_PIL_MASK

◆ SPARC_PSR_PS_BIT_POSITION

◆ SPARC_PSR_PS_MASK

◆ SPARC_PSR_S_BIT_POSITION

◆ SPARC_PSR_S_MASK

◆ SPARC_PSR_VER_BIT_POSITION

◆ SPARC_PSR_VER_MASK

◆ sparc_set_psr

◆ sparc_set_tbr

◆ sparc_set_wim

◆ sparc_set_y

Function Documentation

◆ sparc_disable_interrupts()

◆ sparc_enable_interrupts()

◆ sparc_syscall_exit()