SPARC basic context. More...

#include <cpu.h>

Public Attributes
uint32_t	g5

uint32_t	g7

double	l0_and_l1

uint32_t	l2

uint32_t	l3

uint32_t	l4

uint32_t	l5

uint32_t	l6

uint32_t	l7

uint32_t	i0

uint32_t	i1

uint32_t	i2

uint32_t	i3

uint32_t	i4

uint32_t	i5

uint32_t	i6_fp

uint32_t	i7

uint32_t	o6_sp

uint32_t	o7

uint32_t	psr

uint32_t	isr_dispatch_disable

volatile uint32_t	is_executing

Detailed Description

SPARC basic context.

This structure defines the non-volatile integer and processor state context for the SPARC architecture according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition.

The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.

The register g6 contains the per-CPU control of the current processor. It is an invariant of the processor context. This register must not be saved and restored during context switches or interrupt services.

Definition at line 318 of file cpu.h.

Member Data Documentation

◆ g5

uint32_t Context_Control::g5

This will contain the contents of the g5 register.

Definition at line 320 of file cpu.h.

◆ g7

uint32_t Context_Control::g7

This will contain the contents of the g7 register.

Definition at line 322 of file cpu.h.

◆ i0

uint32_t Context_Control::i0

This will contain the contents of the i0 register.

Definition at line 346 of file cpu.h.

◆ i1

uint32_t Context_Control::i1

This will contain the contents of the i1 register.

Definition at line 348 of file cpu.h.

◆ i2

uint32_t Context_Control::i2

This will contain the contents of the i2 register.

Definition at line 350 of file cpu.h.

◆ i3

uint32_t Context_Control::i3

This will contain the contents of the i3 register.

Definition at line 352 of file cpu.h.

◆ i4

uint32_t Context_Control::i4

This will contain the contents of the i4 register.

Definition at line 354 of file cpu.h.

◆ i5

uint32_t Context_Control::i5

This will contain the contents of the i5 register.

Definition at line 356 of file cpu.h.

◆ i6_fp

uint32_t Context_Control::i6_fp

This will contain the contents of the i6 (e.g. frame pointer) register.

Definition at line 358 of file cpu.h.

◆ i7

uint32_t Context_Control::i7

This will contain the contents of the i7 register.

Definition at line 360 of file cpu.h.

◆ isr_dispatch_disable

uint32_t Context_Control::isr_dispatch_disable

This field is used to prevent heavy nesting of calls to _Thread_Dispatch on an interrupted task's stack. This is problematic on the slower SPARC CPU models at high interrupt rates.

Definition at line 377 of file cpu.h.

◆ l0_and_l1

double Context_Control::l0_and_l1

This will contain the contents of the l0 and l1 registers.

Using a double l0_and_l1 will put everything in this structure on a double word boundary which allows us to use double word loads and stores safely in the context switch.

Definition at line 331 of file cpu.h.

◆ l2

uint32_t Context_Control::l2

This will contain the contents of the l2 register.

Definition at line 333 of file cpu.h.

◆ l3

uint32_t Context_Control::l3

This will contain the contents of the l3 register.

Definition at line 335 of file cpu.h.

◆ l4

uint32_t Context_Control::l4

This will contain the contents of the l4 register.

Definition at line 337 of file cpu.h.

◆ l5

uint32_t Context_Control::l5

This will contain the contents of the l5 registeer.

Definition at line 339 of file cpu.h.

◆ l6

uint32_t Context_Control::l6

This will contain the contents of the l6 register.

Definition at line 341 of file cpu.h.

◆ l7

uint32_t Context_Control::l7

This will contain the contents of the l7 register.

Definition at line 343 of file cpu.h.

◆ o6_sp

uint32_t Context_Control::o6_sp

This will contain the contents of the o6 (e.g. frame pointer) register.

Definition at line 363 of file cpu.h.

◆ o7

uint32_t Context_Control::o7

This will contain the contents of the o7 (e.g. address of CALL instruction) register.

Definition at line 368 of file cpu.h.

◆ psr

uint32_t Context_Control::psr

This will contain the contents of the processor status register.

Definition at line 371 of file cpu.h.

The documentation for this struct was generated from the following file:

cpukit/score/cpu/sparc/include/rtems/score/cpu.h

Public Attributes