MIPS Architecture Support.
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#define | CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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#define | CPU_ISR_PASSES_FRAME_POINTER TRUE |
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#define | CPU_HARDWARE_FP FALSE |
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#define | CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
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#define | CPU_IDLE_TASK_IS_FP FALSE |
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#define | CPU_USE_DEFERRED_FP_SWITCH TRUE |
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#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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#define | CPU_STACK_GROWS_UP FALSE |
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#define | CPU_CACHE_LINE_BYTES 16 |
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#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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#define | CPU_MODES_INTERRUPT_MASK 0x000000ff |
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#define | CPU_SIZEOF_POINTER 4 |
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#define | CPU_MAXIMUM_PROCESSORS 32 |
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#define | _CPU_Context_Get_SP(_context) (uintptr_t) (_context)->sp |
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#define | CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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#define | CPU_STACK_MINIMUM_SIZE (8 * 1024) |
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#define | CPU_ALIGNMENT 8 |
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#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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#define | _CPU_ISR_Disable(_level) |
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#define | _CPU_ISR_Enable(_level) |
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#define | _CPU_ISR_Flash(_xlevel) |
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#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
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#define | _CPU_Context_Initialize_fp(_destination) |
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#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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#define | CPU_USE_LIBC_INIT_FINI_ARRAY FALSE |
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#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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#define | CPU_PER_CPU_CONTROL_SIZE 0 |
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#define | CPU_THREAD_LOCAL_STORAGE_VARIANT 10 |
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MIPS Architecture Support.
◆ _CPU_Context_Initialize_fp
#define _CPU_Context_Initialize_fp |
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_destination | ) |
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Value: { \
*(*(_destination)) = _CPU_Null_fp_context; \
}
◆ _CPU_ISR_Disable
#define _CPU_ISR_Disable |
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_level | ) |
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Value: do { \
unsigned int _scratch; \
mips_get_sr( _scratch ); \
mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
_level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
} while(0)
◆ _CPU_ISR_Enable
#define _CPU_ISR_Enable |
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_level | ) |
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Value: do { \
unsigned int _scratch; \
mips_get_sr( _scratch ); \
mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
} while(0)
◆ _CPU_ISR_Flash
#define _CPU_ISR_Flash |
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_xlevel | ) |
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Value: do { \
unsigned int _scratch2 = _xlevel; \
_CPU_ISR_Enable( _scratch2 ); \
_CPU_ISR_Disable( _scratch2 ); \
_xlevel = _scratch2; \
} while(0)
◆ CPU_Uint32ptr
Type that can store a 32-bit integer or a pointer.
◆ _CPU_Context_restore()
This routine is generally used only to restart self in an efficient manner. It may simply be a label in _CPU_Context_switch.
- Parameters
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[in] | new_context | points to the context to be restored. |
- Note
- May be unnecessary to reload some registers.
Port Specific Information:
XXX document implementation including references if appropriate
◆ _CPU_Context_switch()
CPU switch context.
This routine switches from the run context to the heir context.
- Parameters
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[in] | run | points to the context of the currently executing task |
[in] | heir | points to the context of the heir task |
Port Specific Information:
XXX document implementation including references if appropriate
◆ _CPU_Exception_frame_print()
This method prints the CPU exception frame.
- Parameters
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[in] | frame | points to the frame to be printed |
◆ _CPU_Initialize()
void _CPU_Initialize |
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void |
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CPU initialization.
CPU initialize. This routine performs CPU dependent initialization.
CPU initialize. This routine performs CPU dependent initialization.
CPU initialization.
◆ _CPU_ISR_Get_level()
uint32_t _CPU_ISR_Get_level |
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void |
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Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.
- Note
- This routine usually must be implemented as a subroutine.
Port Specific Information:
XXX document implementation including references if appropriate
◆ _CPU_ISR_Set_level()
void _CPU_ISR_Set_level |
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uint32_t |
level | ) |
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Sets the hardware interrupt level by the level value.
- Parameters
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[in] | level | for or1k can only range over two values: 0 (enable interrupts) and 1 (disable interrupts). In future implementations if fast context switch is implemented, the level can range from 0 to 15. |
- See also
- OpenRISC architecture manual.