RTEMS 6.3
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chip.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef SAMS7_CHIP_H
31#define SAMS7_CHIP_H
32
33#include "compiler.h"
34
35
36/*************************************************
37 * Memory type and its attribute
38 *************************************************/
39#define SHAREABLE 1
40#define NON_SHAREABLE 0
41/*********************************************************************************************************************************************************************
42* Memory Type Definition Memory TEX attribute C attribute B attribute S attribute
43**********************************************************************************************************************************************************************/
44
45#define STRONGLY_ORDERED_SHAREABLE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care //
46#define SHAREABLE_DEVICE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos)) // DO not care //
47#define INNER_OUTER_NORMAL_WT_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
48#define INNER_OUTER_NORMAL_WB_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
49#define INNER_OUTER_NORMAL_NOCACHE_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
50#define INNER_OUTER_NORMAL_WB_RWA_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
51#define NON_SHAREABLE_DEVICE_TYPE ((0x02 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care //
52
53/* Normal memory attributes with outer capability rules to Non_Cacable */
54
55#define INNER_NORMAL_NOCACHE_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
56#define INNER_NORMAL_WB_RWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
57#define INNER_NORMAL_WT_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
58#define INNER_NORMAL_WB_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))
59
60/* SCB Interrupt Control State Register Definitions */
61#ifndef SCB_VTOR_TBLBASE_Pos
62 #define SCB_VTOR_TBLBASE_Pos 29
63 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
64#endif
65
66
67/*
68 * Peripherals
69 */
70#include "include/acc.h"
71#include "include/aes.h"
72#include "include/afec.h"
73#include "include/efc.h"
74#include "include/pio.h"
75#include "include/pio_it.h"
76#include "include/efc.h"
77#include "include/rstc.h"
78#include "include/mpu.h"
79#include "include/gmac.h"
80#include "include/gmacd.h"
81#include "include/video.h"
82#include "include/icm.h"
83#include "include/isi.h"
84#include "include/exceptions.h"
85#include "include/pio_capture.h"
86#include "include/rtc.h"
87#include "include/rtt.h"
88#include "include/tc.h"
89#include "include/timetick.h"
90#include "include/twi.h"
91#include "include/flashd.h"
92#include "include/pmc.h"
93#include "include/pwmc.h"
94#include "include/mcan.h"
95#include "include/supc.h"
96#include "include/usart.h"
97#include "include/uart.h"
98#include "include/isi.h"
99#include "include/hsmci.h"
100#include "include/ssc.h"
101#include "include/twi.h"
102#include "include/trng.h"
103#include "include/wdt.h"
104#include "include/spi.h"
105#include "include/qspi.h"
106#include "include/trace.h"
107#include "include/xdmac.h"
108#include "include/xdma_hardware_interface.h"
109#include "include/xdmad.h"
110#include "include/mcid.h"
111#include "include/twid.h"
112#include "include/spi_dma.h"
113#include "include/qspi_dma.h"
114#include "include/uart_dma.h"
115#include "include/usart_dma.h"
116#include "include/twid.h"
117#include "include/afe_dma.h"
118#include "include/dac_dma.h"
119#include "include/usbhs.h"
120
121#define ENABLE_PERIPHERAL(dwId) PMC_EnablePeripheral(dwId)
122#define DISABLE_PERIPHERAL(dwId) PMC_DisablePeripheral(dwId)
123
124#endif /* SAMS7_CHIP_H */
afe_dma.h
dac_dma.h
pio_it.h
qspi_dma.h
spi_dma.h
uart_dma.h
usart_dma.h
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