cpu.h

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/*
 *  COPYRIGHT (c) 1989-2012.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.org/license/LICENSE.
 */

#ifndef _RTEMS_SCORE_CPU_H
#define _RTEMS_SCORE_CPU_H

#ifdef __cplusplus
extern "C" {
#endif

#include <rtems/score/basedefs.h>
#include <rtems/score/v850.h>

/* conditional compilation parameters */

#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE

#define CPU_HARDWARE_FP FALSE

#define CPU_SOFTWARE_FP FALSE

#define CPU_ALL_TASKS_ARE_FP FALSE

#define CPU_IDLE_TASK_IS_FP FALSE

#define CPU_USE_DEFERRED_FP_SWITCH FALSE

#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE

#define CPU_STACK_GROWS_UP               FALSE

/* FIXME: Is this the right value? */
#define CPU_CACHE_LINE_BYTES 32

#define CPU_STRUCTURE_ALIGNMENT

#define CPU_MODES_INTERRUPT_MASK   0x00000001

#define CPU_MAXIMUM_PROCESSORS 32

typedef struct {
    uint32_t   r1;
    uint32_t   r3_stack_pointer;
    uint32_t   r20;
    uint32_t   r21;
    uint32_t   r22;
    uint32_t   r23;
    uint32_t   r24;
    uint32_t   r25;
    uint32_t   r26;
    uint32_t   r27;
    uint32_t   r28;
    uint32_t   r29;
    uint32_t   r31;
    uint32_t   psw;
} Context_Control;

#define _CPU_Context_Get_SP( _context ) \
  (_context)->r3_stack_pointer

typedef struct {
    uint32_t   special_interrupt_register;
} CPU_Interrupt_frame;

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

#define CPU_STACK_MINIMUM_SIZE          (1024*4)

#define CPU_SIZEOF_POINTER 4

#define CPU_ALIGNMENT              8

#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT

#define CPU_STACK_ALIGNMENT        4

#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES

/*
 *  ISR handler macros
 */

#define _CPU_ISR_Disable( _isr_cookie ) \
  do { \
    unsigned int _psw; \
    \
    v850_get_psw( _psw ); \
    __asm__ __volatile__( "di" ); \
    _isr_cookie = _psw; \
  } while (0)

#define _CPU_ISR_Enable( _isr_cookie )  \
  do { \
    unsigned int _psw = (_isr_cookie); \
    \
    v850_set_psw( _psw ); \
  } while (0)

#define _CPU_ISR_Flash( _isr_cookie ) \
  do { \
    unsigned int _psw = (_isr_cookie); \
    v850_set_psw( _psw ); \
    __asm__ __volatile__( "di" ); \
  } while (0)

RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
{
  return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
    != V850_PSW_INTERRUPT_DISABLE;
}

#define _CPU_ISR_Set_level( new_level ) \
  do { \
    if ( new_level ) \
      __asm__ __volatile__( "di" ); \
    else \
      __asm__ __volatile__( "ei" ); \
  } while (0)

uint32_t   _CPU_ISR_Get_level( void );

/* end of ISR handler macros */

/* Context handler macros */

void _CPU_Context_Initialize(
  Context_Control  *the_context,
  uint32_t         *stack_base,
  uint32_t          size,
  uint32_t          new_level,
  void             *entry_point,
  bool              is_fp,
  void             *tls_area
);

#define _CPU_Context_Restart_self( _the_context ) \
   _CPU_Context_restore( (_the_context) );

/* XXX this should be possible to remove */
#if 0

#define _CPU_Context_Initialize_fp( _destination ) \
  { \
  }
#endif

/* end of Context handler macros */

/* Fatal Error manager macros */

#define _CPU_Fatal_halt( _source, _error ) \
  do { \
    __asm__ __volatile__ ( "di" ); \
    __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
    __asm__ __volatile__ ( "halt" ); \
  } while (0)

/* end of Fatal Error manager macros */

#define CPU_USE_GENERIC_BITFIELD_CODE TRUE

/* functions */

void _CPU_Initialize(void);

void *_CPU_Thread_Idle_body( uintptr_t ignored );

void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);

void _CPU_Context_restore(
  Context_Control *new_context
) RTEMS_NO_RETURN;

/* XXX this should be possible to remove */
#if 0

void _CPU_Context_save_fp(
  Context_Control_fp **fp_context_ptr
);
#endif

/* XXX this should be possible to remove */
#if 0

void _CPU_Context_restore_fp(
  Context_Control_fp **fp_context_ptr
);
#endif

/* FIXME */
typedef CPU_Interrupt_frame CPU_Exception_frame;

void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );

static inline uint32_t CPU_swap_u32(
  uint32_t value
)
{
  unsigned int swapped;

  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
    unsigned int v;

    v = value;
    __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
  #else
    uint32_t byte1, byte2, byte3, byte4;

    byte4 = (value >> 24) & 0xff;
    byte3 = (value >> 16) & 0xff;
    byte2 = (value >> 8)  & 0xff;
    byte1 =  value        & 0xff;

    swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
  #endif
  return swapped;
}

static inline uint16_t CPU_swap_u16( uint16_t value )
{
  unsigned int swapped;

  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
    unsigned int v;

    v = value;
    __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
  #else
    swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
  #endif
  return swapped;
}

typedef uint32_t CPU_Counter_ticks;

uint32_t _CPU_Counter_frequency( void );

CPU_Counter_ticks _CPU_Counter_read( void );

static inline CPU_Counter_ticks _CPU_Counter_difference(
  CPU_Counter_ticks second,
  CPU_Counter_ticks first
)
{
  return second - first;
}

typedef uintptr_t CPU_Uint32ptr;

#ifdef __cplusplus
}
#endif

#endif