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#define | ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) |
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#define | ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) |
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#define | ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) |
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#define | ALT_DMA_CCR_OPT_SAF (0 << 0) |
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#define | ALT_DMA_CCR_OPT_SAI (1 << 0) |
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#define | ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI |
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#define | ALT_DMA_CCR_OPT_SS8 (0 << 1) |
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#define | ALT_DMA_CCR_OPT_SS16 (1 << 1) |
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#define | ALT_DMA_CCR_OPT_SS32 (2 << 1) |
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#define | ALT_DMA_CCR_OPT_SS64 (3 << 1) |
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#define | ALT_DMA_CCR_OPT_SS128 (4 << 1) |
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#define | ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 |
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#define | ALT_DMA_CCR_OPT_SB1 (0x0 << 4) |
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#define | ALT_DMA_CCR_OPT_SB2 (0x1 << 4) |
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#define | ALT_DMA_CCR_OPT_SB3 (0x2 << 4) |
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#define | ALT_DMA_CCR_OPT_SB4 (0x3 << 4) |
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#define | ALT_DMA_CCR_OPT_SB5 (0x4 << 4) |
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#define | ALT_DMA_CCR_OPT_SB6 (0x5 << 4) |
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#define | ALT_DMA_CCR_OPT_SB7 (0x6 << 4) |
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#define | ALT_DMA_CCR_OPT_SB8 (0x7 << 4) |
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#define | ALT_DMA_CCR_OPT_SB9 (0x8 << 4) |
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#define | ALT_DMA_CCR_OPT_SB10 (0x9 << 4) |
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#define | ALT_DMA_CCR_OPT_SB11 (0xa << 4) |
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#define | ALT_DMA_CCR_OPT_SB12 (0xb << 4) |
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#define | ALT_DMA_CCR_OPT_SB13 (0xc << 4) |
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#define | ALT_DMA_CCR_OPT_SB14 (0xd << 4) |
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#define | ALT_DMA_CCR_OPT_SB15 (0xe << 4) |
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#define | ALT_DMA_CCR_OPT_SB16 (0xf << 4) |
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#define | ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 |
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#define | ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) |
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#define | ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) |
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#define | ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) |
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#define | ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) |
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#define | ALT_DMA_CCR_OPT_DAF (0 << 14) |
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#define | ALT_DMA_CCR_OPT_DAI (1 << 14) |
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#define | ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI |
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#define | ALT_DMA_CCR_OPT_DS8 (0 << 15) |
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#define | ALT_DMA_CCR_OPT_DS16 (1 << 15) |
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#define | ALT_DMA_CCR_OPT_DS32 (2 << 15) |
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#define | ALT_DMA_CCR_OPT_DS64 (3 << 15) |
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#define | ALT_DMA_CCR_OPT_DS128 (4 << 15) |
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#define | ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 |
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#define | ALT_DMA_CCR_OPT_DB1 (0x0 << 18) |
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#define | ALT_DMA_CCR_OPT_DB2 (0x1 << 18) |
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#define | ALT_DMA_CCR_OPT_DB3 (0x2 << 18) |
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#define | ALT_DMA_CCR_OPT_DB4 (0x3 << 18) |
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#define | ALT_DMA_CCR_OPT_DB5 (0x4 << 18) |
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#define | ALT_DMA_CCR_OPT_DB6 (0x5 << 18) |
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#define | ALT_DMA_CCR_OPT_DB7 (0x6 << 18) |
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#define | ALT_DMA_CCR_OPT_DB8 (0x7 << 18) |
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#define | ALT_DMA_CCR_OPT_DB9 (0x8 << 18) |
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#define | ALT_DMA_CCR_OPT_DB10 (0x9 << 18) |
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#define | ALT_DMA_CCR_OPT_DB11 (0xa << 18) |
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#define | ALT_DMA_CCR_OPT_DB12 (0xb << 18) |
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#define | ALT_DMA_CCR_OPT_DB13 (0xc << 18) |
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#define | ALT_DMA_CCR_OPT_DB14 (0xd << 18) |
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#define | ALT_DMA_CCR_OPT_DB15 (0xe << 18) |
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#define | ALT_DMA_CCR_OPT_DB16 (0xf << 18) |
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#define | ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 |
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#define | ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) |
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#define | ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) |
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#define | ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) |
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#define | ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) |
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#define | ALT_DMA_CCR_OPT_ES8 (0 << 28) |
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#define | ALT_DMA_CCR_OPT_ES16 (1 << 28) |
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#define | ALT_DMA_CCR_OPT_ES32 (2 << 28) |
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#define | ALT_DMA_CCR_OPT_ES64 (3 << 28) |
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#define | ALT_DMA_CCR_OPT_ES128 (4 << 28) |
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#define | ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 |
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#define | ALT_DMA_CCR_OPT_DEFAULT |
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