alt_dma_program.h

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/******************************************************************************
 *
 * Copyright 2013 Altera Corporation. All Rights Reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. The name of the author may not be used to endorse or promote products
 * derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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 *
 ******************************************************************************/

#ifndef __ALT_DMA_PROGRAM_H__
#define __ALT_DMA_PROGRAM_H__

#include "hwlib.h"
#include "alt_dma_common.h"

#ifdef __cplusplus
extern "C"
{
#endif  /* __cplusplus */

#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE     (32)

#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT    (16)

#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE   (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT)
#endif

typedef struct ALT_DMA_PROGRAM_s
{
    uint32_t flag;

    uint16_t buffer_start;
    uint16_t code_size;

    uint16_t loop0;
    uint16_t loop1;

    uint16_t sar;
    uint16_t dar;

    /*
     * Add a little extra space so that regardless of where this structure
     * sits in memory, a suitable start address can be aligned to the cache
     * line stride while providing the requested buffer space.
     */
    uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +
                    ALT_DMA_PROGRAM_CACHE_LINE_SIZE];
}
ALT_DMA_PROGRAM_t;

typedef enum ALT_DMA_PROGRAM_REG_e
{
    ALT_DMA_PROGRAM_REG_SAR = 0x0,

    ALT_DMA_PROGRAM_REG_DAR = 0x2,

    ALT_DMA_PROGRAM_REG_CCR = 0x1
}
ALT_DMA_PROGRAM_REG_t;

typedef enum ALT_DMA_PROGRAM_INST_MOD_e
{
    ALT_DMA_PROGRAM_INST_MOD_NONE,

    ALT_DMA_PROGRAM_INST_MOD_SINGLE,

    ALT_DMA_PROGRAM_INST_MOD_BURST,

    ALT_DMA_PROGRAM_INST_MOD_PERIPH
}
ALT_DMA_PROGRAM_INST_MOD_t;

ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm);

ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm);

ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm);

ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm);

ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm,
                                             ALT_DMA_PROGRAM_REG_t reg,
                                             uint32_t current, uint32_t * progress);

ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm,
                                           ALT_DMA_PROGRAM_REG_t reg, uint32_t val);

// Assembler Syntax: DMAADDH <address_register>, <16-bit immediate>
ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm,
                                        ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);

// Assembler Syntax: DMAADNH <address_register>, <16-bit immediate>
ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm,
                                        ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);

// Assembler Syntax: DMAEND
ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm);

// Assembler Syntax: DMAFLUSHP <peripheral>
ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm,
                                          ALT_DMA_PERIPH_t periph);

// Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns]
ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm,
                                      ALT_DMA_CHANNEL_t channel, uint32_t val,
                                      ALT_DMA_SECURITY_t sec);

// Assembler Syntax: DMAKILL
ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm);

// Assembler Syntax: DMALD[S|B]
ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm,
                                      ALT_DMA_PROGRAM_INST_MOD_t mod);

// Assembler Syntax: DMALDP<S|B> <peripheral>
ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm,
                                       ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);

// Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations>
ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm,
                                      uint32_t iterations);

// Assembler Syntax: DMALPEND[S|B]
ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm,
                                         ALT_DMA_PROGRAM_INST_MOD_t mod);

// Assembler Syntax: DMALPFE
ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm);

// Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate>
ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm,
                                       ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val);

// Assembler Syntax: DMANOP
ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm);

// Assembler Syntax: DMARMB
ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm);

// Assembler Syntax: DMASEV <event_num>
ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm,
                                       ALT_DMA_EVENT_t evt);

// Assembler Syntax: DMAST[S|B]
ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm,
                                      ALT_DMA_PROGRAM_INST_MOD_t mod);

// Assembler Syntax: DMASTP<S|B> <peripheral>
ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm,
                                       ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);

// Assembler Syntax: DMASTZ
ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm);

// Assembler Syntax: DMAWFE <event_num>[, invalid]
ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm,
                                       ALT_DMA_EVENT_t evt, bool invalid);

// Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph>
ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm,
                                       ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod);

// Assembler Syntax: DMAWMB
ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm);

/*
 * Source Address {Fixed,Incrementing}
 */
#define ALT_DMA_CCR_OPT_SAF         (0 << 0)

#define ALT_DMA_CCR_OPT_SAI         (1 << 0)

#define ALT_DMA_CCR_OPT_SA_DEFAULT  ALT_DMA_CCR_OPT_SAI

/*
 * Source burst Size (in bits)
 */
#define ALT_DMA_CCR_OPT_SS8         (0 << 1)

#define ALT_DMA_CCR_OPT_SS16        (1 << 1)

#define ALT_DMA_CCR_OPT_SS32        (2 << 1)

#define ALT_DMA_CCR_OPT_SS64        (3 << 1)

#define ALT_DMA_CCR_OPT_SS128       (4 << 1)

#define ALT_DMA_CCR_OPT_SS_DEFAULT  ALT_DMA_CCR_OPT_SS8

/*
 * Source burst Length (in transfer(s))
 */
#define ALT_DMA_CCR_OPT_SB1         (0x0 << 4)

#define ALT_DMA_CCR_OPT_SB2         (0x1 << 4)

#define ALT_DMA_CCR_OPT_SB3         (0x2 << 4)

#define ALT_DMA_CCR_OPT_SB4         (0x3 << 4)

#define ALT_DMA_CCR_OPT_SB5         (0x4 << 4)

#define ALT_DMA_CCR_OPT_SB6         (0x5 << 4)

#define ALT_DMA_CCR_OPT_SB7         (0x6 << 4)

#define ALT_DMA_CCR_OPT_SB8         (0x7 << 4)

#define ALT_DMA_CCR_OPT_SB9         (0x8 << 4)

#define ALT_DMA_CCR_OPT_SB10        (0x9 << 4)

#define ALT_DMA_CCR_OPT_SB11        (0xa << 4)

#define ALT_DMA_CCR_OPT_SB12        (0xb << 4)

#define ALT_DMA_CCR_OPT_SB13        (0xc << 4)

#define ALT_DMA_CCR_OPT_SB14        (0xd << 4)

#define ALT_DMA_CCR_OPT_SB15        (0xe << 4)

#define ALT_DMA_CCR_OPT_SB16        (0xf << 4)

#define ALT_DMA_CCR_OPT_SB_DEFAULT  ALT_DMA_CCR_OPT_SB1

/*
 * Source Protection
 */
#define ALT_DMA_CCR_OPT_SP(imm3)    ((imm3) << 8)

#define ALT_DMA_CCR_OPT_SP_DEFAULT  ALT_DMA_CCR_OPT_SP(0)

/*
 * Source cache
 */
#define ALT_DMA_CCR_OPT_SC(imm4)    ((imm4) << 11)

#define ALT_DMA_CCR_OPT_SC_DEFAULT  ALT_DMA_CCR_OPT_SC(0)

/*
 * Destination Address {Fixed,Incrementing}
 */
#define ALT_DMA_CCR_OPT_DAF         (0 << 14)

#define ALT_DMA_CCR_OPT_DAI         (1 << 14)

#define ALT_DMA_CCR_OPT_DA_DEFAULT  ALT_DMA_CCR_OPT_DAI

/*
 * Destination burst Size (in bits)
 */
#define ALT_DMA_CCR_OPT_DS8         (0 << 15)

#define ALT_DMA_CCR_OPT_DS16        (1 << 15)

#define ALT_DMA_CCR_OPT_DS32        (2 << 15)

#define ALT_DMA_CCR_OPT_DS64        (3 << 15)

#define ALT_DMA_CCR_OPT_DS128       (4 << 15)

#define ALT_DMA_CCR_OPT_DS_DEFAULT  ALT_DMA_CCR_OPT_DS8

/*
 * Destination Burst length (in transfer(s))
 */
#define ALT_DMA_CCR_OPT_DB1         (0x0 << 18)

#define ALT_DMA_CCR_OPT_DB2         (0x1 << 18)

#define ALT_DMA_CCR_OPT_DB3         (0x2 << 18)

#define ALT_DMA_CCR_OPT_DB4         (0x3 << 18)

#define ALT_DMA_CCR_OPT_DB5         (0x4 << 18)

#define ALT_DMA_CCR_OPT_DB6         (0x5 << 18)

#define ALT_DMA_CCR_OPT_DB7         (0x6 << 18)

#define ALT_DMA_CCR_OPT_DB8         (0x7 << 18)

#define ALT_DMA_CCR_OPT_DB9         (0x8 << 18)

#define ALT_DMA_CCR_OPT_DB10        (0x9 << 18)

#define ALT_DMA_CCR_OPT_DB11        (0xa << 18)

#define ALT_DMA_CCR_OPT_DB12        (0xb << 18)

#define ALT_DMA_CCR_OPT_DB13        (0xc << 18)

#define ALT_DMA_CCR_OPT_DB14        (0xd << 18)

#define ALT_DMA_CCR_OPT_DB15        (0xe << 18)

#define ALT_DMA_CCR_OPT_DB16        (0xf << 18)

#define ALT_DMA_CCR_OPT_DB_DEFAULT  ALT_DMA_CCR_OPT_DB1

/*
 * Destination Protection
 */
#define ALT_DMA_CCR_OPT_DP(imm3)    ((imm3) << 22)

#define ALT_DMA_CCR_OPT_DP_DEFAULT  ALT_DMA_CCR_OPT_DP(0)

/*
 * Destination Cache
 */
#define ALT_DMA_CCR_OPT_DC(imm4)    ((imm4) << 25)

#define ALT_DMA_CCR_OPT_DC_DEFAULT  ALT_DMA_CCR_OPT_DC(0)

/*
 * Endian Swap size (in bits)
 */
#define ALT_DMA_CCR_OPT_ES8         (0 << 28)

#define ALT_DMA_CCR_OPT_ES16        (1 << 28)

#define ALT_DMA_CCR_OPT_ES32        (2 << 28)

#define ALT_DMA_CCR_OPT_ES64        (3 << 28)

#define ALT_DMA_CCR_OPT_ES128       (4 << 28)

#define ALT_DMA_CCR_OPT_ES_DEFAULT  ALT_DMA_CCR_OPT_ES8

#define ALT_DMA_CCR_OPT_DEFAULT \
    (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
     ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
     ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
     ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
     ALT_DMA_CCR_OPT_ES8)

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif /* __ALT_DMA_PROGRAM_H__ */