Macros
#define	ALT_DMA_CCR_OPT_SAF (0 << 0)

#define	ALT_DMA_CCR_OPT_SAI (1 << 0)

#define	ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI

#define	ALT_DMA_CCR_OPT_SS8 (0 << 1)

#define	ALT_DMA_CCR_OPT_SS16 (1 << 1)

#define	ALT_DMA_CCR_OPT_SS32 (2 << 1)

#define	ALT_DMA_CCR_OPT_SS64 (3 << 1)

#define	ALT_DMA_CCR_OPT_SS128 (4 << 1)

#define	ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8

#define	ALT_DMA_CCR_OPT_SB1 (0x0 << 4)

#define	ALT_DMA_CCR_OPT_SB2 (0x1 << 4)

#define	ALT_DMA_CCR_OPT_SB3 (0x2 << 4)

#define	ALT_DMA_CCR_OPT_SB4 (0x3 << 4)

#define	ALT_DMA_CCR_OPT_SB5 (0x4 << 4)

#define	ALT_DMA_CCR_OPT_SB6 (0x5 << 4)

#define	ALT_DMA_CCR_OPT_SB7 (0x6 << 4)

#define	ALT_DMA_CCR_OPT_SB8 (0x7 << 4)

#define	ALT_DMA_CCR_OPT_SB9 (0x8 << 4)

#define	ALT_DMA_CCR_OPT_SB10 (0x9 << 4)

#define	ALT_DMA_CCR_OPT_SB11 (0xa << 4)

#define	ALT_DMA_CCR_OPT_SB12 (0xb << 4)

#define	ALT_DMA_CCR_OPT_SB13 (0xc << 4)

#define	ALT_DMA_CCR_OPT_SB14 (0xd << 4)

#define	ALT_DMA_CCR_OPT_SB15 (0xe << 4)

#define	ALT_DMA_CCR_OPT_SB16 (0xf << 4)

#define	ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1

#define	ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8)

#define	ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0)

#define	ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11)

#define	ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0)

#define	ALT_DMA_CCR_OPT_DAF (0 << 14)

#define	ALT_DMA_CCR_OPT_DAI (1 << 14)

#define	ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI

#define	ALT_DMA_CCR_OPT_DS8 (0 << 15)

#define	ALT_DMA_CCR_OPT_DS16 (1 << 15)

#define	ALT_DMA_CCR_OPT_DS32 (2 << 15)

#define	ALT_DMA_CCR_OPT_DS64 (3 << 15)

#define	ALT_DMA_CCR_OPT_DS128 (4 << 15)

#define	ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8

#define	ALT_DMA_CCR_OPT_DB1 (0x0 << 18)

#define	ALT_DMA_CCR_OPT_DB2 (0x1 << 18)

#define	ALT_DMA_CCR_OPT_DB3 (0x2 << 18)

#define	ALT_DMA_CCR_OPT_DB4 (0x3 << 18)

#define	ALT_DMA_CCR_OPT_DB5 (0x4 << 18)

#define	ALT_DMA_CCR_OPT_DB6 (0x5 << 18)

#define	ALT_DMA_CCR_OPT_DB7 (0x6 << 18)

#define	ALT_DMA_CCR_OPT_DB8 (0x7 << 18)

#define	ALT_DMA_CCR_OPT_DB9 (0x8 << 18)

#define	ALT_DMA_CCR_OPT_DB10 (0x9 << 18)

#define	ALT_DMA_CCR_OPT_DB11 (0xa << 18)

#define	ALT_DMA_CCR_OPT_DB12 (0xb << 18)

#define	ALT_DMA_CCR_OPT_DB13 (0xc << 18)

#define	ALT_DMA_CCR_OPT_DB14 (0xd << 18)

#define	ALT_DMA_CCR_OPT_DB15 (0xe << 18)

#define	ALT_DMA_CCR_OPT_DB16 (0xf << 18)

#define	ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1

#define	ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22)

#define	ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0)

#define	ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25)

#define	ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0)

#define	ALT_DMA_CCR_OPT_ES8 (0 << 28)

#define	ALT_DMA_CCR_OPT_ES16 (1 << 28)

#define	ALT_DMA_CCR_OPT_ES32 (2 << 28)

#define	ALT_DMA_CCR_OPT_ES64 (3 << 28)

#define	ALT_DMA_CCR_OPT_ES128 (4 << 28)

#define	ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8

#define	ALT_DMA_CCR_OPT_DEFAULT

Detailed Description

The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the dynamic microcode programming of the assembler directive:

DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>]
            [SP<imm3>] [SC<imm4>]
            [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>]
            [DP<imm3>] [DC<imm4>]
            [ES<8|16|32|64|128>]

with a DMAMOV instruction (see: alt_dma_program_DMAMOV()).

For example the assembler directive:

DMAMOV CCR SB1 SS32 DB1 DS32

would be dynamically programmed with the following API call:

alt_dma_program_DMAMOV( pgm,
                        ALT_DMA_PROGRAM_REG_CCR,
                        (   ALT_DMA_CCR_OPT_SB1
                          | ALT_DMA_CCR_OPT_SS32
                          | ALT_DMA_CCR_OPT_SA_DEFAULT
                          | ALT_DMA_CCR_OPT_SP_DEFAULT
                          | ALT_DMA_CCR_OPT_SC_DEFAULT
                          | ALT_DMA_CCR_OPT_DB1
                          | ALT_DMA_CCR_OPT_DS32
                          | ALT_DMA_CCR_OPT_DA_DEFAULT
                          | ALT_DMA_CCR_OPT_DP_DEFAULT
                          | ALT_DMA_CCR_OPT_DC_DEFAULT
                          | ALT_DMA_CCR_OPT_ES8
                        )
                      );

Each CCR option category should be specified regardless of whether it specifies a custom value or the normal default value (i.e. an ALT_DMA_CCR_OPT_*_DEFAULT.

Macro Definition Documentation

◆ ALT_DMA_CCR_OPT_DA_DEFAULT

#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI

Destination Address Default value.

◆ ALT_DMA_CCR_OPT_DAF

#define ALT_DMA_CCR_OPT_DAF (0 << 14)

Destination Address Fixed address burst.

◆ ALT_DMA_CCR_OPT_DAI

#define ALT_DMA_CCR_OPT_DAI (1 << 14)

Destination Address Incrementing address burst.

◆ ALT_DMA_CCR_OPT_DB1

#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18)

Destination Burst length of 1 transfer.

◆ ALT_DMA_CCR_OPT_DB10

#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18)

Destination Burst length of 10 transfers.

◆ ALT_DMA_CCR_OPT_DB11

#define ALT_DMA_CCR_OPT_DB11 (0xa << 18)

Destination Burst length of 11 transfers.

◆ ALT_DMA_CCR_OPT_DB12

#define ALT_DMA_CCR_OPT_DB12 (0xb << 18)

Destination Burst length of 12 transfers.

◆ ALT_DMA_CCR_OPT_DB13

#define ALT_DMA_CCR_OPT_DB13 (0xc << 18)

Destination Burst length of 13 transfers.

◆ ALT_DMA_CCR_OPT_DB14

#define ALT_DMA_CCR_OPT_DB14 (0xd << 18)

Destination Burst length of 14 transfers.

◆ ALT_DMA_CCR_OPT_DB15

#define ALT_DMA_CCR_OPT_DB15 (0xe << 18)

Destination Burst length of 15 transfers.

◆ ALT_DMA_CCR_OPT_DB16

#define ALT_DMA_CCR_OPT_DB16 (0xf << 18)

Destination Burst length of 16 transfers.

◆ ALT_DMA_CCR_OPT_DB2

#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18)

Destination Burst length of 2 transfers.

◆ ALT_DMA_CCR_OPT_DB3

#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18)

Destination Burst length of 3 transfers.

◆ ALT_DMA_CCR_OPT_DB4

#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18)

Destination Burst length of 4 transfers.

◆ ALT_DMA_CCR_OPT_DB5

#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18)

Destination Burst length of 5 transfers.

◆ ALT_DMA_CCR_OPT_DB6

#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18)

Destination Burst length of 6 transfers.

◆ ALT_DMA_CCR_OPT_DB7

#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18)

Destination Burst length of 7 transfers.

◆ ALT_DMA_CCR_OPT_DB8

#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18)

Destination Burst length of 8 transfers.

◆ ALT_DMA_CCR_OPT_DB9

#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18)

Destination Burst length of 9 transfers.

◆ ALT_DMA_CCR_OPT_DB_DEFAULT

#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1

Destination Burst length default transfers.

◆ ALT_DMA_CCR_OPT_DC

#define ALT_DMA_CCR_OPT_DC ( imm4 ) ((imm4) << 25)

Destination Cache bits for AXI bus AWCACHE[3,1:0].

◆ ALT_DMA_CCR_OPT_DC_DEFAULT

#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0)

Destination Cache bits default value.

◆ ALT_DMA_CCR_OPT_DEFAULT

#define ALT_DMA_CCR_OPT_DEFAULT

Value:

(ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
     ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
     ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
     ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
     ALT_DMA_CCR_OPT_ES8)

Default CCR register options for a DMAMOV CCR assembler directive.

◆ ALT_DMA_CCR_OPT_DP

#define ALT_DMA_CCR_OPT_DP ( imm3 ) ((imm3) << 22)

Destination Protection bits for AXI bus AWPROT[2:0].

◆ ALT_DMA_CCR_OPT_DP_DEFAULT

#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0)

Destination Protection bits default value.

◆ ALT_DMA_CCR_OPT_DS128

#define ALT_DMA_CCR_OPT_DS128 (4 << 15)

Destination burst Size of 128 bits.

◆ ALT_DMA_CCR_OPT_DS16

#define ALT_DMA_CCR_OPT_DS16 (1 << 15)

Destination burst Size of 16 bits.

◆ ALT_DMA_CCR_OPT_DS32

#define ALT_DMA_CCR_OPT_DS32 (2 << 15)

Destination burst Size of 32 bits.

◆ ALT_DMA_CCR_OPT_DS64

#define ALT_DMA_CCR_OPT_DS64 (3 << 15)

Destination burst Size of 64 bits.

◆ ALT_DMA_CCR_OPT_DS8

#define ALT_DMA_CCR_OPT_DS8 (0 << 15)

Destination burst Size of 8 bits.

◆ ALT_DMA_CCR_OPT_DS_DEFAULT

#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8

Destination burst Size default bits.

◆ ALT_DMA_CCR_OPT_ES128

#define ALT_DMA_CCR_OPT_ES128 (4 << 28)

Endian Swap: Swap bytes within 128-bit data.

◆ ALT_DMA_CCR_OPT_ES16

#define ALT_DMA_CCR_OPT_ES16 (1 << 28)

Endian Swap: Swap bytes within 16-bit data.

◆ ALT_DMA_CCR_OPT_ES32

#define ALT_DMA_CCR_OPT_ES32 (2 << 28)

Endian Swap: Swap bytes within 32-bit data.

◆ ALT_DMA_CCR_OPT_ES64

#define ALT_DMA_CCR_OPT_ES64 (3 << 28)

Endian Swap: Swap bytes within 64-bit data.

◆ ALT_DMA_CCR_OPT_ES8

#define ALT_DMA_CCR_OPT_ES8 (0 << 28)

Endian Swap: No swap, 8-bit data.

◆ ALT_DMA_CCR_OPT_ES_DEFAULT

#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8

Endian Swap: Default byte swap.

◆ ALT_DMA_CCR_OPT_SA_DEFAULT

#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI

Source Address Default value.

◆ ALT_DMA_CCR_OPT_SAF

#define ALT_DMA_CCR_OPT_SAF (0 << 0)

Source Address Fixed address burst.

◆ ALT_DMA_CCR_OPT_SAI

#define ALT_DMA_CCR_OPT_SAI (1 << 0)

Source Address Incrementing address burst.

◆ ALT_DMA_CCR_OPT_SB1

#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4)

Source Burst length of 1 transfer.

◆ ALT_DMA_CCR_OPT_SB10

#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4)

Source Burst length of 10 transfers.

◆ ALT_DMA_CCR_OPT_SB11

#define ALT_DMA_CCR_OPT_SB11 (0xa << 4)

Source Burst length of 11 transfers.

◆ ALT_DMA_CCR_OPT_SB12

#define ALT_DMA_CCR_OPT_SB12 (0xb << 4)

Source Burst length of 12 transfers.

◆ ALT_DMA_CCR_OPT_SB13

#define ALT_DMA_CCR_OPT_SB13 (0xc << 4)

Source Burst length of 13 transfers.

◆ ALT_DMA_CCR_OPT_SB14

#define ALT_DMA_CCR_OPT_SB14 (0xd << 4)

Source Burst length of 14 transfers.

◆ ALT_DMA_CCR_OPT_SB15

#define ALT_DMA_CCR_OPT_SB15 (0xe << 4)

Source Burst length of 15 transfers.

◆ ALT_DMA_CCR_OPT_SB16

#define ALT_DMA_CCR_OPT_SB16 (0xf << 4)

Source Burst length of 16 transfers.

◆ ALT_DMA_CCR_OPT_SB2

#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4)

Source Burst length of 2 transfers.

◆ ALT_DMA_CCR_OPT_SB3

#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4)

Source Burst length of 3 transfers.

◆ ALT_DMA_CCR_OPT_SB4

#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4)

Source Burst length of 4 transfers.

◆ ALT_DMA_CCR_OPT_SB5

#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4)

Source Burst length of 5 transfers.

◆ ALT_DMA_CCR_OPT_SB6

#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4)

Source Burst length of 6 transfers.

◆ ALT_DMA_CCR_OPT_SB7

#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4)

Source Burst length of 7 transfers.

◆ ALT_DMA_CCR_OPT_SB8

#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4)

Source Burst length of 8 transfers.

◆ ALT_DMA_CCR_OPT_SB9

#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4)

Source Burst length of 9 transfers.

◆ ALT_DMA_CCR_OPT_SB_DEFAULT

#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1

Source Burst length default transfers.

◆ ALT_DMA_CCR_OPT_SC

#define ALT_DMA_CCR_OPT_SC ( imm4 ) ((imm4) << 11)

Source Cache bits for AXI bus ARCACHE[2:0].

◆ ALT_DMA_CCR_OPT_SC_DEFAULT

#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0)

Source Cache bits default value.

◆ ALT_DMA_CCR_OPT_SP

#define ALT_DMA_CCR_OPT_SP ( imm3 ) ((imm3) << 8)

Source Protection bits for AXI bus ARPROT[2:0].

◆ ALT_DMA_CCR_OPT_SP_DEFAULT

#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0)

Source Protection bits default value.

◆ ALT_DMA_CCR_OPT_SS128

#define ALT_DMA_CCR_OPT_SS128 (4 << 1)

Source burst Size of 128 bits.

◆ ALT_DMA_CCR_OPT_SS16

#define ALT_DMA_CCR_OPT_SS16 (1 << 1)

Source burst Size of 16 bits.

◆ ALT_DMA_CCR_OPT_SS32

#define ALT_DMA_CCR_OPT_SS32 (2 << 1)

Source burst Size of 32 bits.

◆ ALT_DMA_CCR_OPT_SS64

#define ALT_DMA_CCR_OPT_SS64 (3 << 1)

Source burst Size of 64 bits.

◆ ALT_DMA_CCR_OPT_SS8

#define ALT_DMA_CCR_OPT_SS8 (0 << 1)

Source burst Size of 8 bits.

◆ ALT_DMA_CCR_OPT_SS_DEFAULT

#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8

Source burst Size default bits.

Macros