 |
RTEMS 7.0-rc1
|
|
RTEMS 7.0-rc1
|
Modules | |
| Configuration_of_CMSIS | |
| STM32U5xx_peripherals | |
| __IO uint32_t XSPI_TypeDef::ABR |
XSPI Alternate Bytes register, Address offset: 0x120
| __IO uint32_t SDMMC_TypeDef::ACKTIME |
SDMMC Acknowledgement timer register, Address offset: 0x40
| __IO uint32_t FLASH_TypeDef::ACR |
FLASH access control register, Address offset: 0x00
| __IO uint32_t TIM_TypeDef::AF1 |
TIM alternate function option register 1, Address offset: 0x60
| __IO uint32_t TIM_TypeDef::AF2 |
TIM alternate function option register 2, Address offset: 0x64
| __IO uint32_t GFXTIM_TypeDef::AFCC1R |
GFXTIM absolute frame counter compare 1 register, Address offset: 0x60
| __IO uint32_t GFXTIM_TypeDef::AFCR |
GFXTIM absolute frame counter register, Address offset: 0x54
| __IO uint32_t GPIO_TypeDef::AFR[2] |
GPIO alternate function registers, Address offset: 0x20-0x24
| __IO uint32_t RCC_TypeDef::AHB1ENR |
AHB1 Peripherals Clock Enable Register Address offset: 0x88
| __IO uint32_t DBGMCU_TypeDef::AHB1FZR |
Debug MCU AHB1 freeze register, Address offset: 0x20
| __IO uint32_t RCC_TypeDef::AHB1RSTR |
AHB1 Peripherals Reset Register Address offset: 0x60
| __IO uint32_t RCC_TypeDef::AHB1SMENR |
AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0
| __IO uint32_t RCC_TypeDef::AHB2ENR1 |
AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C
| __IO uint32_t RCC_TypeDef::AHB2ENR2 |
AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90
| __IO uint32_t RCC_TypeDef::AHB2RSTR1 |
AHB2 Peripherals Reset Register 1 Address offset: 0x64
| __IO uint32_t RCC_TypeDef::AHB2RSTR2 |
AHB2 Peripherals Reset Register 2 Address offset: 0x68
| __IO uint32_t RCC_TypeDef::AHB2SMENR1 |
AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4
| __IO uint32_t RCC_TypeDef::AHB2SMENR2 |
AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8
| __IO uint32_t RCC_TypeDef::AHB3ENR |
AHB3 Peripherals Clock Enable Register Address offset: 0x94
| __IO uint32_t DBGMCU_TypeDef::AHB3FZR |
Debug MCU AHB3 freeze register, Address offset: 0x28
| __IO uint32_t RCC_TypeDef::AHB3RSTR |
AHB3 Peripherals Reset Register Address offset: 0x6C
| __IO uint32_t RCC_TypeDef::AHB3SMENR |
AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC
| __IO uint32_t GFXTIM_TypeDef::ALCC1R |
GFXTIM absolute line counter compare 1 register, Address offset: 0x70
| __IO uint32_t GFXTIM_TypeDef::ALCC2R |
GFXTIM absolute line counter compare 2 register, Address offset: 0x74
| __IO uint32_t GFXTIM_TypeDef::ALCR |
GFXTIM absolute line counter register, Address offset: 0x58
| __IO uint32_t RTC_TypeDef::ALRABINR |
RTC alarm A binary mode register, Address offset: 0x70
| __IO uint32_t RTC_TypeDef::ALRBBINR |
RTC alarm B binary mode register, Address offset: 0x74
| __IO uint32_t RTC_TypeDef::ALRMAR |
RTC alarm A register, Address offset: 0x40
| __IO uint32_t RTC_TypeDef::ALRMASSR |
RTC alarm A sub second register, Address offset: 0x44
| __IO uint32_t RTC_TypeDef::ALRMBR |
RTC alarm B register, Address offset: 0x48
| __IO uint32_t RTC_TypeDef::ALRMBSSR |
RTC alarm B sub second register, Address offset: 0x4C
| __IO uint32_t DMA2D_TypeDef::AMTCR |
DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C
| __IO uint32_t RCC_TypeDef::APB1ENR1 |
APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C
| __IO uint32_t RCC_TypeDef::APB1ENR2 |
APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0
| __IO uint32_t DBGMCU_TypeDef::APB1FZR1 |
Debug MCU APB1 freeze register 1, Address offset: 0x08
| __IO uint32_t DBGMCU_TypeDef::APB1FZR2 |
Debug MCU APB1 freeze register 2, Address offset: 0x0C
| __IO uint32_t RCC_TypeDef::APB1RSTR1 |
APB1 Peripherals Reset Register 1 Address offset: 0x74
| __IO uint32_t RCC_TypeDef::APB1RSTR2 |
APB1 Peripherals Reset Register 2 Address offset: 0x78
| __IO uint32_t RCC_TypeDef::APB1SMENR1 |
APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4
| __IO uint32_t RCC_TypeDef::APB1SMENR2 |
APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8
| __IO uint32_t RCC_TypeDef::APB2ENR |
APB2 Peripherals Clock Enable Register Address offset: 0xA4
| __IO uint32_t DBGMCU_TypeDef::APB2FZR |
Debug MCU APB2 freeze register, Address offset: 0x10
| __IO uint32_t RCC_TypeDef::APB2RSTR |
APB2 Peripherals Reset Register Address offset: 0x7C
| __IO uint32_t RCC_TypeDef::APB2SMENR |
APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC
| __IO uint32_t RCC_TypeDef::APB3ENR |
APB3 Peripherals Clock Enable Register Address offset: 0xA8
| __IO uint32_t DBGMCU_TypeDef::APB3FZR |
Debug MCU APB3 freeze register, Address offset: 0x14
| __IO uint32_t RCC_TypeDef::APB3RSTR |
APB3 Peripherals Reset Register Address offset: 0x80
| __IO uint32_t RCC_TypeDef::APB3SMENR |
APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0
| __IO uint32_t PWR_TypeDef::APCR |
Power apply pull configuration register, Address offset: 0x4C
| __IO uint32_t XSPI_TypeDef::AR |
XSPI Address register, Address offset: 0x048
| __IO uint32_t SDMMC_TypeDef::ARG |
SDMMC argument register, Address offset: 0x08
| __IO uint32_t TIM_TypeDef::ARR |
TIM auto-reload register, Address offset: 0x2C
| __IO uint32_t LPTIM_TypeDef::ARR |
LPTIM Autoreload register, Address offset: 0x18
| __IO uint32_t TAMP_TypeDef::ATCR1 |
TAMP filter control register 1 Address offset: 0x10
| __IO uint32_t TAMP_TypeDef::ATCR2 |
TAMP filter control register 2, Address offset: 0x1C
| __IO uint32_t TAMP_TypeDef::ATOR |
TAMP active tamper output register, Address offset: 0x18
| __IO uint32_t GFXTIM_TypeDef::ATR |
GFXTIM absolute time register, Address offset: 0x50
| __IO uint32_t TAMP_TypeDef::ATSEEDR |
TAMP active tamper seed register, Address offset: 0x14
| __IO uint32_t DAC_TypeDef::AUTOCR |
DAC Autonomous mode register, Address offset: 0x54
| __IO uint32_t USART_TypeDef::AUTOCR |
USART Autonomous mode control register Address offset: 0x30
| __IO uint32_t SPI_TypeDef::AUTOCR |
SPI Autonomous Mode Control register, Address offset: 0x1C
| __IO uint32_t LTDC_TypeDef::AWCR |
LTDC Active Width Configuration Register, Address offset: 0x10
| __IO uint32_t ADC_TypeDef::AWD1TR |
ADC watchdog threshold register, Address offset: 0x20
| __IO uint32_t ADC_TypeDef::AWD2CR |
ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0
| __IO uint32_t ADC_TypeDef::AWD2TR |
ADC watchdog threshold register, Address offset: 0x24
| __IO uint32_t ADC_TypeDef::AWD3CR |
ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4
| __IO uint32_t ADC_TypeDef::AWD3TR |
ADC watchdog threshold register, Address offset: 0x2C
| __IO uint32_t GFXMMU_TypeDef::B0CR |
GFXMMU buffer 0 configuration register, Address offset: 0x20
| __IO uint32_t GFXMMU_TypeDef::B1CR |
GFXMMU buffer 1 configuration register, Address offset: 0x24
| __IO uint32_t GFXMMU_TypeDef::B2CR |
GFXMMU buffer 2 configuration register, Address offset: 0x28
| __IO uint32_t GFXMMU_TypeDef::B3CR |
GFXMMU buffer 3 configuration register, Address offset: 0x2C
| __IO uint32_t LTDC_TypeDef::BCCR |
LTDC Background Color Configuration Register, Address offset: 0x2C
| __IO uint32_t DSI_TypeDef::BCFGR |
DSI Bias Configuration Register, Address offset: 0x808
| __IO uint32_t RCC_TypeDef::BDCR |
Backup Domain Control Register Address offset: 0xF0
| __IO uint32_t PWR_TypeDef::BDCR1 |
Power backup domain control register 1, Address offset: 0x20
| __IO uint32_t PWR_TypeDef::BDCR2 |
Power backup domain control register 2, Address offset: 0x24
| __IO uint32_t PWR_TypeDef::BDSR |
Power backup domain status register, Address offset: 0x40
| __IO uint32_t TIM_TypeDef::BDTR |
TIM break and dead-time register, Address offset: 0x44
| __IO uint32_t LTDC_Layer_TypeDef::BFCR |
LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0
| __IO uint32_t DMA2D_TypeDef::BGCLUT[256] |
DMA2D Background CLUT, Address offset:800-BFC
| __IO uint32_t DMA2D_TypeDef::BGCMAR |
DMA2D Background CLUT Memory Address Register, Address offset: 0x30
| __IO uint32_t DMA2D_TypeDef::BGCOLR |
DMA2D Background Color Register, Address offset: 0x28
| __IO uint32_t DMA2D_TypeDef::BGMAR |
DMA2D Background Memory Address Register, Address offset: 0x14
| __IO uint32_t DMA2D_TypeDef::BGOR |
DMA2D Background Offset Register, Address offset: 0x18
| __IO uint32_t DMA2D_TypeDef::BGPFCCR |
DMA2D Background PFC Control Register, Address offset: 0x24
| __IO uint32_t TAMP_TypeDef::BKP0R |
TAMP backup register 0, Address offset: 0x100
| __IO uint32_t TAMP_TypeDef::BKP10R |
TAMP backup register 10, Address offset: 0x128
| __IO uint32_t TAMP_TypeDef::BKP11R |
TAMP backup register 11, Address offset: 0x12C
| __IO uint32_t TAMP_TypeDef::BKP12R |
TAMP backup register 12, Address offset: 0x130
| __IO uint32_t TAMP_TypeDef::BKP13R |
TAMP backup register 13, Address offset: 0x134
| __IO uint32_t TAMP_TypeDef::BKP14R |
TAMP backup register 14, Address offset: 0x138
| __IO uint32_t TAMP_TypeDef::BKP15R |
TAMP backup register 15, Address offset: 0x13C
| __IO uint32_t TAMP_TypeDef::BKP16R |
TAMP backup register 16, Address offset: 0x140
| __IO uint32_t TAMP_TypeDef::BKP17R |
TAMP backup register 17, Address offset: 0x144
| __IO uint32_t TAMP_TypeDef::BKP18R |
TAMP backup register 18, Address offset: 0x148
| __IO uint32_t TAMP_TypeDef::BKP19R |
TAMP backup register 19, Address offset: 0x14C
| __IO uint32_t TAMP_TypeDef::BKP1R |
TAMP backup register 1, Address offset: 0x104
| __IO uint32_t TAMP_TypeDef::BKP20R |
TAMP backup register 20, Address offset: 0x150
| __IO uint32_t TAMP_TypeDef::BKP21R |
TAMP backup register 21, Address offset: 0x154
| __IO uint32_t TAMP_TypeDef::BKP22R |
TAMP backup register 22, Address offset: 0x158
| __IO uint32_t TAMP_TypeDef::BKP23R |
TAMP backup register 23, Address offset: 0x15C
| __IO uint32_t TAMP_TypeDef::BKP24R |
TAMP backup register 24, Address offset: 0x160
| __IO uint32_t TAMP_TypeDef::BKP25R |
TAMP backup register 25, Address offset: 0x164
| __IO uint32_t TAMP_TypeDef::BKP26R |
TAMP backup register 26, Address offset: 0x168
| __IO uint32_t TAMP_TypeDef::BKP27R |
TAMP backup register 27, Address offset: 0x16C
| __IO uint32_t TAMP_TypeDef::BKP28R |
TAMP backup register 28, Address offset: 0x170
| __IO uint32_t TAMP_TypeDef::BKP29R |
TAMP backup register 29, Address offset: 0x174
| __IO uint32_t TAMP_TypeDef::BKP2R |
TAMP backup register 2, Address offset: 0x108
| __IO uint32_t TAMP_TypeDef::BKP30R |
TAMP backup register 30, Address offset: 0x178
| __IO uint32_t TAMP_TypeDef::BKP31R |
TAMP backup register 31, Address offset: 0x17C
| __IO uint32_t TAMP_TypeDef::BKP3R |
TAMP backup register 3, Address offset: 0x10C
| __IO uint32_t TAMP_TypeDef::BKP4R |
TAMP backup register 4, Address offset: 0x110
| __IO uint32_t TAMP_TypeDef::BKP5R |
TAMP backup register 5, Address offset: 0x114
| __IO uint32_t TAMP_TypeDef::BKP6R |
TAMP backup register 6, Address offset: 0x118
| __IO uint32_t TAMP_TypeDef::BKP7R |
TAMP backup register 7, Address offset: 0x11C
| __IO uint32_t TAMP_TypeDef::BKP8R |
TAMP backup register 8, Address offset: 0x120
| __IO uint32_t TAMP_TypeDef::BKP9R |
TAMP backup register 9, Address offset: 0x124
| __IO uint32_t LTDC_TypeDef::BPCR |
LTDC Back Porch Configuration Register, Address offset: 0x0C
| __IO uint32_t GPIO_TypeDef::BRR |
GPIO Bit Reset register, Address offset: 0x28
| __IO uint32_t USART_TypeDef::BRR |
USART Baud rate register, Address offset: 0x0C
| __IO uint32_t MDF_Filter_TypeDef::BSMXCR |
MDF Bitstream Matrix Control Register, Address offset: 0x84
| __IO uint32_t GPIO_TypeDef::BSRR |
GPIO port bit set/reset register, Address offset: 0x18
| __IO uint32_t FMC_Bank1_TypeDef::BTCR[8] |
NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
| __IO uint32_t FMC_Bank1E_TypeDef::BWTR[7] |
NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
| __IO uint32_t LTDC_Layer_TypeDef::CACR |
LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98
| __IO uint32_t ADC_TypeDef::CALFACT |
ADC Calibration Factors, Address offset: 0xC4
| __IO uint32_t ADC_TypeDef::CALFACT2 |
ADC Linearity Calibration Factors, Address offset: 0xC8
| __IO uint32_t XSPI_TypeDef::CALFCR |
XSPI Full-cycle calibration configuration HSPI only, invalid for OCTOSPI, Address offset: 0x210
| __IO uint32_t XSPI_TypeDef::CALMR |
XSPI DLL master calibration configuration HSPI only, invalid for OCTOSPI, Address offset: 0x218
| __IO uint32_t RTC_TypeDef::CALR |
RTC calibration register, Address offset: 0x28
| __IO uint32_t XSPI_TypeDef::CALSIR |
XSPI slave input calibration configuration HSPI only, invalid for OCTOSPI, Address offset: 0x228
| __IO uint32_t XSPI_TypeDef::CALSOR |
XSPI slave output calibration configuration HSPI only, invalid for OCTOSPI, Address offset: 0x220
| __IO uint32_t DMA_Channel_TypeDef::CBR1 |
DMA channel x block register 1, Address offset: 0x98 + (x * 0x80)
| __IO uint32_t DMA_Channel_TypeDef::CBR2 |
DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80)
| __IO uint32_t SYSCFG_TypeDef::CCCR |
SYSCFG Conpensaion Cell Code register, Address offset: 0x24
| __IO uint32_t FDCAN_GlobalTypeDef::CCCR |
FDCAN CC Control register, Address offset: 0x018
| __IO uint32_t SYSCFG_TypeDef::CCCSR |
SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C
| __IO uint32_t TIM_TypeDef::CCER |
TIM capture/compare enable register, Address offset: 0x20
| __IO uint32_t RCC_TypeDef::CCIPR1 |
IPs Clocks Configuration Register 1 Address offset: 0xE0
| __IO uint32_t RCC_TypeDef::CCIPR2 |
IPs Clocks Configuration Register 2 Address offset: 0xE4
| __IO uint32_t RCC_TypeDef::CCIPR3 |
IPs Clocks Configuration Register 3 Address offset: 0xE8
| __IO uint32_t TIM_TypeDef::CCMR1 |
TIM capture/compare mode register 1, Address offset: 0x18
| __IO uint32_t LPTIM_TypeDef::CCMR1 |
LPTIM Capture/Compare mode register, Address offset: 0x2C
| __IO uint32_t TIM_TypeDef::CCMR2 |
TIM capture/compare mode register 2, Address offset: 0x1C
| __IO uint32_t TIM_TypeDef::CCMR3 |
TIM capture/compare mode register 3, Address offset: 0x50
| __IO uint32_t DAC_TypeDef::CCR |
DAC calibration control register, Address offset: 0x38
| __IO uint32_t DMA_Channel_TypeDef::CCR |
DMA channel x control register, Address offset: 0x64 + (x * 0x80)
| __IO uint32_t DSI_TypeDef::CCR |
DSI HOST Clock Control Register, Address offset: 0x08
| __IO uint32_t GFXMMU_TypeDef::CCR |
GFXMMU Cache Control Register, Address offset: 0x0C
| __IO uint32_t XSPI_TypeDef::CCR |
XSPI Communication Configuration register, Address offset: 0x100
| __IO uint32_t VREFBUF_TypeDef::CCR |
VREFBUF calibration and control register, Address offset: 0x04
| __IO uint32_t ADC_Common_TypeDef::CCR |
ADC common control register, Address offset: 0x308
| __IO uint32_t TIM_TypeDef::CCR1 |
TIM capture/compare register 1, Address offset: 0x34
| __IO uint32_t LPTIM_TypeDef::CCR1 |
LPTIM Capture/Compare register 1, Address offset: 0x14
| __IO uint32_t TIM_TypeDef::CCR2 |
TIM capture/compare register 2, Address offset: 0x38
| __IO uint32_t LPTIM_TypeDef::CCR2 |
LPTIM Capture/Compare register 2, Address offset: 0x34
| __IO uint32_t TIM_TypeDef::CCR3 |
TIM capture/compare register 3, Address offset: 0x3C
| __IO uint32_t TIM_TypeDef::CCR4 |
TIM capture/compare register 4, Address offset: 0x40
| __IO uint32_t TIM_TypeDef::CCR5 |
TIM capture/compare register 5, Address offset: 0x48
| __IO uint32_t TIM_TypeDef::CCR6 |
TIM capture/compare register 6, Address offset: 0x4C
| __IO uint32_t SYSCFG_TypeDef::CCVR |
SYSCFG Conpensaion Cell value register, Address offset: 0x20
| __IO uint32_t DMA_Channel_TypeDef::CDAR |
DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80)
| __IO uint32_t ADC_Common_TypeDef::CDR |
ADC common regular data register for dual mode, Address offset: 0x30C
| __IO uint32_t ADC_Common_TypeDef::CDR2 |
ADC common regular data register for 32-bit dual mode, Address offset: 0x310
| __IO uint32_t LTDC_TypeDef::CDSR |
LTDC Current Display Status Register, Address offset: 0x48
| __IO uint32_t LTDC_Layer_TypeDef::CFBAR |
LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC
| __IO uint32_t LTDC_Layer_TypeDef::CFBLNR |
LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4
| __IO uint32_t LTDC_Layer_TypeDef::CFBLR |
LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0
| __IO uint32_t DMA_Channel_TypeDef::CFCR |
DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80)
| __IO uint32_t UCPD_TypeDef::CFG1 |
UCPD configuration register 1, Address offset: 0x00
| __IO uint32_t SPI_TypeDef::CFG1 |
SPI Configuration register 1, Address offset: 0x08
| __IO uint32_t UCPD_TypeDef::CFG2 |
UCPD configuration register 2, Address offset: 0x04
| __IO uint32_t SPI_TypeDef::CFG2 |
SPI Configuration register 2, Address offset: 0x0C
| __IO uint32_t UCPD_TypeDef::CFG3 |
UCPD configuration register 3, Address offset: 0x08
| __IO uint32_t GTZC_MPCBB_TypeDef::CFGLOCKR1 |
MPCBBx Configuration lock register 1, Address offset: 0x10
| __IO uint32_t GTZC_MPCBB_TypeDef::CFGLOCKR2 |
MPCBBx Configuration lock register 2, Address offset: 0x14
| __IO uint32_t CRS_TypeDef::CFGR |
CRS configuration register, Address offset: 0x04
| __IO uint32_t LPTIM_TypeDef::CFGR |
LPTIM Configuration register, Address offset: 0x0C
| __IO uint32_t DLYB_TypeDef::CFGR |
DELAY BLOCK configuration register, Address offset: 0x04
| __IO uint32_t RCC_TypeDef::CFGR1 |
RCC clock configuration register 1 Address offset: 0x1C
| __IO uint32_t SYSCFG_TypeDef::CFGR1 |
SYSCFG configuration register 1, Address offset: 0x04
| __IO uint32_t ADC_TypeDef::CFGR1 |
ADC Configuration register, Address offset: 0x0C
| __IO uint32_t LPTIM_TypeDef::CFGR2 |
LPTIM Configuration register 2, Address offset: 0x24
| __IO uint32_t RCC_TypeDef::CFGR2 |
RCC clock configuration register 2 Address offset: 0x20
| __IO uint32_t SYSCFG_TypeDef::CFGR2 |
SYSCFG configuration register 2, Address offset: 0x14
| __IO uint32_t ADC_TypeDef::CFGR2 |
ADC Configuration register 2, Address offset: 0x10
| __IO uint32_t RCC_TypeDef::CFGR3 |
RCC clock configuration register 3 Address offset: 0x24
| __IO uint32_t JPEG_TypeDef::CFR |
JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h
| __IO uint32_t WWDG_TypeDef::CFR |
WWDG Configuration register, Address offset: 0x04
| __IO uint32_t GFXTIM_TypeDef::CGCR |
GFXTIM clock generator configuration register, Address offset: 0x04
| __IO uint32_t ADC_TypeDef::CHSELR |
ADC channel select register, Address offset: 0x28
| __IO uint32_t RCC_TypeDef::CICR |
Clock Interrupt Clear Register Address offset: 0x58
| __IO uint32_t USB_OTG_GlobalTypeDef::CID |
User ID Register, Address offset: 03Ch
| __IO uint32_t RCC_TypeDef::CIER |
Clock Interrupt Enable Register Address offset: 0x50
| __IO uint32_t RCC_TypeDef::CIFR |
Clock Interrupt Flag Register Address offset: 0x54
| __IO uint32_t LTDC_Layer_TypeDef::CKCR |
LTDC Layerx Color Keying Configuration Register Address offset: 0x90
| __IO uint32_t FDCAN_Config_TypeDef::CKDIV |
FDCAN clock divider register, Address offset: 0x100 + 0x000
| __IO uint32_t MDF_TypeDef::CKGCR |
MDF Clock Generator Control Register, Address offset: 0x04
| __IO uint32_t DMA_Channel_TypeDef::CLBAR |
DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80)
| __IO uint32_t DSI_TypeDef::CLCR |
DSI Host Clock Lane Configuration Register, Address offset: 0x94
| __IO uint32_t SDMMC_TypeDef::CLKCR |
SDMMC clock control register, Address offset: 0x04
| __IO uint32_t DMA_Channel_TypeDef::CLLR |
DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80)
| __IM RSSLIB_S_CloseExitHDP_TypeDef S_pFuncTypeDef::CloseExitHDP |
RSSLIB Bootloader Close and exit HDP Address offset: 0x28
| __IO uint32_t PKA_TypeDef::CLRFR |
PKA clear flag register, Address offset: 0x08
| __IO uint32_t SAI_Block_TypeDef::CLRFR |
SAI block x clear flag register, Address offset: 0x1C
| __IO uint32_t DSI_TypeDef::CLTCR |
DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98
| __IO uint32_t LTDC_Layer_TypeDef::CLUTWR |
LTDC Layerx CLUT Write Register Address offset: 0x144
| __IO uint32_t DSI_TypeDef::CMCR |
DSI Host Command Mode Configuration Register, Address offset: 0x68
| __IO uint32_t SDMMC_TypeDef::CMD |
SDMMC command register, Address offset: 0x0C
| __IO uint32_t DCACHE_TypeDef::CMDREADDRR |
DCACHE Command End Address register, Address offset: 0x2C
| __IO uint32_t DCACHE_TypeDef::CMDRSADDRR |
DCACHE Command Start Address register, Address offset: 0x28
| __IO uint32_t SYSCFG_TypeDef::CNSLCKR |
SYSCFG CPU non-secure lock register, Address offset: 0x0C
| __IO uint32_t TIM_TypeDef::CNT |
TIM counter register, Address offset: 0x24
| __IO uint32_t LPTIM_TypeDef::CNT |
LPTIM Counter register, Address offset: 0x1C
| __IO uint32_t JPEG_TypeDef::CONFR0 |
JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h
| __IO uint32_t JPEG_TypeDef::CONFR1 |
JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h
| __IO uint32_t JPEG_TypeDef::CONFR2 |
JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h
| __IO uint32_t JPEG_TypeDef::CONFR3 |
JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch
| __IO uint32_t JPEG_TypeDef::CONFR4 |
JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h
| __IO uint32_t JPEG_TypeDef::CONFR5 |
JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h
| __IO uint32_t JPEG_TypeDef::CONFR6 |
JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h
| __IO uint32_t JPEG_TypeDef::CONFR7 |
JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch
| __IO uint32_t TAMP_TypeDef::COUNTR |
TAMP monotonic counter register, Address offset: 0x40
| __IO uint32_t LTDC_TypeDef::CPSR |
LTDC Current Position Status Register, Address offset: 0x44
| __IO uint32_t CRC_TypeDef::CR |
CRC Control register, Address offset: 0x08
| __IO uint32_t DAC_TypeDef::CR |
DAC control register, Address offset: 0x00
| __IO uint32_t CRS_TypeDef::CR |
CRS ccontrol register, Address offset: 0x00
| __IO uint32_t AES_TypeDef::CR |
AES control register, Address offset: 0x00
| __IO uint32_t HASH_TypeDef::CR |
HASH control register, Address offset: 0x00
| __IO uint32_t RNG_TypeDef::CR |
RNG control register, Address offset: 0x00
| __IO uint32_t DBGMCU_TypeDef::CR |
Debug MCU configuration register, Address offset: 0x04
| __IO uint32_t DCMI_TypeDef::CR |
DCMI control register 1, Address offset: 0x00
| __IO uint32_t DMA2D_TypeDef::CR |
DMA2D Control Register, Address offset: 0x00
| __IO uint32_t DSI_TypeDef::CR |
DSI Host Control Register, Address offset: 0x04
| __IO uint32_t FMAC_TypeDef::CR |
FMAC Control register, Address offset: 0x10
| __IO uint32_t GFXMMU_TypeDef::CR |
GFXMMU configuration register, Address offset: 0x00
| __IO uint32_t GTZC_TZSC_TypeDef::CR |
TZSC control register, Address offset: 0x00
| __IO uint32_t GTZC_MPCBB_TypeDef::CR |
MPCBBx control register, Address offset: 0x00
| __IO uint32_t GFXTIM_TypeDef::CR |
GFXTIM configuration register, Address offset: 0x00
| __IO uint32_t JPEG_TypeDef::CR |
JPEG Control Register (JPEG_CR), Address offset: 30h
| __IO uint32_t LTDC_Layer_TypeDef::CR |
LTDC Layerx Control Register Address offset: 0x84
| __IO uint32_t ICACHE_TypeDef::CR |
ICACHE control register, Address offset: 0x00
| __IO uint32_t DCACHE_TypeDef::CR |
DCACHE control register, Address offset: 0x00
| __IO uint32_t PSSI_TypeDef::CR |
PSSI control register, Address offset: 0x000
| __IO uint32_t LPTIM_TypeDef::CR |
LPTIM Control register, Address offset: 0x10
| __IO uint32_t XSPI_TypeDef::CR |
XSPI Control register, Address offset: 0x000
| __IO uint32_t OTFDEC_TypeDef::CR |
OTFDEC Control register, Address offset: 0x000
| __IO uint32_t XSPIM_TypeDef::CR |
OCTOSPIM IO Manager Control register, Address offset: 0x00
| __IO uint32_t RAMCFG_TypeDef::CR |
Control Register, Address offset: 0x00
| __IO uint32_t RCC_TypeDef::CR |
RCC clock control register Address offset: 0x00
| __IO uint32_t PKA_TypeDef::CR |
PKA control register, Address offset: 0x00
| __IO uint32_t RTC_TypeDef::CR |
RTC control register, Address offset: 0x18
| __IO uint32_t DLYB_TypeDef::CR |
DELAY BLOCK control register, Address offset: 0x00
| __IO uint32_t UCPD_TypeDef::CR |
UCPD control register, Address offset: 0x0C
| __IO uint32_t ADC_TypeDef::CR |
ADC control register, Address offset: 0x08
| __IO uint32_t TSC_TypeDef::CR |
TSC control register, Address offset: 0x00
| __IO uint32_t WWDG_TypeDef::CR |
WWDG Control register, Address offset: 0x00
| __IO uint32_t I2C_TypeDef::CR1 |
I2C Control register 1, Address offset: 0x00
| __IO uint32_t TIM_TypeDef::CR1 |
TIM control register 1, Address offset: 0x00
| __IO uint32_t PWR_TypeDef::CR1 |
Power control register 1, Address offset: 0x00
| __IO uint32_t TAMP_TypeDef::CR1 |
TAMP configuration register 1, Address offset: 0x00
| __IO uint32_t USART_TypeDef::CR1 |
USART Control register 1, Address offset: 0x00
| __IO uint32_t SAI_Block_TypeDef::CR1 |
SAI block x configuration register 1, Address offset: 0x04
| __IO uint32_t SPI_TypeDef::CR1 |
SPI/I2S Control register 1, Address offset: 0x00
| __IO uint32_t I2C_TypeDef::CR2 |
I2C Control register 2, Address offset: 0x04
| __IO uint32_t TIM_TypeDef::CR2 |
TIM control register 2, Address offset: 0x04
| __IO uint32_t PWR_TypeDef::CR2 |
Power control register 2, Address offset: 0x04
| __IO uint32_t TAMP_TypeDef::CR2 |
TAMP configuration register 2, Address offset: 0x04
| __IO uint32_t USART_TypeDef::CR2 |
USART Control register 2, Address offset: 0x04
| __IO uint32_t SAI_Block_TypeDef::CR2 |
SAI block x configuration register 2, Address offset: 0x08
| __IO uint32_t SPI_TypeDef::CR2 |
SPI Control register 2, Address offset: 0x04
| __IO uint32_t PWR_TypeDef::CR3 |
Power control register 3, Address offset: 0x08
| __IO uint32_t TAMP_TypeDef::CR3 |
TAMP configuration register 3, Address offset: 0x08
| __IO uint32_t USART_TypeDef::CR3 |
USART Control register 3, Address offset: 0x08
| __IO uint32_t PWR_TypeDef::CR4 |
Power power control register 4, Address offset: 0xA8
| __IO uint32_t PWR_TypeDef::CR5 |
Power power control register 5, Address offset: 0xAC
| __IO uint32_t SPI_TypeDef::CRCPOLY |
SPI CRC Polynomial register, Address offset: 0x40
| __IO uint32_t FDCAN_GlobalTypeDef::CREL |
FDCAN Core Release register, Address offset: 0x000
| __IO uint32_t ICACHE_TypeDef::CRR0 |
ICACHE region 0 configuration register, Address offset: 0x20
| __IO uint32_t ICACHE_TypeDef::CRR1 |
ICACHE region 1 configuration register, Address offset: 0x24
| __IO uint32_t ICACHE_TypeDef::CRR2 |
ICACHE region 2 configuration register, Address offset: 0x28
| __IO uint32_t ICACHE_TypeDef::CRR3 |
ICACHE region 3 configuration register, Address offset: 0x2C
| __IO uint32_t RCC_TypeDef::CRRCR |
RCC Clock Recovery RC Register Address offset: 0x14
| __IO uint32_t DMA_Channel_TypeDef::CSAR |
DMA channel x source address register, Address offset: 0x9C + (x * 0x80)
| __IO uint32_t SYSCFG_TypeDef::CSLCKR |
SYSCFG CPU secure lock register, Address offset: 0x10
| __IO uint32_t HASH_TypeDef::CSR[54] |
HASH context swap registers, Address offset: 0x0F8-0x1CC
| __IO uint32_t DMA_Channel_TypeDef::CSR |
DMA channel x flag status register, Address offset: 0x60 + (x * 0x80)
| __IO uint32_t COMP_TypeDef::CSR |
Comparator control and status register, Address offset: 0x00
| __IO uint32_t OPAMP_TypeDef::CSR |
OPAMP control/status register, Address offset: 0x00
| __IO uint32_t OPAMP_Common_TypeDef::CSR |
OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00
| __IO uint32_t RCC_TypeDef::CSR |
V33 Clock Control & Status Register Address offset: 0xF4
| __IO uint32_t VREFBUF_TypeDef::CSR |
VREFBUF control and status register, Address offset: 0x00
| __IO uint32_t ADC_Common_TypeDef::CSR |
ADC common status register, Address offset: 0x300
| __IO uint32_t CORDIC_TypeDef::CSR |
CORDIC control and status register, Address offset: 0x00
| __IO uint32_t COMP_Common_TypeDef::CSR_EVEN |
COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04
| __IO uint32_t COMP_Common_TypeDef::CSR_ODD |
COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00
| __IO uint32_t DMA_Channel_TypeDef::CTR1 |
DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80)
| __IO uint32_t DMA_Channel_TypeDef::CTR2 |
DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80)
| __IO uint32_t DMA_Channel_TypeDef::CTR3 |
DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80)
| __IO uint32_t DCMI_TypeDef::CWSIZER |
DCMI crop window size, Address offset: 0x24
| __IO uint32_t DCMI_TypeDef::CWSTRTR |
DCMI crop window start, Address offset: 0x20
| __IO uint32_t USB_OTG_DeviceTypeDef::DAINT |
dev All Endpoints Itr Reg, Address offset: 818h
| __IO uint32_t USB_OTG_DeviceTypeDef::DAINTMSK |
dev All Endpoints Itr Mask, Address offset: 81Ch
| __IO uint32_t PWR_TypeDef::DBPR |
Power disable backup domain register, Address offset: 0x28
| __IO uint32_t FDCAN_GlobalTypeDef::DBTP |
FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C
| __IO uint32_t LTDC_Layer_TypeDef::DCCR |
LTDC Layerx Default Color Configuration Register Address offset: 0x9C
| __IO uint32_t USB_OTG_DeviceTypeDef::DCFG |
dev Configuration Register, Address offset: 800h
| __I uint32_t SDMMC_TypeDef::DCOUNT |
SDMMC data counter register, Address offset: 0x30
| __IO uint32_t TIM_TypeDef::DCR |
TIM DMA control register, Address offset: 0x3DC
| __IO uint32_t XSPI_TypeDef::DCR1 |
XSPI Device Configuration register 1, Address offset: 0x008
| __IO uint32_t XSPI_TypeDef::DCR2 |
XSPI Device Configuration register 2, Address offset: 0x00C
| __IO uint32_t XSPI_TypeDef::DCR3 |
XSPI Device Configuration register 3, Address offset: 0x010
| __IO uint32_t XSPI_TypeDef::DCR4 |
XSPI Device Configuration register 4, Address offset: 0x014
| __IO uint32_t USB_OTG_DeviceTypeDef::DCTL |
dev Control Register, Address offset: 804h
| __IO uint32_t SDMMC_TypeDef::DCTRL |
SDMMC data control register, Address offset: 0x2C
| __IO uint32_t USB_OTG_DeviceTypeDef::DEACHINT |
dedicated EP interrupt, Address offset: 838h
| __IO uint32_t USB_OTG_DeviceTypeDef::DEACHMSK |
dedicated EP msk, Address offset: 83Ch
| __IO uint32_t RAMCFG_TypeDef::DEAR |
ECC Double Error Address Register, Address offset: 0x10
| __IO uint32_t MDF_Filter_TypeDef::DFLTCICR |
MDF MCIC Configuration Register, Address offset: 0x8C
| __IO uint32_t MDF_Filter_TypeDef::DFLTCR |
MDF Digital Filter Control Register, Address offset: 0x88
| __IO uint32_t MDF_Filter_TypeDef::DFLTDR |
MDF Digital Filter Data Register, Address offset: 0xF0
| __IO uint32_t MDF_Filter_TypeDef::DFLTIER |
MDF DFLT Interrupt enable Register, Address offset: 0xAC
| __IO uint32_t MDF_Filter_TypeDef::DFLTINTR |
MDF Integrator Configuration Register, Address offset: 0x94
| __IO uint32_t MDF_Filter_TypeDef::DFLTISR |
MDF DFLT Interrupt status Register, Address offset: 0xB0
| __IO uint32_t MDF_Filter_TypeDef::DFLTRSFR |
MDF Reshape Filter Configuration Register, Address offset: 0x90
| __IO uint32_t DAC_TypeDef::DHR12L1 |
DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C
| __IO uint32_t DAC_TypeDef::DHR12L2 |
DAC channel2 12-bit left aligned data holding register, Address offset: 0x18
| __IO uint32_t DAC_TypeDef::DHR12LD |
DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
| __IO uint32_t DAC_TypeDef::DHR12R1 |
DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
| __IO uint32_t DAC_TypeDef::DHR12R2 |
DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
| __IO uint32_t DAC_TypeDef::DHR12RD |
Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
| __IO uint32_t DAC_TypeDef::DHR8R1 |
DAC channel1 8-bit right aligned data holding register, Address offset: 0x10
| __IO uint32_t DAC_TypeDef::DHR8R2 |
DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
| __IO uint32_t DAC_TypeDef::DHR8RD |
DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28
| __IO uint32_t JPEG_TypeDef::DHTMEM[103] |
JPEG DHTMem tables, Address offset: 360h-4F8h
| __IO uint32_t USB_OTG_INEndpointTypeDef::DIEPCTL |
dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h
| __IO uint32_t USB_OTG_INEndpointTypeDef::DIEPDMA |
IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h
| __IO uint32_t USB_OTG_DeviceTypeDef::DIEPEMPMSK |
dev empty msk, Address offset: 834h
| __IO uint32_t USB_OTG_INEndpointTypeDef::DIEPINT |
dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h
| __IO uint32_t USB_OTG_DeviceTypeDef::DIEPMSK |
dev IN Endpoint Mask, Address offset: 810h
| __IO uint32_t USB_OTG_INEndpointTypeDef::DIEPTSIZ |
IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h
| __IO uint32_t USB_OTG_GlobalTypeDef::DIEPTXF[0x0F] |
dev Periodic Transmit FIFO Address offset: 104h
| __IO uint32_t USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ |
EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h
| __IO uint32_t TIM_TypeDef::DIER |
TIM DMA/interrupt enable register, Address offset: 0x0C
| __IO uint32_t LPTIM_TypeDef::DIER |
LPTIM Interrupt Enable register, Address offset: 0x08
| __IO uint32_t ADC_TypeDef::DIFSEL |
ADC Differential Mode Selection Register, Address offset: 0xC0
| __IO uint32_t HASH_TypeDef::DIN |
HASH data input register, Address offset: 0x04
| __IO uint32_t USB_OTG_DeviceTypeDef::DINEP1MSK |
dedicated EP mask, Address offset: 844h
| __IO uint32_t AES_TypeDef::DINR |
AES data input register, Address offset: 0x08
| __IO uint32_t JPEG_TypeDef::DIR |
JPEG Data Input Register (JPEG_DIR), Address offset: 40h
| __IO uint32_t SDMMC_TypeDef::DLEN |
SDMMC data length register, Address offset: 0x28
| __IO uint32_t XSPI_TypeDef::DLR |
XSPI Data Length register, Address offset: 0x040
| __IO uint32_t DSI_TypeDef::DLTCR |
DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C
| __IO uint32_t DSI_TypeDef::DLTRCR |
DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4
| __IO uint32_t MDF_Filter_TypeDef::DLYCR |
MDF Delay control Register, Address offset: 0xA4
| __IO uint32_t TIM_TypeDef::DMAR |
TIM DMA address for full transfer, Address offset: 0x3E0
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::DOEPCTL |
dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::DOEPDMA |
dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::DOEPINT |
dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h
| __IO uint32_t USB_OTG_DeviceTypeDef::DOEPMSK |
dev OUT Endpoint Mask, Address offset: 814h
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::DOEPTSIZ |
dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h
| __IO uint32_t JPEG_TypeDef::DOR |
JPEG Data Output Register (JPEG_DOR), Address offset: 44h
| __IO uint32_t DAC_TypeDef::DOR1 |
DAC channel1 data output register, Address offset: 0x2C
| __IO uint32_t DAC_TypeDef::DOR2 |
DAC channel2 data output register, Address offset: 0x30
| __IO uint32_t USB_OTG_DeviceTypeDef::DOUTEP1MSK |
dedicated EP msk, Address offset: 884h
| __IO uint32_t AES_TypeDef::DOUTR |
AES data output register, Address offset: 0x0C
| __IO uint32_t DSI_TypeDef::DPCBCR |
D-PHY clock band control register, Address offset: 0xC04
| __IO uint32_t DSI_TypeDef::DPCSRCR |
D-PHY clock slew rate control register, Address offset: 0xC34
| __IO uint32_t DSI_TypeDef::DPDL0BCR |
D-PHY data Lane0 band control register, Address offset: 0x0C70
| __IO uint32_t DSI_TypeDef::DPDL0HSOCR |
D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C
| __IO uint32_t DSI_TypeDef::DPDL0LPXOCR |
D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60
| __IO uint32_t DSI_TypeDef::DPDL0SRCR |
D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0
| __IO uint32_t DSI_TypeDef::DPDL1BCR |
D-PHY data Lane1 band control register, Address offset: 0x0D08
| __IO uint32_t DSI_TypeDef::DPDL1HSOCR |
D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4
| __IO uint32_t DSI_TypeDef::DPDL1LPXOCR |
D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8
| __IO uint32_t DSI_TypeDef::DPDL1SRCR |
D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38
| __IO uint32_t CRC_TypeDef::DR |
CRC Data register, Address offset: 0x00
| __IO uint32_t RNG_TypeDef::DR |
RNG data register, Address offset: 0x08
| __IO uint32_t DCMI_TypeDef::DR |
DCMI data register, Address offset: 0x28
| __IO uint32_t PSSI_TypeDef::DR |
PSSI data register, Address offset: 0x028
| __IO uint32_t XSPI_TypeDef::DR |
XSPI Data register, Address offset: 0x050
| __IO uint32_t RTC_TypeDef::DR |
RTC date register, Address offset: 0x04
| __IO uint32_t SAI_Block_TypeDef::DR |
SAI block x data register, Address offset: 0x20
| __IO uint32_t ADC_TypeDef::DR |
ADC regular data register, Address offset: 0x40
| __IO uint32_t USB_OTG_DeviceTypeDef::DSTS |
dev Status Register (RO), Address offset: 808h
| __IO uint32_t USB_OTG_DeviceTypeDef::DTHRCTL |
dev threshold, Address offset: 830h
| __IO uint32_t SDMMC_TypeDef::DTIMER |
SDMMC data timer register, Address offset: 0x24
| __IO uint32_t TIM_TypeDef::DTR2 |
TIM deadtime register 2, Address offset: 0x54
| __IO uint32_t USB_OTG_INEndpointTypeDef::DTXFSTS |
IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h
| __IO uint32_t USB_OTG_DeviceTypeDef::DVBUSDIS |
dev VBUS discharge Register, Address offset: 828h
| __IO uint32_t USB_OTG_DeviceTypeDef::DVBUSPULSE |
dev VBUS Pulse Register, Address offset: 82Ch
| __IO uint32_t GFXMMU_TypeDef::DVR |
GFXMMU default value register, Address offset: 0x10
| __IO uint32_t RAMCFG_TypeDef::ECCKEY |
SRAM ECC Key Register, Address offset: 0x24
| __IO uint32_t FLASH_TypeDef::ECCR |
FLASH ECC register, Address offset: 0x30
| __IO uint32_t FMC_Bank3_TypeDef::ECCR |
NAND Flash ECC result registers, Address offset: 0x94
| __IO uint32_t TIM_TypeDef::ECR |
TIM encoder control register, Address offset: 0x58
| __IO uint32_t FDCAN_GlobalTypeDef::ECR |
FDCAN Error Counter register, Address offset: 0x040
| __IO uint32_t TIM_TypeDef::EGR |
TIM event generation register, Address offset: 0x14
| __IO uint32_t EXTI_TypeDef::EMR1 |
EXTI Event Mask Register 1, Address offset: 0x84
| __IO uint32_t FDCAN_GlobalTypeDef::ENDN |
FDCAN Endian register, Address offset: 0x004
| __IO uint32_t TAMP_TypeDef::ERCFGR |
TAMP erase configuration register, Address offset: 0x54
| __IO uint32_t RAMCFG_TypeDef::ERKEYR |
SRAM Erase Key Register, Address offset: 0x28
| __IO uint32_t DCMI_TypeDef::ESCR |
DCMI embedded synchronization code register, Address offset: 0x18
| __IO uint32_t DCMI_TypeDef::ESUR |
DCMI embedded synchronization unmask register, Address offset: 0x1C
| __IO uint32_t GFXTIM_TypeDef::EVCR |
GFXTIM events control register, Address offset: 0x10
| __IO uint32_t GFXTIM_TypeDef::EVSR |
GFXTIM events selection register, Address offset: 0x14
| __IO uint32_t IWDG_TypeDef::EWCR |
IWDG Early Wakeup register, Address offset: 0x14
| __IO uint32_t EXTI_TypeDef::EXTICR[4] |
EXIT External Interrupt Configuration Register, 0x60 – 0x6C
| __IO uint32_t DSI_TypeDef::FBSR |
DSI Host FIFO and Buffer Status Register, Address offset: 0x168
| __IO uint32_t GFXTIM_TypeDef::FCCRR |
GFXTIM frame clock counter reload register, Address offset: 0x44
| __IO uint32_t GFXMMU_TypeDef::FCR |
GFXMMU flag clear register, Address offset: 0x08
| __IO uint32_t ICACHE_TypeDef::FCR |
ICACHE Flag clear register, Address offset: 0x0C
| __IO uint32_t DCACHE_TypeDef::FCR |
DCACHE Flag clear register, Address offset: 0x0C
| __IO uint32_t XSPI_TypeDef::FCR |
XSPI Flag Clear register, Address offset: 0x024
| __IO uint32_t GTZC_TZIC_TypeDef::FCR1 |
TZIC flag clear register 1, Address offset: 0x20
| __IO uint32_t GTZC_TZIC_TypeDef::FCR2 |
TZIC flag clear register 2, Address offset: 0x24
| __IO uint32_t GTZC_TZIC_TypeDef::FCR3 |
TZIC flag clear register 3, Address offset: 0x28
| __IO uint32_t GTZC_TZIC_TypeDef::FCR4 |
TZIC flag clear register 3, Address offset: 0x2C
| __IO uint32_t DMA2D_TypeDef::FGCLUT[256] |
DMA2D Foreground CLUT, Address offset:400-7FC
| __IO uint32_t DMA2D_TypeDef::FGCMAR |
DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C
| __IO uint32_t DMA2D_TypeDef::FGCOLR |
DMA2D Foreground Color Register, Address offset: 0x20
| __IO uint32_t DMA2D_TypeDef::FGMAR |
DMA2D Foreground Memory Address Register, Address offset: 0x0C
| __IO uint32_t DMA2D_TypeDef::FGOR |
DMA2D Foreground Offset Register, Address offset: 0x10
| __IO uint32_t DMA2D_TypeDef::FGPFCCR |
DMA2D Foreground PFC Control Register, Address offset: 0x1C
| __IO uint32_t SDMMC_TypeDef::FIFO |
SDMMC data FIFO register, Address offset: 0x80
| __IO uint32_t DSI_TypeDef::FIR[2] |
DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF
| __IO uint32_t TAMP_TypeDef::FLTCR |
TAMP filter control register, Address offset: 0x0C
| __IO uint32_t EXTI_TypeDef::FPR1 |
EXTI Falling Pending Register 1, Address offset: 0x10
| __IO uint32_t SYSCFG_TypeDef::FPUIMR |
SYSCFG FPU interrupt mask register, Address offset: 0x08
| __IO uint32_t SAI_Block_TypeDef::FRCR |
SAI block x frame configuration register, Address offset: 0x0C
| __IO uint32_t EXTI_TypeDef::FTSR1 |
EXTI Falling Trigger Selection Register 1, Address offset: 0x04
| __IO uint32_t USB_OTG_GlobalTypeDef::GADPCTL |
ADP Timer, Control and Status Register, Address offset: 60Ch
| __IO uint32_t USB_OTG_GlobalTypeDef::GAHBCFG |
Core AHB Configuration Register, Address offset: 008h
| __IO uint32_t USB_OTG_GlobalTypeDef::GCCFG |
General Purpose IO Register, Address offset: 038h
| __IO uint32_t ADC_TypeDef::GCOMP |
ADC gain compensation register, Address offset: 0x70
| __IO uint32_t LTDC_TypeDef::GCR |
LTDC Global Control Register, Address offset: 0x18
| __IO uint32_t MDF_TypeDef::GCR |
MDF Global Control register, Address offset: 0x00
| __IO uint32_t SAI_TypeDef::GCR |
SAI global configuration register, Address offset: 0x00
| __IO uint32_t USB_OTG_GlobalTypeDef::GDFIFOCFG |
DFIFO Software Config Register, Address offset: 05Ch
| __IO uint32_t DSI_TypeDef::GHCR |
DSI Host Generic Header Configuration Register, Address offset: 0x6C
| __IO uint32_t USB_OTG_GlobalTypeDef::GHWCFG1 |
User HW config1, Address offset: 044h
| __IO uint32_t USB_OTG_GlobalTypeDef::GHWCFG2 |
User HW config2, Address offset: 048h
| __IO uint32_t USB_OTG_GlobalTypeDef::GHWCFG3 |
User HW config3, Address offset: 04Ch
| __IO uint32_t USB_OTG_GlobalTypeDef::GINTMSK |
Core Interrupt Mask Register, Address offset: 018h
| __IO uint32_t USB_OTG_GlobalTypeDef::GINTSTS |
Core Interrupt Register, Address offset: 014h
| __IO uint32_t USB_OTG_GlobalTypeDef::GLPMCFG |
LPM Register, Address offset: 054h
| __IO uint32_t USB_OTG_GlobalTypeDef::GOTGCTL |
USB_OTG Control and Status Register, Address offset: 000h
| __IO uint32_t USB_OTG_GlobalTypeDef::GOTGINT |
USB_OTG Interrupt Register, Address offset: 004h
| __IO uint32_t DSI_TypeDef::GPDR |
DSI Host Generic Payload Data Register, Address offset: 0x70
| __IO uint32_t DSI_TypeDef::GPSR |
DSI Host Generic Packet Status Register, Address offset: 0x74
| __IO uint32_t USB_OTG_GlobalTypeDef::GPWRDN |
Power Down Register, Address offset: 058h
| __IO uint32_t USB_OTG_GlobalTypeDef::GRSTCTL |
Core Reset Register, Address offset: 010h
| __IO uint32_t USB_OTG_GlobalTypeDef::GRXFSIZ |
Receive FIFO Size Register, Address offset: 024h
| __IO uint32_t USB_OTG_GlobalTypeDef::GRXSTSP |
Receive Sts Q Read & POP Register, Address offset: 020h
| __IO uint32_t USB_OTG_GlobalTypeDef::GRXSTSR |
Receive Sts Q Read Register, Address offset: 01Ch
| __IO uint32_t USB_OTG_GlobalTypeDef::GSNPSID |
USB_OTG core ID, Address offset: 040h
| __IO uint32_t USART_TypeDef::GTPR |
USART Guard time and prescaler register, Address offset: 0x10
| __IO uint32_t USB_OTG_GlobalTypeDef::GUSBCFG |
Core USB Configuration Register, Address offset: 00Ch
| __IO uint32_t DSI_TypeDef::GVCIDR |
DSI Host Generic VCID Register, Address offset: 0x30
| __IO uint32_t USB_OTG_HostTypeDef::HAINT |
Host All Channels Interrupt Register, Address offset: 414h
| __IO uint32_t USB_OTG_HostTypeDef::HAINTMSK |
Host All Channels Interrupt Mask, Address offset: 418h
| __IO uint32_t USB_OTG_HostChannelTypeDef::HCCHAR |
Host Channel Characteristics Register, Address offset: 500h
| __IO uint32_t USB_OTG_HostChannelTypeDef::HCDMA |
Host Channel DMA Address Register, Address offset: 514h
| __IO uint32_t USB_OTG_HostTypeDef::HCFG |
Host Configuration Register, Address offset: 400h
| __IO uint32_t USB_OTG_HostChannelTypeDef::HCINT |
Host Channel Interrupt Register, Address offset: 508h
| __IO uint32_t USB_OTG_HostChannelTypeDef::HCINTMSK |
Host Channel Interrupt Mask Register, Address offset: 50Ch
| __IO uint32_t USB_OTG_HostChannelTypeDef::HCSPLT |
Host Channel Split Control Register, Address offset: 504h
| __IO uint32_t USB_OTG_HostChannelTypeDef::HCTSIZ |
Host Channel Transfer Size Register, Address offset: 510h
| __IO uint32_t USB_OTG_HostTypeDef::HFIR |
Host Frame Interval Register, Address offset: 404h
| __IO uint32_t USB_OTG_HostTypeDef::HFNUM |
Host Frame Nbr/Frame Remaining, Address offset: 408h
| __IO uint32_t XSPI_TypeDef::HLCR |
XSPI Hyperbus Latency Configuration register, Address offset: 0x200
| __IO uint32_t ICACHE_TypeDef::HMONR |
ICACHE hit monitor register, Address offset: 0x10
| __IO uint32_t USB_OTG_GlobalTypeDef::HNPTXSTS |
Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch
| __IO uint32_t FDCAN_GlobalTypeDef::HPMS |
FDCAN High Priority Message Status register, Address offset: 0x088
| __IO uint32_t USB_OTG_GlobalTypeDef::HPTXFSIZ |
Host Periodic Tx FIFO Size Reg, Address offset: 100h
| __IO uint32_t USB_OTG_HostTypeDef::HPTXSTS |
Host Periodic Tx FIFO/ Queue Status, Address offset: 410h
| __IO uint32_t HASH_TypeDef::HR[5] |
HASH digest registers, Address offset: 0x0C-0x1C
| __IO uint32_t HASH_DIGEST_TypeDef::HR[8] |
HASH digest registers, Address offset: 0x310-0x32C
| __IO uint32_t GPIO_TypeDef::HSLVR |
GPIO high-speed low voltage register, Address offset: 0x2C
| __IO uint32_t RNG_TypeDef::HTCR |
RNG health test configuration register, Address offset: 0x10
| __IO uint32_t ADC_TypeDef::HTR1 |
ADC watchdog higher threshold register 1, Address offset: 0xAC
| __IO uint32_t ADC_TypeDef::HTR2 |
ADC watchdog Higher threshold register 2, Address offset: 0xB4
| __IO uint32_t ADC_TypeDef::HTR3 |
ADC watchdog Higher threshold register 3, Address offset: 0xBC
| __IO uint32_t JPEG_TypeDef::HUFFBASE[32] |
JPEG HuffSymb tables, Address offset: 190h-20Ch
| __IO uint32_t JPEG_TypeDef::HUFFENC_AC0[88] |
JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch
| __IO uint32_t JPEG_TypeDef::HUFFENC_AC1[88] |
JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh
| __IO uint32_t JPEG_TypeDef::HUFFENC_DC0[8] |
JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh
| __IO uint32_t JPEG_TypeDef::HUFFENC_DC1[8] |
JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh
| __IO uint32_t JPEG_TypeDef::HUFFMIN[16] |
JPEG HuffMin tables, Address offset: 150h-18Ch
| __IO uint32_t JPEG_TypeDef::HUFFSYMB[84] |
JPEG HUFFSYMB tables, Address offset: 210h-35Ch
| __IO uint32_t FDCAN_Config_TypeDef::HWCFG |
FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0
| __IO uint32_t CRC_TypeDef::HWCFGR |
CRC IP HWCFGR register, Address offset: 0x3F0
| __IO uint32_t GFXMMU_TypeDef::HWCFGR |
GFXMMU hardware configuration register, Address offset: 0xFF0
| __IO uint32_t GFXTIM_TypeDef::HWCFGR |
GFXTIM HW configuration register, Address offset: 0x3F0
| __IO uint32_t I2C_TypeDef::ICR |
I2C Interrupt clear register, Address offset: 0x1C
| __IO uint32_t CRS_TypeDef::ICR |
CRS interrupt flag clear register, Address offset: 0x0C
| __IO uint32_t AES_TypeDef::ICR |
AES Interrupt Clear Register, Address offset: 0x308
| __IO uint32_t DCMI_TypeDef::ICR |
DCMI interrupt clear register, Address offset: 0x14
| __IO uint32_t GFXTIM_TypeDef::ICR |
GFXTIM interrupt clear register, Address offset: 0x34
| __IO uint32_t LTDC_TypeDef::ICR |
LTDC Interrupt Clear Register, Address offset: 0x3C
| __IO uint32_t PSSI_TypeDef::ICR |
PSSI interrupt clear register, Address offset: 0x014
| __IO uint32_t LPTIM_TypeDef::ICR |
LPTIM Interrupt Clear register, Address offset: 0x04
| __IO uint32_t OTFDEC_TypeDef::ICR |
OTFDEC Interrupt Clear register, Address offset: 0x304
| __IO uint32_t RAMCFG_TypeDef::ICR |
Interrupt Clear Register, Address offset: 0x14
| __IO uint32_t USART_TypeDef::ICR |
USART Interrupt flag Clear register, Address offset: 0x20
| __IO uint32_t SDMMC_TypeDef::ICR |
SDMMC interrupt clear register, Address offset: 0x38
| __IO uint32_t UCPD_TypeDef::ICR |
UCPD interrupt flag clear register Address offset: 0x18
| __IO uint32_t TSC_TypeDef::ICR |
TSC interrupt clear register, Address offset: 0x08
| __IO uint32_t RCC_TypeDef::ICSCR1 |
RCC internal clock sources calibration register 1 Address offset: 0x08
| __IO uint32_t RCC_TypeDef::ICSCR2 |
RCC internal clock sources calibration register 2 Address offset: 0x0C
| __IO uint32_t RCC_TypeDef::ICSCR3 |
RCC internal clock sources calibration register 3 Address offset: 0x10
| __IO uint32_t RTC_TypeDef::ICSR |
RTC initialization control and status register, Address offset: 0x0C
| __IO uint32_t DBGMCU_TypeDef::IDCODE |
MCU device ID code, Address offset: 0x00
| __IO uint32_t SDMMC_TypeDef::IDMABAR |
SDMMC DMA linked list memory base register,Address offset: 0x68
| __IO uint32_t SDMMC_TypeDef::IDMABASER |
SDMMC DMA buffer base address register, Address offset: 0x58
| __IO uint32_t SDMMC_TypeDef::IDMABSIZE |
SDMMC DMA buffer size register, Address offset: 0x54
| __IO uint32_t SDMMC_TypeDef::IDMACTRL |
SDMMC DMA control register, Address offset: 0x50
| __IO uint32_t SDMMC_TypeDef::IDMALAR |
SDMMC DMA linked list address register, Address offset: 0x64
| __IO uint32_t CRC_TypeDef::IDR |
CRC Independent data register, Address offset: 0x04
| __IO uint32_t GPIO_TypeDef::IDR |
GPIO port input data register, Address offset: 0x10
| __IO uint32_t FDCAN_GlobalTypeDef::IE |
FDCAN Interrupt Enable register, Address offset: 0x054
| __IO uint32_t AES_TypeDef::IER |
AES Interrupt Enable Register, Address offset: 0x300
| __IO uint32_t DCMI_TypeDef::IER |
DCMI interrupt enable register, Address offset: 0x0C
| __IO uint32_t DSI_TypeDef::IER[2] |
DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB
| __IO uint32_t GFXTIM_TypeDef::IER |
GFXTIM interrupt enable register, Address offset: 0x38
| __IO uint32_t LTDC_TypeDef::IER |
LTDC Interrupt Enable Register, Address offset: 0x34
| __IO uint32_t ICACHE_TypeDef::IER |
ICACHE interrupt enable register, Address offset: 0x08
| __IO uint32_t DCACHE_TypeDef::IER |
DCACHE interrupt enable register, Address offset: 0x08
| __IO uint32_t PSSI_TypeDef::IER |
PSSI interrupt enable register, Address offset: 0x00C
| __IO uint32_t OTFDEC_TypeDef::IER |
OTFDEC Interrupt Enable register, Address offset: 0x308
| __IO uint32_t RAMCFG_TypeDef::IER |
Interrupt Enable Register, Address offset: 0x04
| __IO uint32_t TAMP_TypeDef::IER |
TAMP interrupt enable register, Address offset: 0x2C
| __IO uint32_t ADC_TypeDef::IER |
ADC Interrupt Enable Register, Address offset: 0x04
| __IO uint32_t SPI_TypeDef::IER |
SPI Interrupt Enable register, Address offset: 0x10
| __IO uint32_t TSC_TypeDef::IER |
TSC interrupt enable register, Address offset: 0x04
| __IO uint32_t GTZC_TZIC_TypeDef::IER1 |
TZIC interrupt enable register 1, Address offset: 0x00
| __IO uint32_t GTZC_TZIC_TypeDef::IER2 |
TZIC interrupt enable register 2, Address offset: 0x04
| __IO uint32_t GTZC_TZIC_TypeDef::IER3 |
TZIC interrupt enable register 3, Address offset: 0x08
| __IO uint32_t GTZC_TZIC_TypeDef::IER4 |
TZIC interrupt enable register 4, Address offset: 0x0C
| __IO uint32_t DMA2D_TypeDef::IFCR |
DMA2D Interrupt Flag Clear Register, Address offset: 0x08
| __IO uint32_t SPI_TypeDef::IFCR |
SPI Interrupt/Status Flags Clear register, Address offset: 0x18
| __IO uint32_t FDCAN_GlobalTypeDef::ILE |
FDCAN Interrupt Line Enable register, Address offset: 0x05C
| __IO uint32_t FDCAN_GlobalTypeDef::ILS |
FDCAN Interrupt Line Select register, Address offset: 0x058
| __IO uint32_t HASH_TypeDef::IMR |
HASH interrupt enable register, Address offset: 0x20
| __IO uint32_t SAI_Block_TypeDef::IMR |
SAI block x interrupt mask register, Address offset: 0x14
| __IO uint32_t UCPD_TypeDef::IMR |
UCPD interrupt mask register, Address offset: 0x10
| __IO uint32_t EXTI_TypeDef::IMR1 |
EXTI Interrupt Mask Register 1, Address offset: 0x80
| __IO uint32_t CRC_TypeDef::INIT |
Initial CRC value register, Address offset: 0x10
| __IO uint32_t TSC_TypeDef::IOASCR |
TSC I/O analog switch control register, Address offset: 0x18
| __IO uint32_t TSC_TypeDef::IOCCR |
TSC I/O channel control register, Address offset: 0x28
| __IO uint32_t TSC_TypeDef::IOGCSR |
TSC I/O group control status register, Address offset: 0x30
| __IO uint32_t TSC_TypeDef::IOGXCR[8] |
TSC I/O group x counter register, Address offset: 0x34-50
| __IO uint32_t TSC_TypeDef::IOHCR |
TSC I/O hysteresis control register, Address offset: 0x10
| __IO uint32_t TSC_TypeDef::IOSCR |
TSC I/O sampling control register, Address offset: 0x20
| __IO uint32_t GFXMMU_TypeDef::IPIDR |
GFXMMU identification register, Address offset: 0xFF8
| __IO uint32_t GFXTIM_TypeDef::IPIDR |
GFXTIM identification register, Address offset: 0x3F8
| __IO uint32_t FDCAN_Config_TypeDef::IPIDR |
FDCAN IP ID register, Address offset: 0x100 + 0x2F8
| __IO uint32_t XSPI_TypeDef::IR |
XSPI Instruction register, Address offset: 0x110
| __IO uint32_t FDCAN_GlobalTypeDef::IR |
FDCAN Interrupt register, Address offset: 0x050
| __IO uint32_t I2C_TypeDef::ISR |
I2C Interrupt and status register, Address offset: 0x18
| __IO uint32_t CRS_TypeDef::ISR |
CRS interrupt and status register, Address offset: 0x08
| __IO uint32_t AES_TypeDef::ISR |
AES Interrupt Status Register, Address offset: 0x304
| __IO uint32_t DMA2D_TypeDef::ISR |
DMA2D Interrupt Status Register, Address offset: 0x04
| __IO uint32_t DSI_TypeDef::ISR[2] |
DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3
| __IO uint32_t GFXTIM_TypeDef::ISR |
GFXTIM interrupt status register, Address offset: 0x30
| __IO uint32_t LTDC_TypeDef::ISR |
LTDC Interrupt Status Register, Address offset: 0x38
| __IO uint32_t LPTIM_TypeDef::ISR |
LPTIM Interrupt and Status register, Address offset: 0x00
| __IO uint32_t OTFDEC_TypeDef::ISR |
OTFDEC Interrupt Status register, Address offset: 0x300
| __IO uint32_t RAMCFG_TypeDef::ISR |
Interrupt Status Register, Address offset: 0x08
| __IO uint32_t USART_TypeDef::ISR |
USART Interrupt and status register, Address offset: 0x1C
| __IO uint32_t ADC_TypeDef::ISR |
ADC Interrupt and Status Register, Address offset: 0x00
| __IO uint32_t TSC_TypeDef::ISR |
TSC interrupt status register, Address offset: 0x0C
| __IO uint32_t AES_TypeDef::IVR0 |
AES initialization vector register 0, Address offset: 0x20
| __IO uint32_t AES_TypeDef::IVR1 |
AES initialization vector register 1, Address offset: 0x24
| __IO uint32_t AES_TypeDef::IVR2 |
AES initialization vector register 2, Address offset: 0x28
| __IO uint32_t AES_TypeDef::IVR3 |
AES initialization vector register 3, Address offset: 0x2C
| __IO uint32_t ADC_TypeDef::JDR1 |
ADC injected data register 1, Address offset: 0x80
| __IO uint32_t ADC_TypeDef::JDR2 |
ADC injected data register 2, Address offset: 0x84
| __IO uint32_t ADC_TypeDef::JDR3 |
ADC injected data register 3, Address offset: 0x88
| __IO uint32_t ADC_TypeDef::JDR4 |
ADC injected data register 4, Address offset: 0x8C
| __IO uint32_t ADC_TypeDef::JSQR |
ADC injected sequence register, Address offset: 0x4C
| __IO uint32_t AES_TypeDef::KEYR0 |
AES key register 0, Address offset: 0x10
| __IO uint32_t AES_TypeDef::KEYR1 |
AES key register 1, Address offset: 0x14
| __IO uint32_t AES_TypeDef::KEYR2 |
AES key register 2, Address offset: 0x18
| __IO uint32_t AES_TypeDef::KEYR3 |
AES key register 3, Address offset: 0x1C
| __IO uint32_t AES_TypeDef::KEYR4 |
AES key register 4, Address offset: 0x30
| __IO uint32_t AES_TypeDef::KEYR5 |
AES key register 5, Address offset: 0x34
| __IO uint32_t AES_TypeDef::KEYR6 |
AES key register 6, Address offset: 0x38
| __IO uint32_t AES_TypeDef::KEYR7 |
AES key register 7, Address offset: 0x3C
| __IO uint32_t IWDG_TypeDef::KR |
IWDG Key register, Address offset: 0x00
| __IO uint32_t DSI_TypeDef::LCCCR |
DSI Host LTDC Current Color Coding Register, Address offset: 0x110
| __IO uint32_t DSI_TypeDef::LCCR |
DSI Host LTDC Command Configuration Register, Address offset: 0x64
| __IO uint32_t GFXTIM_TypeDef::LCCRR |
GFXTIM line clock counter reload register, Address offset: 0x40
| __IO uint32_t GPIO_TypeDef::LCKR |
GPIO port configuration lock register, Address offset: 0x1C
| __IO uint32_t DSI_TypeDef::LCOLCR |
DSI Host LTDC Color Coding Register, Address offset: 0x10
| __IO uint32_t DSI_TypeDef::LCVCIDR |
DSI Host LTDC Current VCID Register, Address offset: 0x10C
| __IO uint32_t LTDC_TypeDef::LIPCR |
LTDC Line Interrupt Position Configuration Register, Address offset: 0x40
| __IO uint32_t EXTI_TypeDef::LOCKR |
EXTI Lock Register, Address offset: 0x70
| __IO uint32_t DSI_TypeDef::LPCR |
DSI Host LTDC Polarity Configuration Register, Address offset: 0x14
| __IO uint32_t DSI_TypeDef::LPMCCR |
DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118
| __IO uint32_t DSI_TypeDef::LPMCR |
DSI Host Low-Power Mode Configuration Register, Address offset: 0x18
| __IO uint32_t OPAMP_TypeDef::LPOTR |
OPAMP offset trimming register for low power mode, Address offset: 0x08
| __IO uint32_t XSPI_TypeDef::LPTR |
XSPI Low Power Timeout register, Address offset: 0x130
| __IO uint32_t ADC_TypeDef::LTR1 |
ADC watchdog Lower threshold register 1, Address offset: 0xA8
| __IO uint32_t ADC_TypeDef::LTR2 |
ADC watchdog Lower threshold register 2, Address offset: 0xB0
| __IO uint32_t ADC_TypeDef::LTR3 |
ADC watchdog Lower threshold register 3, Address offset: 0xB8
| __IO uint32_t GFXMMU_TypeDef::LUT[2048] |
GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1]
| __IO uint32_t DSI_TypeDef::LVCIDR |
DSI Host LTDC VCID Register, Address offset: 0x0C
| __IO uint32_t DMA2D_TypeDef::LWR |
DMA2D Line Watermark Register, Address offset: 0x48
| __IO uint32_t SDMMC_TypeDef::MASK |
SDMMC mask register, Address offset: 0x3C
| __IO uint32_t DAC_TypeDef::MCR |
DAC mode control register, Address offset: 0x3C
| __IO uint32_t DSI_TypeDef::MCR |
DSI Host Mode Configuration Register, Address offset: 0x34
| __IO uint32_t SYSCFG_TypeDef::MESR |
SYSCFG Memory Erase Status register, Address offset: 0x18
| __IO uint32_t PSSI_TypeDef::MIS |
PSSI masked interrupt status register, Address offset: 0x010
| __IO uint32_t DCMI_TypeDef::MISR |
DCMI masked interrupt status register, Address offset: 0x10
| __IO uint32_t DMA_TypeDef::MISR |
DMA non secure masked interrupt status register, Address offset: 0x0C
| __IO uint32_t RTC_TypeDef::MISR |
RTC masked interrupt status register, Address offset: 0x54
| __IO uint32_t TAMP_TypeDef::MISR |
TAMP masked interrupt status register, Address offset: 0x34
| __IO uint32_t ICACHE_TypeDef::MMONR |
ICACHE miss monitor register, Address offset: 0x14
| __IO uint32_t GPIO_TypeDef::MODER |
GPIO port mode register, Address offset: 0x00
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM1ACFGR |
TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM1AR |
TZSC memory 1 sub-region A watermark register, Address offset: 0x44
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM1BCFGR |
TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM1BR |
TZSC memory 1 sub-region B watermark register, Address offset: 0x4C
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM2ACFGR |
TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM2AR |
TZSC memory 2 sub-region A watermark register, Address offset: 0x54
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM2BCFGR |
TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM2BR |
TZSC memory 2 sub-region B watermark register, Address offset: 0x5C
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM3ACFGR |
TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM3AR |
TZSC memory 3 sub-region A watermark register, Address offset: 0x64
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM4ACFGR |
TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM4AR |
TZSC memory 4 sub-region A watermark register, Address offset: 0x74
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM5ACFGR |
TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM5AR |
TZSC memory 5 sub-region A watermark register, Address offset: 0x84
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM5BCFGR |
TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM5BR |
TZSC memory 5 sub-region B watermark register, Address offset: 0x8C
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM6ACFGR |
TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM6AR |
TZSC memory 6 sub-region A watermark register, Address offset: 0x94
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM6BCFGR |
TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98
| __IO uint32_t GTZC_TZSC_TypeDef::MPCWM6BR |
TZSC memory 6 sub-region B watermark register, Address offset: 0x9C
| __IO uint32_t FDCAN_GlobalTypeDef::NBTP |
FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C
| __IO uint32_t DMA2D_TypeDef::NLR |
DMA2D Number of Line Register, Address offset: 0x44
| __IO uint32_t FLASH_TypeDef::NSBOOTADD0R |
FLASH non-secure boot address 0 register, Address offset: 0x44
| __IO uint32_t FLASH_TypeDef::NSBOOTADD1R |
FLASH non-secure boot address 1 register, Address offset: 0x48
| __IO uint32_t RNG_TypeDef::NSCR |
RNG noise source control register , Address offset: 0x0C
| __IO uint32_t FLASH_TypeDef::NSCR |
FLASH non-secure control register, Address offset: 0x28
| __IO uint32_t FLASH_TypeDef::NSKEYR |
FLASH non-secure key register, Address offset: 0x08
| __IO uint32_t FLASH_TypeDef::NSSR |
FLASH non-secure status register, Address offset: 0x20
| __IO uint32_t I2C_TypeDef::OAR1 |
I2C Own address 1 register, Address offset: 0x08
| __IO uint32_t I2C_TypeDef::OAR2 |
I2C Own address 2 register, Address offset: 0x0C
| __IO uint32_t DMA2D_TypeDef::OCOLR |
DMA2D Output Color Register, Address offset: 0x38
| __IO uint32_t GPIO_TypeDef::ODR |
GPIO port output data register, Address offset: 0x14
| __IO uint32_t MDF_Filter_TypeDef::OECCR |
MDF Offset Error Compensation Control Register, Address offset: 0xB4
| __IO uint32_t FLASH_TypeDef::OEM1KEYR1 |
FLASH OEM1 key register 1, Address offset: 0x70
| __IO uint32_t FLASH_TypeDef::OEM1KEYR2 |
FLASH OEM1 key register 2, Address offset: 0x74
| __IO uint32_t FLASH_TypeDef::OEM2KEYR1 |
FLASH OEM2 key register 1, Address offset: 0x78
| __IO uint32_t FLASH_TypeDef::OEM2KEYR2 |
FLASH OEM2 key register 2, Address offset: 0x7C
| __IO uint32_t ADC_TypeDef::OFR1 |
ADC offset register 1, Address offset: 0x60
| __IO uint32_t ADC_TypeDef::OFR2 |
ADC offset register 2, Address offset: 0x64
| __IO uint32_t ADC_TypeDef::OFR3 |
ADC offset register 3, Address offset: 0x68
| __IO uint32_t ADC_TypeDef::OFR4 |
ADC offset register 4, Address offset: 0x6C
| __IO uint32_t MDF_Filter_TypeDef::OLDCR |
MDF Out-Of Limit Detector Control Register, Address offset: 0x98
| __IO uint32_t MDF_Filter_TypeDef::OLDTHHR |
MDF OLD Threshold High Register, Address offset: 0xA0
| __IO uint32_t MDF_Filter_TypeDef::OLDTHLR |
MDF OLD Threshold Low Register, Address offset: 0x9C
| __IO uint32_t DMA2D_TypeDef::OMAR |
DMA2D Output Memory Address Register, Address offset: 0x3C
| __IO uint32_t DMA2D_TypeDef::OOR |
DMA2D Output Offset Register, Address offset: 0x40
| __IO uint32_t DMA2D_TypeDef::OPFCCR |
DMA2D Output PFC Control Register, Address offset: 0x34
| __IO uint32_t FLASH_TypeDef::OPSR |
FLASH OPSR register, Address offset: 0x34
| __IO uint32_t FLASH_TypeDef::OPTKEYR |
FLASH option key register, Address offset: 0x10
| __IO uint32_t FLASH_TypeDef::OPTR |
FLASH option control register, Address offset: 0x40
| __IO uint32_t FDCAN_Config_TypeDef::OPTR |
FDCAN option register, Address offset: 0x100 + 0x204
| __IO uint32_t MDF_TypeDef::OR |
MDF Option Register, Address offset: 0x20
| __IO uint32_t ADC_TypeDef::OR |
ADC Option Register, Address offset: 0xD0
| __IO uint32_t TIM_TypeDef::OR1 |
TIM option register, Address offset: 0x68
| __IO uint32_t GPIO_TypeDef::OSPEEDR |
GPIO port output speed register, Address offset: 0x08
| __IO uint32_t SYSCFG_TypeDef::OTGHSPHYCR |
SYSCFG USB OTG_HS PHY register Address offset: 0x74
| __IO uint32_t SYSCFG_TypeDef::OTGHSPHYTUNER2 |
SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C
| __IO uint32_t OPAMP_TypeDef::OTR |
OPAMP offset trimming register for normal mode, Address offset: 0x04
| __IO uint32_t GPIO_TypeDef::OTYPER |
GPIO port output type register, Address offset: 0x04
| __IO uint32_t FMAC_TypeDef::PARAM |
FMAC Parameter register, Address offset: 0x0C
| __IO uint32_t FMC_Bank3_TypeDef::PATT |
NAND Flash Attribute memory space timing register, Address offset: 0x8C
| __IO uint32_t DSI_TypeDef::PCONFR |
DSI Host PHY Configuration Register, Address offset: 0xA4
| __IO uint32_t DSI_TypeDef::PCR |
DSI Host Protocol Configuration Register, Address offset: 0x2C
| __IO uint32_t XSPIM_TypeDef::PCR[8] |
OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20
| __IO uint32_t FMC_Bank3_TypeDef::PCR |
NAND Flash control register, Address offset: 0x80
| __IO uint32_t FMC_Bank1_TypeDef::PCSCNTR |
PSRAM chip-select counter register, Address offset: 0x20
| __IO uint32_t ADC_TypeDef::PCSEL |
ADC pre-channel selection, Address offset: 0x1C
| __IO uint32_t DSI_TypeDef::PCTLR |
DSI Host PHY Control Register, Address offset: 0xA0
| __IO uint32_t PWR_TypeDef::PDCRA |
Power Port A pull-down control register, Address offset: 0x54
| __IO uint32_t PWR_TypeDef::PDCRB |
Power Port B pull-down control register, Address offset: 0x5C
| __IO uint32_t PWR_TypeDef::PDCRC |
Power Port C pull-down control register, Address offset: 0x64
| __IO uint32_t PWR_TypeDef::PDCRD |
Power Port D pull-down control register, Address offset: 0x6C
| __IO uint32_t PWR_TypeDef::PDCRE |
Power Port E pull-down control register, Address offset: 0x74
| __IO uint32_t PWR_TypeDef::PDCRF |
Power Port F pull-down control register, Address offset: 0x7C
| __IO uint32_t PWR_TypeDef::PDCRG |
Power Port G pull-down control register, Address offset: 0x84
| __IO uint32_t PWR_TypeDef::PDCRH |
Power Port H pull-down control register, Address offset: 0x8C
| __IO uint32_t PWR_TypeDef::PDCRI |
Power Port I pull-down control register, Address offset: 0x94
| __IO uint32_t PWR_TypeDef::PDCRJ |
Power Port J pull-down control register, Address offset: 0x9C
| __IO uint32_t FLASH_TypeDef::PDKEY1R |
FLASH Bank 1 power-down key register, Address offset: 0x18
| __IO uint32_t FLASH_TypeDef::PDKEY2R |
FLASH Bank 2 power-down key register, Address offset: 0x1C
| __IO uint32_t SAI_TypeDef::PDMCR |
SAI PDM control register, Address offset: 0x44
| __IO uint32_t SAI_TypeDef::PDMDLY |
SAI PDM delay register, Address offset: 0x48
| __IO uint32_t I2C_TypeDef::PECR |
I2C PEC register, Address offset: 0x20
| __IO uint32_t LTDC_Layer_TypeDef::PFCR |
LTDC Layerx Pixel Format Configuration Register Address offset: 0x94
| __IO uint32_t CRC_TypeDef::PIDR |
CRC IP type identification register, Address offset: 0x3F8
| __IO uint32_t XSPI_TypeDef::PIR |
XSPI Polling Interval register, Address offset: 0x090
| __IO uint32_t RCC_TypeDef::PLL1CFGR |
PLL1 Configuration Register Address offset: 0x28
| __IO uint32_t RCC_TypeDef::PLL1DIVR |
PLL1 Dividers Configuration Register Address offset: 0x34
| __IO uint32_t RCC_TypeDef::PLL1FRACR |
PLL1 Fractional Divider Configuration Register Address offset: 0x38
| __IO uint32_t RCC_TypeDef::PLL2CFGR |
PLL2 Configuration Register Address offset: 0x2C
| __IO uint32_t RCC_TypeDef::PLL2DIVR |
PLL2 Dividers Configuration Register Address offset: 0x3C
| __IO uint32_t RCC_TypeDef::PLL2FRACR |
PLL2 Fractional Divider Configuration Register Address offset: 0x40
| __IO uint32_t RCC_TypeDef::PLL3CFGR |
PLL3 Configuration Register Address offset: 0x30
| __IO uint32_t RCC_TypeDef::PLL3DIVR |
PLL3 Dividers Configuration Register Address offset: 0x44
| __IO uint32_t RCC_TypeDef::PLL3FRACR |
PLL3 Fractional Divider Configuration Register Address offset: 0x48
| __IO uint32_t FMC_Bank3_TypeDef::PMEM |
NAND Flash Common memory space timing register, Address offset: 0x88
| __IO uint32_t CRC_TypeDef::POL |
CRC polynomial register, Address offset: 0x14
| __IO uint32_t SDMMC_TypeDef::POWER |
SDMMC power control register, Address offset: 0x00
| __IO uint32_t IWDG_TypeDef::PR |
IWDG Prescaler register, Address offset: 0x04
| __IO uint32_t RTC_TypeDef::PRER |
RTC prescaler register, Address offset: 0x10
| __IO uint32_t USART_TypeDef::PRESC |
USART Prescaler register, Address offset: 0x2C
| __IO uint32_t FLASH_TypeDef::PRIVBB1R1 |
FLASH privilege block-based bank 1 register 1, Address offset: 0xD0
| __IO uint32_t FLASH_TypeDef::PRIVBB1R2 |
FLASH privilege block-based bank 1 register 2, Address offset: 0xD4
| __IO uint32_t FLASH_TypeDef::PRIVBB1R3 |
FLASH privilege block-based bank 1 register 3, Address offset: 0xD8
| __IO uint32_t FLASH_TypeDef::PRIVBB1R4 |
FLASH privilege block-based bank 1 register 4, Address offset: 0xDC
| __IO uint32_t FLASH_TypeDef::PRIVBB1R5 |
FLASH privilege block-based bank 1 register 5, Address offset: 0xE0
| __IO uint32_t FLASH_TypeDef::PRIVBB1R6 |
FLASH privilege block-based bank 1 register 6, Address offset: 0xE4
| __IO uint32_t FLASH_TypeDef::PRIVBB1R7 |
FLASH privilege block-based bank 1 register 7, Address offset: 0xE8
| __IO uint32_t FLASH_TypeDef::PRIVBB1R8 |
FLASH privilege block-based bank 1 register 8, Address offset: 0xEC
| __IO uint32_t FLASH_TypeDef::PRIVBB2R1 |
FLASH privilege block-based bank 2 register 1, Address offset: 0xF0
| __IO uint32_t FLASH_TypeDef::PRIVBB2R2 |
FLASH privilege block-based bank 2 register 2, Address offset: 0xF4
| __IO uint32_t FLASH_TypeDef::PRIVBB2R3 |
FLASH privilege block-based bank 2 register 3, Address offset: 0xF8
| __IO uint32_t FLASH_TypeDef::PRIVBB2R4 |
FLASH privilege block-based bank 2 register 4, Address offset: 0xFC
| __IO uint32_t FLASH_TypeDef::PRIVBB2R5 |
FLASH privilege block-based bank 2 register 5, Address offset: 0x100
| __IO uint32_t FLASH_TypeDef::PRIVBB2R6 |
FLASH privilege block-based bank 2 register 6, Address offset: 0x104
| __IO uint32_t FLASH_TypeDef::PRIVBB2R7 |
FLASH privilege block-based bank 2 register 7, Address offset: 0x108
| __IO uint32_t FLASH_TypeDef::PRIVBB2R8 |
FLASH privilege block-based bank 2 register 8, Address offset: 0x10C
| __IO uint32_t DMA_TypeDef::PRIVCFGR |
DMA privileged configuration register, Address offset: 0x04
| __IO uint32_t FLASH_TypeDef::PRIVCFGR |
FLASH privilege configuration register, Address offset: 0xC4
| __IO uint32_t GTZC_MPCBB_TypeDef::PRIVCFGR[52] |
MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC
| __IO uint32_t OTFDEC_TypeDef::PRIVCFGR |
OTFDEC Privileged access control Configuration register, Address offset: 0x010
| __IO uint32_t PWR_TypeDef::PRIVCFGR |
Power privilege control register, Address offset: 0x34
| __IO uint32_t RCC_TypeDef::PRIVCFGR |
RCC privilege configuration register Address offset: 0x114
| __IO uint32_t RTC_TypeDef::PRIVCFGR |
RTC privilege mode control register, Address offset: 0x1C
| __IO uint32_t TAMP_TypeDef::PRIVCFGR |
TAMP privilege mode control register, Address offset: 0x24
| __IO uint32_t EXTI_TypeDef::PRIVCFGR1 |
EXTI Privilege Configuration Register 1, Address offset: 0x18
| __IO uint32_t GTZC_TZSC_TypeDef::PRIVCFGR1 |
TZSC privilege configuration register 1, Address offset: 0x20
| __IO uint32_t GTZC_TZSC_TypeDef::PRIVCFGR2 |
TZSC privilege configuration register 2, Address offset: 0x24
| __IO uint32_t GTZC_TZSC_TypeDef::PRIVCFGR3 |
TZSC privilege configuration register 3, Address offset: 0x28
| __IO uint32_t TIM_TypeDef::PSC |
TIM prescaler, Address offset: 0x28
| __IO uint32_t XSPI_TypeDef::PSMAR |
XSPI Polling Status Match register, Address offset: 0x088
| __IO uint32_t XSPI_TypeDef::PSMKR |
XSPI Polling Status Mask register, Address offset: 0x080
| __IO uint32_t DSI_TypeDef::PSR |
DSI Host PHY Status Register, Address offset: 0xB0
| __IO uint32_t FDCAN_GlobalTypeDef::PSR |
FDCAN Protocol Status register, Address offset: 0x044
| __IO uint32_t DSI_TypeDef::PTTCR |
DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC
| __IO uint32_t DSI_TypeDef::PUCR |
DSI Host PHY ULPS Control Register, Address offset: 0xA8
| __IO uint32_t PWR_TypeDef::PUCRA |
Power Port A pull-up control register, Address offset: 0x50
| __IO uint32_t PWR_TypeDef::PUCRB |
Power Port B pull-up control register, Address offset: 0x58
| __IO uint32_t PWR_TypeDef::PUCRC |
Power Port C pull-up control register, Address offset: 0x60
| __IO uint32_t PWR_TypeDef::PUCRD |
Power Port D pull-up control register, Address offset: 0x68
| __IO uint32_t PWR_TypeDef::PUCRE |
Power Port E pull-up control register, Address offset: 0x70
| __IO uint32_t PWR_TypeDef::PUCRF |
Power Port F pull-up control register, Address offset: 0x78
| __IO uint32_t PWR_TypeDef::PUCRG |
Power Port G pull-up control register, Address offset: 0x80
| __IO uint32_t PWR_TypeDef::PUCRH |
Power Port H pull-up control register, Address offset: 0x88
| __IO uint32_t PWR_TypeDef::PUCRI |
Power Port I pull-up control register, Address offset: 0x90
| __IO uint32_t PWR_TypeDef::PUCRJ |
Power Port J pull-up control register, Address offset: 0x98
| __IO uint32_t GPIO_TypeDef::PUPDR |
GPIO port pull-up/pull-down register, Address offset: 0x0C
| __IO uint32_t ADC_TypeDef::PWRR |
ADC power register, Address offset: 0x44
| __IO uint32_t JPEG_TypeDef::QMEM0[16] |
JPEG quantization tables 0, Address offset: 50h-8Ch
| __IO uint32_t JPEG_TypeDef::QMEM1[16] |
JPEG quantization tables 1, Address offset: 90h-CCh
| __IO uint32_t JPEG_TypeDef::QMEM2[16] |
JPEG quantization tables 2, Address offset: D0h-10Ch
| __IO uint32_t JPEG_TypeDef::QMEM3[16] |
JPEG quantization tables 3, Address offset: 110h-14Ch
| __IO uint32_t PKA_TypeDef::RAM[1334] |
PKA RAM Address offset: 0x400 -> 0x18D4
| __IO uint32_t DMA_TypeDef::RCFGLOCKR |
DMA lock configuration register, Address offset: 0x08
| __IO uint32_t TIM_TypeDef::RCR |
TIM repetition counter register, Address offset: 0x30
| __IO uint32_t LPTIM_TypeDef::RCR |
LPTIM Repetition register, Address offset: 0x28
| __IO uint32_t FMAC_TypeDef::RDATA |
FMAC Read Data register, Address offset: 0x1C
| __IO uint32_t CORDIC_TypeDef::RDATA |
CORDIC result register, Address offset: 0x08
| __IO uint32_t USART_TypeDef::RDR |
USART Receive Data register, Address offset: 0x24
| __IO uint32_t OTFDEC_Region_TypeDef::REG_CONFIGR |
OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_END_ADDR |
OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_KEYR0 |
OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_KEYR1 |
OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_KEYR2 |
OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_KEYR3 |
OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_NONCER0 |
OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_NONCER1 |
OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4)
| __IO uint32_t OTFDEC_Region_TypeDef::REG_START_ADDR |
OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4)
| uint32_t DMA2D_TypeDef::RESERVED[236] |
Reserved, 0x50-0x3FC
| uint32_t XSPI_TypeDef::RESERVED |
Reserved, Address offset: 0x004
| uint32_t RAMCFG_TypeDef::RESERVED |
Reserved, Address offset: 0x20
| uint32_t SAI_TypeDef::RESERVED[16] |
Reserved, Address offset: 0x04 to 0x40
| uint32_t PKA_TypeDef::Reserved[253] |
Reserved memory area Address offset: 0x0C -> 0x03FC
| uint32_t USB_OTG_HostChannelTypeDef::Reserved[2] |
Reserved, Address offset: 518h
| uint32_t HASH_TypeDef::RESERVED[52] |
Reserved, 0x28-0xF4
| uint32_t RCC_TypeDef::RESERVED[6] |
Reserved Address offset: 0xF8
| uint32_t ADC_Common_TypeDef::RESERVED |
Reserved, Address offset: 0x304
| uint32_t TIM_TypeDef::RESERVED0[220] |
Reserved, Address offset: 0x6C
| uint32_t LTDC_TypeDef::RESERVED0[2] |
Reserved, 0x00-0x04
| uint32_t LTDC_Layer_TypeDef::RESERVED0[2] |
Reserved
| __IO uint32_t LPTIM_TypeDef::RESERVED0 |
Reserved, Address offset: 0x20
| uint32_t RCC_TypeDef::RESERVED0 |
Reserved Address offset: 0x04
| uint32_t TAMP_TypeDef::RESERVED0 |
Reserved, Address offset: 0x28
| uint32_t SDMMC_TypeDef::RESERVED0[3] |
Reserved, 0x44 - 0x4C - 0x4C
| uint32_t DSI_TypeDef::RESERVED0[4] |
Reserved, 0x1C - 0x2B
| uint32_t RTC_TypeDef::RESERVED0 |
Reserved, Address offset: 0x3C
| uint32_t FMC_Bank3_TypeDef::RESERVED0 |
Reserved, 0x90
| __IO uint32_t USB_OTG_INEndpointTypeDef::Reserved04 |
Reserved, Address offset: 900h + (ep_num * 20h) + 04h
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::Reserved04 |
Reserved, Address offset: B00h + (ep_num * 20h) + 04h
| uint32_t USB_OTG_DeviceTypeDef::Reserved0C |
Reserved, Address offset: 80Ch
| __IO uint32_t USB_OTG_INEndpointTypeDef::Reserved0C |
Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::Reserved0C |
Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch
| uint32_t AES_TypeDef::RESERVED1[168] |
Reserved, Address offset: 0x60 – 0x2FC
| uint32_t DSI_TypeDef::RESERVED1 |
Reserved, 0x90
| uint32_t EXTI_TypeDef::RESERVED1[17] |
Reserved 1, 0x1C – 0x5C
| uint32_t DBGMCU_TypeDef::RESERVED1[2] |
Reserved, 0x18 - 0x1C
| uint32_t DMA_Channel_TypeDef::RESERVED1[2] |
Reserved 1, Address offset: 0x54 – 0x58
| uint32_t FLASH_TypeDef::RESERVED1 |
Reserved1, Address offset: 0x04
| uint32_t FDCAN_Config_TypeDef::RESERVED1[128] |
Reserved, 0x100 + 0x004 - 0x100 + 0x200
| uint32_t GFXTIM_TypeDef::RESERVED1[2] |
Reserved, Address offset: 0x18-0x1C
| uint32_t LTDC_TypeDef::RESERVED1[2] |
Reserved, 0x1C-0x20
| uint32_t ICACHE_TypeDef::RESERVED1[2] |
Reserved, Address offset: 0x018-0x01C
| uint32_t DCACHE_TypeDef::RESERVED1[2] |
Reserved, Address offset: 0x18-0x1C
| uint32_t XSPI_TypeDef::RESERVED1[2] |
Reserved, Address offset: 0x018-0x01C
| uint32_t GFXMMU_TypeDef::RESERVED1[3] |
Reserved1, Address offset: 0x14 to 0x1C
| uint32_t GTZC_TZSC_TypeDef::RESERVED1[3] |
Reserved1, Address offset: 0x04-0x0C
| uint32_t GTZC_MPCBB_TypeDef::RESERVED1[3] |
Reserved1, Address offset: 0x04-0x0C
| uint32_t LTDC_Layer_TypeDef::RESERVED1[3] |
Reserved
| uint32_t OTFDEC_TypeDef::RESERVED1[3] |
Reserved, Address offset: 0x004-0x00C
| __IO uint32_t PSSI_TypeDef::RESERVED1[4] |
Reserved, 0x018 - 0x024
| __IO uint32_t LPTIM_TypeDef::RESERVED1 |
Reserved, Address offset: 0x30
| uint32_t TAMP_TypeDef::RESERVED1[4] |
Reserved, Address offset: 0x43 – 0x50
| uint32_t MDF_TypeDef::RESERVED1[6] |
Reserved, 0x08-0x1C
| uint32_t MDF_Filter_TypeDef::RESERVED1[9] |
Reserved, 0xC8-0xE8
| uint32_t RCC_TypeDef::RESERVED1 |
Reserved Address offset: 0x18
| uint32_t SYSCFG_TypeDef::RESERVED1 |
RESERVED1, Address offset: 0x28
| uint32_t SDMMC_TypeDef::RESERVED1[2] |
Reserved, 0x60
| uint32_t FDCAN_GlobalTypeDef::RESERVED1 |
Reserved, 0x008
| uint32_t ADC_TypeDef::RESERVED1 |
Reserved, 0x048
| uint32_t SPI_TypeDef::RESERVED1[3] |
Reserved, 0x24-0x2C
| uint32_t TSC_TypeDef::RESERVED1 |
Reserved, Address offset: 0x14
| uint32_t DSI_TypeDef::RESERVED10[165] |
Reserved, 0x16C - 0x3FF
| uint32_t XSPI_TypeDef::RESERVED10 |
Reserved, Address offset: 0x10C
| uint32_t RCC_TypeDef::RESERVED10 |
Reserved, Address offset: 0xDC
| uint32_t DSI_TypeDef::RESERVED11 |
Reserved, 0x414
| uint32_t XSPI_TypeDef::RESERVED11[3] |
Reserved, Address offset: 0x114-0x11C
| uint32_t RCC_TypeDef::RESERVED11 |
Reserved, Address offset: 0xEC
| uint32_t XSPI_TypeDef::RESERVED12[3] |
Reserved, Address offset: 0x124-0x12C
| uint32_t DSI_TypeDef::RESERVED12[5] |
Reserved, 0x41C - 0x42F
| uint32_t DSI_TypeDef::RESERVED13[244] |
Reserved, 0x43C - 0x804
| uint32_t XSPI_TypeDef::RESERVED13[3] |
Reserved, Address offset: 0x134-0x13C
| uint32_t DSI_TypeDef::RESERVED14[254] |
Reserved, 0x80C - 0xC00
| uint32_t XSPI_TypeDef::RESERVED14 |
Reserved, Address offset: 0x144
| uint32_t DSI_TypeDef::RESERVED15[11] |
Reserved, 0xC08 - 0xC30
| uint32_t XSPI_TypeDef::RESERVED15 |
Reserved, Address offset: 0x14C
| uint32_t XSPI_TypeDef::RESERVED16[3] |
Reserved, Address offset: 0x154-0x15C
| uint32_t DSI_TypeDef::RESERVED16[9] |
Reserved, 0xC38 - 0xC58
| uint32_t DSI_TypeDef::RESERVED17[3] |
Reserved, 0xC64-0xC6C
| uint32_t XSPI_TypeDef::RESERVED17[7] |
Reserved, Address offset: 0x164-0x17C
| uint32_t DSI_TypeDef::RESERVED18[11] |
Reserved, 0xC74 - 0xC9C
| uint32_t XSPI_TypeDef::RESERVED18 |
Reserved, Address offset: 0x184
| __IO uint32_t USB_OTG_INEndpointTypeDef::Reserved18 |
Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch
| __IO uint32_t USB_OTG_OUTEndpointTypeDef::Reserved18[2] |
Reserved, Address offset: B00h + (ep_num * 20h) + 18h
| uint32_t DSI_TypeDef::RESERVED19[20] |
Reserved, 0xCA4 - 0xD04
| uint32_t XSPI_TypeDef::RESERVED19 |
Reserved, Address offset: 0x18C
| uint32_t CRC_TypeDef::RESERVED2 |
Reserved, 0x0C
| uint32_t DBGMCU_TypeDef::RESERVED2 |
Reserved, 0x24
| uint32_t DMA_Channel_TypeDef::RESERVED2[10] |
Reserved 2, Address offset: 0x68 – 0x8C
| __IO uint32_t FLASH_TypeDef::RESERVED2 |
Reserved2, Address offset: 0x14
| uint32_t GFXMMU_TypeDef::RESERVED2[1008] |
Reserved2, Address offset: 0x30 to 0xFEC
| uint32_t GTZC_TZSC_TypeDef::RESERVED2 |
Reserved2, Address offset: 0x1C
| uint32_t RCC_TypeDef::RESERVED2 |
Reserved Address offset: 0x4C
| uint32_t SYSCFG_TypeDef::RESERVED2[17] |
RESERVED2, Address offset: 0x30 - 0x70
| uint32_t OTFDEC_TypeDef::RESERVED2[187] |
Reserved, Address offset: 0x014-0x2FC
| uint32_t LTDC_TypeDef::RESERVED2[1] |
Reserved, 0x28
| uint32_t DSI_TypeDef::RESERVED2[2] |
Reserved, 0xB4 - 0xBB
| uint32_t EXTI_TypeDef::RESERVED2[3] |
Reserved 2, 0x74 – 0x7C
| uint32_t GFXTIM_TypeDef::RESERVED2[3] |
Reserved, Address offset: 0x24-0x2C
| uint32_t SPI_TypeDef::RESERVED2[3] |
Reserved, 0x34-0x3C
| uint32_t TAMP_TypeDef::RESERVED2[42] |
Reserved, Address offset: 0x58 – 0xFC
| uint32_t FDCAN_GlobalTypeDef::RESERVED2[4] |
Reserved, 0x030 - 0x03C
| uint32_t ADC_TypeDef::RESERVED2[4] |
Reserved, 0x050 - 0x05C
| uint32_t GTZC_MPCBB_TypeDef::RESERVED2[58] |
Reserved2, Address offset: 0x18-0xFC
| uint32_t FDCAN_Config_TypeDef::RESERVED2[58] |
Reserved, 0x100 + 0x208 - 0x100 + 0x2EC
| uint32_t SDMMC_TypeDef::RESERVED2[5] |
Reserved, 0x6C-0x7C
| uint32_t XSPI_TypeDef::RESERVED2[6] |
Reserved, Address offset: 0x028-0x03C
| uint32_t TSC_TypeDef::RESERVED2 |
Reserved, Address offset: 0x1C
| uint32_t DSI_TypeDef::RESERVED20[3] |
Reserved, 0xCF8 - 0xD04
| uint32_t XSPI_TypeDef::RESERVED20[3] |
Reserved, Address offset: 0x194-0x19C
| uint32_t USB_OTG_DeviceTypeDef::Reserved20 |
Reserved, Address offset: 820h
| uint32_t DSI_TypeDef::RESERVED21[11] |
Reserved, 0xD0C - 0xD34
| uint32_t XSPI_TypeDef::RESERVED21[23] |
Reserved, Address offset: 0x1A4-0x1FC
| uint32_t XSPI_TypeDef::RESERVED22[3] |
Reserved, Address offset: 0x204-0x20C
| uint32_t XSPI_TypeDef::RESERVED23 |
Reserved, Address offset: 0x214
| uint32_t XSPI_TypeDef::RESERVED24 |
Reserved, Address offset: 0x21C
| uint32_t XSPI_TypeDef::RESERVED25 |
Reserved, Address offset: 0x224
| uint32_t GTZC_MPCBB_TypeDef::RESERVED3[12] |
Reserved3, Address offset: 0x1D0-0x1FC
| uint32_t LTDC_TypeDef::RESERVED3[1] |
Reserved, 0x30
| uint32_t CRC_TypeDef::RESERVED3[246] |
Reserved,
| uint32_t FLASH_TypeDef::RESERVED3[2] |
Reserved3, Address offset: 0x38-0x3C
| uint32_t GFXTIM_TypeDef::RESERVED3[2] |
Reserved, Address offset: 0x48-0x4C
| uint32_t PWR_TypeDef::RESERVED3[2] |
Reserved3, Address offset: 0x0A0-0x0A4
| uint32_t DSI_TypeDef::RESERVED3[3] |
Reserved, 0xD0 - 0xD7
| uint32_t RCC_TypeDef::RESERVED3 |
Reserved Address offset: 0x5C
| uint32_t SYSCFG_TypeDef::RESERVED3 |
RESERVED3, Address offset: 0x78
| uint32_t FDCAN_GlobalTypeDef::RESERVED3 |
Reserved, 0x04C
| uint32_t ADC_TypeDef::RESERVED3[3] |
Reserved, 0x074 - 0x07C
| uint32_t GTZC_TZSC_TypeDef::RESERVED3[5] |
Reserved3, Address offset: 0x2C-0x3C
| uint32_t DMA_Channel_TypeDef::RESERVED3[8] |
Reserved 3, Address offset: 0xAC – 0xC8
| uint32_t XSPI_TypeDef::RESERVED3 |
Reserved, Address offset: 0x044
| uint32_t TSC_TypeDef::RESERVED3 |
Reserved, Address offset: 0x24
| __IO uint32_t USB_OTG_GlobalTypeDef::Reserved30[2] |
Reserved, Address offset: 030h
| uint32_t GFXTIM_TypeDef::RESERVED4[1] |
Reserved, Address offset: 0x5C
| uint32_t GTZC_TZSC_TypeDef::RESERVED4[2] |
Reserved4, Address offset: 0x68-0x6C
| uint32_t DSI_TypeDef::RESERVED4[5] |
Reserved, 0xE0 - 0xF3
| uint32_t XSPI_TypeDef::RESERVED4 |
Reserved, Address offset: 0x04C
| uint32_t RCC_TypeDef::RESERVED4 |
Reserved Address offset: 0x70
| uint32_t RTC_TypeDef::RESERVED4[4] |
Reserved, Address offset: 0x58
| uint32_t ADC_TypeDef::RESERVED4[4] |
Reserved, 0x090 - 0x09C
| uint32_t FDCAN_GlobalTypeDef::RESERVED4[8] |
Reserved, 0x060 - 0x07C
| uint32_t TSC_TypeDef::RESERVED4 |
Reserved, Address offset: 0x2C
| uint32_t USB_OTG_DeviceTypeDef::Reserved40 |
dedicated EP mask, Address offset: 840h
| uint32_t USB_OTG_HostTypeDef::Reserved40C |
Reserved, Address offset: 40Ch
| __IO uint32_t USB_OTG_GlobalTypeDef::Reserved43[39] |
Reserved, Address offset: 058h
| uint32_t USB_OTG_DeviceTypeDef::Reserved44[15] |
Reserved, Address offset: 844-87Ch
| uint32_t XSPI_TypeDef::RESERVED5[11] |
Reserved, Address offset: 0x054-0x07C
| uint32_t DSI_TypeDef::RESERVED5[2] |
Reserved, 0xF8 - 0xFF
| uint32_t GTZC_TZSC_TypeDef::RESERVED5[2] |
Reserved5, Address offset: 0x78-0x7C
| uint32_t GFXTIM_TypeDef::RESERVED5[3] |
Reserved, Address offset: 0x64-0X6C
| uint32_t RCC_TypeDef::RESERVED5 |
Reserved Address offset: 0x84
| uint32_t FDCAN_GlobalTypeDef::RESERVED5 |
Reserved, 0x08C
| uint32_t ADC_TypeDef::RESERVED5 |
Reserved, 0x0CC
| uint32_t DSI_TypeDef::RESERVED6[2] |
Reserved, 0x104 - 0x10B
| uint32_t FLASH_TypeDef::RESERVED6[2] |
Reserved6, Address offset: 0xC8-0xCC
| uint32_t GFXTIM_TypeDef::RESERVED6[2] |
Reserved, Address offset: 0x78-0X7C
| uint32_t XSPI_TypeDef::RESERVED6 |
Reserved, Address offset: 0x084
| uint32_t RCC_TypeDef::RESERVED6 |
Reserved Address offset: 0x98
| __IO uint32_t USB_OTG_GlobalTypeDef::Reserved6 |
Reserved, Address offset: 050h
| uint32_t FDCAN_GlobalTypeDef::RESERVED6[8] |
Reserved, 0x0A0 - 0x0BC
| uint32_t DSI_TypeDef::RESERVED7 |
Reserved, 0x114
| uint32_t GFXTIM_TypeDef::RESERVED7[4] |
Reserved, Address offset: 0x90-0X9C
| uint32_t XSPI_TypeDef::RESERVED7 |
Reserved, Address offset: 0x08C
| uint32_t RCC_TypeDef::RESERVED7 |
Reserved Address offset: 0xAC
| uint32_t GFXTIM_TypeDef::RESERVED8[209] |
Reserved, Address offset: 0xAC-0X3EC
| uint32_t XSPI_TypeDef::RESERVED8[27] |
Reserved, Address offset: 0x094-0x0FC
| uint32_t DSI_TypeDef::RESERVED8[7] |
Reserved, 0x11C - 0x137
| uint32_t RCC_TypeDef::RESERVED8 |
Reserved Address offset: 0xC0
| uint32_t DSI_TypeDef::RESERVED9 |
Reserved, 0x164
| uint32_t XSPI_TypeDef::RESERVED9 |
Reserved, Address offset: 0x104
| uint32_t RCC_TypeDef::RESERVED9 |
Reserved Address offset: 0xD4
| uint32_t USB_OTG_DeviceTypeDef::Reserved9 |
Reserved, Address offset: 824h
| __I uint32_t SDMMC_TypeDef::RESP1 |
SDMMC response 1 register, Address offset: 0x14
| __I uint32_t SDMMC_TypeDef::RESP2 |
SDMMC response 2 register, Address offset: 0x18
| __I uint32_t SDMMC_TypeDef::RESP3 |
SDMMC response 3 register, Address offset: 0x1C
| __I uint32_t SDMMC_TypeDef::RESP4 |
SDMMC response 4 register, Address offset: 0x20
| __I uint32_t SDMMC_TypeDef::RESPCMD |
SDMMC command response register, Address offset: 0x10
| __IO uint32_t GFXTIM_TypeDef::RFC1R |
GFXTIM relative frame counter 1 register, Address offset: 0x80
| __IO uint32_t GFXTIM_TypeDef::RFC1RR |
GFXTIM relative frame counter 1 reload register, Address offset: 0x84
| __IO uint32_t GFXTIM_TypeDef::RFC2R |
GFXTIM relative frame counter 2 register, Address offset: 0x88
| __IO uint32_t GFXTIM_TypeDef::RFC2RR |
GFXTIM relative frame counter 2 reload register, Address offset: 0x8C
| __IO uint32_t DCACHE_TypeDef::RHMONR |
DCACHE Read hit monitor register, Address offset: 0x10
| __IO uint32_t PSSI_TypeDef::RIS |
PSSI raw interrupt status register, Address offset: 0x008
| __IO uint32_t DCMI_TypeDef::RISR |
DCMI raw interrupt status register, Address offset: 0x08
| __IO uint32_t IWDG_TypeDef::RLR |
IWDG Reload register, Address offset: 0x08
| __IO uint32_t DCACHE_TypeDef::RMMONR |
DCACHE Read miss monitor register, Address offset: 0x14
| __IO uint32_t EXTI_TypeDef::RPR1 |
EXTI Rising Pending Register 1, Address offset: 0x0C
| __IO uint32_t USART_TypeDef::RQR |
USART Request register, Address offset: 0x18
| __IO uint32_t SYSCFG_TypeDef::RSSCMDR |
SYSCFG RSS command mode register, Address offset: 0x2C
| __IO uint32_t USART_TypeDef::RTOR |
USART Receiver Time Out register, Address offset: 0x14
| __IO uint32_t EXTI_TypeDef::RTSR1 |
EXTI Rising Trigger Selection Register 1, Address offset: 0x00
| __IO uint32_t FDCAN_GlobalTypeDef::RWD |
FDCAN RAM Watchdog register, Address offset: 0x014
| __IO uint32_t UCPD_TypeDef::RX_ORDEXT1 |
UCPD Rx ordered set extension 1 register, Address offset: 0x34
| __IO uint32_t UCPD_TypeDef::RX_ORDEXT2 |
UCPD Rx ordered set extension 2 register, Address offset: 0x38
| __IO uint32_t UCPD_TypeDef::RX_ORDSET |
UCPD Rx ordered set type register, Address offset: 0x28
| __IO uint32_t UCPD_TypeDef::RX_PAYSZ |
UCPD Rx payload size register, Address offset: 0x2C
| __IO uint32_t SPI_TypeDef::RXCRC |
SPI Receiver CRC register, Address offset: 0x48
| __IO uint32_t I2C_TypeDef::RXDR |
I2C Receive data register, Address offset: 0x24
| __IO uint32_t UCPD_TypeDef::RXDR |
UCPD Rx data register, Address offset: 0x30
| __IO uint32_t SPI_TypeDef::RXDR |
SPI/I2S data register, Address offset: 0x30
| __IO uint32_t FDCAN_GlobalTypeDef::RXF0A |
FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094
| __IO uint32_t FDCAN_GlobalTypeDef::RXF0S |
FDCAN Rx FIFO 0 Status register, Address offset: 0x090
| __IO uint32_t FDCAN_GlobalTypeDef::RXF1A |
FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C
| __IO uint32_t FDCAN_GlobalTypeDef::RXF1S |
FDCAN Rx FIFO 1 Status register, Address offset: 0x098
| __IO uint32_t FDCAN_GlobalTypeDef::RXGFC |
FDCAN Global Filter Configuration register, Address offset: 0x080
| __IO uint32_t MDF_Filter_TypeDef::SADANLVR |
MDF SAD Ambient Noise level Register, Address offset: 0xC4
| __IO uint32_t MDF_Filter_TypeDef::SADCFGR |
MDF SAD configuration register, Address offset: 0xBC
| __IO uint32_t MDF_Filter_TypeDef::SADCR |
MDF SAD Control Register, Address offset: 0xB8
| __IO uint32_t MDF_Filter_TypeDef::SADSDLVR |
MDF SAD Sound level Register, Address offset: 0xC0
| __IO uint32_t MDF_Filter_TypeDef::SCDCR |
MDF short circuit detector control Register, Address offset: 0xA8
| __IO uint32_t RTC_TypeDef::SCR |
RTC status Clear register, Address offset: 0x5C
| __IO uint32_t TAMP_TypeDef::SCR |
TAMP status clear register, Address offset: 0x3C
| __IO uint32_t RAMCFG_TypeDef::SEAR |
ECC Single Error Address Register, Address offset: 0x0C
| __IO uint32_t FLASH_TypeDef::SECBB1R1 |
FLASH secure block-based bank 1 register 1, Address offset: 0x80
| __IO uint32_t FLASH_TypeDef::SECBB1R2 |
FLASH secure block-based bank 1 register 2, Address offset: 0x84
| __IO uint32_t FLASH_TypeDef::SECBB1R3 |
FLASH secure block-based bank 1 register 3, Address offset: 0x88
| __IO uint32_t FLASH_TypeDef::SECBB1R4 |
FLASH secure block-based bank 1 register 4, Address offset: 0x8C
| __IO uint32_t FLASH_TypeDef::SECBB1R5 |
FLASH secure block-based bank 1 register 5, Address offset: 0x90
| __IO uint32_t FLASH_TypeDef::SECBB1R6 |
FLASH secure block-based bank 1 register 6, Address offset: 0x94
| __IO uint32_t FLASH_TypeDef::SECBB1R7 |
FLASH secure block-based bank 1 register 7, Address offset: 0x98
| __IO uint32_t FLASH_TypeDef::SECBB1R8 |
FLASH secure block-based bank 1 register 8, Address offset: 0x9C
| __IO uint32_t FLASH_TypeDef::SECBB2R1 |
FLASH secure block-based bank 2 register 1, Address offset: 0xA0
| __IO uint32_t FLASH_TypeDef::SECBB2R2 |
FLASH secure block-based bank 2 register 2, Address offset: 0xA4
| __IO uint32_t FLASH_TypeDef::SECBB2R3 |
FLASH secure block-based bank 2 register 3, Address offset: 0xA8
| __IO uint32_t FLASH_TypeDef::SECBB2R4 |
FLASH secure block-based bank 2 register 4, Address offset: 0xAC
| __IO uint32_t FLASH_TypeDef::SECBB2R5 |
FLASH secure block-based bank 2 register 5, Address offset: 0xB0
| __IO uint32_t FLASH_TypeDef::SECBB2R6 |
FLASH secure block-based bank 2 register 6, Address offset: 0xB4
| __IO uint32_t FLASH_TypeDef::SECBB2R7 |
FLASH secure block-based bank 2 register 7, Address offset: 0xB8
| __IO uint32_t FLASH_TypeDef::SECBB2R8 |
FLASH secure block-based bank 2 register 8, Address offset: 0xBC
| __IO uint32_t FLASH_TypeDef::SECBOOTADD0R |
FLASH secure boot address 0 register, Address offset: 0x4C
| __IO uint32_t DMA_TypeDef::SECCFGR |
DMA secure configuration register, Address offset: 0x00
| __IO uint32_t GPIO_TypeDef::SECCFGR |
GPIO secure configuration register, Address offset: 0x30
| __IO uint32_t GTZC_MPCBB_TypeDef::SECCFGR[52] |
MPCBBx security configuration registers, Address offset: 0x100-0x1CC
| __IO uint32_t PWR_TypeDef::SECCFGR |
Power Security configuration register, Address offset: 0x30
| __IO uint32_t RCC_TypeDef::SECCFGR |
RCC secure configuration register Address offset: 0x110
| __IO uint32_t RTC_TypeDef::SECCFGR |
RTC secure mode control register, Address offset: 0x20
| __IO uint32_t TAMP_TypeDef::SECCFGR |
TAMP secure mode control register, Address offset: 0x20
| __IO uint32_t SYSCFG_TypeDef::SECCFGR |
SYSCFG secure configuration register, Address offset: 0x00
| __IO uint32_t EXTI_TypeDef::SECCFGR1 |
EXTI Security Configuration Register 1, Address offset: 0x14
| __IO uint32_t GTZC_TZSC_TypeDef::SECCFGR1 |
TZSC secure configuration register 1, Address offset: 0x10
| __IO uint32_t GTZC_TZSC_TypeDef::SECCFGR2 |
TZSC secure configuration register 2, Address offset: 0x14
| __IO uint32_t GTZC_TZSC_TypeDef::SECCFGR3 |
TZSC secure configuration register 3, Address offset: 0x18
| __IO uint32_t FLASH_TypeDef::SECCR |
FLASH secure control register, Address offset: 0x2C
| __IO uint32_t FLASH_TypeDef::SECHDPCR |
FLASH secure HDP control register, Address offset: 0xC0
| __IO uint32_t FLASH_TypeDef::SECKEYR |
FLASH secure key register, Address offset: 0x0C
| __IO uint32_t FLASH_TypeDef::SECSR |
FLASH secure status register, Address offset: 0x24
| __IO uint32_t FLASH_TypeDef::SECWM1R1 |
FLASH secure watermark1 register 1, Address offset: 0x50
| __IO uint32_t FLASH_TypeDef::SECWM1R2 |
FLASH secure watermark1 register 2, Address offset: 0x54
| __IO uint32_t FLASH_TypeDef::SECWM2R1 |
FLASH secure watermark2 register 1, Address offset: 0x60
| __IO uint32_t FLASH_TypeDef::SECWM2R2 |
FLASH secure watermark2 register 2, Address offset: 0x64
| __IO uint32_t DAC_TypeDef::SHHR |
DAC Sample and Hold hold time register, Address offset: 0x48
| __IO uint32_t RTC_TypeDef::SHIFTR |
RTC shift control register, Address offset: 0x2C
| __IO uint32_t DAC_TypeDef::SHRR |
DAC Sample and Hold refresh time register, Address offset: 0x4C
| __IO uint32_t DAC_TypeDef::SHSR1 |
DAC Sample and Hold sample time register 1, Address offset: 0x40
| __IO uint32_t DAC_TypeDef::SHSR2 |
DAC Sample and Hold sample time register 2, Address offset: 0x44
| __IO uint32_t CRC_TypeDef::SIDR |
CRC IP map Size ID register, Address offset: 0x3FC
| __IO uint32_t GFXMMU_TypeDef::SIDR |
GFXMMU size identification register, Address offset: 0xFFC
| __IO uint32_t GFXTIM_TypeDef::SIDR |
GFXTIM size identification register, Address offset: 0x3FC
| __IO uint32_t FDCAN_Config_TypeDef::SIDR |
FDCAN size ID register, Address offset: 0x100 + 0x2FC
| __IO uint32_t MDF_Filter_TypeDef::SITFCR |
MDF Serial Interface Control Register, Address offset: 0x80
| __IO uint32_t SAI_Block_TypeDef::SLOTR |
SAI block x slot register, Address offset: 0x10
| __IO uint32_t TIM_TypeDef::SMCR |
TIM slave mode control register, Address offset: 0x08
| __IO uint32_t DMA_TypeDef::SMISR |
DMA secure masked interrupt status register, Address offset: 0x10
| __IO uint32_t RTC_TypeDef::SMISR |
RTC secure masked interrupt status register, Address offset: 0x58
| __IO uint32_t TAMP_TypeDef::SMISR |
TAMP secure masked interrupt status register,Address offset: 0x38
| __IO uint32_t ADC_TypeDef::SMPR1 |
ADC sample time register 1, Address offset: 0x14
| __IO uint32_t ADC_TypeDef::SMPR2 |
ADC sample time register 2, Address offset: 0x18
| __IO uint32_t MDF_Filter_TypeDef::SNPSDR |
MDF Snapshot Data Register, Address offset: 0xEC
| __IO uint32_t ADC_TypeDef::SQR1 |
ADC regular sequence register 1, Address offset: 0x30
| __IO uint32_t ADC_TypeDef::SQR2 |
ADC regular sequence register 2, Address offset: 0x34
| __IO uint32_t ADC_TypeDef::SQR3 |
ADC regular sequence register 3, Address offset: 0x38
| __IO uint32_t ADC_TypeDef::SQR4 |
ADC regular sequence register 4, Address offset: 0x3C
| __IO uint32_t DAC_TypeDef::SR |
DAC status register, Address offset: 0x34
| __IO uint32_t AES_TypeDef::SR |
AES status register, Address offset: 0x04
| __IO uint32_t HASH_TypeDef::SR |
HASH status register, Address offset: 0x24
| __IO uint32_t RNG_TypeDef::SR |
RNG status register, Address offset: 0x04
| __IO uint32_t DCMI_TypeDef::SR |
DCMI status register, Address offset: 0x04
| __IO uint32_t FMAC_TypeDef::SR |
FMAC Status register, Address offset: 0x14
| __IO uint32_t GFXMMU_TypeDef::SR |
GFXMMU status register, Address offset: 0x04
| __IO uint32_t JPEG_TypeDef::SR |
JPEG Status Register (JPEG_SR), Address offset: 34h
| __IO uint32_t ICACHE_TypeDef::SR |
ICACHE status register, Address offset: 0x04
| __IO uint32_t DCACHE_TypeDef::SR |
DCACHE status register, Address offset: 0x04
| __IO uint32_t PSSI_TypeDef::SR |
PSSI status register, Address offset: 0x004
| __IO uint32_t TIM_TypeDef::SR |
TIM status register, Address offset: 0x10
| __IO uint32_t XSPI_TypeDef::SR |
XSPI Status register, Address offset: 0x020
| __IO uint32_t PWR_TypeDef::SR |
Power status register, Address offset: 0x38
| __IO uint32_t PKA_TypeDef::SR |
PKA status register, Address offset: 0x04
| __IO uint32_t RTC_TypeDef::SR |
RTC Status register, Address offset: 0x50
| __IO uint32_t TAMP_TypeDef::SR |
TAMP status register, Address offset: 0x30
| __IO uint32_t SAI_Block_TypeDef::SR |
SAI block x status register, Address offset: 0x18
| __IO uint32_t UCPD_TypeDef::SR |
UCPD status register, Address offset: 0x14
| __IO uint32_t FMC_Bank3_TypeDef::SR |
NAND Flash FIFO status and interrupt register, Address offset: 0x84
| __IO uint32_t IWDG_TypeDef::SR |
IWDG Status register, Address offset: 0x0C
| __IO uint32_t SPI_TypeDef::SR |
SPI Status register, Address offset: 0x14
| __IO uint32_t WWDG_TypeDef::SR |
WWDG Status register, Address offset: 0x08
| __IO uint32_t GTZC_TZIC_TypeDef::SR1 |
TZIC status register 1, Address offset: 0x10
| __IO uint32_t GTZC_TZIC_TypeDef::SR2 |
TZIC status register 2, Address offset: 0x14
| __IO uint32_t GTZC_TZIC_TypeDef::SR3 |
TZIC status register 3, Address offset: 0x18
| __IO uint32_t GTZC_TZIC_TypeDef::SR4 |
TZIC status register 4, Address offset: 0x1C
| __IO uint32_t LTDC_TypeDef::SRCR |
LTDC Shadow Reload Configuration Register, Address offset: 0x24
| __IO uint32_t RCC_TypeDef::SRDAMR |
SRD Autonomous Mode Register Address offset: 0xD8
| __IO uint32_t LTDC_TypeDef::SSCR |
LTDC Synchronization Size Configuration Register, Address offset: 0x08
| __IO uint32_t RTC_TypeDef::SSR |
RTC sub second register, Address offset: 0x08
| __I uint32_t SDMMC_TypeDef::STA |
SDMMC status register, Address offset: 0x34
| __IO uint32_t HASH_TypeDef::STR |
HASH start register, Address offset: 0x08
| __IO uint32_t AES_TypeDef::SUSP0R |
AES Suspend register 0, Address offset: 0x40
| __IO uint32_t AES_TypeDef::SUSP1R |
AES Suspend register 1, Address offset: 0x44
| __IO uint32_t AES_TypeDef::SUSP2R |
AES Suspend register 2, Address offset: 0x48
| __IO uint32_t AES_TypeDef::SUSP3R |
AES Suspend register 3, Address offset: 0x4C
| __IO uint32_t AES_TypeDef::SUSP4R |
AES Suspend register 4, Address offset: 0x50
| __IO uint32_t AES_TypeDef::SUSP5R |
AES Suspend register 5, Address offset: 0x54
| __IO uint32_t AES_TypeDef::SUSP6R |
AES Suspend register 6, Address offset: 0x58
| __IO uint32_t AES_TypeDef::SUSP7R |
AES Suspend register 7, Address offset: 0x5C
| __IO uint32_t PWR_TypeDef::SVMCR |
Power supply voltage monitoring control register, Address offset: 0x10
| __IO uint32_t PWR_TypeDef::SVMSR |
Power supply voltage monitoring status register, Address offset: 0x3C
| __IO uint32_t EXTI_TypeDef::SWIER1 |
EXTI Software Interrupt event Register 1, Address offset: 0x08
| __IO uint32_t DAC_TypeDef::SWTRIGR |
DAC software trigger register, Address offset: 0x04
| __IO uint32_t DSI_TypeDef::TCCR[6] |
DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F
| __IO uint32_t GFXTIM_TypeDef::TCR |
GFXTIM timers configuration register, Address offset: 0x08
| __IO uint32_t XSPI_TypeDef::TCR |
XSPI Timing Configuration register, Address offset: 0x108
| __IO uint32_t FDCAN_GlobalTypeDef::TDCR |
FDCAN Transmitter Delay Compensation register, Address offset: 0x048
| __IO uint32_t GFXTIM_TypeDef::TDR |
GFXTIM timers disable register, Address offset: 0x0C
| __IO uint32_t USART_TypeDef::TDR |
USART Transmit Data register, Address offset: 0x28
| __IO uint32_t FDCAN_GlobalTypeDef::TEST |
FDCAN Test register, Address offset: 0x010
| __IO uint32_t I2C_TypeDef::TIMEOUTR |
I2C Timeout register, Address offset: 0x14
| __IO uint32_t I2C_TypeDef::TIMINGR |
I2C Timing register, Address offset: 0x10
| __IO uint32_t TIM_TypeDef::TISEL |
TIM Input Selection register, Address offset: 0x5C
| __IO uint32_t FDCAN_GlobalTypeDef::TOCC |
FDCAN Timeout Counter Configuration register, Address offset: 0x028
| __IO uint32_t FDCAN_GlobalTypeDef::TOCV |
FDCAN Timeout Counter Value register, Address offset: 0x02C
| __IO uint32_t RTC_TypeDef::TR |
RTC time register, Address offset: 0x00
| __IO uint32_t FDCAN_GlobalTypeDef::TSCC |
FDCAN Timestamp Counter Configuration register, Address offset: 0x020
| __IO uint32_t FDCAN_GlobalTypeDef::TSCV |
FDCAN Timestamp Counter Value register, Address offset: 0x024
| __IO uint32_t RTC_TypeDef::TSDR |
RTC time stamp date register, Address offset: 0x34
| __IO uint32_t GFXTIM_TypeDef::TSR |
GFXTIM timers status register, Address offset: 0x3C
| __IO uint32_t RTC_TypeDef::TSSSR |
RTC time-stamp sub second register, Address offset: 0x38
| __IO uint32_t RTC_TypeDef::TSTR |
RTC time stamp time register, Address offset: 0x30
| __IO uint32_t LTDC_TypeDef::TWCR |
LTDC Total Width Configuration Register, Address offset: 0x14
| __IO uint32_t UCPD_TypeDef::TX_ORDSET |
UCPD Tx ordered set type register, Address offset: 0x1C
| __IO uint32_t UCPD_TypeDef::TX_PAYSZ |
UCPD Tx payload size register, Address offset: 0x20
| __IO uint32_t FDCAN_GlobalTypeDef::TXBAR |
FDCAN Tx Buffer Add Request register, Address offset: 0x0CC
| __IO uint32_t FDCAN_GlobalTypeDef::TXBC |
FDCAN Tx Buffer Configuration register, Address offset: 0x0C0
| __IO uint32_t FDCAN_GlobalTypeDef::TXBCF |
FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8
| __IO uint32_t FDCAN_GlobalTypeDef::TXBCIE |
FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0
| __IO uint32_t FDCAN_GlobalTypeDef::TXBCR |
FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0
| __IO uint32_t FDCAN_GlobalTypeDef::TXBRP |
FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8
| __IO uint32_t FDCAN_GlobalTypeDef::TXBTIE |
FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC
| __IO uint32_t FDCAN_GlobalTypeDef::TXBTO |
FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4
| __IO uint32_t SPI_TypeDef::TXCRC |
SPI Transmitter CRC register, Address offset: 0x44
| __IO uint32_t I2C_TypeDef::TXDR |
I2C Transmit data register, Address offset: 0x28
| __IO uint32_t UCPD_TypeDef::TXDR |
UCPD Tx data register, Address offset: 0x24
| __IO uint32_t SPI_TypeDef::TXDR |
SPI Transmit data register, Address offset: 0x20
| __IO uint32_t FDCAN_GlobalTypeDef::TXEFA |
FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8
| __IO uint32_t FDCAN_GlobalTypeDef::TXEFS |
FDCAN Tx Event FIFO Status register, Address offset: 0x0E4
| __IO uint32_t FDCAN_GlobalTypeDef::TXFQS |
FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4
| __IO uint32_t PWR_TypeDef::UCPDR |
Power USB Type-C and Power Delivery register, Address offset: 0x2C
| __IO uint32_t SPI_TypeDef::UDRDR |
SPI Underrun data register, Address offset: 0x4C
| __IO uint32_t DSI_TypeDef::VCCCR |
DSI Host Video Chunks Current Configuration Register, Address offset: 0x140
| __IO uint32_t DSI_TypeDef::VCCR |
DSI Host Video Chunks Configuration Register, Address offset: 0x40
| __IO uint32_t CRC_TypeDef::VERR |
CRC IP version register, Address offset: 0x3F4
| __IO uint32_t GFXMMU_TypeDef::VERR |
GFXMMU version register, Address offset: 0xFF4
| __IO uint32_t GFXTIM_TypeDef::VERR |
GFXTIM version register, Address offset: 0x3F4
| __IO uint32_t FDCAN_Config_TypeDef::VERR |
FDCAN IP version register, Address offset: 0x100 + 0x2F4
| __IO uint32_t DSI_TypeDef::VHBPCCR |
DSI Host Video HBP Current Configuration Register, Address offset: 0x14C
| __IO uint32_t DSI_TypeDef::VHBPCR |
DSI Host Video HBP Configuration Register, Address offset: 0x4C
| __IO uint32_t DSI_TypeDef::VHSACCR |
DSI Host Video HSA Current Configuration Register, Address offset: 0x148
| __IO uint32_t DSI_TypeDef::VHSACR |
DSI Host Video HSA Configuration Register, Address offset: 0x48
| __IO uint32_t DSI_TypeDef::VLCCR |
DSI Host Video Line Current Configuration Register, Address offset: 0x150
| __IO uint32_t DSI_TypeDef::VLCR |
DSI Host Video Line Configuration Register, Address offset: 0x50
| __IO uint32_t DSI_TypeDef::VMCCR |
DSI Host Video Mode Current Configuration Register, Address offset: 0x138
| __IO uint32_t DSI_TypeDef::VMCR |
DSI Host Video Mode Configuration Register, Address offset: 0x38
| __IO uint32_t DSI_TypeDef::VNPCCR |
DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144
| __IO uint32_t DSI_TypeDef::VNPCR |
DSI Host Video Null Packet Configuration Register, Address offset: 0x44
| __IO uint32_t PWR_TypeDef::VOSR |
Power voltage scaling register, Address offset: 0x0C
| __IO uint32_t DSI_TypeDef::VPCCR |
DSI Host Video Packet Current Configuration Register, Address offset: 0x13C
| __IO uint32_t DSI_TypeDef::VPCR |
DSI Host Video Packet Configuration Register, Address offset: 0x3C
| __IO uint32_t DSI_TypeDef::VR |
DSI Host Version Register, Address offset: 0x00
| __IO uint32_t DSI_TypeDef::VSCR |
DSI Host Video Shadow Control Register, Address offset: 0x100
| __IO uint32_t DSI_TypeDef::VVACCR |
DSI Host Video VA Current Configuration Register, Address offset: 0x160
| __IO uint32_t DSI_TypeDef::VVACR |
DSI Host Video VA Configuration Register, Address offset: 0x60
| __IO uint32_t DSI_TypeDef::VVBPCCR |
DSI Host Video VBP Current Configuration Register, Address offset: 0x158
| __IO uint32_t DSI_TypeDef::VVBPCR |
DSI Host Video VBP Configuration Register, Address offset: 0x58
| __IO uint32_t DSI_TypeDef::VVFPCCR |
DSI Host Video VFP Current Configuration Register, Address offset: 0x15C
| __IO uint32_t DSI_TypeDef::VVFPCR |
DSI Host Video VFP Configuration Register, Address offset: 0x5C
| __IO uint32_t DSI_TypeDef::VVSACCR |
DSI Host Video VSA Current Configuration Register, Address offset: 0x154
| __IO uint32_t DSI_TypeDef::VVSACR |
DSI Host Video VSA Configuration Register, Address offset: 0x54
| __IO uint32_t XSPI_TypeDef::WABR |
XSPI Write Alternate Bytes register, Address offset: 0x1A0
| __IO uint32_t XSPI_TypeDef::WCCR |
XSPI Write Communication Configuration register, Address offset: 0x180
| __IO uint32_t DSI_TypeDef::WCFGR |
DSI Wrapper Configuration Register, Address offset: 0x400
| __IO uint32_t DSI_TypeDef::WCR |
DSI Wrapper Control Register, Address offset: 0x404
| __IO uint32_t FMAC_TypeDef::WDATA |
FMAC Write Data register, Address offset: 0x18
| __IO uint32_t CORDIC_TypeDef::WDATA |
CORDIC argument register, Address offset: 0x04
| __IO uint32_t GFXTIM_TypeDef::WDGCR |
GFXTIM watchdog counter register, Address offset: 0xA0
| __IO uint32_t GFXTIM_TypeDef::WDGPAR |
GFXTIM watchdog pre-alarm register, Address offset: 0xA8
| __IO uint32_t GFXTIM_TypeDef::WDGRR |
GFXTIM watchdog reload register, Address offset: 0xA4
| __IO uint32_t GFXTIM_TypeDef::WDGTCR |
GFXTIM watchdog timer configuration register, Address offset: 0x20
| __IO uint32_t DCACHE_TypeDef::WHMONR |
DCACHE Write hit monitor register, Address offset: 0x20
| __IO uint32_t LTDC_Layer_TypeDef::WHPCR |
LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88
| __IO uint32_t DSI_TypeDef::WIER |
DSI Wrapper Interrupt Enable Register, Address offset: 0x408
| __IO uint32_t DSI_TypeDef::WIFCR |
DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410
| __IO uint32_t IWDG_TypeDef::WINR |
IWDG Window register, Address offset: 0x10
| __IO uint32_t XSPI_TypeDef::WIR |
XSPI Write Instruction register, Address offset: 0x190
| __IO uint32_t DSI_TypeDef::WISR |
DSI Wrapper Interrupt and Status Register, Address offset: 0x40C
| __IO uint32_t DCACHE_TypeDef::WMMONR |
DCACHE Write miss monitor register, Address offset: 0x24
| __IO uint32_t XSPI_TypeDef::WPABR |
XSPI Wrap Alternate Bytes register, Address offset: 0x160
| __IO uint32_t XSPI_TypeDef::WPCCR |
XSPI Wrap Communication Configuration register, Address offset: 0x140
| __IO uint32_t DSI_TypeDef::WPCR[1] |
DSI Wrapper PHY Configuration Register 0, Address offset: 0x418
| __IO uint32_t XSPI_TypeDef::WPIR |
XSPI Wrap Instruction register, Address offset: 0x150
| __IO uint32_t RTC_TypeDef::WPR |
RTC write protection register, Address offset: 0x24
| __IO uint32_t RAMCFG_TypeDef::WPR1 |
SRAM Write Protection Register 1, Address offset: 0x18
| __IO uint32_t RAMCFG_TypeDef::WPR2 |
SRAM Write Protection Register 2, Address offset: 0x1C
| __IO uint32_t XSPI_TypeDef::WPTCR |
XSPI Wrap Timing Configuration register, Address offset: 0x148
| uint32_t DSI_TypeDef::WPTR |
DSI Wrapper PLL tuning register, Address offset: 0x434
| __IO uint32_t FLASH_TypeDef::WRP1AR |
FLASH WRP1 area A address register, Address offset: 0x58
| __IO uint32_t FLASH_TypeDef::WRP1BR |
FLASH WRP1 area B address register, Address offset: 0x5C
| __IO uint32_t FLASH_TypeDef::WRP2AR |
FLASH WRP2 area A address register, Address offset: 0x68
| __IO uint32_t FLASH_TypeDef::WRP2BR |
FLASH WRP2 area B address register, Address offset: 0x6C
| __IO uint32_t DSI_TypeDef::WRPCR |
DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430
| __IO uint32_t XSPI_TypeDef::WTCR |
XSPI Write Timing Configuration register, Address offset: 0x188
| __IO uint32_t PWR_TypeDef::WUCR1 |
Power wakeup control register 1, Address offset: 0x14
| __IO uint32_t PWR_TypeDef::WUCR2 |
Power wakeup control register 2, Address offset: 0x18
| __IO uint32_t PWR_TypeDef::WUCR3 |
Power wakeup control register 3, Address offset: 0x1C
| __IO uint32_t PWR_TypeDef::WUSCR |
Power wakeup status clear register, Address offset: 0x48
| __IO uint32_t PWR_TypeDef::WUSR |
Power wakeup status register, Address offset: 0x44
| __IO uint32_t RTC_TypeDef::WUTR |
RTC wakeup timer register, Address offset: 0x14
| __IO uint32_t LTDC_Layer_TypeDef::WVPCR |
LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C
| __IO uint32_t FMAC_TypeDef::X1BUFCFG |
FMAC X1 Buffer Configuration register, Address offset: 0x00
| __IO uint32_t FMAC_TypeDef::X2BUFCFG |
FMAC X2 Buffer Configuration register, Address offset: 0x04
| __IO uint32_t FDCAN_GlobalTypeDef::XIDAM |
FDCAN Extended ID AND Mask register, Address offset: 0x084
| __IO uint32_t FMAC_TypeDef::YBUFCFG |
FMAC Y Buffer Configuration register, Address offset: 0x08
1.9.6