RTEMS 6.1-rc5
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stm32h7xx.h
Go to the documentation of this file.
1/*
2 * The file was modified by RTEMS contributors.
3 */
40#ifndef STM32H7xx_H
41#define STM32H7xx_H
42
43#ifdef __rtems__
44#include <bspopts.h>
45#endif /* __rtems__ */
46#ifdef __cplusplus
47 extern "C" {
48#endif /* __cplusplus */
49
57#if !defined (STM32H7)
58#define STM32H7
59#endif /* STM32H7 */
60
61
62/* Uncomment the line below according to the target STM32H7 device used in your
63 application
64 */
65
66#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
67 !defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
68 !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
69 !defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
70 /* #define STM32H742xx */
71 /* #define STM32H743xx */
72 /* #define STM32H753xx */
73 /* #define STM32H750xx */
74 /* #define STM32H747xx */
75 /* #define STM32H747xG */
76 /* #define STM32H757xx */
77 /* #define STM32H745xx */
78 /* #define STM32H745xG */
79 /* #define STM32H755xx */
80 /* #define STM32H7B0xx */
81 /* #define STM32H7A3xx */
82 /* #define STM32H7A3xxQ */
83 /* #define STM32H7B3xx */
84 /* #define STM32H7B3xxQ */
85 /* #define STM32H735xx */
86 /* #define STM32H733xx */
87 /* #define STM32H730xx */
88 /* #define STM32H730xxQ */
89 /* #define STM32H725xx */
90 /* #define STM32H723xx */
91#endif
92
93/* Tip: To avoid modifying this file each time you need to switch between these
94 devices, you can define the device in your toolchain compiler preprocessor.
95 */
96
97#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
98 #error "Dual core device, please select CORE_CM4 or CORE_CM7"
99#endif
100
101#if !defined (USE_HAL_DRIVER)
107 /*#define USE_HAL_DRIVER */
108#endif /* USE_HAL_DRIVER */
109
113#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01)
114#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A)
115#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04)
116#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00)
117#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
118 |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
119 |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
120 |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))
121
130#if defined(STM32H743xx)
131 #include "stm32h743xx.h"
132#elif defined(STM32H753xx)
133 #include "stm32h753xx.h"
134#elif defined(STM32H750xx)
135 #include "stm32h750xx.h"
136#elif defined(STM32H742xx)
137 #include "stm32h742xx.h"
138#elif defined(STM32H745xx)
139 #include "stm32h745xx.h"
140#elif defined(STM32H745xG)
141 #include "stm32h745xg.h"
142#elif defined(STM32H755xx)
143 #include "stm32h755xx.h"
144#elif defined(STM32H747xx)
145 #include "stm32h747xx.h"
146#elif defined(STM32H747xG)
147 #include "stm32h747xg.h"
148#elif defined(STM32H757xx)
149 #include "stm32h757xx.h"
150#elif defined(STM32H7B0xx)
151 #include "stm32h7b0xx.h"
152#elif defined(STM32H7B0xxQ)
153 #include "stm32h7b0xxq.h"
154#elif defined(STM32H7A3xx)
155 #include "stm32h7a3xx.h"
156#elif defined(STM32H7B3xx)
157 #include "stm32h7b3xx.h"
158#elif defined(STM32H7A3xxQ)
159 #include "stm32h7a3xxq.h"
160#elif defined(STM32H7B3xxQ)
161 #include "stm32h7b3xxq.h"
162#elif defined(STM32H735xx)
163 #include "stm32h735xx.h"
164#elif defined(STM32H733xx)
165 #include "stm32h733xx.h"
166#elif defined(STM32H730xx)
167 #include "stm32h730xx.h"
168#elif defined(STM32H730xxQ)
169 #include "stm32h730xxq.h"
170#elif defined(STM32H725xx)
171 #include "stm32h725xx.h"
172#elif defined(STM32H723xx)
173 #include "stm32h723xx.h"
174#else
175 #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
176#endif
177
185typedef enum
186{
187 RESET = 0,
188 SET = !RESET
189} FlagStatus, ITStatus;
190
191typedef enum
192{
193 DISABLE = 0,
194 ENABLE = !DISABLE
195} FunctionalState;
196#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
197
198typedef enum
199{
200 SUCCESS = 0,
201 ERROR = !SUCCESS
202} ErrorStatus;
203
212#define SET_BIT(REG, BIT) ((REG) |= (BIT))
213
214#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
215
216#define READ_BIT(REG, BIT) ((REG) & (BIT))
217
218#define CLEAR_REG(REG) ((REG) = (0x0))
219
220#define WRITE_REG(REG, VAL) ((REG) = (VAL))
221
222#define READ_REG(REG) ((REG))
223
224#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
225
226#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
227
228/* Use of CMSIS compiler intrinsics for register exclusive access */
229/* Atomic 32-bit register access macro to set one or several bits */
230#define ATOMIC_SET_BIT(REG, BIT) \
231 do { \
232 uint32_t val; \
233 do { \
234 val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
235 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
236 } while(0)
237
238/* Atomic 32-bit register access macro to clear one or several bits */
239#define ATOMIC_CLEAR_BIT(REG, BIT) \
240 do { \
241 uint32_t val; \
242 do { \
243 val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
244 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
245 } while(0)
246
247/* Atomic 32-bit register access macro to clear and set one or several bits */
248#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
249 do { \
250 uint32_t val; \
251 do { \
252 val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
253 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
254 } while(0)
255
256/* Atomic 16-bit register access macro to set one or several bits */
257#define ATOMIC_SETH_BIT(REG, BIT) \
258 do { \
259 uint16_t val; \
260 do { \
261 val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
262 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
263 } while(0)
264
265/* Atomic 16-bit register access macro to clear one or several bits */
266#define ATOMIC_CLEARH_BIT(REG, BIT) \
267 do { \
268 uint16_t val; \
269 do { \
270 val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
271 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
272 } while(0)
273
274/* Atomic 16-bit register access macro to clear and set one or several bits */
275#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
276 do { \
277 uint16_t val; \
278 do { \
279 val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
280 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
281 } while(0)
282
287#if defined (USE_HAL_DRIVER)
288 #include "stm32h7xx_hal.h"
289#endif /* USE_HAL_DRIVER */
290
291
292#ifdef __cplusplus
293}
294#endif /* __cplusplus */
295
296#endif /* STM32H7xx_H */
CMSIS STM32H723xx Device Peripheral Access Layer Header File.
CMSIS STM32H725xx Device Peripheral Access Layer Header File.
CMSIS STM32H730xx Device Peripheral Access Layer Header File.
CMSIS STM32H733xx Device Peripheral Access Layer Header File.
CMSIS STM32H735xx Device Peripheral Access Layer Header File.
CMSIS STM32H742xx Device Peripheral Access Layer Header File.
CMSIS STM32H743xx Device Peripheral Access Layer Header File.
CMSIS STM32H745xG Device Peripheral Access Layer Header File.
CMSIS STM32H745xx Device Peripheral Access Layer Header File.
CMSIS STM32H747xG Device Peripheral Access Layer Header File.
CMSIS STM32H747xx Device Peripheral Access Layer Header File.
CMSIS STM32H750xx Device Peripheral Access Layer Header File.
CMSIS STM32H753xx Device Peripheral Access Layer Header File.
CMSIS STM32H755xx Device Peripheral Access Layer Header File.
CMSIS STM32H757xx Device Peripheral Access Layer Header File.
CMSIS STM32H7A3xx Device Peripheral Access Layer Header File.
CMSIS STM32H7A3xxQ Device Peripheral Access Layer Header File.
CMSIS STM32H7B0xx Device Peripheral Access Layer Header File.
CMSIS STM32H7B3xx Device Peripheral Access Layer Header File.
CMSIS STM32H7B3xxQ Device Peripheral Access Layer Header File.
This file contains all the functions prototypes for the HAL module driver.