RTEMS 6.1-rc5
|
CMSIS STM32H742xx Device Peripheral Access Layer Header File. More...
Go to the source code of this file.
Data Structures | |
struct | ADC_TypeDef |
Analog to Digital Converter. More... | |
struct | ADC_Common_TypeDef |
struct | VREFBUF_TypeDef |
VREFBUF. More... | |
struct | FDCAN_GlobalTypeDef |
FD Controller Area Network. More... | |
struct | TTCAN_TypeDef |
TTFD Controller Area Network. More... | |
struct | FDCAN_ClockCalibrationUnit_TypeDef |
FD Controller Area Network. More... | |
struct | CEC_TypeDef |
Consumer Electronics Control. More... | |
struct | CRC_TypeDef |
CRC calculation unit. More... | |
struct | CRS_TypeDef |
Clock Recovery System. More... | |
struct | DAC_TypeDef |
Digital to Analog Converter. More... | |
struct | DFSDM_Filter_TypeDef |
DFSDM module registers. More... | |
struct | DFSDM_Channel_TypeDef |
DFSDM channel configuration registers. More... | |
struct | DBGMCU_TypeDef |
Debug MCU. More... | |
struct | DCMI_TypeDef |
DCMI. More... | |
struct | DMA_Stream_TypeDef |
DMA Controller. More... | |
struct | DMA_TypeDef |
struct | BDMA_Channel_TypeDef |
struct | BDMA_TypeDef |
struct | DMAMUX_Channel_TypeDef |
struct | DMAMUX_ChannelStatus_TypeDef |
struct | DMAMUX_RequestGen_TypeDef |
struct | DMAMUX_RequestGenStatus_TypeDef |
struct | MDMA_TypeDef |
MDMA Controller. More... | |
struct | MDMA_Channel_TypeDef |
struct | DMA2D_TypeDef |
DMA2D Controller. More... | |
struct | ETH_TypeDef |
Ethernet MAC. More... | |
struct | EXTI_TypeDef |
External Interrupt/Event Controller. More... | |
struct | EXTI_Core_TypeDef |
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only. More... | |
struct | FLASH_TypeDef |
FLASH Registers. More... | |
struct | FMC_Bank1_TypeDef |
Flexible Memory Controller. More... | |
struct | FMC_Bank1E_TypeDef |
Flexible Memory Controller Bank1E. More... | |
struct | FMC_Bank2_TypeDef |
Flexible Memory Controller Bank2. More... | |
struct | FMC_Bank3_TypeDef |
Flexible Memory Controller Bank3. More... | |
struct | FMC_Bank5_6_TypeDef |
Flexible Memory Controller Bank5 and 6. More... | |
struct | GPIO_TypeDef |
General Purpose I/O. More... | |
struct | OPAMP_TypeDef |
Operational Amplifier (OPAMP) More... | |
struct | SYSCFG_TypeDef |
System configuration controller. More... | |
struct | I2C_TypeDef |
Inter-integrated Circuit Interface. More... | |
struct | IWDG_TypeDef |
Independent WATCHDOG. More... | |
struct | PWR_TypeDef |
Power Control. More... | |
struct | RCC_TypeDef |
Reset and Clock Control. More... | |
struct | RTC_TypeDef |
Real-Time Clock. More... | |
struct | SAI_TypeDef |
Serial Audio Interface. More... | |
struct | SAI_Block_TypeDef |
struct | SPDIFRX_TypeDef |
SPDIF-RX Interface. More... | |
struct | SDMMC_TypeDef |
Secure digital input/output Interface. More... | |
struct | DLYB_TypeDef |
Delay Block DLYB. More... | |
struct | HSEM_TypeDef |
HW Semaphore HSEM. More... | |
struct | HSEM_Common_TypeDef |
struct | SPI_TypeDef |
Serial Peripheral Interface. More... | |
struct | QUADSPI_TypeDef |
QUAD Serial Peripheral Interface. More... | |
struct | TIM_TypeDef |
TIM. More... | |
struct | LPTIM_TypeDef |
LPTIMIMER. More... | |
struct | COMPOPT_TypeDef |
Comparator. More... | |
struct | COMP_TypeDef |
struct | COMP_Common_TypeDef |
struct | USART_TypeDef |
Universal Synchronous Asynchronous Receiver Transmitter. More... | |
struct | SWPMI_TypeDef |
Single Wire Protocol Master Interface SPWMI. More... | |
struct | WWDG_TypeDef |
Window WATCHDOG. More... | |
struct | RAMECC_MonitorTypeDef |
RAM_ECC_Specific_Registers. More... | |
struct | RAMECC_TypeDef |
struct | HRTIM_Master_TypeDef |
High resolution Timer (HRTIM) More... | |
struct | HRTIM_Timerx_TypeDef |
struct | HRTIM_Common_TypeDef |
struct | HRTIM_TypeDef |
struct | RNG_TypeDef |
RNG. More... | |
struct | MDIOS_TypeDef |
MDIOS. More... | |
struct | USB_OTG_GlobalTypeDef |
USB_OTG_Core_Registers. More... | |
struct | USB_OTG_DeviceTypeDef |
USB_OTG_device_Registers. More... | |
struct | USB_OTG_INEndpointTypeDef |
USB_OTG_IN_Endpoint-Specific_Register. More... | |
struct | USB_OTG_OUTEndpointTypeDef |
USB_OTG_OUT_Endpoint-Specific_Registers. More... | |
struct | USB_OTG_HostTypeDef |
USB_OTG_Host_Mode_Register_Structures. More... | |
struct | USB_OTG_HostChannelTypeDef |
USB_OTG_Host_Channel_Specific_Registers. More... | |
struct | GPV_TypeDef |
Global Programmer View. More... | |
Macros | |
#define | __CM7_REV 0x0101U |
Configuration of the Cortex-M7 Processor and Core Peripherals. | |
#define | __MPU_PRESENT 1U |
#define | __NVIC_PRIO_BITS 4U |
#define | __Vendor_SysTickConfig 0U |
#define | __FPU_PRESENT 1U |
#define | __ICACHE_PRESENT 1U |
#define | __DCACHE_PRESENT 1U |
#define | D1_ITCMRAM_BASE (0x00000000UL) |
#define | D1_ITCMICP_BASE (0x00100000UL) |
#define | D1_DTCMRAM_BASE (0x20000000UL) |
#define | D1_AXIFLASH_BASE (0x08000000UL) |
#define | D1_AXIICP_BASE (0x1FF00000UL) |
#define | D1_AXISRAM_BASE (0x24000000UL) |
#define | D2_AXISRAM_BASE (0x10000000UL) |
#define | D2_AHBSRAM_BASE (0x30000000UL) |
#define | D3_BKPSRAM_BASE (0x38800000UL) |
#define | D3_SRAM_BASE (0x38000000UL) |
#define | PERIPH_BASE (0x40000000UL) |
#define | QSPI_BASE (0x90000000UL) |
#define | FLASH_BANK1_BASE (0x08000000UL) |
#define | FLASH_BANK2_BASE (0x08100000UL) |
#define | FLASH_END (0x081FFFFFUL) |
#define | FLASH_BASE FLASH_BANK1_BASE |
#define | UID_BASE (0x1FF1E800UL) |
#define | FLASHSIZE_BASE (0x1FF1E880UL) |
#define | D2_APB1PERIPH_BASE PERIPH_BASE |
#define | D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
#define | D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
#define | D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) |
#define | D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
#define | D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) |
#define | D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) |
#define | D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) |
#define | APB1PERIPH_BASE PERIPH_BASE |
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
#define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
#define | AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) |
#define | MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) |
#define | DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) |
#define | FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) |
#define | FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) |
#define | QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) |
#define | DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) |
#define | SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) |
#define | DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) |
#define | RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) |
#define | DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) |
#define | DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) |
#define | DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) |
#define | ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) |
#define | ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) |
#define | ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) |
#define | ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) |
#define | ETH_MAC_BASE (ETH_BASE) |
#define | USB1_OTG_HS_PERIPH_BASE (0x40040000UL) |
#define | USB2_OTG_FS_PERIPH_BASE (0x40080000UL) |
#define | USB_OTG_GLOBAL_BASE (0x000UL) |
#define | USB_OTG_DEVICE_BASE (0x800UL) |
#define | USB_OTG_IN_ENDPOINT_BASE (0x900UL) |
#define | USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) |
#define | USB_OTG_EP_REG_SIZE (0x20UL) |
#define | USB_OTG_HOST_BASE (0x400UL) |
#define | USB_OTG_HOST_PORT_BASE (0x440UL) |
#define | USB_OTG_HOST_CHANNEL_BASE (0x500UL) |
#define | USB_OTG_HOST_CHANNEL_SIZE (0x20UL) |
#define | USB_OTG_PCGCCTL_BASE (0xE00UL) |
#define | USB_OTG_FIFO_BASE (0x1000UL) |
#define | USB_OTG_FIFO_SIZE (0x1000UL) |
#define | DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) |
#define | RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) |
#define | SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) |
#define | DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) |
#define | RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) |
#define | GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) |
#define | GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) |
#define | GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) |
#define | GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) |
#define | GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) |
#define | GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) |
#define | GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) |
#define | GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) |
#define | GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) |
#define | GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) |
#define | GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) |
#define | RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) |
#define | PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) |
#define | CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) |
#define | BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) |
#define | DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) |
#define | ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) |
#define | ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) |
#define | HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) |
#define | RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) |
#define | WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) |
#define | TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) |
#define | TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) |
#define | TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) |
#define | TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) |
#define | TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) |
#define | TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) |
#define | TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) |
#define | TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) |
#define | TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) |
#define | LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) |
#define | SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) |
#define | SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) |
#define | SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) |
#define | USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) |
#define | USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) |
#define | UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) |
#define | UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) |
#define | I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) |
#define | I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) |
#define | I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) |
#define | CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) |
#define | DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) |
#define | UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) |
#define | UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) |
#define | CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) |
#define | SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) |
#define | OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) |
#define | OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) |
#define | OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) |
#define | MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) |
#define | FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) |
#define | FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) |
#define | FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) |
#define | SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) |
#define | TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) |
#define | TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) |
#define | USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) |
#define | USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) |
#define | SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) |
#define | SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) |
#define | TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) |
#define | TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) |
#define | TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) |
#define | SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) |
#define | SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) |
#define | SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) |
#define | SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) |
#define | SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) |
#define | SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) |
#define | SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) |
#define | SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) |
#define | SAI3_Block_A_BASE (SAI3_BASE + 0x004UL) |
#define | SAI3_Block_B_BASE (SAI3_BASE + 0x024UL) |
#define | DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) |
#define | DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) |
#define | DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) |
#define | DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) |
#define | DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) |
#define | DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) |
#define | DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) |
#define | DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) |
#define | DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) |
#define | DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) |
#define | DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) |
#define | DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) |
#define | DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) |
#define | HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) |
#define | HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) |
#define | HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) |
#define | HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) |
#define | HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) |
#define | HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) |
#define | HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) |
#define | EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) |
#define | EXTI_D1_BASE (EXTI_BASE + 0x0080UL) |
#define | EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) |
#define | SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) |
#define | LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) |
#define | SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) |
#define | I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) |
#define | LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) |
#define | LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) |
#define | LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) |
#define | LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) |
#define | COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) |
#define | COMP1_BASE (COMP12_BASE + 0x0CUL) |
#define | COMP2_BASE (COMP12_BASE + 0x10UL) |
#define | VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) |
#define | RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) |
#define | IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) |
#define | SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) |
#define | SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) |
#define | SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) |
#define | BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) |
#define | BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) |
#define | BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) |
#define | BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) |
#define | BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) |
#define | BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) |
#define | BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) |
#define | BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) |
#define | DMAMUX2_Channel0_BASE (DMAMUX2_BASE) |
#define | DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) |
#define | DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) |
#define | DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) |
#define | DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) |
#define | DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) |
#define | DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) |
#define | DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) |
#define | DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) |
#define | DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) |
#define | DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) |
#define | DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) |
#define | DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) |
#define | DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) |
#define | DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) |
#define | DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) |
#define | DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) |
#define | DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) |
#define | DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) |
#define | DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) |
#define | DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) |
#define | DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) |
#define | DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) |
#define | DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) |
#define | DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) |
#define | DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) |
#define | DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) |
#define | DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) |
#define | DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) |
#define | DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) |
#define | DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) |
#define | DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) |
#define | DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) |
#define | DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) |
#define | DMAMUX1_Channel0_BASE (DMAMUX1_BASE) |
#define | DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) |
#define | DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) |
#define | DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) |
#define | DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) |
#define | DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) |
#define | DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) |
#define | DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) |
#define | DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) |
#define | DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) |
#define | DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) |
#define | DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) |
#define | DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) |
#define | DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) |
#define | DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) |
#define | DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) |
#define | DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) |
#define | DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) |
#define | DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) |
#define | DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) |
#define | DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) |
#define | DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) |
#define | DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) |
#define | DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) |
#define | DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) |
#define | DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) |
#define | FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) |
#define | FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) |
#define | FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) |
#define | FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) |
#define | FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) |
#define | DBGMCU_BASE (0x5C001000UL) |
#define | MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) |
#define | MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) |
#define | MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) |
#define | MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) |
#define | MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) |
#define | MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) |
#define | MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) |
#define | MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) |
#define | MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) |
#define | MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) |
#define | MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) |
#define | MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) |
#define | MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) |
#define | MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) |
#define | MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) |
#define | MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) |
#define | RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) |
#define | RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) |
#define | RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) |
#define | RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) |
#define | RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) |
#define | RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) |
#define | RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) |
#define | RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) |
#define | RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) |
#define | RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) |
#define | RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) |
#define | RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) |
#define | GPV_BASE (PERIPH_BASE + 0x11000000UL) |
#define | TIM2 ((TIM_TypeDef *) TIM2_BASE) |
#define | TIM3 ((TIM_TypeDef *) TIM3_BASE) |
#define | TIM4 ((TIM_TypeDef *) TIM4_BASE) |
#define | TIM5 ((TIM_TypeDef *) TIM5_BASE) |
#define | TIM6 ((TIM_TypeDef *) TIM6_BASE) |
#define | TIM7 ((TIM_TypeDef *) TIM7_BASE) |
#define | TIM13 ((TIM_TypeDef *) TIM13_BASE) |
#define | TIM14 ((TIM_TypeDef *) TIM14_BASE) |
#define | VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) |
#define | IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) |
#define | SPI2 ((SPI_TypeDef *) SPI2_BASE) |
#define | SPI3 ((SPI_TypeDef *) SPI3_BASE) |
#define | SPI4 ((SPI_TypeDef *) SPI4_BASE) |
#define | SPI5 ((SPI_TypeDef *) SPI5_BASE) |
#define | SPI6 ((SPI_TypeDef *) SPI6_BASE) |
#define | USART2 ((USART_TypeDef *) USART2_BASE) |
#define | USART3 ((USART_TypeDef *) USART3_BASE) |
#define | USART6 ((USART_TypeDef *) USART6_BASE) |
#define | UART7 ((USART_TypeDef *) UART7_BASE) |
#define | UART8 ((USART_TypeDef *) UART8_BASE) |
#define | CRS ((CRS_TypeDef *) CRS_BASE) |
#define | UART4 ((USART_TypeDef *) UART4_BASE) |
#define | UART5 ((USART_TypeDef *) UART5_BASE) |
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define | I2C2 ((I2C_TypeDef *) I2C2_BASE) |
#define | I2C3 ((I2C_TypeDef *) I2C3_BASE) |
#define | I2C4 ((I2C_TypeDef *) I2C4_BASE) |
#define | FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) |
#define | FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) |
#define | FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) |
#define | CEC ((CEC_TypeDef *) CEC_BASE) |
#define | LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
#define | PWR ((PWR_TypeDef *) PWR_BASE) |
#define | DAC1 ((DAC_TypeDef *) DAC1_BASE) |
#define | LPUART1 ((USART_TypeDef *) LPUART1_BASE) |
#define | SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) |
#define | LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) |
#define | LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) |
#define | LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) |
#define | LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) |
#define | SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
#define | COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) |
#define | COMP1 ((COMP_TypeDef *) COMP1_BASE) |
#define | COMP2 ((COMP_TypeDef *) COMP2_BASE) |
#define | COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) |
#define | OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
#define | OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) |
#define | OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) |
#define | EXTI ((EXTI_TypeDef *) EXTI_BASE) |
#define | EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) |
#define | EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) |
#define | TIM1 ((TIM_TypeDef *) TIM1_BASE) |
#define | SPI1 ((SPI_TypeDef *) SPI1_BASE) |
#define | TIM8 ((TIM_TypeDef *) TIM8_BASE) |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | TIM12 ((TIM_TypeDef *) TIM12_BASE) |
#define | TIM15 ((TIM_TypeDef *) TIM15_BASE) |
#define | TIM16 ((TIM_TypeDef *) TIM16_BASE) |
#define | TIM17 ((TIM_TypeDef *) TIM17_BASE) |
#define | HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) |
#define | HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) |
#define | HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) |
#define | HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) |
#define | HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) |
#define | HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) |
#define | HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) |
#define | SAI1 ((SAI_TypeDef *) SAI1_BASE) |
#define | SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
#define | SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
#define | SAI2 ((SAI_TypeDef *) SAI2_BASE) |
#define | SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) |
#define | SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) |
#define | SAI3 ((SAI_TypeDef *) SAI3_BASE) |
#define | SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) |
#define | SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) |
#define | SAI4 ((SAI_TypeDef *) SAI4_BASE) |
#define | SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) |
#define | SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) |
#define | SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) |
#define | DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) |
#define | DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) |
#define | DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) |
#define | DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) |
#define | DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) |
#define | DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) |
#define | DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) |
#define | DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) |
#define | DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) |
#define | DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) |
#define | DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) |
#define | DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) |
#define | DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) |
#define | DCMI ((DCMI_TypeDef *) DCMI_BASE) |
#define | RCC ((RCC_TypeDef *) RCC_BASE) |
#define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
#define | CRC ((CRC_TypeDef *) CRC_BASE) |
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
#define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
#define | GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
#define | GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
#define | GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) |
#define | GPIOK ((GPIO_TypeDef *) GPIOK_BASE) |
#define | ADC1 ((ADC_TypeDef *) ADC1_BASE) |
#define | ADC2 ((ADC_TypeDef *) ADC2_BASE) |
#define | ADC3 ((ADC_TypeDef *) ADC3_BASE) |
#define | ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) |
#define | ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) |
#define | RNG ((RNG_TypeDef *) RNG_BASE) |
#define | SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) |
#define | DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) |
#define | BDMA ((BDMA_TypeDef *) BDMA_BASE) |
#define | BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) |
#define | BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) |
#define | BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) |
#define | BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) |
#define | BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) |
#define | BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) |
#define | BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) |
#define | BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) |
#define | RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) |
#define | RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) |
#define | RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) |
#define | RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) |
#define | RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) |
#define | RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) |
#define | RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) |
#define | RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) |
#define | RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) |
#define | RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) |
#define | RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) |
#define | RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) |
#define | RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) |
#define | RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) |
#define | RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) |
#define | DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) |
#define | DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) |
#define | DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) |
#define | DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) |
#define | DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) |
#define | DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) |
#define | DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) |
#define | DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) |
#define | DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) |
#define | DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) |
#define | DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) |
#define | DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) |
#define | DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) |
#define | DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) |
#define | DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) |
#define | DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) |
#define | DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) |
#define | DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) |
#define | DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) |
#define | DMA2 ((DMA_TypeDef *) DMA2_BASE) |
#define | DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
#define | DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
#define | DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
#define | DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
#define | DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
#define | DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
#define | DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
#define | DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
#define | DMA1 ((DMA_TypeDef *) DMA1_BASE) |
#define | DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
#define | DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
#define | DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
#define | DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
#define | DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
#define | DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
#define | DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
#define | DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
#define | DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) |
#define | DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) |
#define | DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) |
#define | DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) |
#define | DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) |
#define | DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) |
#define | DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) |
#define | DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) |
#define | DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) |
#define | DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) |
#define | DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) |
#define | DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) |
#define | DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) |
#define | DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) |
#define | DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) |
#define | DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) |
#define | DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) |
#define | DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) |
#define | DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) |
#define | DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) |
#define | DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) |
#define | DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) |
#define | DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) |
#define | DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) |
#define | DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) |
#define | DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) |
#define | DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) |
#define | FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
#define | FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
#define | FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) |
#define | FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
#define | FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) |
#define | QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) |
#define | DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) |
#define | SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) |
#define | DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) |
#define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
#define | HSEM ((HSEM_TypeDef *) HSEM_BASE) |
#define | HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) |
#define | MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) |
#define | ETH ((ETH_TypeDef *)ETH_BASE) |
#define | MDMA ((MDMA_TypeDef *)MDMA_BASE) |
#define | MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) |
#define | MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) |
#define | MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) |
#define | MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) |
#define | MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) |
#define | MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) |
#define | MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) |
#define | MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) |
#define | MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) |
#define | MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) |
#define | MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) |
#define | MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) |
#define | MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) |
#define | MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) |
#define | MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) |
#define | MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) |
#define | USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) |
#define | USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) |
#define | USB_OTG_HS USB1_OTG_HS |
#define | USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE |
#define | USB_OTG_FS USB2_OTG_FS |
#define | USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE |
#define | GPV ((GPV_TypeDef *) GPV_BASE) |
#define | LSI_STARTUP_TIME 130U |
#define | ADC_VER_V5_X |
#define | ADC_ISR_ADRDY_Pos (0U) |
#define | ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) |
#define | ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk |
#define | ADC_ISR_EOSMP_Pos (1U) |
#define | ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) |
#define | ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk |
#define | ADC_ISR_EOC_Pos (2U) |
#define | ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) |
#define | ADC_ISR_EOC ADC_ISR_EOC_Msk |
#define | ADC_ISR_EOS_Pos (3U) |
#define | ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) |
#define | ADC_ISR_EOS ADC_ISR_EOS_Msk |
#define | ADC_ISR_OVR_Pos (4U) |
#define | ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) |
#define | ADC_ISR_OVR ADC_ISR_OVR_Msk |
#define | ADC_ISR_JEOC_Pos (5U) |
#define | ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) |
#define | ADC_ISR_JEOC ADC_ISR_JEOC_Msk |
#define | ADC_ISR_JEOS_Pos (6U) |
#define | ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) |
#define | ADC_ISR_JEOS ADC_ISR_JEOS_Msk |
#define | ADC_ISR_AWD1_Pos (7U) |
#define | ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) |
#define | ADC_ISR_AWD1 ADC_ISR_AWD1_Msk |
#define | ADC_ISR_AWD2_Pos (8U) |
#define | ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) |
#define | ADC_ISR_AWD2 ADC_ISR_AWD2_Msk |
#define | ADC_ISR_AWD3_Pos (9U) |
#define | ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) |
#define | ADC_ISR_AWD3 ADC_ISR_AWD3_Msk |
#define | ADC_ISR_JQOVF_Pos (10U) |
#define | ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) |
#define | ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk |
#define | ADC_ISR_LDORDY_Pos (12U) |
#define | ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) |
#define | ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk |
#define | ADC_IER_ADRDYIE_Pos (0U) |
#define | ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) |
#define | ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk |
#define | ADC_IER_EOSMPIE_Pos (1U) |
#define | ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) |
#define | ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk |
#define | ADC_IER_EOCIE_Pos (2U) |
#define | ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) |
#define | ADC_IER_EOCIE ADC_IER_EOCIE_Msk |
#define | ADC_IER_EOSIE_Pos (3U) |
#define | ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) |
#define | ADC_IER_EOSIE ADC_IER_EOSIE_Msk |
#define | ADC_IER_OVRIE_Pos (4U) |
#define | ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) |
#define | ADC_IER_OVRIE ADC_IER_OVRIE_Msk |
#define | ADC_IER_JEOCIE_Pos (5U) |
#define | ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) |
#define | ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk |
#define | ADC_IER_JEOSIE_Pos (6U) |
#define | ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) |
#define | ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk |
#define | ADC_IER_AWD1IE_Pos (7U) |
#define | ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) |
#define | ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk |
#define | ADC_IER_AWD2IE_Pos (8U) |
#define | ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) |
#define | ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk |
#define | ADC_IER_AWD3IE_Pos (9U) |
#define | ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) |
#define | ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk |
#define | ADC_IER_JQOVFIE_Pos (10U) |
#define | ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) |
#define | ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk |
#define | ADC_CR_ADEN_Pos (0U) |
#define | ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) |
#define | ADC_CR_ADEN ADC_CR_ADEN_Msk |
#define | ADC_CR_ADDIS_Pos (1U) |
#define | ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) |
#define | ADC_CR_ADDIS ADC_CR_ADDIS_Msk |
#define | ADC_CR_ADSTART_Pos (2U) |
#define | ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) |
#define | ADC_CR_ADSTART ADC_CR_ADSTART_Msk |
#define | ADC_CR_JADSTART_Pos (3U) |
#define | ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) |
#define | ADC_CR_JADSTART ADC_CR_JADSTART_Msk |
#define | ADC_CR_ADSTP_Pos (4U) |
#define | ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) |
#define | ADC_CR_ADSTP ADC_CR_ADSTP_Msk |
#define | ADC_CR_JADSTP_Pos (5U) |
#define | ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) |
#define | ADC_CR_JADSTP ADC_CR_JADSTP_Msk |
#define | ADC_CR_BOOST_Pos (8U) |
#define | ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) |
#define | ADC_CR_BOOST ADC_CR_BOOST_Msk |
#define | ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) |
#define | ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) |
#define | ADC_CR_ADCALLIN_Pos (16U) |
#define | ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) |
#define | ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk |
#define | ADC_CR_LINCALRDYW1_Pos (22U) |
#define | ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) |
#define | ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk |
#define | ADC_CR_LINCALRDYW2_Pos (23U) |
#define | ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) |
#define | ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk |
#define | ADC_CR_LINCALRDYW3_Pos (24U) |
#define | ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) |
#define | ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk |
#define | ADC_CR_LINCALRDYW4_Pos (25U) |
#define | ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) |
#define | ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk |
#define | ADC_CR_LINCALRDYW5_Pos (26U) |
#define | ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) |
#define | ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk |
#define | ADC_CR_LINCALRDYW6_Pos (27U) |
#define | ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) |
#define | ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk |
#define | ADC_CR_ADVREGEN_Pos (28U) |
#define | ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) |
#define | ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk |
#define | ADC_CR_DEEPPWD_Pos (29U) |
#define | ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) |
#define | ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk |
#define | ADC_CR_ADCALDIF_Pos (30U) |
#define | ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) |
#define | ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk |
#define | ADC_CR_ADCAL_Pos (31U) |
#define | ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) |
#define | ADC_CR_ADCAL ADC_CR_ADCAL_Msk |
#define | ADC_CFGR_DMNGT_Pos (0U) |
#define | ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) |
#define | ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk |
#define | ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) |
#define | ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) |
#define | ADC_CFGR_RES_Pos (2U) |
#define | ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) |
#define | ADC_CFGR_RES ADC_CFGR_RES_Msk |
#define | ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) |
#define | ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) |
#define | ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) |
#define | ADC_CFGR_EXTSEL_Pos (5U) |
#define | ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) |
#define | ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk |
#define | ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) |
#define | ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) |
#define | ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) |
#define | ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) |
#define | ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) |
#define | ADC_CFGR_EXTEN_Pos (10U) |
#define | ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) |
#define | ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk |
#define | ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) |
#define | ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) |
#define | ADC_CFGR_OVRMOD_Pos (12U) |
#define | ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) |
#define | ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk |
#define | ADC_CFGR_CONT_Pos (13U) |
#define | ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) |
#define | ADC_CFGR_CONT ADC_CFGR_CONT_Msk |
#define | ADC_CFGR_AUTDLY_Pos (14U) |
#define | ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) |
#define | ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk |
#define | ADC_CFGR_DISCEN_Pos (16U) |
#define | ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) |
#define | ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk |
#define | ADC_CFGR_DISCNUM_Pos (17U) |
#define | ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) |
#define | ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk |
#define | ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) |
#define | ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) |
#define | ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) |
#define | ADC_CFGR_JDISCEN_Pos (20U) |
#define | ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) |
#define | ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk |
#define | ADC_CFGR_JQM_Pos (21U) |
#define | ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) |
#define | ADC_CFGR_JQM ADC_CFGR_JQM_Msk |
#define | ADC_CFGR_AWD1SGL_Pos (22U) |
#define | ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) |
#define | ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk |
#define | ADC_CFGR_AWD1EN_Pos (23U) |
#define | ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) |
#define | ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk |
#define | ADC_CFGR_JAWD1EN_Pos (24U) |
#define | ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) |
#define | ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk |
#define | ADC_CFGR_JAUTO_Pos (25U) |
#define | ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) |
#define | ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk |
#define | ADC_CFGR_AWD1CH_Pos (26U) |
#define | ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) |
#define | ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk |
#define | ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) |
#define | ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) |
#define | ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) |
#define | ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) |
#define | ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) |
#define | ADC_CFGR_JQDIS_Pos (31U) |
#define | ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) |
#define | ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk |
#define | ADC_CFGR2_ROVSE_Pos (0U) |
#define | ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) |
#define | ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk |
#define | ADC_CFGR2_JOVSE_Pos (1U) |
#define | ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) |
#define | ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk |
#define | ADC_CFGR2_OVSS_Pos (5U) |
#define | ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) |
#define | ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk |
#define | ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) |
#define | ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) |
#define | ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) |
#define | ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) |
#define | ADC_CFGR2_TROVS_Pos (9U) |
#define | ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) |
#define | ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk |
#define | ADC_CFGR2_ROVSM_Pos (10U) |
#define | ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) |
#define | ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk |
#define | ADC_CFGR2_RSHIFT1_Pos (11U) |
#define | ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) |
#define | ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk |
#define | ADC_CFGR2_RSHIFT2_Pos (12U) |
#define | ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) |
#define | ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk |
#define | ADC_CFGR2_RSHIFT3_Pos (13U) |
#define | ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) |
#define | ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk |
#define | ADC_CFGR2_RSHIFT4_Pos (14U) |
#define | ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) |
#define | ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk |
#define | ADC_CFGR2_OVSR_Pos (16U) |
#define | ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk |
#define | ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) |
#define | ADC_CFGR2_LSHIFT_Pos (28U) |
#define | ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) |
#define | ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk |
#define | ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) |
#define | ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) |
#define | ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) |
#define | ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) |
#define | ADC_SMPR1_SMP0_Pos (0U) |
#define | ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) |
#define | ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk |
#define | ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) |
#define | ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) |
#define | ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) |
#define | ADC_SMPR1_SMP1_Pos (3U) |
#define | ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) |
#define | ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk |
#define | ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) |
#define | ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) |
#define | ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) |
#define | ADC_SMPR1_SMP2_Pos (6U) |
#define | ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) |
#define | ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk |
#define | ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) |
#define | ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) |
#define | ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) |
#define | ADC_SMPR1_SMP3_Pos (9U) |
#define | ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) |
#define | ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk |
#define | ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) |
#define | ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) |
#define | ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) |
#define | ADC_SMPR1_SMP4_Pos (12U) |
#define | ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) |
#define | ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk |
#define | ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) |
#define | ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) |
#define | ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) |
#define | ADC_SMPR1_SMP5_Pos (15U) |
#define | ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) |
#define | ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk |
#define | ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) |
#define | ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) |
#define | ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) |
#define | ADC_SMPR1_SMP6_Pos (18U) |
#define | ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) |
#define | ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk |
#define | ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) |
#define | ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) |
#define | ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) |
#define | ADC_SMPR1_SMP7_Pos (21U) |
#define | ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) |
#define | ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk |
#define | ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) |
#define | ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) |
#define | ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) |
#define | ADC_SMPR1_SMP8_Pos (24U) |
#define | ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) |
#define | ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk |
#define | ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) |
#define | ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) |
#define | ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) |
#define | ADC_SMPR1_SMP9_Pos (27U) |
#define | ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) |
#define | ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk |
#define | ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) |
#define | ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) |
#define | ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) |
#define | ADC_SMPR2_SMP10_Pos (0U) |
#define | ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) |
#define | ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk |
#define | ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) |
#define | ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) |
#define | ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) |
#define | ADC_SMPR2_SMP11_Pos (3U) |
#define | ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) |
#define | ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk |
#define | ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) |
#define | ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) |
#define | ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) |
#define | ADC_SMPR2_SMP12_Pos (6U) |
#define | ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) |
#define | ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk |
#define | ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) |
#define | ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) |
#define | ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) |
#define | ADC_SMPR2_SMP13_Pos (9U) |
#define | ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) |
#define | ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk |
#define | ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) |
#define | ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) |
#define | ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) |
#define | ADC_SMPR2_SMP14_Pos (12U) |
#define | ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) |
#define | ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk |
#define | ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) |
#define | ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) |
#define | ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) |
#define | ADC_SMPR2_SMP15_Pos (15U) |
#define | ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) |
#define | ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk |
#define | ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) |
#define | ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) |
#define | ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) |
#define | ADC_SMPR2_SMP16_Pos (18U) |
#define | ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) |
#define | ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk |
#define | ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) |
#define | ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) |
#define | ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) |
#define | ADC_SMPR2_SMP17_Pos (21U) |
#define | ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) |
#define | ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk |
#define | ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) |
#define | ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) |
#define | ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) |
#define | ADC_SMPR2_SMP18_Pos (24U) |
#define | ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) |
#define | ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk |
#define | ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) |
#define | ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) |
#define | ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) |
#define | ADC_SMPR2_SMP19_Pos (27U) |
#define | ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) |
#define | ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk |
#define | ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) |
#define | ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) |
#define | ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) |
#define | ADC_PCSEL_PCSEL_Pos (0U) |
#define | ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk |
#define | ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) |
#define | ADC_LTR_LT_Pos (0U) |
#define | ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) |
#define | ADC_LTR_LT ADC_LTR_LT_Msk |
#define | ADC_HTR_HT_Pos (0U) |
#define | ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) |
#define | ADC_HTR_HT ADC_HTR_HT_Msk |
#define | ADC_SQR1_L_Pos (0U) |
#define | ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) |
#define | ADC_SQR1_L ADC_SQR1_L_Msk |
#define | ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) |
#define | ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) |
#define | ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) |
#define | ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) |
#define | ADC_SQR1_SQ1_Pos (6U) |
#define | ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) |
#define | ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk |
#define | ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) |
#define | ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) |
#define | ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) |
#define | ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) |
#define | ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) |
#define | ADC_SQR1_SQ2_Pos (12U) |
#define | ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) |
#define | ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk |
#define | ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) |
#define | ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) |
#define | ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) |
#define | ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) |
#define | ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) |
#define | ADC_SQR1_SQ3_Pos (18U) |
#define | ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) |
#define | ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk |
#define | ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) |
#define | ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) |
#define | ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) |
#define | ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) |
#define | ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) |
#define | ADC_SQR1_SQ4_Pos (24U) |
#define | ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) |
#define | ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk |
#define | ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) |
#define | ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) |
#define | ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) |
#define | ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) |
#define | ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) |
#define | ADC_SQR2_SQ5_Pos (0U) |
#define | ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) |
#define | ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk |
#define | ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) |
#define | ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) |
#define | ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) |
#define | ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) |
#define | ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) |
#define | ADC_SQR2_SQ6_Pos (6U) |
#define | ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) |
#define | ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk |
#define | ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) |
#define | ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) |
#define | ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) |
#define | ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) |
#define | ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) |
#define | ADC_SQR2_SQ7_Pos (12U) |
#define | ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) |
#define | ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk |
#define | ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) |
#define | ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) |
#define | ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) |
#define | ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) |
#define | ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) |
#define | ADC_SQR2_SQ8_Pos (18U) |
#define | ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) |
#define | ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk |
#define | ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) |
#define | ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) |
#define | ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) |
#define | ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) |
#define | ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) |
#define | ADC_SQR2_SQ9_Pos (24U) |
#define | ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) |
#define | ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk |
#define | ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) |
#define | ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) |
#define | ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) |
#define | ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) |
#define | ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) |
#define | ADC_SQR3_SQ10_Pos (0U) |
#define | ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) |
#define | ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk |
#define | ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) |
#define | ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) |
#define | ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) |
#define | ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) |
#define | ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) |
#define | ADC_SQR3_SQ11_Pos (6U) |
#define | ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) |
#define | ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk |
#define | ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) |
#define | ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) |
#define | ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) |
#define | ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) |
#define | ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) |
#define | ADC_SQR3_SQ12_Pos (12U) |
#define | ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) |
#define | ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk |
#define | ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) |
#define | ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) |
#define | ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) |
#define | ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) |
#define | ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) |
#define | ADC_SQR3_SQ13_Pos (18U) |
#define | ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) |
#define | ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk |
#define | ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) |
#define | ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) |
#define | ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) |
#define | ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) |
#define | ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) |
#define | ADC_SQR3_SQ14_Pos (24U) |
#define | ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) |
#define | ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk |
#define | ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) |
#define | ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) |
#define | ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) |
#define | ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) |
#define | ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) |
#define | ADC_SQR4_SQ15_Pos (0U) |
#define | ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) |
#define | ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk |
#define | ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) |
#define | ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) |
#define | ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) |
#define | ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) |
#define | ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) |
#define | ADC_SQR4_SQ16_Pos (6U) |
#define | ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) |
#define | ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk |
#define | ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) |
#define | ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) |
#define | ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) |
#define | ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) |
#define | ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) |
#define | ADC_DR_RDATA_Pos (0U) |
#define | ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) |
#define | ADC_DR_RDATA ADC_DR_RDATA_Msk |
#define | ADC_JSQR_JL_Pos (0U) |
#define | ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) |
#define | ADC_JSQR_JL ADC_JSQR_JL_Msk |
#define | ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) |
#define | ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) |
#define | ADC_JSQR_JEXTSEL_Pos (2U) |
#define | ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) |
#define | ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk |
#define | ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) |
#define | ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) |
#define | ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) |
#define | ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) |
#define | ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) |
#define | ADC_JSQR_JEXTEN_Pos (7U) |
#define | ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) |
#define | ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk |
#define | ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) |
#define | ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) |
#define | ADC_JSQR_JSQ1_Pos (9U) |
#define | ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) |
#define | ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk |
#define | ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) |
#define | ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) |
#define | ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) |
#define | ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) |
#define | ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) |
#define | ADC_JSQR_JSQ2_Pos (15U) |
#define | ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) |
#define | ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk |
#define | ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) |
#define | ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) |
#define | ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) |
#define | ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) |
#define | ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) |
#define | ADC_JSQR_JSQ3_Pos (21U) |
#define | ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) |
#define | ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk |
#define | ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) |
#define | ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) |
#define | ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) |
#define | ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) |
#define | ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) |
#define | ADC_JSQR_JSQ4_Pos (27U) |
#define | ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) |
#define | ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk |
#define | ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) |
#define | ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) |
#define | ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) |
#define | ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) |
#define | ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) |
#define | ADC_OFR1_OFFSET1_Pos (0U) |
#define | ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk |
#define | ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) |
#define | ADC_OFR1_OFFSET1_CH_Pos (26U) |
#define | ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) |
#define | ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk |
#define | ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) |
#define | ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) |
#define | ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) |
#define | ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) |
#define | ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) |
#define | ADC_OFR1_SSATE_Pos (31U) |
#define | ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) |
#define | ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk |
#define | ADC_OFR2_OFFSET2_Pos (0U) |
#define | ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk |
#define | ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) |
#define | ADC_OFR2_OFFSET2_CH_Pos (26U) |
#define | ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) |
#define | ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk |
#define | ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) |
#define | ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) |
#define | ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) |
#define | ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) |
#define | ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) |
#define | ADC_OFR2_SSATE_Pos (31U) |
#define | ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) |
#define | ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk |
#define | ADC_OFR3_OFFSET3_Pos (0U) |
#define | ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk |
#define | ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) |
#define | ADC_OFR3_OFFSET3_CH_Pos (26U) |
#define | ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) |
#define | ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk |
#define | ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) |
#define | ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) |
#define | ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) |
#define | ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) |
#define | ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) |
#define | ADC_OFR3_SSATE_Pos (31U) |
#define | ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) |
#define | ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk |
#define | ADC_OFR4_OFFSET4_Pos (0U) |
#define | ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk |
#define | ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) |
#define | ADC_OFR4_OFFSET4_CH_Pos (26U) |
#define | ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) |
#define | ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk |
#define | ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) |
#define | ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) |
#define | ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) |
#define | ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) |
#define | ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) |
#define | ADC_OFR4_SSATE_Pos (31U) |
#define | ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) |
#define | ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk |
#define | ADC_JDR1_JDATA_Pos (0U) |
#define | ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk |
#define | ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) |
#define | ADC_JDR2_JDATA_Pos (0U) |
#define | ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk |
#define | ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) |
#define | ADC_JDR3_JDATA_Pos (0U) |
#define | ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk |
#define | ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) |
#define | ADC_JDR4_JDATA_Pos (0U) |
#define | ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk |
#define | ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) |
#define | ADC_AWD2CR_AWD2CH_Pos (0U) |
#define | ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk |
#define | ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_Pos (0U) |
#define | ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk |
#define | ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) |
#define | ADC_DIFSEL_DIFSEL_Pos (0U) |
#define | ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk |
#define | ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) |
#define | ADC_CALFACT_CALFACT_S_Pos (0U) |
#define | ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk |
#define | ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) |
#define | ADC_CALFACT_CALFACT_D_Pos (16U) |
#define | ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk |
#define | ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) |
#define | ADC_CALFACT2_LINCALFACT_Pos (0U) |
#define | ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk |
#define | ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) |
#define | ADC_CSR_ADRDY_MST_Pos (0U) |
#define | ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) |
#define | ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk |
#define | ADC_CSR_EOSMP_MST_Pos (1U) |
#define | ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) |
#define | ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk |
#define | ADC_CSR_EOC_MST_Pos (2U) |
#define | ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) |
#define | ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk |
#define | ADC_CSR_EOS_MST_Pos (3U) |
#define | ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) |
#define | ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk |
#define | ADC_CSR_OVR_MST_Pos (4U) |
#define | ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) |
#define | ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk |
#define | ADC_CSR_JEOC_MST_Pos (5U) |
#define | ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) |
#define | ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk |
#define | ADC_CSR_JEOS_MST_Pos (6U) |
#define | ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) |
#define | ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk |
#define | ADC_CSR_AWD1_MST_Pos (7U) |
#define | ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) |
#define | ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk |
#define | ADC_CSR_AWD2_MST_Pos (8U) |
#define | ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) |
#define | ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk |
#define | ADC_CSR_AWD3_MST_Pos (9U) |
#define | ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) |
#define | ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk |
#define | ADC_CSR_JQOVF_MST_Pos (10U) |
#define | ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) |
#define | ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk |
#define | ADC_CSR_ADRDY_SLV_Pos (16U) |
#define | ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) |
#define | ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk |
#define | ADC_CSR_EOSMP_SLV_Pos (17U) |
#define | ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) |
#define | ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk |
#define | ADC_CSR_EOC_SLV_Pos (18U) |
#define | ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) |
#define | ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk |
#define | ADC_CSR_EOS_SLV_Pos (19U) |
#define | ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) |
#define | ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk |
#define | ADC_CSR_OVR_SLV_Pos (20U) |
#define | ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) |
#define | ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk |
#define | ADC_CSR_JEOC_SLV_Pos (21U) |
#define | ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) |
#define | ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk |
#define | ADC_CSR_JEOS_SLV_Pos (22U) |
#define | ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) |
#define | ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk |
#define | ADC_CSR_AWD1_SLV_Pos (23U) |
#define | ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) |
#define | ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk |
#define | ADC_CSR_AWD2_SLV_Pos (24U) |
#define | ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) |
#define | ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk |
#define | ADC_CSR_AWD3_SLV_Pos (25U) |
#define | ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) |
#define | ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk |
#define | ADC_CSR_JQOVF_SLV_Pos (26U) |
#define | ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) |
#define | ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk |
#define | ADC_CCR_DUAL_Pos (0U) |
#define | ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) |
#define | ADC_CCR_DUAL ADC_CCR_DUAL_Msk |
#define | ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) |
#define | ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) |
#define | ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) |
#define | ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) |
#define | ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) |
#define | ADC_CCR_DELAY_Pos (8U) |
#define | ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) |
#define | ADC_CCR_DELAY ADC_CCR_DELAY_Msk |
#define | ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) |
#define | ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) |
#define | ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) |
#define | ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) |
#define | ADC_CCR_DAMDF_Pos (14U) |
#define | ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) |
#define | ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk |
#define | ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) |
#define | ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) |
#define | ADC_CCR_CKMODE_Pos (16U) |
#define | ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) |
#define | ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk |
#define | ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) |
#define | ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) |
#define | ADC_CCR_PRESC_Pos (18U) |
#define | ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) |
#define | ADC_CCR_PRESC ADC_CCR_PRESC_Msk |
#define | ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) |
#define | ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) |
#define | ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) |
#define | ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) |
#define | ADC_CCR_VREFEN_Pos (22U) |
#define | ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) |
#define | ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk |
#define | ADC_CCR_TSEN_Pos (23U) |
#define | ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) |
#define | ADC_CCR_TSEN ADC_CCR_TSEN_Msk |
#define | ADC_CCR_VBATEN_Pos (24U) |
#define | ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) |
#define | ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk |
#define | ADC_CDR_RDATA_MST_Pos (0U) |
#define | ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) |
#define | ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk |
#define | ADC_CDR_RDATA_SLV_Pos (16U) |
#define | ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) |
#define | ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk |
#define | ADC_CDR2_RDATA_ALT_Pos (0U) |
#define | ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) |
#define | ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk |
#define | VREFBUF_CSR_ENVR_Pos (0U) |
#define | VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) |
#define | VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk |
#define | VREFBUF_CSR_HIZ_Pos (1U) |
#define | VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) |
#define | VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk |
#define | VREFBUF_CSR_VRR_Pos (3U) |
#define | VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) |
#define | VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk |
#define | VREFBUF_CSR_VRS_Pos (4U) |
#define | VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) |
#define | VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk |
#define | VREFBUF_CSR_VRS_OUT1 (0U) |
#define | VREFBUF_CSR_VRS_OUT2_Pos (4U) |
#define | VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) |
#define | VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk |
#define | VREFBUF_CSR_VRS_OUT3_Pos (5U) |
#define | VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) |
#define | VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk |
#define | VREFBUF_CSR_VRS_OUT4_Pos (4U) |
#define | VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) |
#define | VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk |
#define | VREFBUF_CCR_TRIM_Pos (0U) |
#define | VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) |
#define | VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk |
#define | FDCAN_CREL_DAY_Pos (0U) |
#define | FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) |
#define | FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk |
#define | FDCAN_CREL_MON_Pos (8U) |
#define | FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) |
#define | FDCAN_CREL_MON FDCAN_CREL_MON_Msk |
#define | FDCAN_CREL_YEAR_Pos (16U) |
#define | FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) |
#define | FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk |
#define | FDCAN_CREL_SUBSTEP_Pos (20U) |
#define | FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) |
#define | FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk |
#define | FDCAN_CREL_STEP_Pos (24U) |
#define | FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) |
#define | FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk |
#define | FDCAN_CREL_REL_Pos (28U) |
#define | FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) |
#define | FDCAN_CREL_REL FDCAN_CREL_REL_Msk |
#define | FDCAN_ENDN_ETV_Pos (0U) |
#define | FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) |
#define | FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk |
#define | FDCAN_DBTP_DSJW_Pos (0U) |
#define | FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) |
#define | FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk |
#define | FDCAN_DBTP_DTSEG2_Pos (4U) |
#define | FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) |
#define | FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk |
#define | FDCAN_DBTP_DTSEG1_Pos (8U) |
#define | FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) |
#define | FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk |
#define | FDCAN_DBTP_DBRP_Pos (16U) |
#define | FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) |
#define | FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk |
#define | FDCAN_DBTP_TDC_Pos (23U) |
#define | FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) |
#define | FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk |
#define | FDCAN_TEST_LBCK_Pos (4U) |
#define | FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) |
#define | FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk |
#define | FDCAN_TEST_TX_Pos (5U) |
#define | FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) |
#define | FDCAN_TEST_TX FDCAN_TEST_TX_Msk |
#define | FDCAN_TEST_RX_Pos (7U) |
#define | FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) |
#define | FDCAN_TEST_RX FDCAN_TEST_RX_Msk |
#define | FDCAN_RWD_WDC_Pos (0U) |
#define | FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) |
#define | FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk |
#define | FDCAN_RWD_WDV_Pos (8U) |
#define | FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) |
#define | FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk |
#define | FDCAN_CCCR_INIT_Pos (0U) |
#define | FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) |
#define | FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk |
#define | FDCAN_CCCR_CCE_Pos (1U) |
#define | FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) |
#define | FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk |
#define | FDCAN_CCCR_ASM_Pos (2U) |
#define | FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) |
#define | FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk |
#define | FDCAN_CCCR_CSA_Pos (3U) |
#define | FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) |
#define | FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk |
#define | FDCAN_CCCR_CSR_Pos (4U) |
#define | FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) |
#define | FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk |
#define | FDCAN_CCCR_MON_Pos (5U) |
#define | FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) |
#define | FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk |
#define | FDCAN_CCCR_DAR_Pos (6U) |
#define | FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) |
#define | FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk |
#define | FDCAN_CCCR_TEST_Pos (7U) |
#define | FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) |
#define | FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk |
#define | FDCAN_CCCR_FDOE_Pos (8U) |
#define | FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) |
#define | FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk |
#define | FDCAN_CCCR_BRSE_Pos (9U) |
#define | FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) |
#define | FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk |
#define | FDCAN_CCCR_PXHD_Pos (12U) |
#define | FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) |
#define | FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk |
#define | FDCAN_CCCR_EFBI_Pos (13U) |
#define | FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) |
#define | FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk |
#define | FDCAN_CCCR_TXP_Pos (14U) |
#define | FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) |
#define | FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk |
#define | FDCAN_CCCR_NISO_Pos (15U) |
#define | FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) |
#define | FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk |
#define | FDCAN_NBTP_NTSEG2_Pos (0U) |
#define | FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) |
#define | FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk |
#define | FDCAN_NBTP_NTSEG1_Pos (8U) |
#define | FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) |
#define | FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk |
#define | FDCAN_NBTP_NBRP_Pos (16U) |
#define | FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) |
#define | FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk |
#define | FDCAN_NBTP_NSJW_Pos (25U) |
#define | FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) |
#define | FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk |
#define | FDCAN_TSCC_TSS_Pos (0U) |
#define | FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) |
#define | FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk |
#define | FDCAN_TSCC_TCP_Pos (16U) |
#define | FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) |
#define | FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk |
#define | FDCAN_TSCV_TSC_Pos (0U) |
#define | FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) |
#define | FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk |
#define | FDCAN_TOCC_ETOC_Pos (0U) |
#define | FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) |
#define | FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk |
#define | FDCAN_TOCC_TOS_Pos (1U) |
#define | FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) |
#define | FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk |
#define | FDCAN_TOCC_TOP_Pos (16U) |
#define | FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) |
#define | FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk |
#define | FDCAN_TOCV_TOC_Pos (0U) |
#define | FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) |
#define | FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk |
#define | FDCAN_ECR_TEC_Pos (0U) |
#define | FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) |
#define | FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk |
#define | FDCAN_ECR_REC_Pos (8U) |
#define | FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) |
#define | FDCAN_ECR_REC FDCAN_ECR_REC_Msk |
#define | FDCAN_ECR_RP_Pos (15U) |
#define | FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) |
#define | FDCAN_ECR_RP FDCAN_ECR_RP_Msk |
#define | FDCAN_ECR_CEL_Pos (16U) |
#define | FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) |
#define | FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk |
#define | FDCAN_PSR_LEC_Pos (0U) |
#define | FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) |
#define | FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk |
#define | FDCAN_PSR_ACT_Pos (3U) |
#define | FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) |
#define | FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk |
#define | FDCAN_PSR_EP_Pos (5U) |
#define | FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) |
#define | FDCAN_PSR_EP FDCAN_PSR_EP_Msk |
#define | FDCAN_PSR_EW_Pos (6U) |
#define | FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) |
#define | FDCAN_PSR_EW FDCAN_PSR_EW_Msk |
#define | FDCAN_PSR_BO_Pos (7U) |
#define | FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) |
#define | FDCAN_PSR_BO FDCAN_PSR_BO_Msk |
#define | FDCAN_PSR_DLEC_Pos (8U) |
#define | FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) |
#define | FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk |
#define | FDCAN_PSR_RESI_Pos (11U) |
#define | FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) |
#define | FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk |
#define | FDCAN_PSR_RBRS_Pos (12U) |
#define | FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) |
#define | FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk |
#define | FDCAN_PSR_REDL_Pos (13U) |
#define | FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) |
#define | FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk |
#define | FDCAN_PSR_PXE_Pos (14U) |
#define | FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) |
#define | FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk |
#define | FDCAN_PSR_TDCV_Pos (16U) |
#define | FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) |
#define | FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk |
#define | FDCAN_TDCR_TDCF_Pos (0U) |
#define | FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) |
#define | FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk |
#define | FDCAN_TDCR_TDCO_Pos (8U) |
#define | FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) |
#define | FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk |
#define | FDCAN_IR_RF0N_Pos (0U) |
#define | FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) |
#define | FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk |
#define | FDCAN_IR_RF0W_Pos (1U) |
#define | FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) |
#define | FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk |
#define | FDCAN_IR_RF0F_Pos (2U) |
#define | FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) |
#define | FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk |
#define | FDCAN_IR_RF0L_Pos (3U) |
#define | FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) |
#define | FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk |
#define | FDCAN_IR_RF1N_Pos (4U) |
#define | FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) |
#define | FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk |
#define | FDCAN_IR_RF1W_Pos (5U) |
#define | FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) |
#define | FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk |
#define | FDCAN_IR_RF1F_Pos (6U) |
#define | FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) |
#define | FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk |
#define | FDCAN_IR_RF1L_Pos (7U) |
#define | FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) |
#define | FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk |
#define | FDCAN_IR_HPM_Pos (8U) |
#define | FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) |
#define | FDCAN_IR_HPM FDCAN_IR_HPM_Msk |
#define | FDCAN_IR_TC_Pos (9U) |
#define | FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) |
#define | FDCAN_IR_TC FDCAN_IR_TC_Msk |
#define | FDCAN_IR_TCF_Pos (10U) |
#define | FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) |
#define | FDCAN_IR_TCF FDCAN_IR_TCF_Msk |
#define | FDCAN_IR_TFE_Pos (11U) |
#define | FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) |
#define | FDCAN_IR_TFE FDCAN_IR_TFE_Msk |
#define | FDCAN_IR_TEFN_Pos (12U) |
#define | FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) |
#define | FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk |
#define | FDCAN_IR_TEFW_Pos (13U) |
#define | FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) |
#define | FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk |
#define | FDCAN_IR_TEFF_Pos (14U) |
#define | FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) |
#define | FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk |
#define | FDCAN_IR_TEFL_Pos (15U) |
#define | FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) |
#define | FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk |
#define | FDCAN_IR_TSW_Pos (16U) |
#define | FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) |
#define | FDCAN_IR_TSW FDCAN_IR_TSW_Msk |
#define | FDCAN_IR_MRAF_Pos (17U) |
#define | FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) |
#define | FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk |
#define | FDCAN_IR_TOO_Pos (18U) |
#define | FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) |
#define | FDCAN_IR_TOO FDCAN_IR_TOO_Msk |
#define | FDCAN_IR_DRX_Pos (19U) |
#define | FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) |
#define | FDCAN_IR_DRX FDCAN_IR_DRX_Msk |
#define | FDCAN_IR_ELO_Pos (22U) |
#define | FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) |
#define | FDCAN_IR_ELO FDCAN_IR_ELO_Msk |
#define | FDCAN_IR_EP_Pos (23U) |
#define | FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) |
#define | FDCAN_IR_EP FDCAN_IR_EP_Msk |
#define | FDCAN_IR_EW_Pos (24U) |
#define | FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) |
#define | FDCAN_IR_EW FDCAN_IR_EW_Msk |
#define | FDCAN_IR_BO_Pos (25U) |
#define | FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) |
#define | FDCAN_IR_BO FDCAN_IR_BO_Msk |
#define | FDCAN_IR_WDI_Pos (26U) |
#define | FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) |
#define | FDCAN_IR_WDI FDCAN_IR_WDI_Msk |
#define | FDCAN_IR_PEA_Pos (27U) |
#define | FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) |
#define | FDCAN_IR_PEA FDCAN_IR_PEA_Msk |
#define | FDCAN_IR_PED_Pos (28U) |
#define | FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) |
#define | FDCAN_IR_PED FDCAN_IR_PED_Msk |
#define | FDCAN_IR_ARA_Pos (29U) |
#define | FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) |
#define | FDCAN_IR_ARA FDCAN_IR_ARA_Msk |
#define | FDCAN_IE_RF0NE_Pos (0U) |
#define | FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) |
#define | FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk |
#define | FDCAN_IE_RF0WE_Pos (1U) |
#define | FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) |
#define | FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk |
#define | FDCAN_IE_RF0FE_Pos (2U) |
#define | FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) |
#define | FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk |
#define | FDCAN_IE_RF0LE_Pos (3U) |
#define | FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) |
#define | FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk |
#define | FDCAN_IE_RF1NE_Pos (4U) |
#define | FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) |
#define | FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk |
#define | FDCAN_IE_RF1WE_Pos (5U) |
#define | FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) |
#define | FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk |
#define | FDCAN_IE_RF1FE_Pos (6U) |
#define | FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) |
#define | FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk |
#define | FDCAN_IE_RF1LE_Pos (7U) |
#define | FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) |
#define | FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk |
#define | FDCAN_IE_HPME_Pos (8U) |
#define | FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) |
#define | FDCAN_IE_HPME FDCAN_IE_HPME_Msk |
#define | FDCAN_IE_TCE_Pos (9U) |
#define | FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) |
#define | FDCAN_IE_TCE FDCAN_IE_TCE_Msk |
#define | FDCAN_IE_TCFE_Pos (10U) |
#define | FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) |
#define | FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk |
#define | FDCAN_IE_TFEE_Pos (11U) |
#define | FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) |
#define | FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk |
#define | FDCAN_IE_TEFNE_Pos (12U) |
#define | FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) |
#define | FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk |
#define | FDCAN_IE_TEFWE_Pos (13U) |
#define | FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) |
#define | FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk |
#define | FDCAN_IE_TEFFE_Pos (14U) |
#define | FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) |
#define | FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk |
#define | FDCAN_IE_TEFLE_Pos (15U) |
#define | FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) |
#define | FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk |
#define | FDCAN_IE_TSWE_Pos (16U) |
#define | FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) |
#define | FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk |
#define | FDCAN_IE_MRAFE_Pos (17U) |
#define | FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) |
#define | FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk |
#define | FDCAN_IE_TOOE_Pos (18U) |
#define | FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) |
#define | FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk |
#define | FDCAN_IE_DRXE_Pos (19U) |
#define | FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) |
#define | FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk |
#define | FDCAN_IE_BECE_Pos (20U) |
#define | FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) |
#define | FDCAN_IE_BECE FDCAN_IE_BECE_Msk |
#define | FDCAN_IE_BEUE_Pos (21U) |
#define | FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) |
#define | FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk |
#define | FDCAN_IE_ELOE_Pos (22U) |
#define | FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) |
#define | FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk |
#define | FDCAN_IE_EPE_Pos (23U) |
#define | FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) |
#define | FDCAN_IE_EPE FDCAN_IE_EPE_Msk |
#define | FDCAN_IE_EWE_Pos (24U) |
#define | FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) |
#define | FDCAN_IE_EWE FDCAN_IE_EWE_Msk |
#define | FDCAN_IE_BOE_Pos (25U) |
#define | FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) |
#define | FDCAN_IE_BOE FDCAN_IE_BOE_Msk |
#define | FDCAN_IE_WDIE_Pos (26U) |
#define | FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) |
#define | FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk |
#define | FDCAN_IE_PEAE_Pos (27U) |
#define | FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) |
#define | FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk |
#define | FDCAN_IE_PEDE_Pos (28U) |
#define | FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) |
#define | FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk |
#define | FDCAN_IE_ARAE_Pos (29U) |
#define | FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) |
#define | FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk |
#define | FDCAN_ILS_RF0NL_Pos (0U) |
#define | FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) |
#define | FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk |
#define | FDCAN_ILS_RF0WL_Pos (1U) |
#define | FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) |
#define | FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk |
#define | FDCAN_ILS_RF0FL_Pos (2U) |
#define | FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) |
#define | FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk |
#define | FDCAN_ILS_RF0LL_Pos (3U) |
#define | FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) |
#define | FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk |
#define | FDCAN_ILS_RF1NL_Pos (4U) |
#define | FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) |
#define | FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk |
#define | FDCAN_ILS_RF1WL_Pos (5U) |
#define | FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) |
#define | FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk |
#define | FDCAN_ILS_RF1FL_Pos (6U) |
#define | FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) |
#define | FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk |
#define | FDCAN_ILS_RF1LL_Pos (7U) |
#define | FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) |
#define | FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk |
#define | FDCAN_ILS_HPML_Pos (8U) |
#define | FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) |
#define | FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk |
#define | FDCAN_ILS_TCL_Pos (9U) |
#define | FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) |
#define | FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk |
#define | FDCAN_ILS_TCFL_Pos (10U) |
#define | FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) |
#define | FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk |
#define | FDCAN_ILS_TFEL_Pos (11U) |
#define | FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) |
#define | FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk |
#define | FDCAN_ILS_TEFNL_Pos (12U) |
#define | FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) |
#define | FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk |
#define | FDCAN_ILS_TEFWL_Pos (13U) |
#define | FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) |
#define | FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk |
#define | FDCAN_ILS_TEFFL_Pos (14U) |
#define | FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) |
#define | FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk |
#define | FDCAN_ILS_TEFLL_Pos (15U) |
#define | FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) |
#define | FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk |
#define | FDCAN_ILS_TSWL_Pos (16U) |
#define | FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) |
#define | FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk |
#define | FDCAN_ILS_MRAFE_Pos (17U) |
#define | FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) |
#define | FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk |
#define | FDCAN_ILS_TOOE_Pos (18U) |
#define | FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) |
#define | FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk |
#define | FDCAN_ILS_DRXE_Pos (19U) |
#define | FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) |
#define | FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk |
#define | FDCAN_ILS_BECE_Pos (20U) |
#define | FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) |
#define | FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk |
#define | FDCAN_ILS_BEUE_Pos (21U) |
#define | FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) |
#define | FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk |
#define | FDCAN_ILS_ELOE_Pos (22U) |
#define | FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) |
#define | FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk |
#define | FDCAN_ILS_EPE_Pos (23U) |
#define | FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) |
#define | FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk |
#define | FDCAN_ILS_EWE_Pos (24U) |
#define | FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) |
#define | FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk |
#define | FDCAN_ILS_BOE_Pos (25U) |
#define | FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) |
#define | FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk |
#define | FDCAN_ILS_WDIE_Pos (26U) |
#define | FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) |
#define | FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk |
#define | FDCAN_ILS_PEAE_Pos (27U) |
#define | FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) |
#define | FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk |
#define | FDCAN_ILS_PEDE_Pos (28U) |
#define | FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) |
#define | FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk |
#define | FDCAN_ILS_ARAE_Pos (29U) |
#define | FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) |
#define | FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk |
#define | FDCAN_ILE_EINT0_Pos (0U) |
#define | FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) |
#define | FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk |
#define | FDCAN_ILE_EINT1_Pos (1U) |
#define | FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) |
#define | FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk |
#define | FDCAN_GFC_RRFE_Pos (0U) |
#define | FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) |
#define | FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk |
#define | FDCAN_GFC_RRFS_Pos (1U) |
#define | FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) |
#define | FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk |
#define | FDCAN_GFC_ANFE_Pos (2U) |
#define | FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) |
#define | FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk |
#define | FDCAN_GFC_ANFS_Pos (4U) |
#define | FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) |
#define | FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk |
#define | FDCAN_SIDFC_FLSSA_Pos (2U) |
#define | FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) |
#define | FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk |
#define | FDCAN_SIDFC_LSS_Pos (16U) |
#define | FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) |
#define | FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk |
#define | FDCAN_XIDFC_FLESA_Pos (2U) |
#define | FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) |
#define | FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk |
#define | FDCAN_XIDFC_LSE_Pos (16U) |
#define | FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) |
#define | FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk |
#define | FDCAN_XIDAM_EIDM_Pos (0U) |
#define | FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) |
#define | FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk |
#define | FDCAN_HPMS_BIDX_Pos (0U) |
#define | FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) |
#define | FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk |
#define | FDCAN_HPMS_MSI_Pos (6U) |
#define | FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) |
#define | FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk |
#define | FDCAN_HPMS_FIDX_Pos (8U) |
#define | FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) |
#define | FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk |
#define | FDCAN_HPMS_FLST_Pos (15U) |
#define | FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) |
#define | FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk |
#define | FDCAN_NDAT1_ND0_Pos (0U) |
#define | FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) |
#define | FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk |
#define | FDCAN_NDAT1_ND1_Pos (1U) |
#define | FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) |
#define | FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk |
#define | FDCAN_NDAT1_ND2_Pos (2U) |
#define | FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) |
#define | FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk |
#define | FDCAN_NDAT1_ND3_Pos (3U) |
#define | FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) |
#define | FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk |
#define | FDCAN_NDAT1_ND4_Pos (4U) |
#define | FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) |
#define | FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk |
#define | FDCAN_NDAT1_ND5_Pos (5U) |
#define | FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) |
#define | FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk |
#define | FDCAN_NDAT1_ND6_Pos (6U) |
#define | FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) |
#define | FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk |
#define | FDCAN_NDAT1_ND7_Pos (7U) |
#define | FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) |
#define | FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk |
#define | FDCAN_NDAT1_ND8_Pos (8U) |
#define | FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) |
#define | FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk |
#define | FDCAN_NDAT1_ND9_Pos (9U) |
#define | FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) |
#define | FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk |
#define | FDCAN_NDAT1_ND10_Pos (10U) |
#define | FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) |
#define | FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk |
#define | FDCAN_NDAT1_ND11_Pos (11U) |
#define | FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) |
#define | FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk |
#define | FDCAN_NDAT1_ND12_Pos (12U) |
#define | FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) |
#define | FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk |
#define | FDCAN_NDAT1_ND13_Pos (13U) |
#define | FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) |
#define | FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk |
#define | FDCAN_NDAT1_ND14_Pos (14U) |
#define | FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) |
#define | FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk |
#define | FDCAN_NDAT1_ND15_Pos (15U) |
#define | FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) |
#define | FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk |
#define | FDCAN_NDAT1_ND16_Pos (16U) |
#define | FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) |
#define | FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk |
#define | FDCAN_NDAT1_ND17_Pos (17U) |
#define | FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) |
#define | FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk |
#define | FDCAN_NDAT1_ND18_Pos (18U) |
#define | FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) |
#define | FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk |
#define | FDCAN_NDAT1_ND19_Pos (19U) |
#define | FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) |
#define | FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk |
#define | FDCAN_NDAT1_ND20_Pos (20U) |
#define | FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) |
#define | FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk |
#define | FDCAN_NDAT1_ND21_Pos (21U) |
#define | FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) |
#define | FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk |
#define | FDCAN_NDAT1_ND22_Pos (22U) |
#define | FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) |
#define | FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk |
#define | FDCAN_NDAT1_ND23_Pos (23U) |
#define | FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) |
#define | FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk |
#define | FDCAN_NDAT1_ND24_Pos (24U) |
#define | FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) |
#define | FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk |
#define | FDCAN_NDAT1_ND25_Pos (25U) |
#define | FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) |
#define | FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk |
#define | FDCAN_NDAT1_ND26_Pos (26U) |
#define | FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) |
#define | FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk |
#define | FDCAN_NDAT1_ND27_Pos (27U) |
#define | FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) |
#define | FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk |
#define | FDCAN_NDAT1_ND28_Pos (28U) |
#define | FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) |
#define | FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk |
#define | FDCAN_NDAT1_ND29_Pos (29U) |
#define | FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) |
#define | FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk |
#define | FDCAN_NDAT1_ND30_Pos (30U) |
#define | FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) |
#define | FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk |
#define | FDCAN_NDAT1_ND31_Pos (31U) |
#define | FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) |
#define | FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk |
#define | FDCAN_NDAT2_ND32_Pos (0U) |
#define | FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) |
#define | FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk |
#define | FDCAN_NDAT2_ND33_Pos (1U) |
#define | FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) |
#define | FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk |
#define | FDCAN_NDAT2_ND34_Pos (2U) |
#define | FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) |
#define | FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk |
#define | FDCAN_NDAT2_ND35_Pos (3U) |
#define | FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) |
#define | FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk |
#define | FDCAN_NDAT2_ND36_Pos (4U) |
#define | FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) |
#define | FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk |
#define | FDCAN_NDAT2_ND37_Pos (5U) |
#define | FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) |
#define | FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk |
#define | FDCAN_NDAT2_ND38_Pos (6U) |
#define | FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) |
#define | FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk |
#define | FDCAN_NDAT2_ND39_Pos (7U) |
#define | FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) |
#define | FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk |
#define | FDCAN_NDAT2_ND40_Pos (8U) |
#define | FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) |
#define | FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk |
#define | FDCAN_NDAT2_ND41_Pos (9U) |
#define | FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) |
#define | FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk |
#define | FDCAN_NDAT2_ND42_Pos (10U) |
#define | FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) |
#define | FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk |
#define | FDCAN_NDAT2_ND43_Pos (11U) |
#define | FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) |
#define | FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk |
#define | FDCAN_NDAT2_ND44_Pos (12U) |
#define | FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) |
#define | FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk |
#define | FDCAN_NDAT2_ND45_Pos (13U) |
#define | FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) |
#define | FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk |
#define | FDCAN_NDAT2_ND46_Pos (14U) |
#define | FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) |
#define | FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk |
#define | FDCAN_NDAT2_ND47_Pos (15U) |
#define | FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) |
#define | FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk |
#define | FDCAN_NDAT2_ND48_Pos (16U) |
#define | FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) |
#define | FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk |
#define | FDCAN_NDAT2_ND49_Pos (17U) |
#define | FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) |
#define | FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk |
#define | FDCAN_NDAT2_ND50_Pos (18U) |
#define | FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) |
#define | FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk |
#define | FDCAN_NDAT2_ND51_Pos (19U) |
#define | FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) |
#define | FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk |
#define | FDCAN_NDAT2_ND52_Pos (20U) |
#define | FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) |
#define | FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk |
#define | FDCAN_NDAT2_ND53_Pos (21U) |
#define | FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) |
#define | FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk |
#define | FDCAN_NDAT2_ND54_Pos (22U) |
#define | FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) |
#define | FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk |
#define | FDCAN_NDAT2_ND55_Pos (23U) |
#define | FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) |
#define | FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk |
#define | FDCAN_NDAT2_ND56_Pos (24U) |
#define | FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) |
#define | FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk |
#define | FDCAN_NDAT2_ND57_Pos (25U) |
#define | FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) |
#define | FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk |
#define | FDCAN_NDAT2_ND58_Pos (26U) |
#define | FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) |
#define | FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk |
#define | FDCAN_NDAT2_ND59_Pos (27U) |
#define | FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) |
#define | FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk |
#define | FDCAN_NDAT2_ND60_Pos (28U) |
#define | FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) |
#define | FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk |
#define | FDCAN_NDAT2_ND61_Pos (29U) |
#define | FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) |
#define | FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk |
#define | FDCAN_NDAT2_ND62_Pos (30U) |
#define | FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) |
#define | FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk |
#define | FDCAN_NDAT2_ND63_Pos (31U) |
#define | FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) |
#define | FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk |
#define | FDCAN_RXF0C_F0SA_Pos (2U) |
#define | FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) |
#define | FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk |
#define | FDCAN_RXF0C_F0S_Pos (16U) |
#define | FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) |
#define | FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk |
#define | FDCAN_RXF0C_F0WM_Pos (24U) |
#define | FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) |
#define | FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk |
#define | FDCAN_RXF0C_F0OM_Pos (31U) |
#define | FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) |
#define | FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk |
#define | FDCAN_RXF0S_F0FL_Pos (0U) |
#define | FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) |
#define | FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk |
#define | FDCAN_RXF0S_F0GI_Pos (8U) |
#define | FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) |
#define | FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk |
#define | FDCAN_RXF0S_F0PI_Pos (16U) |
#define | FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) |
#define | FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk |
#define | FDCAN_RXF0S_F0F_Pos (24U) |
#define | FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) |
#define | FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk |
#define | FDCAN_RXF0S_RF0L_Pos (25U) |
#define | FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) |
#define | FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk |
#define | FDCAN_RXF0A_F0AI_Pos (0U) |
#define | FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) |
#define | FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk |
#define | FDCAN_RXBC_RBSA_Pos (2U) |
#define | FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) |
#define | FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk |
#define | FDCAN_RXF1C_F1SA_Pos (2U) |
#define | FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) |
#define | FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk |
#define | FDCAN_RXF1C_F1S_Pos (16U) |
#define | FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) |
#define | FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk |
#define | FDCAN_RXF1C_F1WM_Pos (24U) |
#define | FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) |
#define | FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk |
#define | FDCAN_RXF1C_F1OM_Pos (31U) |
#define | FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) |
#define | FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk |
#define | FDCAN_RXF1S_F1FL_Pos (0U) |
#define | FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) |
#define | FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk |
#define | FDCAN_RXF1S_F1GI_Pos (8U) |
#define | FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) |
#define | FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk |
#define | FDCAN_RXF1S_F1PI_Pos (16U) |
#define | FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) |
#define | FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk |
#define | FDCAN_RXF1S_F1F_Pos (24U) |
#define | FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) |
#define | FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk |
#define | FDCAN_RXF1S_RF1L_Pos (25U) |
#define | FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) |
#define | FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk |
#define | FDCAN_RXF1A_F1AI_Pos (0U) |
#define | FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) |
#define | FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk |
#define | FDCAN_RXESC_F0DS_Pos (0U) |
#define | FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) |
#define | FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk |
#define | FDCAN_RXESC_F1DS_Pos (4U) |
#define | FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) |
#define | FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk |
#define | FDCAN_RXESC_RBDS_Pos (8U) |
#define | FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) |
#define | FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk |
#define | FDCAN_TXBC_TBSA_Pos (2U) |
#define | FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) |
#define | FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk |
#define | FDCAN_TXBC_NDTB_Pos (16U) |
#define | FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) |
#define | FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk |
#define | FDCAN_TXBC_TFQS_Pos (24U) |
#define | FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) |
#define | FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk |
#define | FDCAN_TXBC_TFQM_Pos (30U) |
#define | FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) |
#define | FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk |
#define | FDCAN_TXFQS_TFFL_Pos (0U) |
#define | FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) |
#define | FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk |
#define | FDCAN_TXFQS_TFGI_Pos (8U) |
#define | FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) |
#define | FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk |
#define | FDCAN_TXFQS_TFQPI_Pos (16U) |
#define | FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) |
#define | FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk |
#define | FDCAN_TXFQS_TFQF_Pos (21U) |
#define | FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) |
#define | FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk |
#define | FDCAN_TXESC_TBDS_Pos (0U) |
#define | FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) |
#define | FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk |
#define | FDCAN_TXBRP_TRP_Pos (0U) |
#define | FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) |
#define | FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk |
#define | FDCAN_TXBAR_AR_Pos (0U) |
#define | FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) |
#define | FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk |
#define | FDCAN_TXBCR_CR_Pos (0U) |
#define | FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) |
#define | FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk |
#define | FDCAN_TXBTO_TO_Pos (0U) |
#define | FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) |
#define | FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk |
#define | FDCAN_TXBCF_CF_Pos (0U) |
#define | FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) |
#define | FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk |
#define | FDCAN_TXBTIE_TIE_Pos (0U) |
#define | FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) |
#define | FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk |
#define | FDCAN_TXBCIE_CFIE_Pos (0U) |
#define | FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) |
#define | FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk |
#define | FDCAN_TXEFC_EFSA_Pos (2U) |
#define | FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) |
#define | FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk |
#define | FDCAN_TXEFC_EFS_Pos (16U) |
#define | FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) |
#define | FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk |
#define | FDCAN_TXEFC_EFWM_Pos (24U) |
#define | FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) |
#define | FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk |
#define | FDCAN_TXEFS_EFFL_Pos (0U) |
#define | FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) |
#define | FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk |
#define | FDCAN_TXEFS_EFGI_Pos (8U) |
#define | FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) |
#define | FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk |
#define | FDCAN_TXEFS_EFPI_Pos (16U) |
#define | FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) |
#define | FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk |
#define | FDCAN_TXEFS_EFF_Pos (24U) |
#define | FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) |
#define | FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk |
#define | FDCAN_TXEFS_TEFL_Pos (25U) |
#define | FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) |
#define | FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk |
#define | FDCAN_TXEFA_EFAI_Pos (0U) |
#define | FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) |
#define | FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk |
#define | FDCAN_TTTMC_TMSA_Pos (2U) |
#define | FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) |
#define | FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk |
#define | FDCAN_TTTMC_TME_Pos (16U) |
#define | FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) |
#define | FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk |
#define | FDCAN_TTRMC_RID_Pos (0U) |
#define | FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) |
#define | FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk |
#define | FDCAN_TTRMC_XTD_Pos (30U) |
#define | FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) |
#define | FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk |
#define | FDCAN_TTRMC_RMPS_Pos (31U) |
#define | FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) |
#define | FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk |
#define | FDCAN_TTOCF_OM_Pos (0U) |
#define | FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) |
#define | FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk |
#define | FDCAN_TTOCF_GEN_Pos (3U) |
#define | FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) |
#define | FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk |
#define | FDCAN_TTOCF_TM_Pos (4U) |
#define | FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) |
#define | FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk |
#define | FDCAN_TTOCF_LDSDL_Pos (5U) |
#define | FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) |
#define | FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk |
#define | FDCAN_TTOCF_IRTO_Pos (8U) |
#define | FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) |
#define | FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk |
#define | FDCAN_TTOCF_EECS_Pos (15U) |
#define | FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) |
#define | FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk |
#define | FDCAN_TTOCF_AWL_Pos (16U) |
#define | FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) |
#define | FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk |
#define | FDCAN_TTOCF_EGTF_Pos (24U) |
#define | FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) |
#define | FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk |
#define | FDCAN_TTOCF_ECC_Pos (25U) |
#define | FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) |
#define | FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk |
#define | FDCAN_TTOCF_EVTP_Pos (26U) |
#define | FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) |
#define | FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk |
#define | FDCAN_TTMLM_CCM_Pos (0U) |
#define | FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) |
#define | FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk |
#define | FDCAN_TTMLM_CSS_Pos (6U) |
#define | FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) |
#define | FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk |
#define | FDCAN_TTMLM_TXEW_Pos (8U) |
#define | FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) |
#define | FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk |
#define | FDCAN_TTMLM_ENTT_Pos (16U) |
#define | FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) |
#define | FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk |
#define | FDCAN_TURCF_NCL_Pos (0U) |
#define | FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) |
#define | FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk |
#define | FDCAN_TURCF_DC_Pos (16U) |
#define | FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) |
#define | FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk |
#define | FDCAN_TURCF_ELT_Pos (31U) |
#define | FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) |
#define | FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk |
#define | FDCAN_TTOCN_SGT_Pos (0U) |
#define | FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) |
#define | FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk |
#define | FDCAN_TTOCN_ECS_Pos (1U) |
#define | FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) |
#define | FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk |
#define | FDCAN_TTOCN_SWP_Pos (2U) |
#define | FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) |
#define | FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk |
#define | FDCAN_TTOCN_SWS_Pos (3U) |
#define | FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) |
#define | FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk |
#define | FDCAN_TTOCN_RTIE_Pos (5U) |
#define | FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) |
#define | FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk |
#define | FDCAN_TTOCN_TMC_Pos (6U) |
#define | FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) |
#define | FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk |
#define | FDCAN_TTOCN_TTIE_Pos (8U) |
#define | FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) |
#define | FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk |
#define | FDCAN_TTOCN_GCS_Pos (9U) |
#define | FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) |
#define | FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk |
#define | FDCAN_TTOCN_FGP_Pos (10U) |
#define | FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) |
#define | FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk |
#define | FDCAN_TTOCN_TMG_Pos (11U) |
#define | FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) |
#define | FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk |
#define | FDCAN_TTOCN_NIG_Pos (12U) |
#define | FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) |
#define | FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk |
#define | FDCAN_TTOCN_ESCN_Pos (13U) |
#define | FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) |
#define | FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk |
#define | FDCAN_TTOCN_LCKC_Pos (15U) |
#define | FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) |
#define | FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk |
#define | FDCAN_TTGTP_TP_Pos (0U) |
#define | FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) |
#define | FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk |
#define | FDCAN_TTGTP_CTP_Pos (16U) |
#define | FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) |
#define | FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk |
#define | FDCAN_TTTMK_TM_Pos (0U) |
#define | FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) |
#define | FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk |
#define | FDCAN_TTTMK_TICC_Pos (16U) |
#define | FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) |
#define | FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk |
#define | FDCAN_TTTMK_LCKM_Pos (31U) |
#define | FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) |
#define | FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk |
#define | FDCAN_TTIR_SBC_Pos (0U) |
#define | FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) |
#define | FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk |
#define | FDCAN_TTIR_SMC_Pos (1U) |
#define | FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) |
#define | FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk |
#define | FDCAN_TTIR_CSM_Pos (2U) |
#define | FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) |
#define | FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk |
#define | FDCAN_TTIR_SOG_Pos (3U) |
#define | FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) |
#define | FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk |
#define | FDCAN_TTIR_RTMI_Pos (4U) |
#define | FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) |
#define | FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk |
#define | FDCAN_TTIR_TTMI_Pos (5U) |
#define | FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) |
#define | FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk |
#define | FDCAN_TTIR_SWE_Pos (6U) |
#define | FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) |
#define | FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk |
#define | FDCAN_TTIR_GTW_Pos (7U) |
#define | FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) |
#define | FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk |
#define | FDCAN_TTIR_GTD_Pos (8U) |
#define | FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) |
#define | FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk |
#define | FDCAN_TTIR_GTE_Pos (9U) |
#define | FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) |
#define | FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk |
#define | FDCAN_TTIR_TXU_Pos (10U) |
#define | FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) |
#define | FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk |
#define | FDCAN_TTIR_TXO_Pos (11U) |
#define | FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) |
#define | FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk |
#define | FDCAN_TTIR_SE1_Pos (12U) |
#define | FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) |
#define | FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk |
#define | FDCAN_TTIR_SE2_Pos (13U) |
#define | FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) |
#define | FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk |
#define | FDCAN_TTIR_ELC_Pos (14U) |
#define | FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) |
#define | FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk |
#define | FDCAN_TTIR_IWT_Pos (15U) |
#define | FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) |
#define | FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk |
#define | FDCAN_TTIR_WT_Pos (16U) |
#define | FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) |
#define | FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk |
#define | FDCAN_TTIR_AW_Pos (17U) |
#define | FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) |
#define | FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk |
#define | FDCAN_TTIR_CER_Pos (18U) |
#define | FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) |
#define | FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk |
#define | FDCAN_TTIE_SBCE_Pos (0U) |
#define | FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) |
#define | FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk |
#define | FDCAN_TTIE_SMCE_Pos (1U) |
#define | FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) |
#define | FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk |
#define | FDCAN_TTIE_CSME_Pos (2U) |
#define | FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) |
#define | FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk |
#define | FDCAN_TTIE_SOGE_Pos (3U) |
#define | FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) |
#define | FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk |
#define | FDCAN_TTIE_RTMIE_Pos (4U) |
#define | FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) |
#define | FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk |
#define | FDCAN_TTIE_TTMIE_Pos (5U) |
#define | FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) |
#define | FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk |
#define | FDCAN_TTIE_SWEE_Pos (6U) |
#define | FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) |
#define | FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk |
#define | FDCAN_TTIE_GTWE_Pos (7U) |
#define | FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) |
#define | FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk |
#define | FDCAN_TTIE_GTDE_Pos (8U) |
#define | FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) |
#define | FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk |
#define | FDCAN_TTIE_GTEE_Pos (9U) |
#define | FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) |
#define | FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk |
#define | FDCAN_TTIE_TXUE_Pos (10U) |
#define | FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) |
#define | FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk |
#define | FDCAN_TTIE_TXOE_Pos (11U) |
#define | FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) |
#define | FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk |
#define | FDCAN_TTIE_SE1E_Pos (12U) |
#define | FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) |
#define | FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk |
#define | FDCAN_TTIE_SE2E_Pos (13U) |
#define | FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) |
#define | FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk |
#define | FDCAN_TTIE_ELCE_Pos (14U) |
#define | FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) |
#define | FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk |
#define | FDCAN_TTIE_IWTE_Pos (15U) |
#define | FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) |
#define | FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk |
#define | FDCAN_TTIE_WTE_Pos (16U) |
#define | FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) |
#define | FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk |
#define | FDCAN_TTIE_AWE_Pos (17U) |
#define | FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) |
#define | FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk |
#define | FDCAN_TTIE_CERE_Pos (18U) |
#define | FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) |
#define | FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk |
#define | FDCAN_TTILS_SBCS_Pos (0U) |
#define | FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) |
#define | FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk |
#define | FDCAN_TTILS_SMCS_Pos (1U) |
#define | FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) |
#define | FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk |
#define | FDCAN_TTILS_CSMS_Pos (2U) |
#define | FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) |
#define | FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk |
#define | FDCAN_TTILS_SOGS_Pos (3U) |
#define | FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) |
#define | FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk |
#define | FDCAN_TTILS_RTMIS_Pos (4U) |
#define | FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) |
#define | FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk |
#define | FDCAN_TTILS_TTMIS_Pos (5U) |
#define | FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) |
#define | FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk |
#define | FDCAN_TTILS_SWES_Pos (6U) |
#define | FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) |
#define | FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk |
#define | FDCAN_TTILS_GTWS_Pos (7U) |
#define | FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) |
#define | FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk |
#define | FDCAN_TTILS_GTDS_Pos (8U) |
#define | FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) |
#define | FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk |
#define | FDCAN_TTILS_GTES_Pos (9U) |
#define | FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) |
#define | FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk |
#define | FDCAN_TTILS_TXUS_Pos (10U) |
#define | FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) |
#define | FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk |
#define | FDCAN_TTILS_TXOS_Pos (11U) |
#define | FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) |
#define | FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk |
#define | FDCAN_TTILS_SE1S_Pos (12U) |
#define | FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) |
#define | FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk |
#define | FDCAN_TTILS_SE2S_Pos (13U) |
#define | FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) |
#define | FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk |
#define | FDCAN_TTILS_ELCS_Pos (14U) |
#define | FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) |
#define | FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk |
#define | FDCAN_TTILS_IWTS_Pos (15U) |
#define | FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) |
#define | FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk |
#define | FDCAN_TTILS_WTS_Pos (16U) |
#define | FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) |
#define | FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk |
#define | FDCAN_TTILS_AWS_Pos (17U) |
#define | FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) |
#define | FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk |
#define | FDCAN_TTILS_CERS_Pos (18U) |
#define | FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) |
#define | FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk |
#define | FDCAN_TTOST_EL_Pos (0U) |
#define | FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) |
#define | FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk |
#define | FDCAN_TTOST_MS_Pos (2U) |
#define | FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) |
#define | FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk |
#define | FDCAN_TTOST_SYS_Pos (4U) |
#define | FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) |
#define | FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk |
#define | FDCAN_TTOST_QGTP_Pos (6U) |
#define | FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) |
#define | FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk |
#define | FDCAN_TTOST_QCS_Pos (7U) |
#define | FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) |
#define | FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk |
#define | FDCAN_TTOST_RTO_Pos (8U) |
#define | FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) |
#define | FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk |
#define | FDCAN_TTOST_WGTD_Pos (22U) |
#define | FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) |
#define | FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk |
#define | FDCAN_TTOST_GFI_Pos (23U) |
#define | FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) |
#define | FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk |
#define | FDCAN_TTOST_TMP_Pos (24U) |
#define | FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) |
#define | FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk |
#define | FDCAN_TTOST_GSI_Pos (27U) |
#define | FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) |
#define | FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk |
#define | FDCAN_TTOST_WFE_Pos (28U) |
#define | FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) |
#define | FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk |
#define | FDCAN_TTOST_AWE_Pos (29U) |
#define | FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) |
#define | FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk |
#define | FDCAN_TTOST_WECS_Pos (30U) |
#define | FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) |
#define | FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk |
#define | FDCAN_TTOST_SPL_Pos (31U) |
#define | FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) |
#define | FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk |
#define | FDCAN_TURNA_NAV_Pos (0U) |
#define | FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) |
#define | FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk |
#define | FDCAN_TTLGT_LT_Pos (0U) |
#define | FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) |
#define | FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk |
#define | FDCAN_TTLGT_GT_Pos (16U) |
#define | FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) |
#define | FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk |
#define | FDCAN_TTCTC_CT_Pos (0U) |
#define | FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) |
#define | FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk |
#define | FDCAN_TTCTC_CC_Pos (16U) |
#define | FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) |
#define | FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk |
#define | FDCAN_TTCPT_CCV_Pos (0U) |
#define | FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) |
#define | FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk |
#define | FDCAN_TTCPT_SWV_Pos (16U) |
#define | FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) |
#define | FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk |
#define | FDCAN_TTCSM_CSM_Pos (0U) |
#define | FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) |
#define | FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk |
#define | FDCAN_TTTS_SWTSEL_Pos (0U) |
#define | FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) |
#define | FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk |
#define | FDCAN_TTTS_EVTSEL_Pos (4U) |
#define | FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) |
#define | FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk |
#define | FDCANCCU_CREL_DAY_Pos (0U) |
#define | FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) |
#define | FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk |
#define | FDCANCCU_CREL_MON_Pos (8U) |
#define | FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) |
#define | FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk |
#define | FDCANCCU_CREL_YEAR_Pos (16U) |
#define | FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) |
#define | FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk |
#define | FDCANCCU_CREL_SUBSTEP_Pos (20U) |
#define | FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) |
#define | FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk |
#define | FDCANCCU_CREL_STEP_Pos (24U) |
#define | FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) |
#define | FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk |
#define | FDCANCCU_CREL_REL_Pos (28U) |
#define | FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) |
#define | FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk |
#define | FDCANCCU_CCFG_TQBT_Pos (0U) |
#define | FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) |
#define | FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk |
#define | FDCANCCU_CCFG_BCC_Pos (6U) |
#define | FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) |
#define | FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk |
#define | FDCANCCU_CCFG_CFL_Pos (7U) |
#define | FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) |
#define | FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk |
#define | FDCANCCU_CCFG_OCPM_Pos (8U) |
#define | FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) |
#define | FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk |
#define | FDCANCCU_CCFG_CDIV_Pos (16U) |
#define | FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) |
#define | FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk |
#define | FDCANCCU_CCFG_SWR_Pos (31U) |
#define | FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) |
#define | FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk |
#define | FDCANCCU_CSTAT_OCPC_Pos (0U) |
#define | FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) |
#define | FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk |
#define | FDCANCCU_CSTAT_TQC_Pos (18U) |
#define | FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) |
#define | FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk |
#define | FDCANCCU_CSTAT_CALS_Pos (30U) |
#define | FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) |
#define | FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk |
#define | FDCANCCU_CWD_WDC_Pos (0U) |
#define | FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) |
#define | FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk |
#define | FDCANCCU_CWD_WDV_Pos (16U) |
#define | FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) |
#define | FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk |
#define | FDCANCCU_IR_CWE_Pos (0U) |
#define | FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) |
#define | FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk |
#define | FDCANCCU_IR_CSC_Pos (1U) |
#define | FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) |
#define | FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk |
#define | FDCANCCU_IE_CWEE_Pos (0U) |
#define | FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) |
#define | FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk |
#define | FDCANCCU_IE_CSCE_Pos (1U) |
#define | FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) |
#define | FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk |
#define | CEC_CR_CECEN_Pos (0U) |
#define | CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) |
#define | CEC_CR_CECEN CEC_CR_CECEN_Msk |
#define | CEC_CR_TXSOM_Pos (1U) |
#define | CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) |
#define | CEC_CR_TXSOM CEC_CR_TXSOM_Msk |
#define | CEC_CR_TXEOM_Pos (2U) |
#define | CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) |
#define | CEC_CR_TXEOM CEC_CR_TXEOM_Msk |
#define | CEC_CFGR_SFT_Pos (0U) |
#define | CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) |
#define | CEC_CFGR_SFT CEC_CFGR_SFT_Msk |
#define | CEC_CFGR_RXTOL_Pos (3U) |
#define | CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) |
#define | CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk |
#define | CEC_CFGR_BRESTP_Pos (4U) |
#define | CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) |
#define | CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk |
#define | CEC_CFGR_BREGEN_Pos (5U) |
#define | CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) |
#define | CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk |
#define | CEC_CFGR_LBPEGEN_Pos (6U) |
#define | CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) |
#define | CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk |
#define | CEC_CFGR_SFTOPT_Pos (8U) |
#define | CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) |
#define | CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk |
#define | CEC_CFGR_BRDNOGEN_Pos (7U) |
#define | CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) |
#define | CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk |
#define | CEC_CFGR_OAR_Pos (16U) |
#define | CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) |
#define | CEC_CFGR_OAR CEC_CFGR_OAR_Msk |
#define | CEC_CFGR_LSTN_Pos (31U) |
#define | CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) |
#define | CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk |
#define | CEC_TXDR_TXD_Pos (0U) |
#define | CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) |
#define | CEC_TXDR_TXD CEC_TXDR_TXD_Msk |
#define | CEC_RXDR_RXD_Pos (0U) |
#define | CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) |
#define | CEC_RXDR_RXD CEC_RXDR_RXD_Msk |
#define | CEC_ISR_RXBR_Pos (0U) |
#define | CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) |
#define | CEC_ISR_RXBR CEC_ISR_RXBR_Msk |
#define | CEC_ISR_RXEND_Pos (1U) |
#define | CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) |
#define | CEC_ISR_RXEND CEC_ISR_RXEND_Msk |
#define | CEC_ISR_RXOVR_Pos (2U) |
#define | CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) |
#define | CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk |
#define | CEC_ISR_BRE_Pos (3U) |
#define | CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) |
#define | CEC_ISR_BRE CEC_ISR_BRE_Msk |
#define | CEC_ISR_SBPE_Pos (4U) |
#define | CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) |
#define | CEC_ISR_SBPE CEC_ISR_SBPE_Msk |
#define | CEC_ISR_LBPE_Pos (5U) |
#define | CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) |
#define | CEC_ISR_LBPE CEC_ISR_LBPE_Msk |
#define | CEC_ISR_RXACKE_Pos (6U) |
#define | CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) |
#define | CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk |
#define | CEC_ISR_ARBLST_Pos (7U) |
#define | CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) |
#define | CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk |
#define | CEC_ISR_TXBR_Pos (8U) |
#define | CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) |
#define | CEC_ISR_TXBR CEC_ISR_TXBR_Msk |
#define | CEC_ISR_TXEND_Pos (9U) |
#define | CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) |
#define | CEC_ISR_TXEND CEC_ISR_TXEND_Msk |
#define | CEC_ISR_TXUDR_Pos (10U) |
#define | CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) |
#define | CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk |
#define | CEC_ISR_TXERR_Pos (11U) |
#define | CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) |
#define | CEC_ISR_TXERR CEC_ISR_TXERR_Msk |
#define | CEC_ISR_TXACKE_Pos (12U) |
#define | CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) |
#define | CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk |
#define | CEC_IER_RXBRIE_Pos (0U) |
#define | CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) |
#define | CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk |
#define | CEC_IER_RXENDIE_Pos (1U) |
#define | CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) |
#define | CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk |
#define | CEC_IER_RXOVRIE_Pos (2U) |
#define | CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) |
#define | CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk |
#define | CEC_IER_BREIE_Pos (3U) |
#define | CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) |
#define | CEC_IER_BREIE CEC_IER_BREIE_Msk |
#define | CEC_IER_SBPEIE_Pos (4U) |
#define | CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) |
#define | CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk |
#define | CEC_IER_LBPEIE_Pos (5U) |
#define | CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) |
#define | CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk |
#define | CEC_IER_RXACKEIE_Pos (6U) |
#define | CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) |
#define | CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk |
#define | CEC_IER_ARBLSTIE_Pos (7U) |
#define | CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) |
#define | CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk |
#define | CEC_IER_TXBRIE_Pos (8U) |
#define | CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) |
#define | CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk |
#define | CEC_IER_TXENDIE_Pos (9U) |
#define | CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) |
#define | CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk |
#define | CEC_IER_TXUDRIE_Pos (10U) |
#define | CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) |
#define | CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk |
#define | CEC_IER_TXERRIE_Pos (11U) |
#define | CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) |
#define | CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk |
#define | CEC_IER_TXACKEIE_Pos (12U) |
#define | CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) |
#define | CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk |
#define | CRC_DR_DR_Pos (0U) |
#define | CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) |
#define | CRC_DR_DR CRC_DR_DR_Msk |
#define | CRC_IDR_IDR_Pos (0U) |
#define | CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) |
#define | CRC_IDR_IDR CRC_IDR_IDR_Msk |
#define | CRC_CR_RESET_Pos (0U) |
#define | CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) |
#define | CRC_CR_RESET CRC_CR_RESET_Msk |
#define | CRC_CR_POLYSIZE_Pos (3U) |
#define | CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) |
#define | CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk |
#define | CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) |
#define | CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) |
#define | CRC_CR_REV_IN_Pos (5U) |
#define | CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) |
#define | CRC_CR_REV_IN CRC_CR_REV_IN_Msk |
#define | CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) |
#define | CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) |
#define | CRC_CR_REV_OUT_Pos (7U) |
#define | CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) |
#define | CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk |
#define | CRC_INIT_INIT_Pos (0U) |
#define | CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) |
#define | CRC_INIT_INIT CRC_INIT_INIT_Msk |
#define | CRC_POL_POL_Pos (0U) |
#define | CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) |
#define | CRC_POL_POL CRC_POL_POL_Msk |
#define | CRS_CR_SYNCOKIE_Pos (0U) |
#define | CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) |
#define | CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk |
#define | CRS_CR_SYNCWARNIE_Pos (1U) |
#define | CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) |
#define | CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk |
#define | CRS_CR_ERRIE_Pos (2U) |
#define | CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) |
#define | CRS_CR_ERRIE CRS_CR_ERRIE_Msk |
#define | CRS_CR_ESYNCIE_Pos (3U) |
#define | CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) |
#define | CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk |
#define | CRS_CR_CEN_Pos (5U) |
#define | CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) |
#define | CRS_CR_CEN CRS_CR_CEN_Msk |
#define | CRS_CR_AUTOTRIMEN_Pos (6U) |
#define | CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) |
#define | CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk |
#define | CRS_CR_SWSYNC_Pos (7U) |
#define | CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) |
#define | CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk |
#define | CRS_CR_TRIM_Pos (8U) |
#define | CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) |
#define | CRS_CR_TRIM CRS_CR_TRIM_Msk |
#define | CRS_CFGR_RELOAD_Pos (0U) |
#define | CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) |
#define | CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk |
#define | CRS_CFGR_FELIM_Pos (16U) |
#define | CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) |
#define | CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk |
#define | CRS_CFGR_SYNCDIV_Pos (24U) |
#define | CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) |
#define | CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk |
#define | CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) |
#define | CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) |
#define | CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) |
#define | CRS_CFGR_SYNCSRC_Pos (28U) |
#define | CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) |
#define | CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk |
#define | CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) |
#define | CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) |
#define | CRS_CFGR_SYNCPOL_Pos (31U) |
#define | CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) |
#define | CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk |
#define | CRS_ISR_SYNCOKF_Pos (0U) |
#define | CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) |
#define | CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk |
#define | CRS_ISR_SYNCWARNF_Pos (1U) |
#define | CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) |
#define | CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk |
#define | CRS_ISR_ERRF_Pos (2U) |
#define | CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) |
#define | CRS_ISR_ERRF CRS_ISR_ERRF_Msk |
#define | CRS_ISR_ESYNCF_Pos (3U) |
#define | CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) |
#define | CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk |
#define | CRS_ISR_SYNCERR_Pos (8U) |
#define | CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) |
#define | CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk |
#define | CRS_ISR_SYNCMISS_Pos (9U) |
#define | CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) |
#define | CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk |
#define | CRS_ISR_TRIMOVF_Pos (10U) |
#define | CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) |
#define | CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk |
#define | CRS_ISR_FEDIR_Pos (15U) |
#define | CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) |
#define | CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk |
#define | CRS_ISR_FECAP_Pos (16U) |
#define | CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) |
#define | CRS_ISR_FECAP CRS_ISR_FECAP_Msk |
#define | CRS_ICR_SYNCOKC_Pos (0U) |
#define | CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) |
#define | CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk |
#define | CRS_ICR_SYNCWARNC_Pos (1U) |
#define | CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) |
#define | CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk |
#define | CRS_ICR_ERRC_Pos (2U) |
#define | CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) |
#define | CRS_ICR_ERRC CRS_ICR_ERRC_Msk |
#define | CRS_ICR_ESYNCC_Pos (3U) |
#define | CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) |
#define | CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk |
#define | DAC_CR_EN1_Pos (0U) |
#define | DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) |
#define | DAC_CR_EN1 DAC_CR_EN1_Msk |
#define | DAC_CR_TEN1_Pos (1U) |
#define | DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) |
#define | DAC_CR_TEN1 DAC_CR_TEN1_Msk |
#define | DAC_CR_TSEL1_Pos (2U) |
#define | DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) |
#define | DAC_CR_TSEL1 DAC_CR_TSEL1_Msk |
#define | DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) |
#define | DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) |
#define | DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) |
#define | DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) |
#define | DAC_CR_WAVE1_Pos (6U) |
#define | DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) |
#define | DAC_CR_WAVE1 DAC_CR_WAVE1_Msk |
#define | DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) |
#define | DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) |
#define | DAC_CR_MAMP1_Pos (8U) |
#define | DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) |
#define | DAC_CR_MAMP1 DAC_CR_MAMP1_Msk |
#define | DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) |
#define | DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) |
#define | DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) |
#define | DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) |
#define | DAC_CR_DMAEN1_Pos (12U) |
#define | DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) |
#define | DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk |
#define | DAC_CR_DMAUDRIE1_Pos (13U) |
#define | DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) |
#define | DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk |
#define | DAC_CR_CEN1_Pos (14U) |
#define | DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) |
#define | DAC_CR_CEN1 DAC_CR_CEN1_Msk |
#define | DAC_CR_EN2_Pos (16U) |
#define | DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) |
#define | DAC_CR_EN2 DAC_CR_EN2_Msk |
#define | DAC_CR_TEN2_Pos (17U) |
#define | DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) |
#define | DAC_CR_TEN2 DAC_CR_TEN2_Msk |
#define | DAC_CR_TSEL2_Pos (18U) |
#define | DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) |
#define | DAC_CR_TSEL2 DAC_CR_TSEL2_Msk |
#define | DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) |
#define | DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) |
#define | DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) |
#define | DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) |
#define | DAC_CR_WAVE2_Pos (22U) |
#define | DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) |
#define | DAC_CR_WAVE2 DAC_CR_WAVE2_Msk |
#define | DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) |
#define | DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) |
#define | DAC_CR_MAMP2_Pos (24U) |
#define | DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) |
#define | DAC_CR_MAMP2 DAC_CR_MAMP2_Msk |
#define | DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) |
#define | DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) |
#define | DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) |
#define | DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) |
#define | DAC_CR_DMAEN2_Pos (28U) |
#define | DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) |
#define | DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk |
#define | DAC_CR_DMAUDRIE2_Pos (29U) |
#define | DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) |
#define | DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk |
#define | DAC_CR_CEN2_Pos (30U) |
#define | DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) |
#define | DAC_CR_CEN2 DAC_CR_CEN2_Msk |
#define | DAC_SWTRIGR_SWTRIG1_Pos (0U) |
#define | DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) |
#define | DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk |
#define | DAC_SWTRIGR_SWTRIG2_Pos (1U) |
#define | DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) |
#define | DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk |
#define | DAC_DHR12R1_DACC1DHR_Pos (0U) |
#define | DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) |
#define | DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk |
#define | DAC_DHR12L1_DACC1DHR_Pos (4U) |
#define | DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) |
#define | DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk |
#define | DAC_DHR8R1_DACC1DHR_Pos (0U) |
#define | DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) |
#define | DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk |
#define | DAC_DHR12R2_DACC2DHR_Pos (0U) |
#define | DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) |
#define | DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk |
#define | DAC_DHR12L2_DACC2DHR_Pos (4U) |
#define | DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) |
#define | DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk |
#define | DAC_DHR8R2_DACC2DHR_Pos (0U) |
#define | DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) |
#define | DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk |
#define | DAC_DHR12RD_DACC1DHR_Pos (0U) |
#define | DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) |
#define | DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk |
#define | DAC_DHR12RD_DACC2DHR_Pos (16U) |
#define | DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) |
#define | DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk |
#define | DAC_DHR12LD_DACC1DHR_Pos (4U) |
#define | DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) |
#define | DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk |
#define | DAC_DHR12LD_DACC2DHR_Pos (20U) |
#define | DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) |
#define | DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk |
#define | DAC_DHR8RD_DACC1DHR_Pos (0U) |
#define | DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) |
#define | DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk |
#define | DAC_DHR8RD_DACC2DHR_Pos (8U) |
#define | DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) |
#define | DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk |
#define | DAC_DOR1_DACC1DOR_Pos (0U) |
#define | DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) |
#define | DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk |
#define | DAC_DOR2_DACC2DOR_Pos (0U) |
#define | DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) |
#define | DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk |
#define | DAC_SR_DMAUDR1_Pos (13U) |
#define | DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) |
#define | DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk |
#define | DAC_SR_CAL_FLAG1_Pos (14U) |
#define | DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) |
#define | DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk |
#define | DAC_SR_BWST1_Pos (15U) |
#define | DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) |
#define | DAC_SR_BWST1 DAC_SR_BWST1_Msk |
#define | DAC_SR_DMAUDR2_Pos (29U) |
#define | DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) |
#define | DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk |
#define | DAC_SR_CAL_FLAG2_Pos (30U) |
#define | DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) |
#define | DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk |
#define | DAC_SR_BWST2_Pos (31U) |
#define | DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) |
#define | DAC_SR_BWST2 DAC_SR_BWST2_Msk |
#define | DAC_CCR_OTRIM1_Pos (0U) |
#define | DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) |
#define | DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk |
#define | DAC_CCR_OTRIM2_Pos (16U) |
#define | DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) |
#define | DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk |
#define | DAC_MCR_MODE1_Pos (0U) |
#define | DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) |
#define | DAC_MCR_MODE1 DAC_MCR_MODE1_Msk |
#define | DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) |
#define | DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) |
#define | DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) |
#define | DAC_MCR_MODE2_Pos (16U) |
#define | DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) |
#define | DAC_MCR_MODE2 DAC_MCR_MODE2_Msk |
#define | DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) |
#define | DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) |
#define | DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) |
#define | DAC_SHSR1_TSAMPLE1_Pos (0U) |
#define | DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) |
#define | DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk |
#define | DAC_SHSR2_TSAMPLE2_Pos (0U) |
#define | DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) |
#define | DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk |
#define | DAC_SHHR_THOLD1_Pos (0U) |
#define | DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) |
#define | DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk |
#define | DAC_SHHR_THOLD2_Pos (16U) |
#define | DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) |
#define | DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk |
#define | DAC_SHRR_TREFRESH1_Pos (0U) |
#define | DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) |
#define | DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk |
#define | DAC_SHRR_TREFRESH2_Pos (16U) |
#define | DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) |
#define | DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk |
#define | DCMI_CR_CAPTURE_Pos (0U) |
#define | DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) |
#define | DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk |
#define | DCMI_CR_CM_Pos (1U) |
#define | DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) |
#define | DCMI_CR_CM DCMI_CR_CM_Msk |
#define | DCMI_CR_CROP_Pos (2U) |
#define | DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) |
#define | DCMI_CR_CROP DCMI_CR_CROP_Msk |
#define | DCMI_CR_JPEG_Pos (3U) |
#define | DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) |
#define | DCMI_CR_JPEG DCMI_CR_JPEG_Msk |
#define | DCMI_CR_ESS_Pos (4U) |
#define | DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) |
#define | DCMI_CR_ESS DCMI_CR_ESS_Msk |
#define | DCMI_CR_PCKPOL_Pos (5U) |
#define | DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) |
#define | DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk |
#define | DCMI_CR_HSPOL_Pos (6U) |
#define | DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) |
#define | DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk |
#define | DCMI_CR_VSPOL_Pos (7U) |
#define | DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) |
#define | DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk |
#define | DCMI_CR_FCRC_0 (0x00000100U) |
#define | DCMI_CR_FCRC_1 (0x00000200U) |
#define | DCMI_CR_EDM_0 (0x00000400U) |
#define | DCMI_CR_EDM_1 (0x00000800U) |
#define | DCMI_CR_CRE_Pos (12U) |
#define | DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) |
#define | DCMI_CR_CRE DCMI_CR_CRE_Msk |
#define | DCMI_CR_ENABLE_Pos (14U) |
#define | DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) |
#define | DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk |
#define | DCMI_CR_BSM_Pos (16U) |
#define | DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) |
#define | DCMI_CR_BSM DCMI_CR_BSM_Msk |
#define | DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) |
#define | DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) |
#define | DCMI_CR_OEBS_Pos (18U) |
#define | DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) |
#define | DCMI_CR_OEBS DCMI_CR_OEBS_Msk |
#define | DCMI_CR_LSM_Pos (19U) |
#define | DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) |
#define | DCMI_CR_LSM DCMI_CR_LSM_Msk |
#define | DCMI_CR_OELS_Pos (20U) |
#define | DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) |
#define | DCMI_CR_OELS DCMI_CR_OELS_Msk |
#define | DCMI_SR_HSYNC_Pos (0U) |
#define | DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) |
#define | DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk |
#define | DCMI_SR_VSYNC_Pos (1U) |
#define | DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) |
#define | DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk |
#define | DCMI_SR_FNE_Pos (2U) |
#define | DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) |
#define | DCMI_SR_FNE DCMI_SR_FNE_Msk |
#define | DCMI_RIS_FRAME_RIS_Pos (0U) |
#define | DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) |
#define | DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk |
#define | DCMI_RIS_OVR_RIS_Pos (1U) |
#define | DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) |
#define | DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk |
#define | DCMI_RIS_ERR_RIS_Pos (2U) |
#define | DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) |
#define | DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk |
#define | DCMI_RIS_VSYNC_RIS_Pos (3U) |
#define | DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) |
#define | DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk |
#define | DCMI_RIS_LINE_RIS_Pos (4U) |
#define | DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) |
#define | DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk |
#define | DCMI_IER_FRAME_IE_Pos (0U) |
#define | DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) |
#define | DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk |
#define | DCMI_IER_OVR_IE_Pos (1U) |
#define | DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) |
#define | DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk |
#define | DCMI_IER_ERR_IE_Pos (2U) |
#define | DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) |
#define | DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk |
#define | DCMI_IER_VSYNC_IE_Pos (3U) |
#define | DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) |
#define | DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk |
#define | DCMI_IER_LINE_IE_Pos (4U) |
#define | DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) |
#define | DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk |
#define | DCMI_MIS_FRAME_MIS_Pos (0U) |
#define | DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) |
#define | DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk |
#define | DCMI_MIS_OVR_MIS_Pos (1U) |
#define | DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) |
#define | DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk |
#define | DCMI_MIS_ERR_MIS_Pos (2U) |
#define | DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) |
#define | DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk |
#define | DCMI_MIS_VSYNC_MIS_Pos (3U) |
#define | DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) |
#define | DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk |
#define | DCMI_MIS_LINE_MIS_Pos (4U) |
#define | DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) |
#define | DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk |
#define | DCMI_ICR_FRAME_ISC_Pos (0U) |
#define | DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) |
#define | DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk |
#define | DCMI_ICR_OVR_ISC_Pos (1U) |
#define | DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) |
#define | DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk |
#define | DCMI_ICR_ERR_ISC_Pos (2U) |
#define | DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) |
#define | DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk |
#define | DCMI_ICR_VSYNC_ISC_Pos (3U) |
#define | DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) |
#define | DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk |
#define | DCMI_ICR_LINE_ISC_Pos (4U) |
#define | DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) |
#define | DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk |
#define | DCMI_ESCR_FSC_Pos (0U) |
#define | DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) |
#define | DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk |
#define | DCMI_ESCR_LSC_Pos (8U) |
#define | DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) |
#define | DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk |
#define | DCMI_ESCR_LEC_Pos (16U) |
#define | DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) |
#define | DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk |
#define | DCMI_ESCR_FEC_Pos (24U) |
#define | DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) |
#define | DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk |
#define | DCMI_ESUR_FSU_Pos (0U) |
#define | DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) |
#define | DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk |
#define | DCMI_ESUR_LSU_Pos (8U) |
#define | DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) |
#define | DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk |
#define | DCMI_ESUR_LEU_Pos (16U) |
#define | DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) |
#define | DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk |
#define | DCMI_ESUR_FEU_Pos (24U) |
#define | DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) |
#define | DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk |
#define | DCMI_CWSTRT_HOFFCNT_Pos (0U) |
#define | DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) |
#define | DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk |
#define | DCMI_CWSTRT_VST_Pos (16U) |
#define | DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) |
#define | DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk |
#define | DCMI_CWSIZE_CAPCNT_Pos (0U) |
#define | DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) |
#define | DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk |
#define | DCMI_CWSIZE_VLINE_Pos (16U) |
#define | DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) |
#define | DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk |
#define | DCMI_DR_BYTE0_Pos (0U) |
#define | DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) |
#define | DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk |
#define | DCMI_DR_BYTE1_Pos (8U) |
#define | DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) |
#define | DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk |
#define | DCMI_DR_BYTE2_Pos (16U) |
#define | DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) |
#define | DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk |
#define | DCMI_DR_BYTE3_Pos (24U) |
#define | DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) |
#define | DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk |
#define | DFSDM_CHCFGR1_DFSDMEN_Pos (31U) |
#define | DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) |
#define | DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk |
#define | DFSDM_CHCFGR1_CKOUTSRC_Pos (30U) |
#define | DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) |
#define | DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk |
#define | DFSDM_CHCFGR1_CKOUTDIV_Pos (16U) |
#define | DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) |
#define | DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk |
#define | DFSDM_CHCFGR1_DATPACK_Pos (14U) |
#define | DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) |
#define | DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk |
#define | DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) |
#define | DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) |
#define | DFSDM_CHCFGR1_DATMPX_Pos (12U) |
#define | DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) |
#define | DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk |
#define | DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) |
#define | DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) |
#define | DFSDM_CHCFGR1_CHINSEL_Pos (8U) |
#define | DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) |
#define | DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk |
#define | DFSDM_CHCFGR1_CHEN_Pos (7U) |
#define | DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) |
#define | DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk |
#define | DFSDM_CHCFGR1_CKABEN_Pos (6U) |
#define | DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) |
#define | DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk |
#define | DFSDM_CHCFGR1_SCDEN_Pos (5U) |
#define | DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) |
#define | DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk |
#define | DFSDM_CHCFGR1_SPICKSEL_Pos (2U) |
#define | DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) |
#define | DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk |
#define | DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) |
#define | DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) |
#define | DFSDM_CHCFGR1_SITP_Pos (0U) |
#define | DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) |
#define | DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk |
#define | DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) |
#define | DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) |
#define | DFSDM_CHCFGR2_OFFSET_Pos (8U) |
#define | DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) |
#define | DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk |
#define | DFSDM_CHCFGR2_DTRBS_Pos (3U) |
#define | DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) |
#define | DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk |
#define | DFSDM_CHAWSCDR_AWFORD_Pos (22U) |
#define | DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) |
#define | DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk |
#define | DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) |
#define | DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) |
#define | DFSDM_CHAWSCDR_AWFOSR_Pos (16U) |
#define | DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) |
#define | DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk |
#define | DFSDM_CHAWSCDR_BKSCD_Pos (12U) |
#define | DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) |
#define | DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk |
#define | DFSDM_CHAWSCDR_SCDT_Pos (0U) |
#define | DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) |
#define | DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk |
#define | DFSDM_CHWDATR_WDATA_Pos (0U) |
#define | DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) |
#define | DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk |
#define | DFSDM_CHDATINR_INDAT0_Pos (0U) |
#define | DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) |
#define | DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk |
#define | DFSDM_CHDATINR_INDAT1_Pos (16U) |
#define | DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) |
#define | DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk |
#define | DFSDM_FLTCR1_AWFSEL_Pos (30U) |
#define | DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) |
#define | DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk |
#define | DFSDM_FLTCR1_FAST_Pos (29U) |
#define | DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) |
#define | DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk |
#define | DFSDM_FLTCR1_RCH_Pos (24U) |
#define | DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) |
#define | DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk |
#define | DFSDM_FLTCR1_RDMAEN_Pos (21U) |
#define | DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) |
#define | DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk |
#define | DFSDM_FLTCR1_RSYNC_Pos (19U) |
#define | DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) |
#define | DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk |
#define | DFSDM_FLTCR1_RCONT_Pos (18U) |
#define | DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) |
#define | DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk |
#define | DFSDM_FLTCR1_RSWSTART_Pos (17U) |
#define | DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) |
#define | DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk |
#define | DFSDM_FLTCR1_JEXTEN_Pos (13U) |
#define | DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) |
#define | DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk |
#define | DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) |
#define | DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) |
#define | DFSDM_FLTCR1_JEXTSEL_Pos (8U) |
#define | DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) |
#define | DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk |
#define | DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) |
#define | DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) |
#define | DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) |
#define | DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) |
#define | DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) |
#define | DFSDM_FLTCR1_JDMAEN_Pos (5U) |
#define | DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) |
#define | DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk |
#define | DFSDM_FLTCR1_JSCAN_Pos (4U) |
#define | DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) |
#define | DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk |
#define | DFSDM_FLTCR1_JSYNC_Pos (3U) |
#define | DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) |
#define | DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk |
#define | DFSDM_FLTCR1_JSWSTART_Pos (1U) |
#define | DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) |
#define | DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk |
#define | DFSDM_FLTCR1_DFEN_Pos (0U) |
#define | DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) |
#define | DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk |
#define | DFSDM_FLTCR2_AWDCH_Pos (16U) |
#define | DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) |
#define | DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk |
#define | DFSDM_FLTCR2_EXCH_Pos (8U) |
#define | DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) |
#define | DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk |
#define | DFSDM_FLTCR2_CKABIE_Pos (6U) |
#define | DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) |
#define | DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk |
#define | DFSDM_FLTCR2_SCDIE_Pos (5U) |
#define | DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) |
#define | DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk |
#define | DFSDM_FLTCR2_AWDIE_Pos (4U) |
#define | DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) |
#define | DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk |
#define | DFSDM_FLTCR2_ROVRIE_Pos (3U) |
#define | DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) |
#define | DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk |
#define | DFSDM_FLTCR2_JOVRIE_Pos (2U) |
#define | DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) |
#define | DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk |
#define | DFSDM_FLTCR2_REOCIE_Pos (1U) |
#define | DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) |
#define | DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk |
#define | DFSDM_FLTCR2_JEOCIE_Pos (0U) |
#define | DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) |
#define | DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk |
#define | DFSDM_FLTISR_SCDF_Pos (24U) |
#define | DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) |
#define | DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk |
#define | DFSDM_FLTISR_CKABF_Pos (16U) |
#define | DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) |
#define | DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk |
#define | DFSDM_FLTISR_RCIP_Pos (14U) |
#define | DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) |
#define | DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk |
#define | DFSDM_FLTISR_JCIP_Pos (13U) |
#define | DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) |
#define | DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk |
#define | DFSDM_FLTISR_AWDF_Pos (4U) |
#define | DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) |
#define | DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk |
#define | DFSDM_FLTISR_ROVRF_Pos (3U) |
#define | DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) |
#define | DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk |
#define | DFSDM_FLTISR_JOVRF_Pos (2U) |
#define | DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) |
#define | DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk |
#define | DFSDM_FLTISR_REOCF_Pos (1U) |
#define | DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) |
#define | DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk |
#define | DFSDM_FLTISR_JEOCF_Pos (0U) |
#define | DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) |
#define | DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk |
#define | DFSDM_FLTICR_CLRSCDF_Pos (24U) |
#define | DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) |
#define | DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk |
#define | DFSDM_FLTICR_CLRCKABF_Pos (16U) |
#define | DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) |
#define | DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk |
#define | DFSDM_FLTICR_CLRROVRF_Pos (3U) |
#define | DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) |
#define | DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk |
#define | DFSDM_FLTICR_CLRJOVRF_Pos (2U) |
#define | DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) |
#define | DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk |
#define | DFSDM_FLTJCHGR_JCHG_Pos (0U) |
#define | DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) |
#define | DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk |
#define | DFSDM_FLTFCR_FORD_Pos (29U) |
#define | DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) |
#define | DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk |
#define | DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) |
#define | DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) |
#define | DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) |
#define | DFSDM_FLTFCR_FOSR_Pos (16U) |
#define | DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) |
#define | DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk |
#define | DFSDM_FLTFCR_IOSR_Pos (0U) |
#define | DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) |
#define | DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk |
#define | DFSDM_FLTJDATAR_JDATA_Pos (8U) |
#define | DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) |
#define | DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk |
#define | DFSDM_FLTJDATAR_JDATACH_Pos (0U) |
#define | DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) |
#define | DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk |
#define | DFSDM_FLTRDATAR_RDATA_Pos (8U) |
#define | DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) |
#define | DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk |
#define | DFSDM_FLTRDATAR_RPEND_Pos (4U) |
#define | DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) |
#define | DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk |
#define | DFSDM_FLTRDATAR_RDATACH_Pos (0U) |
#define | DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) |
#define | DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk |
#define | DFSDM_FLTAWHTR_AWHT_Pos (8U) |
#define | DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) |
#define | DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk |
#define | DFSDM_FLTAWHTR_BKAWH_Pos (0U) |
#define | DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) |
#define | DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk |
#define | DFSDM_FLTAWLTR_AWLT_Pos (8U) |
#define | DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) |
#define | DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk |
#define | DFSDM_FLTAWLTR_BKAWL_Pos (0U) |
#define | DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) |
#define | DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk |
#define | DFSDM_FLTAWSR_AWHTF_Pos (8U) |
#define | DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) |
#define | DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk |
#define | DFSDM_FLTAWSR_AWLTF_Pos (0U) |
#define | DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) |
#define | DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk |
#define | DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U) |
#define | DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) |
#define | DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk |
#define | DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U) |
#define | DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) |
#define | DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk |
#define | DFSDM_FLTEXMAX_EXMAX_Pos (8U) |
#define | DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) |
#define | DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk |
#define | DFSDM_FLTEXMAX_EXMAXCH_Pos (0U) |
#define | DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) |
#define | DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk |
#define | DFSDM_FLTEXMIN_EXMIN_Pos (8U) |
#define | DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) |
#define | DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk |
#define | DFSDM_FLTEXMIN_EXMINCH_Pos (0U) |
#define | DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) |
#define | DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk |
#define | DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U) |
#define | DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) |
#define | DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk |
#define | BDMA_ISR_GIF0_Pos (0U) |
#define | BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) |
#define | BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk |
#define | BDMA_ISR_TCIF0_Pos (1U) |
#define | BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) |
#define | BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk |
#define | BDMA_ISR_HTIF0_Pos (2U) |
#define | BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) |
#define | BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk |
#define | BDMA_ISR_TEIF0_Pos (3U) |
#define | BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) |
#define | BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk |
#define | BDMA_ISR_GIF1_Pos (4U) |
#define | BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) |
#define | BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk |
#define | BDMA_ISR_TCIF1_Pos (5U) |
#define | BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) |
#define | BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk |
#define | BDMA_ISR_HTIF1_Pos (6U) |
#define | BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) |
#define | BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk |
#define | BDMA_ISR_TEIF1_Pos (7U) |
#define | BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) |
#define | BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk |
#define | BDMA_ISR_GIF2_Pos (8U) |
#define | BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) |
#define | BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk |
#define | BDMA_ISR_TCIF2_Pos (9U) |
#define | BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) |
#define | BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk |
#define | BDMA_ISR_HTIF2_Pos (10U) |
#define | BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) |
#define | BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk |
#define | BDMA_ISR_TEIF2_Pos (11U) |
#define | BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) |
#define | BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk |
#define | BDMA_ISR_GIF3_Pos (12U) |
#define | BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) |
#define | BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk |
#define | BDMA_ISR_TCIF3_Pos (13U) |
#define | BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) |
#define | BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk |
#define | BDMA_ISR_HTIF3_Pos (14U) |
#define | BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) |
#define | BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk |
#define | BDMA_ISR_TEIF3_Pos (15U) |
#define | BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) |
#define | BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk |
#define | BDMA_ISR_GIF4_Pos (16U) |
#define | BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) |
#define | BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk |
#define | BDMA_ISR_TCIF4_Pos (17U) |
#define | BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) |
#define | BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk |
#define | BDMA_ISR_HTIF4_Pos (18U) |
#define | BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) |
#define | BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk |
#define | BDMA_ISR_TEIF4_Pos (19U) |
#define | BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) |
#define | BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk |
#define | BDMA_ISR_GIF5_Pos (20U) |
#define | BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) |
#define | BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk |
#define | BDMA_ISR_TCIF5_Pos (21U) |
#define | BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) |
#define | BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk |
#define | BDMA_ISR_HTIF5_Pos (22U) |
#define | BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) |
#define | BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk |
#define | BDMA_ISR_TEIF5_Pos (23U) |
#define | BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) |
#define | BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk |
#define | BDMA_ISR_GIF6_Pos (24U) |
#define | BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) |
#define | BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk |
#define | BDMA_ISR_TCIF6_Pos (25U) |
#define | BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) |
#define | BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk |
#define | BDMA_ISR_HTIF6_Pos (26U) |
#define | BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) |
#define | BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk |
#define | BDMA_ISR_TEIF6_Pos (27U) |
#define | BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) |
#define | BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk |
#define | BDMA_ISR_GIF7_Pos (28U) |
#define | BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) |
#define | BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk |
#define | BDMA_ISR_TCIF7_Pos (29U) |
#define | BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) |
#define | BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk |
#define | BDMA_ISR_HTIF7_Pos (30U) |
#define | BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) |
#define | BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk |
#define | BDMA_ISR_TEIF7_Pos (31U) |
#define | BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) |
#define | BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk |
#define | BDMA_IFCR_CGIF0_Pos (0U) |
#define | BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) |
#define | BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk |
#define | BDMA_IFCR_CTCIF0_Pos (1U) |
#define | BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) |
#define | BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk |
#define | BDMA_IFCR_CHTIF0_Pos (2U) |
#define | BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) |
#define | BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk |
#define | BDMA_IFCR_CTEIF0_Pos (3U) |
#define | BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) |
#define | BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk |
#define | BDMA_IFCR_CGIF1_Pos (4U) |
#define | BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) |
#define | BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk |
#define | BDMA_IFCR_CTCIF1_Pos (5U) |
#define | BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) |
#define | BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk |
#define | BDMA_IFCR_CHTIF1_Pos (6U) |
#define | BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) |
#define | BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk |
#define | BDMA_IFCR_CTEIF1_Pos (7U) |
#define | BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) |
#define | BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk |
#define | BDMA_IFCR_CGIF2_Pos (8U) |
#define | BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) |
#define | BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk |
#define | BDMA_IFCR_CTCIF2_Pos (9U) |
#define | BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) |
#define | BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk |
#define | BDMA_IFCR_CHTIF2_Pos (10U) |
#define | BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) |
#define | BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk |
#define | BDMA_IFCR_CTEIF2_Pos (11U) |
#define | BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) |
#define | BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk |
#define | BDMA_IFCR_CGIF3_Pos (12U) |
#define | BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) |
#define | BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk |
#define | BDMA_IFCR_CTCIF3_Pos (13U) |
#define | BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) |
#define | BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk |
#define | BDMA_IFCR_CHTIF3_Pos (14U) |
#define | BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) |
#define | BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk |
#define | BDMA_IFCR_CTEIF3_Pos (15U) |
#define | BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) |
#define | BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk |
#define | BDMA_IFCR_CGIF4_Pos (16U) |
#define | BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) |
#define | BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk |
#define | BDMA_IFCR_CTCIF4_Pos (17U) |
#define | BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) |
#define | BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk |
#define | BDMA_IFCR_CHTIF4_Pos (18U) |
#define | BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) |
#define | BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk |
#define | BDMA_IFCR_CTEIF4_Pos (19U) |
#define | BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) |
#define | BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk |
#define | BDMA_IFCR_CGIF5_Pos (20U) |
#define | BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) |
#define | BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk |
#define | BDMA_IFCR_CTCIF5_Pos (21U) |
#define | BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) |
#define | BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk |
#define | BDMA_IFCR_CHTIF5_Pos (22U) |
#define | BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) |
#define | BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk |
#define | BDMA_IFCR_CTEIF5_Pos (23U) |
#define | BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) |
#define | BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk |
#define | BDMA_IFCR_CGIF6_Pos (24U) |
#define | BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) |
#define | BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk |
#define | BDMA_IFCR_CTCIF6_Pos (25U) |
#define | BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) |
#define | BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk |
#define | BDMA_IFCR_CHTIF6_Pos (26U) |
#define | BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) |
#define | BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk |
#define | BDMA_IFCR_CTEIF6_Pos (27U) |
#define | BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) |
#define | BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk |
#define | BDMA_IFCR_CGIF7_Pos (28U) |
#define | BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) |
#define | BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk |
#define | BDMA_IFCR_CTCIF7_Pos (29U) |
#define | BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) |
#define | BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk |
#define | BDMA_IFCR_CHTIF7_Pos (30U) |
#define | BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) |
#define | BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk |
#define | BDMA_IFCR_CTEIF7_Pos (31U) |
#define | BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) |
#define | BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk |
#define | BDMA_CCR_EN_Pos (0U) |
#define | BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) |
#define | BDMA_CCR_EN BDMA_CCR_EN_Msk |
#define | BDMA_CCR_TCIE_Pos (1U) |
#define | BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) |
#define | BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk |
#define | BDMA_CCR_HTIE_Pos (2U) |
#define | BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) |
#define | BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk |
#define | BDMA_CCR_TEIE_Pos (3U) |
#define | BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) |
#define | BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk |
#define | BDMA_CCR_DIR_Pos (4U) |
#define | BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) |
#define | BDMA_CCR_DIR BDMA_CCR_DIR_Msk |
#define | BDMA_CCR_CIRC_Pos (5U) |
#define | BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) |
#define | BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk |
#define | BDMA_CCR_PINC_Pos (6U) |
#define | BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) |
#define | BDMA_CCR_PINC BDMA_CCR_PINC_Msk |
#define | BDMA_CCR_MINC_Pos (7U) |
#define | BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) |
#define | BDMA_CCR_MINC BDMA_CCR_MINC_Msk |
#define | BDMA_CCR_PSIZE_Pos (8U) |
#define | BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) |
#define | BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk |
#define | BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) |
#define | BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) |
#define | BDMA_CCR_MSIZE_Pos (10U) |
#define | BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) |
#define | BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk |
#define | BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) |
#define | BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) |
#define | BDMA_CCR_PL_Pos (12U) |
#define | BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) |
#define | BDMA_CCR_PL BDMA_CCR_PL_Msk |
#define | BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) |
#define | BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) |
#define | BDMA_CCR_MEM2MEM_Pos (14U) |
#define | BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) |
#define | BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk |
#define | BDMA_CCR_DBM_Pos (15U) |
#define | BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) |
#define | BDMA_CCR_DBM BDMA_CCR_DBM_Msk |
#define | BDMA_CCR_CT_Pos (16U) |
#define | BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) |
#define | BDMA_CCR_CT BDMA_CCR_CT_Msk |
#define | BDMA_CNDTR_NDT_Pos (0U) |
#define | BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) |
#define | BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk |
#define | BDMA_CPAR_PA_Pos (0U) |
#define | BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) |
#define | BDMA_CPAR_PA BDMA_CPAR_PA_Msk |
#define | BDMA_CM0AR_MA_Pos (0U) |
#define | BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) |
#define | BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk |
#define | BDMA_CM1AR_MA_Pos (0U) |
#define | BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) |
#define | BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk |
#define | ETH_MACCR_ARP_Pos (31U) |
#define | ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) |
#define | ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */ |
#define | ETH_MACCR_SARC_Pos (28U) |
#define | ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) |
#define | ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ |
#define | ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ |
#define | ETH_MACCR_SARC_INSADDR0_Pos (29U) |
#define | ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) |
#define | ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ |
#define | ETH_MACCR_SARC_INSADDR1_Pos (29U) |
#define | ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) |
#define | ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */ |
#define | ETH_MACCR_SARC_REPADDR0_Pos (28U) |
#define | ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) |
#define | ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */ |
#define | ETH_MACCR_SARC_REPADDR1_Pos (28U) |
#define | ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) |
#define | ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */ |
#define | ETH_MACCR_IPC_Pos (27U) |
#define | ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) |
#define | ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */ |
#define | ETH_MACCR_IPG_Pos (24U) |
#define | ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) |
#define | ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ |
#define | ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ |
#define | ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ |
#define | ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ |
#define | ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ |
#define | ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ |
#define | ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ |
#define | ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ |
#define | ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ |
#define | ETH_MACCR_GPSLCE_Pos (23U) |
#define | ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) |
#define | ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ |
#define | ETH_MACCR_S2KP_Pos (22U) |
#define | ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) |
#define | ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */ |
#define | ETH_MACCR_CST_Pos (21U) |
#define | ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) |
#define | ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */ |
#define | ETH_MACCR_ACS_Pos (20U) |
#define | ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) |
#define | ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */ |
#define | ETH_MACCR_WD_Pos (19U) |
#define | ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) |
#define | ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */ |
#define | ETH_MACCR_JD_Pos (17U) |
#define | ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) |
#define | ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */ |
#define | ETH_MACCR_JE_Pos (16U) |
#define | ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) |
#define | ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */ |
#define | ETH_MACCR_FES_Pos (14U) |
#define | ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) |
#define | ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */ |
#define | ETH_MACCR_DM_Pos (13U) |
#define | ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) |
#define | ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */ |
#define | ETH_MACCR_LM_Pos (12U) |
#define | ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) |
#define | ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */ |
#define | ETH_MACCR_ECRSFD_Pos (11U) |
#define | ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) |
#define | ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */ |
#define | ETH_MACCR_DO_Pos (10U) |
#define | ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) |
#define | ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */ |
#define | ETH_MACCR_DCRS_Pos (9U) |
#define | ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) |
#define | ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */ |
#define | ETH_MACCR_DR_Pos (8U) |
#define | ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) |
#define | ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */ |
#define | ETH_MACCR_BL_Pos (5U) |
#define | ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) |
#define | ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */ |
#define | ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) |
#define | ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) |
#define | ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) |
#define | ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) |
#define | ETH_MACCR_DC_Pos (4U) |
#define | ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) |
#define | ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */ |
#define | ETH_MACCR_PRELEN_Pos (2U) |
#define | ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) |
#define | ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */ |
#define | ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) |
#define | ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) |
#define | ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) |
#define | ETH_MACCR_TE_Pos (1U) |
#define | ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) |
#define | ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */ |
#define | ETH_MACCR_RE_Pos (0U) |
#define | ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) |
#define | ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */ |
#define | ETH_MACECR_EIPG_Pos (25U) |
#define | ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) |
#define | ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */ |
#define | ETH_MACECR_EIPGEN_Pos (24U) |
#define | ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) |
#define | ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */ |
#define | ETH_MACECR_USP_Pos (18U) |
#define | ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) |
#define | ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */ |
#define | ETH_MACECR_SPEN_Pos (17U) |
#define | ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) |
#define | ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */ |
#define | ETH_MACECR_DCRCC_Pos (16U) |
#define | ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) |
#define | ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */ |
#define | ETH_MACECR_GPSL_Pos (0U) |
#define | ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) |
#define | ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */ |
#define | ETH_MACPFR_RA_Pos (31U) |
#define | ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) |
#define | ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */ |
#define | ETH_MACPFR_DNTU_Pos (21U) |
#define | ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) |
#define | ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */ |
#define | ETH_MACPFR_IPFE_Pos (20U) |
#define | ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) |
#define | ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */ |
#define | ETH_MACPFR_VTFE_Pos (16U) |
#define | ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) |
#define | ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */ |
#define | ETH_MACPFR_HPF_Pos (10U) |
#define | ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) |
#define | ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */ |
#define | ETH_MACPFR_SAF_Pos (9U) |
#define | ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) |
#define | ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */ |
#define | ETH_MACPFR_SAIF_Pos (8U) |
#define | ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) |
#define | ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */ |
#define | ETH_MACPFR_PCF_Pos (6U) |
#define | ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) |
#define | ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ |
#define | ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ |
#define | ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) |
#define | ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) |
#define | ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ |
#define | ETH_MACPFR_PCF_FORWARDALL_Pos (7U) |
#define | ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) |
#define | ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */ |
#define | ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U) |
#define | ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) |
#define | ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */ |
#define | ETH_MACPFR_DBF_Pos (5U) |
#define | ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) |
#define | ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */ |
#define | ETH_MACPFR_PM_Pos (4U) |
#define | ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) |
#define | ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */ |
#define | ETH_MACPFR_DAIF_Pos (3U) |
#define | ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) |
#define | ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */ |
#define | ETH_MACPFR_HMC_Pos (2U) |
#define | ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) |
#define | ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */ |
#define | ETH_MACPFR_HUC_Pos (1U) |
#define | ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) |
#define | ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */ |
#define | ETH_MACPFR_PR_Pos (0U) |
#define | ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) |
#define | ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */ |
#define | ETH_MACWTR_PWE_Pos (8U) |
#define | ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) |
#define | ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */ |
#define | ETH_MACWTR_WTO_Pos (0U) |
#define | ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) |
#define | ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ |
#define | ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ |
#define | ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ |
#define | ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ |
#define | ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ |
#define | ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ |
#define | ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ |
#define | ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ |
#define | ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ |
#define | ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ |
#define | ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ |
#define | ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ |
#define | ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ |
#define | ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ |
#define | ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ |
#define | ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ |
#define | ETH_MACHTHR_HTH_Pos (0U) |
#define | ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) |
#define | ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */ |
#define | ETH_MACHTLR_HTL_Pos (0U) |
#define | ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) |
#define | ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */ |
#define | ETH_MACVTR_EIVLRXS_Pos (31U) |
#define | ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) |
#define | ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */ |
#define | ETH_MACVTR_EIVLS_Pos (28U) |
#define | ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) |
#define | ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ |
#define | ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ |
#define | ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) |
#define | ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) |
#define | ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ |
#define | ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) |
#define | ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) |
#define | ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ |
#define | ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) |
#define | ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) |
#define | ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ |
#define | ETH_MACVTR_ERIVLT_Pos (27U) |
#define | ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) |
#define | ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */ |
#define | ETH_MACVTR_EDVLP_Pos (26U) |
#define | ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) |
#define | ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */ |
#define | ETH_MACVTR_VTHM_Pos (25U) |
#define | ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) |
#define | ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */ |
#define | ETH_MACVTR_EVLRXS_Pos (24U) |
#define | ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) |
#define | ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */ |
#define | ETH_MACVTR_EVLS_Pos (21U) |
#define | ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) |
#define | ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ |
#define | ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ |
#define | ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) |
#define | ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) |
#define | ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ |
#define | ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) |
#define | ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) |
#define | ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ |
#define | ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) |
#define | ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) |
#define | ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ |
#define | ETH_MACVTR_DOVLTC_Pos (20U) |
#define | ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) |
#define | ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */ |
#define | ETH_MACVTR_ERSVLM_Pos (19U) |
#define | ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) |
#define | ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */ |
#define | ETH_MACVTR_ESVL_Pos (18U) |
#define | ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) |
#define | ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */ |
#define | ETH_MACVTR_VTIM_Pos (17U) |
#define | ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) |
#define | ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */ |
#define | ETH_MACVTR_ETV_Pos (16U) |
#define | ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) |
#define | ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */ |
#define | ETH_MACVTR_VL_Pos (0U) |
#define | ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) |
#define | ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */ |
#define | ETH_MACVTR_VL_UP_Pos (13U) |
#define | ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) |
#define | ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */ |
#define | ETH_MACVTR_VL_CFIDEI_Pos (12U) |
#define | ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) |
#define | ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */ |
#define | ETH_MACVTR_VL_VID_Pos (0U) |
#define | ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) |
#define | ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */ |
#define | ETH_MACVHTR_VLHT_Pos (0U) |
#define | ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) |
#define | ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */ |
#define | ETH_MACVIR_VLTI_Pos (20U) |
#define | ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) |
#define | ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */ |
#define | ETH_MACVIR_CSVL_Pos (19U) |
#define | ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) |
#define | ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */ |
#define | ETH_MACVIR_VLP_Pos (18U) |
#define | ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) |
#define | ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */ |
#define | ETH_MACVIR_VLC_Pos (16U) |
#define | ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) |
#define | ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ |
#define | ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ |
#define | ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) |
#define | ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) |
#define | ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ |
#define | ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) |
#define | ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) |
#define | ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ |
#define | ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) |
#define | ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) |
#define | ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ |
#define | ETH_MACVIR_VLT_Pos (0U) |
#define | ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) |
#define | ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */ |
#define | ETH_MACVIR_VLT_UP_Pos (13U) |
#define | ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) |
#define | ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */ |
#define | ETH_MACVIR_VLT_CFIDEI_Pos (12U) |
#define | ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) |
#define | ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */ |
#define | ETH_MACVIR_VLT_VID_Pos (0U) |
#define | ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) |
#define | ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */ |
#define | ETH_MACIVIR_VLTI_Pos (20U) |
#define | ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) |
#define | ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */ |
#define | ETH_MACIVIR_CSVL_Pos (19U) |
#define | ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) |
#define | ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */ |
#define | ETH_MACIVIR_VLP_Pos (18U) |
#define | ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) |
#define | ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */ |
#define | ETH_MACIVIR_VLC_Pos (16U) |
#define | ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) |
#define | ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ |
#define | ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ |
#define | ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) |
#define | ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) |
#define | ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ |
#define | ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U) |
#define | ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) |
#define | ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ |
#define | ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U) |
#define | ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) |
#define | ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ |
#define | ETH_MACIVIR_VLT_Pos (0U) |
#define | ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) |
#define | ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */ |
#define | ETH_MACIVIR_VLT_UP_Pos (13U) |
#define | ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) |
#define | ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */ |
#define | ETH_MACIVIR_VLT_CFIDEI_Pos (12U) |
#define | ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) |
#define | ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */ |
#define | ETH_MACIVIR_VLT_VID_Pos (0U) |
#define | ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) |
#define | ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */ |
#define | ETH_MACTFCR_PT_Pos (16U) |
#define | ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) |
#define | ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */ |
#define | ETH_MACTFCR_DZPQ_Pos (7U) |
#define | ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) |
#define | ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */ |
#define | ETH_MACTFCR_PLT_Pos (4U) |
#define | ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) |
#define | ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ |
#define | ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ |
#define | ETH_MACTFCR_PLT_MINUS28_Pos (4U) |
#define | ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) |
#define | ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ |
#define | ETH_MACTFCR_PLT_MINUS36_Pos (5U) |
#define | ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) |
#define | ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */ |
#define | ETH_MACTFCR_PLT_MINUS144_Pos (4U) |
#define | ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) |
#define | ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */ |
#define | ETH_MACTFCR_PLT_MINUS256_Pos (6U) |
#define | ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) |
#define | ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */ |
#define | ETH_MACTFCR_PLT_MINUS512_Pos (4U) |
#define | ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) |
#define | ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */ |
#define | ETH_MACTFCR_TFE_Pos (1U) |
#define | ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) |
#define | ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */ |
#define | ETH_MACTFCR_FCB_Pos (0U) |
#define | ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) |
#define | ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */ |
#define | ETH_MACRFCR_UP_Pos (1U) |
#define | ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) |
#define | ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */ |
#define | ETH_MACRFCR_RFE_Pos (0U) |
#define | ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) |
#define | ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */ |
#define | ETH_MACISR_RXSTSIS_Pos (14U) |
#define | ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) |
#define | ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */ |
#define | ETH_MACISR_TXSTSIS_Pos (13U) |
#define | ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) |
#define | ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */ |
#define | ETH_MACISR_TSIS_Pos (12U) |
#define | ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) |
#define | ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */ |
#define | ETH_MACISR_MMCTXIS_Pos (10U) |
#define | ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) |
#define | ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */ |
#define | ETH_MACISR_MMCRXIS_Pos (9U) |
#define | ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) |
#define | ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */ |
#define | ETH_MACISR_MMCIS_Pos (8U) |
#define | ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) |
#define | ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */ |
#define | ETH_MACISR_LPIIS_Pos (5U) |
#define | ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) |
#define | ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */ |
#define | ETH_MACISR_PMTIS_Pos (4U) |
#define | ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) |
#define | ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */ |
#define | ETH_MACISR_PHYIS_Pos (3U) |
#define | ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) |
#define | ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */ |
#define | ETH_MACIER_RXSTSIE_Pos (14U) |
#define | ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) |
#define | ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */ |
#define | ETH_MACIER_TXSTSIE_Pos (13U) |
#define | ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) |
#define | ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */ |
#define | ETH_MACIER_TSIE_Pos (12U) |
#define | ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) |
#define | ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */ |
#define | ETH_MACIER_LPIIE_Pos (5U) |
#define | ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) |
#define | ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */ |
#define | ETH_MACIER_PMTIE_Pos (4U) |
#define | ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) |
#define | ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */ |
#define | ETH_MACIER_PHYIE_Pos (3U) |
#define | ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) |
#define | ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */ |
#define | ETH_MACRXTXSR_RWT_Pos (8U) |
#define | ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) |
#define | ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */ |
#define | ETH_MACRXTXSR_EXCOL_Pos (5U) |
#define | ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) |
#define | ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */ |
#define | ETH_MACRXTXSR_LCOL_Pos (4U) |
#define | ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) |
#define | ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */ |
#define | ETH_MACRXTXSR_EXDEF_Pos (3U) |
#define | ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) |
#define | ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */ |
#define | ETH_MACRXTXSR_LCARR_Pos (2U) |
#define | ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) |
#define | ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */ |
#define | ETH_MACRXTXSR_NCARR_Pos (1U) |
#define | ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) |
#define | ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */ |
#define | ETH_MACRXTXSR_TJT_Pos (0U) |
#define | ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) |
#define | ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */ |
#define | ETH_MACPCSR_RWKFILTRST_Pos (31U) |
#define | ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) |
#define | ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */ |
#define | ETH_MACPCSR_RWKPTR_Pos (24U) |
#define | ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) |
#define | ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */ |
#define | ETH_MACPCSR_RWKPFE_Pos (10U) |
#define | ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) |
#define | ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */ |
#define | ETH_MACPCSR_GLBLUCAST_Pos (9U) |
#define | ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) |
#define | ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */ |
#define | ETH_MACPCSR_RWKPRCVD_Pos (6U) |
#define | ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) |
#define | ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */ |
#define | ETH_MACPCSR_MGKPRCVD_Pos (5U) |
#define | ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) |
#define | ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */ |
#define | ETH_MACPCSR_RWKPKTEN_Pos (2U) |
#define | ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) |
#define | ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */ |
#define | ETH_MACPCSR_MGKPKTEN_Pos (1U) |
#define | ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) |
#define | ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */ |
#define | ETH_MACPCSR_PWRDWN_Pos (0U) |
#define | ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) |
#define | ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */ |
#define | ETH_MACRWUPFR_D_Pos (0U) |
#define | ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) |
#define | ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */ |
#define | ETH_MACLCSR_LPITCSE_Pos (21U) |
#define | ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) |
#define | ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ |
#define | ETH_MACLCSR_LPITE_Pos (20U) |
#define | ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) |
#define | ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */ |
#define | ETH_MACLCSR_LPITXA_Pos (19U) |
#define | ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) |
#define | ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */ |
#define | ETH_MACLCSR_PLS_Pos (17U) |
#define | ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) |
#define | ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */ |
#define | ETH_MACLCSR_LPIEN_Pos (16U) |
#define | ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) |
#define | ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */ |
#define | ETH_MACLCSR_RLPIST_Pos (9U) |
#define | ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) |
#define | ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */ |
#define | ETH_MACLCSR_TLPIST_Pos (8U) |
#define | ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) |
#define | ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */ |
#define | ETH_MACLCSR_RLPIEX_Pos (3U) |
#define | ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) |
#define | ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */ |
#define | ETH_MACLCSR_RLPIEN_Pos (2U) |
#define | ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) |
#define | ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */ |
#define | ETH_MACLCSR_TLPIEX_Pos (1U) |
#define | ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) |
#define | ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */ |
#define | ETH_MACLCSR_TLPIEN_Pos (0U) |
#define | ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) |
#define | ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */ |
#define | ETH_MACLTCR_LST_Pos (16U) |
#define | ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) |
#define | ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */ |
#define | ETH_MACLTCR_TWT_Pos (0U) |
#define | ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) |
#define | ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */ |
#define | ETH_MACLETR_LPIET_Pos (0U) |
#define | ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) |
#define | ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */ |
#define | ETH_MAC1USTCR_TIC1USCNTR_Pos (0U) |
#define | ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) |
#define | ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */ |
#define | ETH_MACVR_USERVER_Pos (8U) |
#define | ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) |
#define | ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */ |
#define | ETH_MACVR_SNPSVER_Pos (0U) |
#define | ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) |
#define | ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */ |
#define | ETH_MACDR_TFCSTS_Pos (17U) |
#define | ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) |
#define | ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ |
#define | ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ |
#define | ETH_MACDR_TFCSTS_WAIT_Pos (17U) |
#define | ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) |
#define | ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ |
#define | ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U) |
#define | ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) |
#define | ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */ |
#define | ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U) |
#define | ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) |
#define | ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */ |
#define | ETH_MACDR_TPESTS_Pos (16U) |
#define | ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) |
#define | ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */ |
#define | ETH_MACDR_RFCFCSTS_Pos (1U) |
#define | ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) |
#define | ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */ |
#define | ETH_MACDR_RPESTS_Pos (0U) |
#define | ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) |
#define | ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */ |
#define | ETH_MACHWF0R_ACTPHYSEL_Pos (28U) |
#define | ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) |
#define | ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ |
#define | ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ |
#define | ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) |
#define | ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) |
#define | ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ |
#define | ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U) |
#define | ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) |
#define | ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */ |
#define | ETH_MACHWF0R_SAVLANINS_Pos (27U) |
#define | ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) |
#define | ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */ |
#define | ETH_MACHWF0R_TSSTSSEL_Pos (25U) |
#define | ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) |
#define | ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */ |
#define | ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U) |
#define | ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) |
#define | ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */ |
#define | ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U) |
#define | ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) |
#define | ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */ |
#define | ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U) |
#define | ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) |
#define | ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */ |
#define | ETH_MACHWF0R_MACADR64SEL_Pos (24U) |
#define | ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) |
#define | ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */ |
#define | ETH_MACHWF0R_MACADR32SEL_Pos (23U) |
#define | ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) |
#define | ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */ |
#define | ETH_MACHWF0R_ADDMACADRSEL_Pos (18U) |
#define | ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) |
#define | ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */ |
#define | ETH_MACHWF0R_RXCOESEL_Pos (16U) |
#define | ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) |
#define | ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */ |
#define | ETH_MACHWF0R_TXCOESEL_Pos (14U) |
#define | ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) |
#define | ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */ |
#define | ETH_MACHWF0R_EEESEL_Pos (13U) |
#define | ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) |
#define | ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */ |
#define | ETH_MACHWF0R_TSSEL_Pos (12U) |
#define | ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) |
#define | ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */ |
#define | ETH_MACHWF0R_ARPOFFSEL_Pos (9U) |
#define | ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) |
#define | ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */ |
#define | ETH_MACHWF0R_MMCSEL_Pos (8U) |
#define | ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) |
#define | ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */ |
#define | ETH_MACHWF0R_MGKSEL_Pos (7U) |
#define | ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) |
#define | ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */ |
#define | ETH_MACHWF0R_RWKSEL_Pos (6U) |
#define | ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) |
#define | ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */ |
#define | ETH_MACHWF0R_SMASEL_Pos (5U) |
#define | ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) |
#define | ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */ |
#define | ETH_MACHWF0R_VLHASH_Pos (4U) |
#define | ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) |
#define | ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */ |
#define | ETH_MACHWF0R_PCSSEL_Pos (3U) |
#define | ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) |
#define | ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */ |
#define | ETH_MACHWF0R_HDSEL_Pos (2U) |
#define | ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) |
#define | ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */ |
#define | ETH_MACHWF0R_GMIISEL_Pos (1U) |
#define | ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) |
#define | ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */ |
#define | ETH_MACHWF0R_MIISEL_Pos (0U) |
#define | ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) |
#define | ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */ |
#define | ETH_MACHWF1R_L3L4FNUM_Pos (27U) |
#define | ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) |
#define | ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */ |
#define | ETH_MACHWF1R_HASHTBLSZ_Pos (24U) |
#define | ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) |
#define | ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */ |
#define | ETH_MACHWF1R_AVSEL_Pos (20U) |
#define | ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) |
#define | ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */ |
#define | ETH_MACHWF1R_DBGMEMA_Pos (19U) |
#define | ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) |
#define | ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */ |
#define | ETH_MACHWF1R_TSOEN_Pos (18U) |
#define | ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) |
#define | ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */ |
#define | ETH_MACHWF1R_SPHEN_Pos (17U) |
#define | ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) |
#define | ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */ |
#define | ETH_MACHWF1R_DCBEN_Pos (16U) |
#define | ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) |
#define | ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */ |
#define | ETH_MACHWF1R_ADDR64_Pos (14U) |
#define | ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) |
#define | ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */ |
#define | ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) |
#define | ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) |
#define | ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) |
#define | ETH_MACHWF1R_ADVTHWORD_Pos (13U) |
#define | ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) |
#define | ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */ |
#define | ETH_MACHWF1R_PTOEN_Pos (12U) |
#define | ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) |
#define | ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */ |
#define | ETH_MACHWF1R_OSTEN_Pos (11U) |
#define | ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) |
#define | ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */ |
#define | ETH_MACHWF1R_TXFIFOSIZE_Pos (6U) |
#define | ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) |
#define | ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */ |
#define | ETH_MACHWF1R_RXFIFOSIZE_Pos (0U) |
#define | ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) |
#define | ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */ |
#define | ETH_MACHWF2R_AUXSNAPNUM_Pos (28U) |
#define | ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) |
#define | ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */ |
#define | ETH_MACHWF2R_PPSOUTNUM_Pos (24U) |
#define | ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) |
#define | ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */ |
#define | ETH_MACHWF2R_TXCHCNT_Pos (18U) |
#define | ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) |
#define | ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */ |
#define | ETH_MACHWF2R_RXCHCNT_Pos (13U) |
#define | ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) |
#define | ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */ |
#define | ETH_MACHWF2R_TXQCNT_Pos (6U) |
#define | ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) |
#define | ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */ |
#define | ETH_MACHWF2R_RXQCNT_Pos (0U) |
#define | ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) |
#define | ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */ |
#define | ETH_MACMDIOAR_PSE_Pos (27U) |
#define | ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) |
#define | ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */ |
#define | ETH_MACMDIOAR_BTB_Pos (26U) |
#define | ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) |
#define | ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */ |
#define | ETH_MACMDIOAR_PA_Pos (21U) |
#define | ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) |
#define | ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */ |
#define | ETH_MACMDIOAR_RDA_Pos (16U) |
#define | ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) |
#define | ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */ |
#define | ETH_MACMDIOAR_NTC_Pos (12U) |
#define | ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) |
#define | ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */ |
#define | ETH_MACMDIOAR_CR_Pos (8U) |
#define | ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) |
#define | ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ |
#define | ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ |
#define | ETH_MACMDIOAR_CR_DIV62_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) |
#define | ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ |
#define | ETH_MACMDIOAR_CR_DIV16_Pos (9U) |
#define | ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) |
#define | ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */ |
#define | ETH_MACMDIOAR_CR_DIV26_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) |
#define | ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */ |
#define | ETH_MACMDIOAR_CR_DIV102_Pos (10U) |
#define | ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) |
#define | ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */ |
#define | ETH_MACMDIOAR_CR_DIV124_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) |
#define | ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */ |
#define | ETH_MACMDIOAR_CR_DIV4AR_Pos (11U) |
#define | ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV6AR_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV8AR_Pos (9U) |
#define | ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV10AR_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV12AR_Pos (10U) |
#define | ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV14AR_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV16AR_Pos (9U) |
#define | ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_CR_DIV18AR_Pos (8U) |
#define | ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) |
#define | ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */ |
#define | ETH_MACMDIOAR_SKAP_Pos (4U) |
#define | ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) |
#define | ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */ |
#define | ETH_MACMDIOAR_MOC_Pos (2U) |
#define | ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) |
#define | ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */ |
#define | ETH_MACMDIOAR_MOC_WR_Pos (2U) |
#define | ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) |
#define | ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */ |
#define | ETH_MACMDIOAR_MOC_PRDIA_Pos (3U) |
#define | ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) |
#define | ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */ |
#define | ETH_MACMDIOAR_MOC_RD_Pos (2U) |
#define | ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) |
#define | ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */ |
#define | ETH_MACMDIOAR_C45E_Pos (1U) |
#define | ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) |
#define | ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */ |
#define | ETH_MACMDIOAR_MB_Pos (0U) |
#define | ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) |
#define | ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */ |
#define | ETH_MACMDIODR_RA_Pos (16U) |
#define | ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) |
#define | ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */ |
#define | ETH_MACMDIODR_MD_Pos (0U) |
#define | ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) |
#define | ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */ |
#define | ETH_MACARPAR_ARPPA_Pos (0U) |
#define | ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) |
#define | ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */ |
#define | ETH_MACA0HR_AE_Pos (31U) |
#define | ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) |
#define | ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/ |
#define | ETH_MACA0HR_ADDRHI_Pos (0U) |
#define | ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) |
#define | ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/ |
#define | ETH_MACA0LR_ADDRLO_Pos (0U) |
#define | ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) |
#define | ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/ |
#define | ETH_MACA1HR_AE_Pos (31U) |
#define | ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) |
#define | ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/ |
#define | ETH_MACA1HR_SA_Pos (30U) |
#define | ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) |
#define | ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */ |
#define | ETH_MACA1HR_MBC_Pos (24U) |
#define | ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) |
#define | ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */ |
#define | ETH_MACA1HR_ADDRHI_Pos (0U) |
#define | ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) |
#define | ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/ |
#define | ETH_MACA1LR_ADDRLO_Pos (0U) |
#define | ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) |
#define | ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/ |
#define | ETH_MACA2HR_AE_Pos (31U) |
#define | ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) |
#define | ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/ |
#define | ETH_MACA2HR_SA_Pos (30U) |
#define | ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) |
#define | ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */ |
#define | ETH_MACA2HR_MBC_Pos (24U) |
#define | ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) |
#define | ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */ |
#define | ETH_MACA2HR_ADDRHI_Pos (0U) |
#define | ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) |
#define | ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/ |
#define | ETH_MACA2LR_ADDRLO_Pos (0U) |
#define | ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) |
#define | ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/ |
#define | ETH_MACA3HR_AE_Pos (31U) |
#define | ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) |
#define | ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/ |
#define | ETH_MACA3HR_SA_Pos (30U) |
#define | ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) |
#define | ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */ |
#define | ETH_MACA3HR_MBC_Pos (24U) |
#define | ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) |
#define | ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */ |
#define | ETH_MACA3HR_ADDRHI_Pos (0U) |
#define | ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) |
#define | ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/ |
#define | ETH_MACA3LR_ADDRLO_Pos (0U) |
#define | ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) |
#define | ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/ |
#define | ETH_MACAHR_AE_Pos (31U) |
#define | ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) |
#define | ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */ |
#define | ETH_MACAHR_SA_Pos (30U) |
#define | ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) |
#define | ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */ |
#define | ETH_MACAHR_MBC_Pos (24U) |
#define | ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) |
#define | ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
#define | ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ |
#define | ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ |
#define | ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ |
#define | ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ |
#define | ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ |
#define | ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ |
#define | ETH_MACAHR_MACAH_Pos (0U) |
#define | ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) |
#define | ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ |
#define | ETH_MACALR_MACAL_Pos (0U) |
#define | ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) |
#define | ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */ |
#define | ETH_MMCCR_UCDBC_Pos (8U) |
#define | ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) |
#define | ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */ |
#define | ETH_MMCCR_CNTPRSTLVL_Pos (5U) |
#define | ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) |
#define | ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */ |
#define | ETH_MMCCR_CNTPRST_Pos (4U) |
#define | ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) |
#define | ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */ |
#define | ETH_MMCCR_CNTFREEZ_Pos (3U) |
#define | ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) |
#define | ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */ |
#define | ETH_MMCCR_RSTONRD_Pos (2U) |
#define | ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) |
#define | ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */ |
#define | ETH_MMCCR_CNTSTOPRO_Pos (1U) |
#define | ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) |
#define | ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */ |
#define | ETH_MMCCR_CNTRST_Pos (0U) |
#define | ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) |
#define | ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */ |
#define | ETH_MMCRIR_RXLPITRCIS_Pos (27U) |
#define | ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) |
#define | ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */ |
#define | ETH_MMCRIR_RXLPIUSCIS_Pos (26U) |
#define | ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) |
#define | ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */ |
#define | ETH_MMCRIR_RXUCGPIS_Pos (17U) |
#define | ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) |
#define | ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */ |
#define | ETH_MMCRIR_RXALGNERPIS_Pos (6U) |
#define | ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) |
#define | ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */ |
#define | ETH_MMCRIR_RXCRCERPIS_Pos (5U) |
#define | ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) |
#define | ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */ |
#define | ETH_MMCTIR_TXLPITRCIS_Pos (27U) |
#define | ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) |
#define | ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */ |
#define | ETH_MMCTIR_TXLPIUSCIS_Pos (26U) |
#define | ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) |
#define | ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */ |
#define | ETH_MMCTIR_TXGPKTIS_Pos (21U) |
#define | ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) |
#define | ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */ |
#define | ETH_MMCTIR_TXMCOLGPIS_Pos (15U) |
#define | ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) |
#define | ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */ |
#define | ETH_MMCTIR_TXSCOLGPIS_Pos (14U) |
#define | ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) |
#define | ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */ |
#define | ETH_MMCRIMR_RXLPITRCIM_Pos (27U) |
#define | ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) |
#define | ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */ |
#define | ETH_MMCRIMR_RXLPIUSCIM_Pos (26U) |
#define | ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) |
#define | ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */ |
#define | ETH_MMCRIMR_RXUCGPIM_Pos (17U) |
#define | ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) |
#define | ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */ |
#define | ETH_MMCRIMR_RXALGNERPIM_Pos (6U) |
#define | ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) |
#define | ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */ |
#define | ETH_MMCRIMR_RXCRCERPIM_Pos (5U) |
#define | ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) |
#define | ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */ |
#define | ETH_MMCTIMR_TXLPITRCIM_Pos (27U) |
#define | ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) |
#define | ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/ |
#define | ETH_MMCTIMR_TXLPIUSCIM_Pos (26U) |
#define | ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) |
#define | ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/ |
#define | ETH_MMCTIMR_TXGPKTIM_Pos (21U) |
#define | ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) |
#define | ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/ |
#define | ETH_MMCTIMR_TXMCOLGPIM_Pos (15U) |
#define | ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) |
#define | ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */ |
#define | ETH_MMCTIMR_TXSCOLGPIM_Pos (14U) |
#define | ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) |
#define | ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */ |
#define | ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U) |
#define | ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) |
#define | ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */ |
#define | ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U) |
#define | ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) |
#define | ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */ |
#define | ETH_MMCTPCGR_TXPKTG_Pos (0U) |
#define | ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) |
#define | ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */ |
#define | ETH_MMCRCRCEPR_RXCRCERR_Pos (0U) |
#define | ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) |
#define | ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */ |
#define | ETH_MMCRAEPR_RXALGNERR_Pos (0U) |
#define | ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) |
#define | ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */ |
#define | ETH_MMCRUPGR_RXUCASTG_Pos (0U) |
#define | ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) |
#define | ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */ |
#define | ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U) |
#define | ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) |
#define | ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */ |
#define | ETH_MMCTLPITCR_TXLPITRC_Pos (0U) |
#define | ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) |
#define | ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */ |
#define | ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U) |
#define | ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) |
#define | ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */ |
#define | ETH_MMCRLPITCR_RXLPITRC_Pos (0U) |
#define | ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) |
#define | ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */ |
#define | ETH_MACL3L4CR_L4DPIM_Pos (21U) |
#define | ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) |
#define | ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */ |
#define | ETH_MACL3L4CR_L4DPM_Pos (20U) |
#define | ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) |
#define | ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */ |
#define | ETH_MACL3L4CR_L4SPIM_Pos (19U) |
#define | ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) |
#define | ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */ |
#define | ETH_MACL3L4CR_L4SPM_Pos (18U) |
#define | ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) |
#define | ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */ |
#define | ETH_MACL3L4CR_L4PEN_Pos (16U) |
#define | ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) |
#define | ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */ |
#define | ETH_MACL3L4CR_L3HDBM_Pos (11U) |
#define | ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) |
#define | ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */ |
#define | ETH_MACL3L4CR_L3HSBM_Pos (6U) |
#define | ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) |
#define | ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */ |
#define | ETH_MACL3L4CR_L3DAIM_Pos (5U) |
#define | ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) |
#define | ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */ |
#define | ETH_MACL3L4CR_L3DAM_Pos (4U) |
#define | ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) |
#define | ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */ |
#define | ETH_MACL3L4CR_L3SAIM_Pos (3U) |
#define | ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) |
#define | ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */ |
#define | ETH_MACL3L4CR_L3SAM_Pos (2U) |
#define | ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) |
#define | ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/ |
#define | ETH_MACL3L4CR_L3PEN_Pos (0U) |
#define | ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) |
#define | ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */ |
#define | ETH_MACL4AR_L4DP_Pos (16U) |
#define | ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) |
#define | ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */ |
#define | ETH_MACL4AR_L4SP_Pos (0U) |
#define | ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) |
#define | ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */ |
#define | ETH_MACL3A0R_L3A0_Pos (0U) |
#define | ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) |
#define | ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */ |
#define | ETH_MACL3A1R_L3A1_Pos (0U) |
#define | ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) |
#define | ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */ |
#define | ETH_MACL3A2R_L3A2_Pos (0U) |
#define | ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) |
#define | ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */ |
#define | ETH_MACL3A3R_L3A3_Pos (0U) |
#define | ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) |
#define | ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */ |
#define | ETH_MACTSCR_TXTSSTSM_Pos (24U) |
#define | ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) |
#define | ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */ |
#define | ETH_MACTSCR_CSC_Pos (19U) |
#define | ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) |
#define | ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */ |
#define | ETH_MACTSCR_TSENMACADDR_Pos (18U) |
#define | ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) |
#define | ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */ |
#define | ETH_MACTSCR_SNAPTYPSEL_Pos (16U) |
#define | ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) |
#define | ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */ |
#define | ETH_MACTSCR_TSMSTRENA_Pos (15U) |
#define | ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) |
#define | ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */ |
#define | ETH_MACTSCR_TSEVNTENA_Pos (14U) |
#define | ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) |
#define | ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */ |
#define | ETH_MACTSCR_TSIPV4ENA_Pos (13U) |
#define | ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) |
#define | ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */ |
#define | ETH_MACTSCR_TSIPV6ENA_Pos (12U) |
#define | ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) |
#define | ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */ |
#define | ETH_MACTSCR_TSIPENA_Pos (11U) |
#define | ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) |
#define | ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */ |
#define | ETH_MACTSCR_TSVER2ENA_Pos (10U) |
#define | ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) |
#define | ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */ |
#define | ETH_MACTSCR_TSCTRLSSR_Pos (9U) |
#define | ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) |
#define | ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */ |
#define | ETH_MACTSCR_TSENALL_Pos (8U) |
#define | ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) |
#define | ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */ |
#define | ETH_MACTSCR_TSADDREG_Pos (5U) |
#define | ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) |
#define | ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */ |
#define | ETH_MACTSCR_TSUPDT_Pos (3U) |
#define | ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) |
#define | ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */ |
#define | ETH_MACTSCR_TSINIT_Pos (2U) |
#define | ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) |
#define | ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */ |
#define | ETH_MACTSCR_TSCFUPDT_Pos (1U) |
#define | ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) |
#define | ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/ |
#define | ETH_MACTSCR_TSENA_Pos (0U) |
#define | ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) |
#define | ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */ |
#define | ETH_MACMACSSIR_SSINC_Pos (16U) |
#define | ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) |
#define | ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */ |
#define | ETH_MACMACSSIR_SNSINC_Pos (8U) |
#define | ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) |
#define | ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */ |
#define | ETH_MACSTSR_TSS_Pos (0U) |
#define | ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) |
#define | ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */ |
#define | ETH_MACSTNR_TSSS_Pos (0U) |
#define | ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) |
#define | ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */ |
#define | ETH_MACSTSUR_TSS_Pos (0U) |
#define | ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) |
#define | ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */ |
#define | ETH_MACSTNUR_ADDSUB_Pos (31U) |
#define | ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) |
#define | ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */ |
#define | ETH_MACSTNUR_TSSS_Pos (0U) |
#define | ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) |
#define | ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */ |
#define | ETH_MACTSAR_TSAR_Pos (0U) |
#define | ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) |
#define | ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */ |
#define | ETH_MACTSSR_ATSNS_Pos (25U) |
#define | ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) |
#define | ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */ |
#define | ETH_MACTSSR_ATSSTM_Pos (24U) |
#define | ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) |
#define | ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */ |
#define | ETH_MACTSSR_ATSSTN_Pos (16U) |
#define | ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) |
#define | ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */ |
#define | ETH_MACTSSR_TXTSSIS_Pos (15U) |
#define | ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) |
#define | ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */ |
#define | ETH_MACTSSR_TSTRGTERR0_Pos (3U) |
#define | ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) |
#define | ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */ |
#define | ETH_MACTSSR_AUXTSTRIG_Pos (2U) |
#define | ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) |
#define | ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/ |
#define | ETH_MACTSSR_TSTARGT0_Pos (1U) |
#define | ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) |
#define | ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */ |
#define | ETH_MACTSSR_TSSOVF_Pos (0U) |
#define | ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) |
#define | ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */ |
#define | ETH_MACTTSSNR_TXTSSMIS_Pos (31U) |
#define | ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) |
#define | ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */ |
#define | ETH_MACTTSSNR_TXTSSLO_Pos (0U) |
#define | ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) |
#define | ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */ |
#define | ETH_MACTTSSSR_TXTSSHI_Pos (0U) |
#define | ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) |
#define | ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */ |
#define | ETH_MACACR_ATSEN3_Pos (7U) |
#define | ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) |
#define | ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */ |
#define | ETH_MACACR_ATSEN2_Pos (6U) |
#define | ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) |
#define | ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */ |
#define | ETH_MACACR_ATSEN1_Pos (5U) |
#define | ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) |
#define | ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */ |
#define | ETH_MACACR_ATSEN0_Pos (4U) |
#define | ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) |
#define | ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */ |
#define | ETH_MACACR_ATSFC_Pos (0U) |
#define | ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) |
#define | ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */ |
#define | ETH_MACATSNR_AUXTSLO_Pos (0U) |
#define | ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) |
#define | ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */ |
#define | ETH_MACATSSR_AUXTSHI_Pos (0U) |
#define | ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) |
#define | ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */ |
#define | ETH_MACTSIACR_OSTIAC_Pos (0U) |
#define | ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) |
#define | ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */ |
#define | ETH_MACTSEACR_OSTEAC_Pos (0U) |
#define | ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) |
#define | ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */ |
#define | ETH_MACTSICNR_TSIC_Pos (0U) |
#define | ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) |
#define | ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */ |
#define | ETH_MACTSECNR_TSEC_Pos (0U) |
#define | ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) |
#define | ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */ |
#define | ETH_MACPPSCR_TRGTMODSEL0_Pos (5U) |
#define | ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) |
#define | ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */ |
#define | ETH_MACPPSCR_PPSEN0_Pos (4U) |
#define | ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) |
#define | ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */ |
#define | ETH_MACPPSCR_PPSCTRL_Pos (0U) |
#define | ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) |
#define | ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */ |
#define | ETH_MACPPSTTSR_TSTRH0_Pos (0U) |
#define | ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) |
#define | ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */ |
#define | ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U) |
#define | ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) |
#define | ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */ |
#define | ETH_MACPPSTTNR_TTSL0_Pos (0U) |
#define | ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) |
#define | ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */ |
#define | ETH_MACPPSIR_PPSINT0_Pos (0U) |
#define | ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) |
#define | ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */ |
#define | ETH_MACPPSWR_PPSWIDTH0_Pos (0U) |
#define | ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) |
#define | ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */ |
#define | ETH_MACPOCR_DN_Pos (8U) |
#define | ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) |
#define | ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */ |
#define | ETH_MACPOCR_DRRDIS_Pos (6U) |
#define | ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) |
#define | ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */ |
#define | ETH_MACPOCR_APDREQTRIG_Pos (5U) |
#define | ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) |
#define | ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */ |
#define | ETH_MACPOCR_ASYNCTRIG_Pos (4U) |
#define | ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) |
#define | ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */ |
#define | ETH_MACPOCR_APDREQEN_Pos (2U) |
#define | ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) |
#define | ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */ |
#define | ETH_MACPOCR_ASYNCEN_Pos (1U) |
#define | ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) |
#define | ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */ |
#define | ETH_MACPOCR_PTOEN_Pos (0U) |
#define | ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) |
#define | ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */ |
#define | ETH_MACSPI0R_SPI0_Pos (0U) |
#define | ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) |
#define | ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */ |
#define | ETH_MACSPI1R_SPI1_Pos (0U) |
#define | ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) |
#define | ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */ |
#define | ETH_MACSPI2R_SPI2_Pos (0U) |
#define | ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) |
#define | ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */ |
#define | ETH_MACLMIR_LMPDRI_Pos (24U) |
#define | ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) |
#define | ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */ |
#define | ETH_MACLMIR_DRSYNCR_Pos (8U) |
#define | ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) |
#define | ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */ |
#define | ETH_MACLMIR_LSI_Pos (0U) |
#define | ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) |
#define | ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */ |
#define | ETH_MTLOMR_CNTCLR_Pos (9U) |
#define | ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) |
#define | ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */ |
#define | ETH_MTLOMR_CNTPRST_Pos (8U) |
#define | ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) |
#define | ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */ |
#define | ETH_MTLOMR_DTXSTS_Pos (1U) |
#define | ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) |
#define | ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */ |
#define | ETH_MTLISR_MACIS_Pos (16U) |
#define | ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) |
#define | ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */ |
#define | ETH_MTLISR_QIS_Pos (0U) |
#define | ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) |
#define | ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */ |
#define | ETH_MTLTQOMR_TTC_Pos (4U) |
#define | ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) |
#define | ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ |
#define | ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ |
#define | ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ |
#define | ETH_MTLTQOMR_TSF_Pos (1U) |
#define | ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) |
#define | ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ |
#define | ETH_MTLTQOMR_FTQ_Pos (0U) |
#define | ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) |
#define | ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */ |
#define | ETH_MTLTQUR_UFCNTOVF_Pos (11U) |
#define | ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) |
#define | ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */ |
#define | ETH_MTLTQUR_UFPKTCNT_Pos (0U) |
#define | ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) |
#define | ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */ |
#define | ETH_MTLTQDR_STXSTSF_Pos (20U) |
#define | ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) |
#define | ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */ |
#define | ETH_MTLTQDR_PTXQ_Pos (16U) |
#define | ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) |
#define | ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */ |
#define | ETH_MTLTQDR_TXSTSFSTS_Pos (5U) |
#define | ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) |
#define | ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */ |
#define | ETH_MTLTQDR_TXQSTS_Pos (4U) |
#define | ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) |
#define | ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */ |
#define | ETH_MTLTQDR_TWCSTS_Pos (3U) |
#define | ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) |
#define | ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */ |
#define | ETH_MTLTQDR_TRCSTS_Pos (1U) |
#define | ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) |
#define | ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ |
#define | ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ |
#define | ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ |
#define | ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ |
#define | ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ |
#define | ETH_MTLTQDR_TXQPAUSED_Pos (0U) |
#define | ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) |
#define | ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ |
#define | ETH_MTLQICSR_RXOIE_Pos (24U) |
#define | ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) |
#define | ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */ |
#define | ETH_MTLQICSR_RXOVFIS_Pos (16U) |
#define | ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) |
#define | ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */ |
#define | ETH_MTLQICSR_TXUIE_Pos (8U) |
#define | ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) |
#define | ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */ |
#define | ETH_MTLQICSR_TXUNFIS_Pos (0U) |
#define | ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) |
#define | ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */ |
#define | ETH_MTLRQOMR_RQS_Pos (20U) |
#define | ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) |
#define | ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */ |
#define | ETH_MTLRQOMR_RFD_Pos (14U) |
#define | ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) |
#define | ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ |
#define | ETH_MTLRQOMR_RFA_Pos (8U) |
#define | ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) |
#define | ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */ |
#define | ETH_MTLRQOMR_EHFC_Pos (7U) |
#define | ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) |
#define | ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */ |
#define | ETH_MTLRQOMR_DISTCPEF_Pos (6U) |
#define | ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) |
#define | ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */ |
#define | ETH_MTLRQOMR_RSF_Pos (5U) |
#define | ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) |
#define | ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */ |
#define | ETH_MTLRQOMR_FEP_Pos (4U) |
#define | ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) |
#define | ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */ |
#define | ETH_MTLRQOMR_FUP_Pos (3U) |
#define | ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) |
#define | ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */ |
#define | ETH_MTLRQOMR_RTC_Pos (0U) |
#define | ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) |
#define | ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ |
#define | ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ |
#define | ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ |
#define | ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ |
#define | ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ |
#define | ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) |
#define | ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) |
#define | ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */ |
#define | ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U) |
#define | ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) |
#define | ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */ |
#define | ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U) |
#define | ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) |
#define | ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */ |
#define | ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U) |
#define | ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) |
#define | ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */ |
#define | ETH_MTLRQDR_PRXQ_Pos (16U) |
#define | ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) |
#define | ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */ |
#define | ETH_MTLRQDR_RXQSTS_Pos (4U) |
#define | ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) |
#define | ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ |
#define | ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ |
#define | ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) |
#define | ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) |
#define | ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ |
#define | ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U) |
#define | ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) |
#define | ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */ |
#define | ETH_MTLRQDR_RXQSTS_FULL_Pos (4U) |
#define | ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) |
#define | ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */ |
#define | ETH_MTLRQDR_RRCSTS_Pos (1U) |
#define | ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) |
#define | ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ |
#define | ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ |
#define | ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) |
#define | ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) |
#define | ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ |
#define | ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U) |
#define | ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) |
#define | ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */ |
#define | ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U) |
#define | ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) |
#define | ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */ |
#define | ETH_MTLRQDR_RWCSTS_Pos (0U) |
#define | ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) |
#define | ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */ |
#define | ETH_MTLRQCR_RQPA_Pos (3U) |
#define | ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) |
#define | ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */ |
#define | ETH_MTLRQCR_RQW_Pos (0U) |
#define | ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) |
#define | ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */ |
#define | ETH_DMAMR_INTM_Pos (16U) |
#define | ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) |
#define | ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */ |
#define | ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) |
#define | ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) |
#define | ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) |
#define | ETH_DMAMR_PR_Pos (12U) |
#define | ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) |
#define | ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ |
#define | ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ |
#define | ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ |
#define | ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ |
#define | ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ |
#define | ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ |
#define | ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ |
#define | ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ |
#define | ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ |
#define | ETH_DMAMR_TXPR_Pos (11U) |
#define | ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) |
#define | ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ |
#define | ETH_DMAMR_DA_Pos (1U) |
#define | ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) |
#define | ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */ |
#define | ETH_DMAMR_SWR_Pos (0U) |
#define | ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) |
#define | ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */ |
#define | ETH_DMASBMR_RB_Pos (15U) |
#define | ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) |
#define | ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */ |
#define | ETH_DMASBMR_MB_Pos (14U) |
#define | ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) |
#define | ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */ |
#define | ETH_DMASBMR_AAL_Pos (12U) |
#define | ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) |
#define | ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */ |
#define | ETH_DMASBMR_FB_Pos (0U) |
#define | ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) |
#define | ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */ |
#define | ETH_DMAISR_MACIS_Pos (17U) |
#define | ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) |
#define | ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */ |
#define | ETH_DMAISR_MTLIS_Pos (16U) |
#define | ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) |
#define | ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */ |
#define | ETH_DMAISR_DMACIS_Pos (0U) |
#define | ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) |
#define | ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */ |
#define | ETH_DMADSR_TPS_Pos (12U) |
#define | ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) |
#define | ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ |
#define | ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ |
#define | ETH_DMADSR_TPS_FETCHING_Pos (12U) |
#define | ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) |
#define | ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ |
#define | ETH_DMADSR_TPS_WAITING_Pos (13U) |
#define | ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) |
#define | ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */ |
#define | ETH_DMADSR_TPS_READING_Pos (12U) |
#define | ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) |
#define | ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */ |
#define | ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U) |
#define | ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) |
#define | ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */ |
#define | ETH_DMADSR_TPS_SUSPENDED_Pos (13U) |
#define | ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) |
#define | ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */ |
#define | ETH_DMADSR_TPS_CLOSING_Pos (12U) |
#define | ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) |
#define | ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */ |
#define | ETH_DMADSR_RPS_Pos (8U) |
#define | ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) |
#define | ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ |
#define | ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ |
#define | ETH_DMADSR_RPS_FETCHING_Pos (12U) |
#define | ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) |
#define | ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ |
#define | ETH_DMADSR_RPS_WAITING_Pos (12U) |
#define | ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) |
#define | ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */ |
#define | ETH_DMADSR_RPS_SUSPENDED_Pos (14U) |
#define | ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) |
#define | ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */ |
#define | ETH_DMADSR_RPS_CLOSING_Pos (12U) |
#define | ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) |
#define | ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */ |
#define | ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U) |
#define | ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) |
#define | ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */ |
#define | ETH_DMADSR_RPS_TRANSFERRING_Pos (12U) |
#define | ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) |
#define | ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */ |
#define | ETH_DMACCR_DSL_Pos (18U) |
#define | ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) |
#define | ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ |
#define | ETH_DMACCR_DSL_0BIT (0U) |
#define | ETH_DMACCR_DSL_32BIT (0x00040000U) |
#define | ETH_DMACCR_DSL_64BIT (0x00080000U) |
#define | ETH_DMACCR_DSL_128BIT (0x00100000U) |
#define | ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ |
#define | ETH_DMACCR_MSS_Pos (0U) |
#define | ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) |
#define | ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ |
#define | ETH_DMACTCR_TPBL_Pos (16U) |
#define | ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) |
#define | ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ |
#define | ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ |
#define | ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ |
#define | ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ |
#define | ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ |
#define | ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ |
#define | ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ |
#define | ETH_DMACTCR_TSE_Pos (12U) |
#define | ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) |
#define | ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ |
#define | ETH_DMACTCR_OSP_Pos (4U) |
#define | ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) |
#define | ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */ |
#define | ETH_DMACTCR_ST_Pos (0U) |
#define | ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) |
#define | ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */ |
#define | ETH_DMACRCR_RPF_Pos (31U) |
#define | ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) |
#define | ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */ |
#define | ETH_DMACRCR_RPBL_Pos (16U) |
#define | ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) |
#define | ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ |
#define | ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ |
#define | ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ |
#define | ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ |
#define | ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ |
#define | ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ |
#define | ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ |
#define | ETH_DMACRCR_RBSZ_Pos (1U) |
#define | ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) |
#define | ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ |
#define | ETH_DMACRCR_SR_Pos (0U) |
#define | ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) |
#define | ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */ |
#define | ETH_DMACTDLAR_TDESLA_Pos (2U) |
#define | ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) |
#define | ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */ |
#define | ETH_DMACRDLAR_RDESLA_Pos (2U) |
#define | ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) |
#define | ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */ |
#define | ETH_DMACTDTPR_TDT_Pos (2U) |
#define | ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) |
#define | ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */ |
#define | ETH_DMACRDTPR_RDT_Pos (2U) |
#define | ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) |
#define | ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */ |
#define | ETH_DMACTDRLR_TDRL_Pos (0U) |
#define | ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) |
#define | ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */ |
#define | ETH_DMACRDRLR_RDRL_Pos (0U) |
#define | ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) |
#define | ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */ |
#define | ETH_DMACIER_NIE_Pos (15U) |
#define | ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) |
#define | ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */ |
#define | ETH_DMACIER_AIE_Pos (14U) |
#define | ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) |
#define | ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */ |
#define | ETH_DMACIER_CDEE_Pos (13U) |
#define | ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) |
#define | ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */ |
#define | ETH_DMACIER_FBEE_Pos (12U) |
#define | ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) |
#define | ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */ |
#define | ETH_DMACIER_ERIE_Pos (11U) |
#define | ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) |
#define | ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */ |
#define | ETH_DMACIER_ETIE_Pos (10U) |
#define | ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) |
#define | ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */ |
#define | ETH_DMACIER_RWTE_Pos (9U) |
#define | ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) |
#define | ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */ |
#define | ETH_DMACIER_RSE_Pos (8U) |
#define | ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) |
#define | ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */ |
#define | ETH_DMACIER_RBUE_Pos (7U) |
#define | ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) |
#define | ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */ |
#define | ETH_DMACIER_RIE_Pos (6U) |
#define | ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) |
#define | ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */ |
#define | ETH_DMACIER_TBUE_Pos (2U) |
#define | ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) |
#define | ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */ |
#define | ETH_DMACIER_TXSE_Pos (1U) |
#define | ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) |
#define | ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */ |
#define | ETH_DMACIER_TIE_Pos (0U) |
#define | ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) |
#define | ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */ |
#define | ETH_DMACRIWTR_RWT_Pos (0U) |
#define | ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) |
#define | ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */ |
#define | ETH_DMACCATDR_CURTDESAPTR_Pos (0U) |
#define | ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) |
#define | ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */ |
#define | ETH_DMACCARDR_CURRDESAPTR_Pos (0U) |
#define | ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) |
#define | ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */ |
#define | ETH_DMACCATBR_CURTBUFAPTR_Pos (0U) |
#define | ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) |
#define | ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */ |
#define | ETH_DMACCARBR_CURRBUFAPTR_Pos (0U) |
#define | ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) |
#define | ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */ |
#define | ETH_DMACSR_REB_Pos (19U) |
#define | ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) |
#define | ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */ |
#define | ETH_DMACSR_TEB_Pos (16U) |
#define | ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) |
#define | ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */ |
#define | ETH_DMACSR_NIS_Pos (15U) |
#define | ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) |
#define | ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */ |
#define | ETH_DMACSR_AIS_Pos (14U) |
#define | ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) |
#define | ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */ |
#define | ETH_DMACSR_CDE_Pos (13U) |
#define | ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) |
#define | ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */ |
#define | ETH_DMACSR_FBE_Pos (12U) |
#define | ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) |
#define | ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */ |
#define | ETH_DMACSR_ERI_Pos (11U) |
#define | ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) |
#define | ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */ |
#define | ETH_DMACSR_ETI_Pos (10U) |
#define | ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) |
#define | ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */ |
#define | ETH_DMACSR_RWT_Pos (9U) |
#define | ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) |
#define | ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */ |
#define | ETH_DMACSR_RPS_Pos (8U) |
#define | ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) |
#define | ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */ |
#define | ETH_DMACSR_RBU_Pos (7U) |
#define | ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) |
#define | ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */ |
#define | ETH_DMACSR_RI_Pos (6U) |
#define | ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) |
#define | ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */ |
#define | ETH_DMACSR_TBU_Pos (2U) |
#define | ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) |
#define | ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */ |
#define | ETH_DMACSR_TPS_Pos (1U) |
#define | ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) |
#define | ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */ |
#define | ETH_DMACSR_TI_Pos (0U) |
#define | ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) |
#define | ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */ |
#define | ETH_DMACMFCR_MFCO_Pos (15U) |
#define | ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) |
#define | ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */ |
#define | ETH_DMACMFCR_MFC_Pos (0U) |
#define | ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) |
#define | ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */ |
#define | DMA_SxCR_MBURST_Pos (23U) |
#define | DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) |
#define | DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk |
#define | DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) |
#define | DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) |
#define | DMA_SxCR_PBURST_Pos (21U) |
#define | DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) |
#define | DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk |
#define | DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) |
#define | DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) |
#define | DMA_SxCR_TRBUFF_Pos (20U) |
#define | DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) |
#define | DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk |
#define | DMA_SxCR_CT_Pos (19U) |
#define | DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) |
#define | DMA_SxCR_CT DMA_SxCR_CT_Msk |
#define | DMA_SxCR_DBM_Pos (18U) |
#define | DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) |
#define | DMA_SxCR_DBM DMA_SxCR_DBM_Msk |
#define | DMA_SxCR_PL_Pos (16U) |
#define | DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) |
#define | DMA_SxCR_PL DMA_SxCR_PL_Msk |
#define | DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) |
#define | DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) |
#define | DMA_SxCR_PINCOS_Pos (15U) |
#define | DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) |
#define | DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk |
#define | DMA_SxCR_MSIZE_Pos (13U) |
#define | DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) |
#define | DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk |
#define | DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) |
#define | DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) |
#define | DMA_SxCR_PSIZE_Pos (11U) |
#define | DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) |
#define | DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */ |
#define | DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) |
#define | DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) |
#define | DMA_SxCR_MINC_Pos (10U) |
#define | DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) |
#define | DMA_SxCR_MINC DMA_SxCR_MINC_Msk |
#define | DMA_SxCR_PINC_Pos (9U) |
#define | DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) |
#define | DMA_SxCR_PINC DMA_SxCR_PINC_Msk |
#define | DMA_SxCR_CIRC_Pos (8U) |
#define | DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) |
#define | DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk |
#define | DMA_SxCR_DIR_Pos (6U) |
#define | DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) |
#define | DMA_SxCR_DIR DMA_SxCR_DIR_Msk |
#define | DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) |
#define | DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) |
#define | DMA_SxCR_PFCTRL_Pos (5U) |
#define | DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) |
#define | DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk |
#define | DMA_SxCR_TCIE_Pos (4U) |
#define | DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) |
#define | DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk |
#define | DMA_SxCR_HTIE_Pos (3U) |
#define | DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) |
#define | DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk |
#define | DMA_SxCR_TEIE_Pos (2U) |
#define | DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) |
#define | DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk |
#define | DMA_SxCR_DMEIE_Pos (1U) |
#define | DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) |
#define | DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk |
#define | DMA_SxCR_EN_Pos (0U) |
#define | DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) |
#define | DMA_SxCR_EN DMA_SxCR_EN_Msk |
#define | DMA_SxNDT_Pos (0U) |
#define | DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT DMA_SxNDT_Msk |
#define | DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) |
#define | DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) |
#define | DMA_SxFCR_FEIE_Pos (7U) |
#define | DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) |
#define | DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk |
#define | DMA_SxFCR_FS_Pos (3U) |
#define | DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) |
#define | DMA_SxFCR_FS DMA_SxFCR_FS_Msk |
#define | DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) |
#define | DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) |
#define | DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) |
#define | DMA_SxFCR_DMDIS_Pos (2U) |
#define | DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) |
#define | DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk |
#define | DMA_SxFCR_FTH_Pos (0U) |
#define | DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) |
#define | DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk |
#define | DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) |
#define | DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) |
#define | DMA_LISR_TCIF3_Pos (27U) |
#define | DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) |
#define | DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk |
#define | DMA_LISR_HTIF3_Pos (26U) |
#define | DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) |
#define | DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk |
#define | DMA_LISR_TEIF3_Pos (25U) |
#define | DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) |
#define | DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk |
#define | DMA_LISR_DMEIF3_Pos (24U) |
#define | DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) |
#define | DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk |
#define | DMA_LISR_FEIF3_Pos (22U) |
#define | DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) |
#define | DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk |
#define | DMA_LISR_TCIF2_Pos (21U) |
#define | DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) |
#define | DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk |
#define | DMA_LISR_HTIF2_Pos (20U) |
#define | DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) |
#define | DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk |
#define | DMA_LISR_TEIF2_Pos (19U) |
#define | DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) |
#define | DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk |
#define | DMA_LISR_DMEIF2_Pos (18U) |
#define | DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) |
#define | DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk |
#define | DMA_LISR_FEIF2_Pos (16U) |
#define | DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) |
#define | DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk |
#define | DMA_LISR_TCIF1_Pos (11U) |
#define | DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) |
#define | DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk |
#define | DMA_LISR_HTIF1_Pos (10U) |
#define | DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) |
#define | DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk |
#define | DMA_LISR_TEIF1_Pos (9U) |
#define | DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) |
#define | DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk |
#define | DMA_LISR_DMEIF1_Pos (8U) |
#define | DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) |
#define | DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk |
#define | DMA_LISR_FEIF1_Pos (6U) |
#define | DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) |
#define | DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk |
#define | DMA_LISR_TCIF0_Pos (5U) |
#define | DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) |
#define | DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk |
#define | DMA_LISR_HTIF0_Pos (4U) |
#define | DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) |
#define | DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk |
#define | DMA_LISR_TEIF0_Pos (3U) |
#define | DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) |
#define | DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk |
#define | DMA_LISR_DMEIF0_Pos (2U) |
#define | DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) |
#define | DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk |
#define | DMA_LISR_FEIF0_Pos (0U) |
#define | DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) |
#define | DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk |
#define | DMA_HISR_TCIF7_Pos (27U) |
#define | DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) |
#define | DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk |
#define | DMA_HISR_HTIF7_Pos (26U) |
#define | DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) |
#define | DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk |
#define | DMA_HISR_TEIF7_Pos (25U) |
#define | DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) |
#define | DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk |
#define | DMA_HISR_DMEIF7_Pos (24U) |
#define | DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) |
#define | DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk |
#define | DMA_HISR_FEIF7_Pos (22U) |
#define | DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) |
#define | DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk |
#define | DMA_HISR_TCIF6_Pos (21U) |
#define | DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) |
#define | DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk |
#define | DMA_HISR_HTIF6_Pos (20U) |
#define | DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) |
#define | DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk |
#define | DMA_HISR_TEIF6_Pos (19U) |
#define | DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) |
#define | DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk |
#define | DMA_HISR_DMEIF6_Pos (18U) |
#define | DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) |
#define | DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk |
#define | DMA_HISR_FEIF6_Pos (16U) |
#define | DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) |
#define | DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk |
#define | DMA_HISR_TCIF5_Pos (11U) |
#define | DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) |
#define | DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk |
#define | DMA_HISR_HTIF5_Pos (10U) |
#define | DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) |
#define | DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk |
#define | DMA_HISR_TEIF5_Pos (9U) |
#define | DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) |
#define | DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk |
#define | DMA_HISR_DMEIF5_Pos (8U) |
#define | DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) |
#define | DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk |
#define | DMA_HISR_FEIF5_Pos (6U) |
#define | DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) |
#define | DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk |
#define | DMA_HISR_TCIF4_Pos (5U) |
#define | DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) |
#define | DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk |
#define | DMA_HISR_HTIF4_Pos (4U) |
#define | DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) |
#define | DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk |
#define | DMA_HISR_TEIF4_Pos (3U) |
#define | DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) |
#define | DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk |
#define | DMA_HISR_DMEIF4_Pos (2U) |
#define | DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) |
#define | DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk |
#define | DMA_HISR_FEIF4_Pos (0U) |
#define | DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) |
#define | DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk |
#define | DMA_LIFCR_CTCIF3_Pos (27U) |
#define | DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) |
#define | DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk |
#define | DMA_LIFCR_CHTIF3_Pos (26U) |
#define | DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) |
#define | DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk |
#define | DMA_LIFCR_CTEIF3_Pos (25U) |
#define | DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) |
#define | DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk |
#define | DMA_LIFCR_CDMEIF3_Pos (24U) |
#define | DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) |
#define | DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk |
#define | DMA_LIFCR_CFEIF3_Pos (22U) |
#define | DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) |
#define | DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk |
#define | DMA_LIFCR_CTCIF2_Pos (21U) |
#define | DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) |
#define | DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk |
#define | DMA_LIFCR_CHTIF2_Pos (20U) |
#define | DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) |
#define | DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk |
#define | DMA_LIFCR_CTEIF2_Pos (19U) |
#define | DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) |
#define | DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk |
#define | DMA_LIFCR_CDMEIF2_Pos (18U) |
#define | DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) |
#define | DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk |
#define | DMA_LIFCR_CFEIF2_Pos (16U) |
#define | DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) |
#define | DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk |
#define | DMA_LIFCR_CTCIF1_Pos (11U) |
#define | DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) |
#define | DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk |
#define | DMA_LIFCR_CHTIF1_Pos (10U) |
#define | DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) |
#define | DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk |
#define | DMA_LIFCR_CTEIF1_Pos (9U) |
#define | DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) |
#define | DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk |
#define | DMA_LIFCR_CDMEIF1_Pos (8U) |
#define | DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) |
#define | DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk |
#define | DMA_LIFCR_CFEIF1_Pos (6U) |
#define | DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) |
#define | DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk |
#define | DMA_LIFCR_CTCIF0_Pos (5U) |
#define | DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) |
#define | DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk |
#define | DMA_LIFCR_CHTIF0_Pos (4U) |
#define | DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) |
#define | DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk |
#define | DMA_LIFCR_CTEIF0_Pos (3U) |
#define | DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) |
#define | DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk |
#define | DMA_LIFCR_CDMEIF0_Pos (2U) |
#define | DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) |
#define | DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk |
#define | DMA_LIFCR_CFEIF0_Pos (0U) |
#define | DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) |
#define | DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk |
#define | DMA_HIFCR_CTCIF7_Pos (27U) |
#define | DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) |
#define | DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk |
#define | DMA_HIFCR_CHTIF7_Pos (26U) |
#define | DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) |
#define | DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk |
#define | DMA_HIFCR_CTEIF7_Pos (25U) |
#define | DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) |
#define | DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk |
#define | DMA_HIFCR_CDMEIF7_Pos (24U) |
#define | DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) |
#define | DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk |
#define | DMA_HIFCR_CFEIF7_Pos (22U) |
#define | DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) |
#define | DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk |
#define | DMA_HIFCR_CTCIF6_Pos (21U) |
#define | DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) |
#define | DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk |
#define | DMA_HIFCR_CHTIF6_Pos (20U) |
#define | DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) |
#define | DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk |
#define | DMA_HIFCR_CTEIF6_Pos (19U) |
#define | DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) |
#define | DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk |
#define | DMA_HIFCR_CDMEIF6_Pos (18U) |
#define | DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) |
#define | DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk |
#define | DMA_HIFCR_CFEIF6_Pos (16U) |
#define | DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) |
#define | DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk |
#define | DMA_HIFCR_CTCIF5_Pos (11U) |
#define | DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) |
#define | DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk |
#define | DMA_HIFCR_CHTIF5_Pos (10U) |
#define | DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) |
#define | DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk |
#define | DMA_HIFCR_CTEIF5_Pos (9U) |
#define | DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) |
#define | DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk |
#define | DMA_HIFCR_CDMEIF5_Pos (8U) |
#define | DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) |
#define | DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk |
#define | DMA_HIFCR_CFEIF5_Pos (6U) |
#define | DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) |
#define | DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk |
#define | DMA_HIFCR_CTCIF4_Pos (5U) |
#define | DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) |
#define | DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk |
#define | DMA_HIFCR_CHTIF4_Pos (4U) |
#define | DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) |
#define | DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk |
#define | DMA_HIFCR_CTEIF4_Pos (3U) |
#define | DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) |
#define | DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk |
#define | DMA_HIFCR_CDMEIF4_Pos (2U) |
#define | DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) |
#define | DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk |
#define | DMA_HIFCR_CFEIF4_Pos (0U) |
#define | DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) |
#define | DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk |
#define | DMA_SxPAR_PA_Pos (0U) |
#define | DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) |
#define | DMA_SxPAR_PA DMA_SxPAR_PA_Msk |
#define | DMA_SxM0AR_M0A_Pos (0U) |
#define | DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) |
#define | DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk |
#define | DMA_SxM1AR_M1A_Pos (0U) |
#define | DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) |
#define | DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk |
#define | DMAMUX_CxCR_DMAREQ_ID_Pos (0U) |
#define | DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk |
#define | DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) |
#define | DMAMUX_CxCR_SOIE_Pos (8U) |
#define | DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) |
#define | DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk |
#define | DMAMUX_CxCR_EGE_Pos (9U) |
#define | DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) |
#define | DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk |
#define | DMAMUX_CxCR_SE_Pos (16U) |
#define | DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) |
#define | DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk |
#define | DMAMUX_CxCR_SPOL_Pos (17U) |
#define | DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) |
#define | DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk |
#define | DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) |
#define | DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) |
#define | DMAMUX_CxCR_NBREQ_Pos (19U) |
#define | DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) |
#define | DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk |
#define | DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) |
#define | DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) |
#define | DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) |
#define | DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) |
#define | DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) |
#define | DMAMUX_CxCR_SYNC_ID_Pos (24U) |
#define | DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) |
#define | DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk |
#define | DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) |
#define | DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) |
#define | DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) |
#define | DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) |
#define | DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) |
#define | DMAMUX_CSR_SOF0_Pos (0U) |
#define | DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) |
#define | DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk |
#define | DMAMUX_CSR_SOF1_Pos (1U) |
#define | DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) |
#define | DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk |
#define | DMAMUX_CSR_SOF2_Pos (2U) |
#define | DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) |
#define | DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk |
#define | DMAMUX_CSR_SOF3_Pos (3U) |
#define | DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) |
#define | DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk |
#define | DMAMUX_CSR_SOF4_Pos (4U) |
#define | DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) |
#define | DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk |
#define | DMAMUX_CSR_SOF5_Pos (5U) |
#define | DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) |
#define | DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk |
#define | DMAMUX_CSR_SOF6_Pos (6U) |
#define | DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) |
#define | DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk |
#define | DMAMUX_CSR_SOF7_Pos (7U) |
#define | DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) |
#define | DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk |
#define | DMAMUX_CSR_SOF8_Pos (8U) |
#define | DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) |
#define | DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk |
#define | DMAMUX_CSR_SOF9_Pos (9U) |
#define | DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) |
#define | DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk |
#define | DMAMUX_CSR_SOF10_Pos (10U) |
#define | DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) |
#define | DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk |
#define | DMAMUX_CSR_SOF11_Pos (11U) |
#define | DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) |
#define | DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk |
#define | DMAMUX_CSR_SOF12_Pos (12U) |
#define | DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) |
#define | DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk |
#define | DMAMUX_CSR_SOF13_Pos (13U) |
#define | DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) |
#define | DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk |
#define | DMAMUX_CSR_SOF14_Pos (14U) |
#define | DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) |
#define | DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk |
#define | DMAMUX_CSR_SOF15_Pos (15U) |
#define | DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) |
#define | DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk |
#define | DMAMUX_CFR_CSOF0_Pos (0U) |
#define | DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) |
#define | DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk |
#define | DMAMUX_CFR_CSOF1_Pos (1U) |
#define | DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) |
#define | DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk |
#define | DMAMUX_CFR_CSOF2_Pos (2U) |
#define | DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) |
#define | DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk |
#define | DMAMUX_CFR_CSOF3_Pos (3U) |
#define | DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) |
#define | DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk |
#define | DMAMUX_CFR_CSOF4_Pos (4U) |
#define | DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) |
#define | DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk |
#define | DMAMUX_CFR_CSOF5_Pos (5U) |
#define | DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) |
#define | DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk |
#define | DMAMUX_CFR_CSOF6_Pos (6U) |
#define | DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) |
#define | DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk |
#define | DMAMUX_CFR_CSOF7_Pos (7U) |
#define | DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) |
#define | DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk |
#define | DMAMUX_CFR_CSOF8_Pos (8U) |
#define | DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) |
#define | DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk |
#define | DMAMUX_CFR_CSOF9_Pos (9U) |
#define | DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) |
#define | DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk |
#define | DMAMUX_CFR_CSOF10_Pos (10U) |
#define | DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) |
#define | DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk |
#define | DMAMUX_CFR_CSOF11_Pos (11U) |
#define | DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) |
#define | DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk |
#define | DMAMUX_CFR_CSOF12_Pos (12U) |
#define | DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) |
#define | DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk |
#define | DMAMUX_CFR_CSOF13_Pos (13U) |
#define | DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) |
#define | DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk |
#define | DMAMUX_CFR_CSOF14_Pos (14U) |
#define | DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) |
#define | DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk |
#define | DMAMUX_CFR_CSOF15_Pos (15U) |
#define | DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) |
#define | DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk |
#define | DMAMUX_RGxCR_SIG_ID_Pos (0U) |
#define | DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) |
#define | DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk |
#define | DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) |
#define | DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) |
#define | DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) |
#define | DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) |
#define | DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) |
#define | DMAMUX_RGxCR_OIE_Pos (8U) |
#define | DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) |
#define | DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk |
#define | DMAMUX_RGxCR_GE_Pos (16U) |
#define | DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) |
#define | DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk |
#define | DMAMUX_RGxCR_GPOL_Pos (17U) |
#define | DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) |
#define | DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk |
#define | DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) |
#define | DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) |
#define | DMAMUX_RGxCR_GNBREQ_Pos (19U) |
#define | DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) |
#define | DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk |
#define | DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) |
#define | DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) |
#define | DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) |
#define | DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) |
#define | DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) |
#define | DMAMUX_RGSR_OF0_Pos (0U) |
#define | DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) |
#define | DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk |
#define | DMAMUX_RGSR_OF1_Pos (1U) |
#define | DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) |
#define | DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk |
#define | DMAMUX_RGSR_OF2_Pos (2U) |
#define | DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) |
#define | DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk |
#define | DMAMUX_RGSR_OF3_Pos (3U) |
#define | DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) |
#define | DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk |
#define | DMAMUX_RGSR_OF4_Pos (4U) |
#define | DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) |
#define | DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk |
#define | DMAMUX_RGSR_OF5_Pos (5U) |
#define | DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) |
#define | DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk |
#define | DMAMUX_RGSR_OF6_Pos (6U) |
#define | DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) |
#define | DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk |
#define | DMAMUX_RGSR_OF7_Pos (7U) |
#define | DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) |
#define | DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk |
#define | DMAMUX_RGCFR_COF0_Pos (0U) |
#define | DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) |
#define | DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk |
#define | DMAMUX_RGCFR_COF1_Pos (1U) |
#define | DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) |
#define | DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk |
#define | DMAMUX_RGCFR_COF2_Pos (2U) |
#define | DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) |
#define | DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk |
#define | DMAMUX_RGCFR_COF3_Pos (3U) |
#define | DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) |
#define | DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk |
#define | DMAMUX_RGCFR_COF4_Pos (4U) |
#define | DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) |
#define | DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk |
#define | DMAMUX_RGCFR_COF5_Pos (5U) |
#define | DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) |
#define | DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk |
#define | DMAMUX_RGCFR_COF6_Pos (6U) |
#define | DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) |
#define | DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk |
#define | DMAMUX_RGCFR_COF7_Pos (7U) |
#define | DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) |
#define | DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk |
#define | DMA2D_CR_START_Pos (0U) |
#define | DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) |
#define | DMA2D_CR_START DMA2D_CR_START_Msk |
#define | DMA2D_CR_SUSP_Pos (1U) |
#define | DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) |
#define | DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk |
#define | DMA2D_CR_ABORT_Pos (2U) |
#define | DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) |
#define | DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk |
#define | DMA2D_CR_LOM_Pos (6U) |
#define | DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) |
#define | DMA2D_CR_LOM DMA2D_CR_LOM_Msk |
#define | DMA2D_CR_TEIE_Pos (8U) |
#define | DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) |
#define | DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk |
#define | DMA2D_CR_TCIE_Pos (9U) |
#define | DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) |
#define | DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk |
#define | DMA2D_CR_TWIE_Pos (10U) |
#define | DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) |
#define | DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk |
#define | DMA2D_CR_CAEIE_Pos (11U) |
#define | DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) |
#define | DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk |
#define | DMA2D_CR_CTCIE_Pos (12U) |
#define | DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) |
#define | DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk |
#define | DMA2D_CR_CEIE_Pos (13U) |
#define | DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) |
#define | DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk |
#define | DMA2D_CR_MODE_Pos (16U) |
#define | DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) |
#define | DMA2D_CR_MODE DMA2D_CR_MODE_Msk |
#define | DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) |
#define | DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) |
#define | DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) |
#define | DMA2D_ISR_TEIF_Pos (0U) |
#define | DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) |
#define | DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk |
#define | DMA2D_ISR_TCIF_Pos (1U) |
#define | DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) |
#define | DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk |
#define | DMA2D_ISR_TWIF_Pos (2U) |
#define | DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) |
#define | DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk |
#define | DMA2D_ISR_CAEIF_Pos (3U) |
#define | DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) |
#define | DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk |
#define | DMA2D_ISR_CTCIF_Pos (4U) |
#define | DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) |
#define | DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk |
#define | DMA2D_ISR_CEIF_Pos (5U) |
#define | DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) |
#define | DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk |
#define | DMA2D_IFCR_CTEIF_Pos (0U) |
#define | DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) |
#define | DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk |
#define | DMA2D_IFCR_CTCIF_Pos (1U) |
#define | DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) |
#define | DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk |
#define | DMA2D_IFCR_CTWIF_Pos (2U) |
#define | DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) |
#define | DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk |
#define | DMA2D_IFCR_CAECIF_Pos (3U) |
#define | DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) |
#define | DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk |
#define | DMA2D_IFCR_CCTCIF_Pos (4U) |
#define | DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) |
#define | DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk |
#define | DMA2D_IFCR_CCEIF_Pos (5U) |
#define | DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) |
#define | DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk |
#define | DMA2D_FGMAR_MA_Pos (0U) |
#define | DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) |
#define | DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk |
#define | DMA2D_FGOR_LO_Pos (0U) |
#define | DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) |
#define | DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk |
#define | DMA2D_BGMAR_MA_Pos (0U) |
#define | DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) |
#define | DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk |
#define | DMA2D_BGOR_LO_Pos (0U) |
#define | DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) |
#define | DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk |
#define | DMA2D_FGPFCCR_CM_Pos (0U) |
#define | DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) |
#define | DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk |
#define | DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) |
#define | DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) |
#define | DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) |
#define | DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) |
#define | DMA2D_FGPFCCR_CCM_Pos (4U) |
#define | DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) |
#define | DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk |
#define | DMA2D_FGPFCCR_START_Pos (5U) |
#define | DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) |
#define | DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk |
#define | DMA2D_FGPFCCR_CS_Pos (8U) |
#define | DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) |
#define | DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk |
#define | DMA2D_FGPFCCR_AM_Pos (16U) |
#define | DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) |
#define | DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk |
#define | DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) |
#define | DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) |
#define | DMA2D_FGPFCCR_CSS_Pos (18U) |
#define | DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) |
#define | DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */ |
#define | DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) |
#define | DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) |
#define | DMA2D_FGPFCCR_AI_Pos (20U) |
#define | DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) |
#define | DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk |
#define | DMA2D_FGPFCCR_RBS_Pos (21U) |
#define | DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) |
#define | DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk |
#define | DMA2D_FGPFCCR_ALPHA_Pos (24U) |
#define | DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) |
#define | DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk |
#define | DMA2D_FGCOLR_BLUE_Pos (0U) |
#define | DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) |
#define | DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk |
#define | DMA2D_FGCOLR_GREEN_Pos (8U) |
#define | DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) |
#define | DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk |
#define | DMA2D_FGCOLR_RED_Pos (16U) |
#define | DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) |
#define | DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk |
#define | DMA2D_BGPFCCR_CM_Pos (0U) |
#define | DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) |
#define | DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk |
#define | DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) |
#define | DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) |
#define | DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) |
#define | DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) |
#define | DMA2D_BGPFCCR_CCM_Pos (4U) |
#define | DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) |
#define | DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk |
#define | DMA2D_BGPFCCR_START_Pos (5U) |
#define | DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) |
#define | DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk |
#define | DMA2D_BGPFCCR_CS_Pos (8U) |
#define | DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) |
#define | DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk |
#define | DMA2D_BGPFCCR_AM_Pos (16U) |
#define | DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) |
#define | DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk |
#define | DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) |
#define | DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) |
#define | DMA2D_BGPFCCR_AI_Pos (20U) |
#define | DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) |
#define | DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk |
#define | DMA2D_BGPFCCR_RBS_Pos (21U) |
#define | DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) |
#define | DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk |
#define | DMA2D_BGPFCCR_ALPHA_Pos (24U) |
#define | DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) |
#define | DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk |
#define | DMA2D_BGCOLR_BLUE_Pos (0U) |
#define | DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) |
#define | DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk |
#define | DMA2D_BGCOLR_GREEN_Pos (8U) |
#define | DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) |
#define | DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk |
#define | DMA2D_BGCOLR_RED_Pos (16U) |
#define | DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) |
#define | DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk |
#define | DMA2D_FGCMAR_MA_Pos (0U) |
#define | DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) |
#define | DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk |
#define | DMA2D_BGCMAR_MA_Pos (0U) |
#define | DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) |
#define | DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk |
#define | DMA2D_OPFCCR_CM_Pos (0U) |
#define | DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) |
#define | DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk |
#define | DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) |
#define | DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) |
#define | DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) |
#define | DMA2D_OPFCCR_SB_Pos (8U) |
#define | DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) |
#define | DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk |
#define | DMA2D_OPFCCR_AI_Pos (20U) |
#define | DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) |
#define | DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk |
#define | DMA2D_OPFCCR_RBS_Pos (21U) |
#define | DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) |
#define | DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk |
#define | DMA2D_OCOLR_BLUE_1_Pos (0U) |
#define | DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/ |
#define | DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk |
#define | DMA2D_OCOLR_GREEN_1_Pos (8U) |
#define | DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/ |
#define | DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk |
#define | DMA2D_OCOLR_RED_1_Pos (16U) |
#define | DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */ |
#define | DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk |
#define | DMA2D_OCOLR_ALPHA_1_Pos (24U) |
#define | DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/ |
#define | DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk |
#define | DMA2D_OCOLR_BLUE_2_Pos (0U) |
#define | DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/ |
#define | DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk |
#define | DMA2D_OCOLR_GREEN_2_Pos (5U) |
#define | DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */ |
#define | DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk |
#define | DMA2D_OCOLR_RED_2_Pos (11U) |
#define | DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/ |
#define | DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk |
#define | DMA2D_OCOLR_BLUE_3_Pos (0U) |
#define | DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/ |
#define | DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk |
#define | DMA2D_OCOLR_GREEN_3_Pos (5U) |
#define | DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/ |
#define | DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk |
#define | DMA2D_OCOLR_RED_3_Pos (10U) |
#define | DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/ |
#define | DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk |
#define | DMA2D_OCOLR_ALPHA_3_Pos (15U) |
#define | DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/ |
#define | DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk |
#define | DMA2D_OCOLR_BLUE_4_Pos (0U) |
#define | DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/ |
#define | DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk |
#define | DMA2D_OCOLR_GREEN_4_Pos (4U) |
#define | DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/ |
#define | DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk |
#define | DMA2D_OCOLR_RED_4_Pos (8U) |
#define | DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/ |
#define | DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk |
#define | DMA2D_OCOLR_ALPHA_4_Pos (12U) |
#define | DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/ |
#define | DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk |
#define | DMA2D_OMAR_MA_Pos (0U) |
#define | DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) |
#define | DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk |
#define | DMA2D_OOR_LO_Pos (0U) |
#define | DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) |
#define | DMA2D_OOR_LO DMA2D_OOR_LO_Msk |
#define | DMA2D_NLR_NL_Pos (0U) |
#define | DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) |
#define | DMA2D_NLR_NL DMA2D_NLR_NL_Msk |
#define | DMA2D_NLR_PL_Pos (16U) |
#define | DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) |
#define | DMA2D_NLR_PL DMA2D_NLR_PL_Msk |
#define | DMA2D_LWR_LW_Pos (0U) |
#define | DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) |
#define | DMA2D_LWR_LW DMA2D_LWR_LW_Msk |
#define | DMA2D_AMTCR_EN_Pos (0U) |
#define | DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) |
#define | DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk |
#define | DMA2D_AMTCR_DT_Pos (8U) |
#define | DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) |
#define | DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk |
#define | EXTI_RTSR1_TR_Pos (0U) |
#define | EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) |
#define | EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk |
#define | EXTI_RTSR1_TR0_Pos (0U) |
#define | EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) |
#define | EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk |
#define | EXTI_RTSR1_TR1_Pos (1U) |
#define | EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) |
#define | EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk |
#define | EXTI_RTSR1_TR2_Pos (2U) |
#define | EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) |
#define | EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk |
#define | EXTI_RTSR1_TR3_Pos (3U) |
#define | EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) |
#define | EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk |
#define | EXTI_RTSR1_TR4_Pos (4U) |
#define | EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) |
#define | EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk |
#define | EXTI_RTSR1_TR5_Pos (5U) |
#define | EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) |
#define | EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk |
#define | EXTI_RTSR1_TR6_Pos (6U) |
#define | EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) |
#define | EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk |
#define | EXTI_RTSR1_TR7_Pos (7U) |
#define | EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) |
#define | EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk |
#define | EXTI_RTSR1_TR8_Pos (8U) |
#define | EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) |
#define | EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk |
#define | EXTI_RTSR1_TR9_Pos (9U) |
#define | EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) |
#define | EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk |
#define | EXTI_RTSR1_TR10_Pos (10U) |
#define | EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) |
#define | EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk |
#define | EXTI_RTSR1_TR11_Pos (11U) |
#define | EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) |
#define | EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk |
#define | EXTI_RTSR1_TR12_Pos (12U) |
#define | EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) |
#define | EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk |
#define | EXTI_RTSR1_TR13_Pos (13U) |
#define | EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) |
#define | EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk |
#define | EXTI_RTSR1_TR14_Pos (14U) |
#define | EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) |
#define | EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk |
#define | EXTI_RTSR1_TR15_Pos (15U) |
#define | EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) |
#define | EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk |
#define | EXTI_RTSR1_TR16_Pos (16U) |
#define | EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) |
#define | EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk |
#define | EXTI_RTSR1_TR17_Pos (17U) |
#define | EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) |
#define | EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk |
#define | EXTI_RTSR1_TR18_Pos (18U) |
#define | EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) |
#define | EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk |
#define | EXTI_RTSR1_TR19_Pos (19U) |
#define | EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) |
#define | EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk |
#define | EXTI_RTSR1_TR20_Pos (20U) |
#define | EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) |
#define | EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk |
#define | EXTI_RTSR1_TR21_Pos (21U) |
#define | EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) |
#define | EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk |
#define | EXTI_FTSR1_TR_Pos (0U) |
#define | EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) |
#define | EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk |
#define | EXTI_FTSR1_TR0_Pos (0U) |
#define | EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) |
#define | EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk |
#define | EXTI_FTSR1_TR1_Pos (1U) |
#define | EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) |
#define | EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk |
#define | EXTI_FTSR1_TR2_Pos (2U) |
#define | EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) |
#define | EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk |
#define | EXTI_FTSR1_TR3_Pos (3U) |
#define | EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) |
#define | EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk |
#define | EXTI_FTSR1_TR4_Pos (4U) |
#define | EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) |
#define | EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk |
#define | EXTI_FTSR1_TR5_Pos (5U) |
#define | EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) |
#define | EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk |
#define | EXTI_FTSR1_TR6_Pos (6U) |
#define | EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) |
#define | EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk |
#define | EXTI_FTSR1_TR7_Pos (7U) |
#define | EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) |
#define | EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk |
#define | EXTI_FTSR1_TR8_Pos (8U) |
#define | EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) |
#define | EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk |
#define | EXTI_FTSR1_TR9_Pos (9U) |
#define | EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) |
#define | EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk |
#define | EXTI_FTSR1_TR10_Pos (10U) |
#define | EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) |
#define | EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk |
#define | EXTI_FTSR1_TR11_Pos (11U) |
#define | EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) |
#define | EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk |
#define | EXTI_FTSR1_TR12_Pos (12U) |
#define | EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) |
#define | EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk |
#define | EXTI_FTSR1_TR13_Pos (13U) |
#define | EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) |
#define | EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk |
#define | EXTI_FTSR1_TR14_Pos (14U) |
#define | EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) |
#define | EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk |
#define | EXTI_FTSR1_TR15_Pos (15U) |
#define | EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) |
#define | EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk |
#define | EXTI_FTSR1_TR16_Pos (16U) |
#define | EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) |
#define | EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk |
#define | EXTI_FTSR1_TR17_Pos (17U) |
#define | EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) |
#define | EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk |
#define | EXTI_FTSR1_TR18_Pos (18U) |
#define | EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) |
#define | EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk |
#define | EXTI_FTSR1_TR19_Pos (19U) |
#define | EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) |
#define | EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk |
#define | EXTI_FTSR1_TR20_Pos (20U) |
#define | EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) |
#define | EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk |
#define | EXTI_FTSR1_TR21_Pos (21U) |
#define | EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) |
#define | EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk |
#define | EXTI_SWIER1_SWIER0_Pos (0U) |
#define | EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) |
#define | EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk |
#define | EXTI_SWIER1_SWIER1_Pos (1U) |
#define | EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) |
#define | EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk |
#define | EXTI_SWIER1_SWIER2_Pos (2U) |
#define | EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) |
#define | EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk |
#define | EXTI_SWIER1_SWIER3_Pos (3U) |
#define | EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) |
#define | EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk |
#define | EXTI_SWIER1_SWIER4_Pos (4U) |
#define | EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) |
#define | EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk |
#define | EXTI_SWIER1_SWIER5_Pos (5U) |
#define | EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) |
#define | EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk |
#define | EXTI_SWIER1_SWIER6_Pos (6U) |
#define | EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) |
#define | EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk |
#define | EXTI_SWIER1_SWIER7_Pos (7U) |
#define | EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) |
#define | EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk |
#define | EXTI_SWIER1_SWIER8_Pos (8U) |
#define | EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) |
#define | EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk |
#define | EXTI_SWIER1_SWIER9_Pos (9U) |
#define | EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) |
#define | EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk |
#define | EXTI_SWIER1_SWIER10_Pos (10U) |
#define | EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) |
#define | EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk |
#define | EXTI_SWIER1_SWIER11_Pos (11U) |
#define | EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) |
#define | EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk |
#define | EXTI_SWIER1_SWIER12_Pos (12U) |
#define | EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) |
#define | EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk |
#define | EXTI_SWIER1_SWIER13_Pos (13U) |
#define | EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) |
#define | EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk |
#define | EXTI_SWIER1_SWIER14_Pos (14U) |
#define | EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) |
#define | EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk |
#define | EXTI_SWIER1_SWIER15_Pos (15U) |
#define | EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) |
#define | EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk |
#define | EXTI_SWIER1_SWIER16_Pos (16U) |
#define | EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) |
#define | EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk |
#define | EXTI_SWIER1_SWIER17_Pos (17U) |
#define | EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) |
#define | EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk |
#define | EXTI_SWIER1_SWIER18_Pos (18U) |
#define | EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) |
#define | EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk |
#define | EXTI_SWIER1_SWIER19_Pos (19U) |
#define | EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) |
#define | EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk |
#define | EXTI_SWIER1_SWIER20_Pos (20U) |
#define | EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) |
#define | EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk |
#define | EXTI_SWIER1_SWIER21_Pos (21U) |
#define | EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) |
#define | EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk |
#define | EXTI_D3PMR1_MR0_Pos (0U) |
#define | EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) |
#define | EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk |
#define | EXTI_D3PMR1_MR1_Pos (1U) |
#define | EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) |
#define | EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk |
#define | EXTI_D3PMR1_MR2_Pos (2U) |
#define | EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) |
#define | EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk |
#define | EXTI_D3PMR1_MR3_Pos (3U) |
#define | EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) |
#define | EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk |
#define | EXTI_D3PMR1_MR4_Pos (4U) |
#define | EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) |
#define | EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk |
#define | EXTI_D3PMR1_MR5_Pos (5U) |
#define | EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) |
#define | EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk |
#define | EXTI_D3PMR1_MR6_Pos (6U) |
#define | EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) |
#define | EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk |
#define | EXTI_D3PMR1_MR7_Pos (7U) |
#define | EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) |
#define | EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk |
#define | EXTI_D3PMR1_MR8_Pos (8U) |
#define | EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) |
#define | EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk |
#define | EXTI_D3PMR1_MR9_Pos (9U) |
#define | EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) |
#define | EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk |
#define | EXTI_D3PMR1_MR10_Pos (10U) |
#define | EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) |
#define | EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk |
#define | EXTI_D3PMR1_MR11_Pos (11U) |
#define | EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) |
#define | EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk |
#define | EXTI_D3PMR1_MR12_Pos (12U) |
#define | EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) |
#define | EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk |
#define | EXTI_D3PMR1_MR13_Pos (13U) |
#define | EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) |
#define | EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk |
#define | EXTI_D3PMR1_MR14_Pos (14U) |
#define | EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) |
#define | EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk |
#define | EXTI_D3PMR1_MR15_Pos (15U) |
#define | EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) |
#define | EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk |
#define | EXTI_D3PMR1_MR19_Pos (19U) |
#define | EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) |
#define | EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk |
#define | EXTI_D3PMR1_MR20_Pos (20U) |
#define | EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) |
#define | EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk |
#define | EXTI_D3PMR1_MR21_Pos (21U) |
#define | EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) |
#define | EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk |
#define | EXTI_D3PMR1_MR25_Pos (24U) |
#define | EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) |
#define | EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk |
#define | EXTI_D3PCR1L_PCS0_Pos (0U) |
#define | EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) |
#define | EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk |
#define | EXTI_D3PCR1L_PCS1_Pos (2U) |
#define | EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) |
#define | EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk |
#define | EXTI_D3PCR1L_PCS2_Pos (4U) |
#define | EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) |
#define | EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk |
#define | EXTI_D3PCR1L_PCS3_Pos (6U) |
#define | EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) |
#define | EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk |
#define | EXTI_D3PCR1L_PCS4_Pos (8U) |
#define | EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) |
#define | EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk |
#define | EXTI_D3PCR1L_PCS5_Pos (10U) |
#define | EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) |
#define | EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk |
#define | EXTI_D3PCR1L_PCS6_Pos (12U) |
#define | EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) |
#define | EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk |
#define | EXTI_D3PCR1L_PCS7_Pos (14U) |
#define | EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) |
#define | EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk |
#define | EXTI_D3PCR1L_PCS8_Pos (16U) |
#define | EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) |
#define | EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk |
#define | EXTI_D3PCR1L_PCS9_Pos (18U) |
#define | EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) |
#define | EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk |
#define | EXTI_D3PCR1L_PCS10_Pos (20U) |
#define | EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) |
#define | EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk |
#define | EXTI_D3PCR1L_PCS11_Pos (22U) |
#define | EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) |
#define | EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk |
#define | EXTI_D3PCR1L_PCS12_Pos (24U) |
#define | EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) |
#define | EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk |
#define | EXTI_D3PCR1L_PCS13_Pos (26U) |
#define | EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) |
#define | EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk |
#define | EXTI_D3PCR1L_PCS14_Pos (28U) |
#define | EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) |
#define | EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk |
#define | EXTI_D3PCR1L_PCS15_Pos (30U) |
#define | EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) |
#define | EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk |
#define | EXTI_D3PCR1H_PCS19_Pos (6U) |
#define | EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) |
#define | EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk |
#define | EXTI_D3PCR1H_PCS20_Pos (8U) |
#define | EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) |
#define | EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk |
#define | EXTI_D3PCR1H_PCS21_Pos (10U) |
#define | EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) |
#define | EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk |
#define | EXTI_D3PCR1H_PCS25_Pos (18U) |
#define | EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) |
#define | EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk |
#define | EXTI_RTSR2_TR_Pos (17U) |
#define | EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) |
#define | EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk |
#define | EXTI_RTSR2_TR49_Pos (17U) |
#define | EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) |
#define | EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk |
#define | EXTI_RTSR2_TR51_Pos (19U) |
#define | EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) |
#define | EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk |
#define | EXTI_FTSR2_TR_Pos (17U) |
#define | EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) |
#define | EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk |
#define | EXTI_FTSR2_TR49_Pos (17U) |
#define | EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) |
#define | EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk |
#define | EXTI_FTSR2_TR51_Pos (19U) |
#define | EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) |
#define | EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk |
#define | EXTI_SWIER2_SWIER49_Pos (17U) |
#define | EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) |
#define | EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk |
#define | EXTI_SWIER2_SWIER51_Pos (19U) |
#define | EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) |
#define | EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk |
#define | EXTI_D3PMR2_MR34_Pos (2U) |
#define | EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) |
#define | EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk |
#define | EXTI_D3PMR2_MR35_Pos (3U) |
#define | EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) |
#define | EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk |
#define | EXTI_D3PMR2_MR41_Pos (9U) |
#define | EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) |
#define | EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk |
#define | EXTI_D3PMR2_MR48_Pos (16U) |
#define | EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) |
#define | EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk |
#define | EXTI_D3PMR2_MR49_Pos (17U) |
#define | EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) |
#define | EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk |
#define | EXTI_D3PMR2_MR50_Pos (18U) |
#define | EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) |
#define | EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk |
#define | EXTI_D3PMR2_MR51_Pos (19U) |
#define | EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) |
#define | EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk |
#define | EXTI_D3PMR2_MR52_Pos (20U) |
#define | EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) |
#define | EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk |
#define | EXTI_D3PMR2_MR53_Pos (21U) |
#define | EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) |
#define | EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk |
#define | EXTI_D3PCR2L_PCS34_Pos (4U) |
#define | EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) |
#define | EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk |
#define | EXTI_D3PCR2L_PCS35_Pos (6U) |
#define | EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) |
#define | EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk |
#define | EXTI_D3PCR2L_PCS41_Pos (18U) |
#define | EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) |
#define | EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk |
#define | EXTI_D3PCR2H_PCS48_Pos (0U) |
#define | EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) |
#define | EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk |
#define | EXTI_D3PCR2H_PCS49_Pos (2U) |
#define | EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) |
#define | EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk |
#define | EXTI_D3PCR2H_PCS50_Pos (4U) |
#define | EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) |
#define | EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk |
#define | EXTI_D3PCR2H_PCS51_Pos (6U) |
#define | EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) |
#define | EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk |
#define | EXTI_D3PCR2H_PCS52_Pos (8U) |
#define | EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) |
#define | EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk |
#define | EXTI_D3PCR2H_PCS53_Pos (10U) |
#define | EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) |
#define | EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk |
#define | EXTI_RTSR3_TR_Pos (18U) |
#define | EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) |
#define | EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk |
#define | EXTI_RTSR3_TR82_Pos (18U) |
#define | EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) |
#define | EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk |
#define | EXTI_RTSR3_TR84_Pos (20U) |
#define | EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) |
#define | EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk |
#define | EXTI_RTSR3_TR85_Pos (21U) |
#define | EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) |
#define | EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk |
#define | EXTI_RTSR3_TR86_Pos (22U) |
#define | EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) |
#define | EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk |
#define | EXTI_FTSR3_TR_Pos (18U) |
#define | EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) |
#define | EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk |
#define | EXTI_FTSR3_TR82_Pos (18U) |
#define | EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) |
#define | EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk |
#define | EXTI_FTSR3_TR84_Pos (20U) |
#define | EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) |
#define | EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk |
#define | EXTI_FTSR3_TR85_Pos (21U) |
#define | EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) |
#define | EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk |
#define | EXTI_FTSR3_TR86_Pos (22U) |
#define | EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) |
#define | EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk |
#define | EXTI_SWIER3_SWI_Pos (18U) |
#define | EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) |
#define | EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk |
#define | EXTI_SWIER3_SWIER82_Pos (18U) |
#define | EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) |
#define | EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk |
#define | EXTI_SWIER3_SWIER84_Pos (20U) |
#define | EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) |
#define | EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk |
#define | EXTI_SWIER3_SWIER85_Pos (21U) |
#define | EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) |
#define | EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk |
#define | EXTI_SWIER3_SWIER86_Pos (22U) |
#define | EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) |
#define | EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk |
#define | EXTI_IMR1_IM_Pos (0U) |
#define | EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) |
#define | EXTI_IMR1_IM EXTI_IMR1_IM_Msk |
#define | EXTI_IMR1_IM0_Pos (0U) |
#define | EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) |
#define | EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk |
#define | EXTI_IMR1_IM1_Pos (1U) |
#define | EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) |
#define | EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk |
#define | EXTI_IMR1_IM2_Pos (2U) |
#define | EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) |
#define | EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk |
#define | EXTI_IMR1_IM3_Pos (3U) |
#define | EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) |
#define | EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk |
#define | EXTI_IMR1_IM4_Pos (4U) |
#define | EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) |
#define | EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk |
#define | EXTI_IMR1_IM5_Pos (5U) |
#define | EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) |
#define | EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk |
#define | EXTI_IMR1_IM6_Pos (6U) |
#define | EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) |
#define | EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk |
#define | EXTI_IMR1_IM7_Pos (7U) |
#define | EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) |
#define | EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk |
#define | EXTI_IMR1_IM8_Pos (8U) |
#define | EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) |
#define | EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk |
#define | EXTI_IMR1_IM9_Pos (9U) |
#define | EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) |
#define | EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk |
#define | EXTI_IMR1_IM10_Pos (10U) |
#define | EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) |
#define | EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk |
#define | EXTI_IMR1_IM11_Pos (11U) |
#define | EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) |
#define | EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk |
#define | EXTI_IMR1_IM12_Pos (12U) |
#define | EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) |
#define | EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk |
#define | EXTI_IMR1_IM13_Pos (13U) |
#define | EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) |
#define | EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk |
#define | EXTI_IMR1_IM14_Pos (14U) |
#define | EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) |
#define | EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk |
#define | EXTI_IMR1_IM15_Pos (15U) |
#define | EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) |
#define | EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk |
#define | EXTI_IMR1_IM16_Pos (16U) |
#define | EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) |
#define | EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk |
#define | EXTI_IMR1_IM17_Pos (17U) |
#define | EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) |
#define | EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk |
#define | EXTI_IMR1_IM18_Pos (18U) |
#define | EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) |
#define | EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk |
#define | EXTI_IMR1_IM19_Pos (19U) |
#define | EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) |
#define | EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk |
#define | EXTI_IMR1_IM20_Pos (20U) |
#define | EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) |
#define | EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk |
#define | EXTI_IMR1_IM21_Pos (21U) |
#define | EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) |
#define | EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk |
#define | EXTI_IMR1_IM22_Pos (22U) |
#define | EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) |
#define | EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk |
#define | EXTI_IMR1_IM23_Pos (23U) |
#define | EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) |
#define | EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk |
#define | EXTI_IMR1_IM24_Pos (24U) |
#define | EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) |
#define | EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk |
#define | EXTI_IMR1_IM25_Pos (25U) |
#define | EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) |
#define | EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk |
#define | EXTI_IMR1_IM26_Pos (26U) |
#define | EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) |
#define | EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk |
#define | EXTI_IMR1_IM27_Pos (27U) |
#define | EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) |
#define | EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk |
#define | EXTI_IMR1_IM28_Pos (28U) |
#define | EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) |
#define | EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk |
#define | EXTI_IMR1_IM29_Pos (29U) |
#define | EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) |
#define | EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk |
#define | EXTI_IMR1_IM30_Pos (30U) |
#define | EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) |
#define | EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk |
#define | EXTI_IMR1_IM31_Pos (31U) |
#define | EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) |
#define | EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk |
#define | EXTI_EMR1_EM_Pos (0U) |
#define | EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) |
#define | EXTI_EMR1_EM EXTI_EMR1_EM_Msk |
#define | EXTI_EMR1_EM0_Pos (0U) |
#define | EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) |
#define | EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk |
#define | EXTI_EMR1_EM1_Pos (1U) |
#define | EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) |
#define | EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk |
#define | EXTI_EMR1_EM2_Pos (2U) |
#define | EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) |
#define | EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk |
#define | EXTI_EMR1_EM3_Pos (3U) |
#define | EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) |
#define | EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk |
#define | EXTI_EMR1_EM4_Pos (4U) |
#define | EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) |
#define | EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk |
#define | EXTI_EMR1_EM5_Pos (5U) |
#define | EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) |
#define | EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk |
#define | EXTI_EMR1_EM6_Pos (6U) |
#define | EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) |
#define | EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk |
#define | EXTI_EMR1_EM7_Pos (7U) |
#define | EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) |
#define | EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk |
#define | EXTI_EMR1_EM8_Pos (8U) |
#define | EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) |
#define | EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk |
#define | EXTI_EMR1_EM9_Pos (9U) |
#define | EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) |
#define | EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk |
#define | EXTI_EMR1_EM10_Pos (10U) |
#define | EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) |
#define | EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk |
#define | EXTI_EMR1_EM11_Pos (11U) |
#define | EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) |
#define | EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk |
#define | EXTI_EMR1_EM12_Pos (12U) |
#define | EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) |
#define | EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk |
#define | EXTI_EMR1_EM13_Pos (13U) |
#define | EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) |
#define | EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk |
#define | EXTI_EMR1_EM14_Pos (14U) |
#define | EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) |
#define | EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk |
#define | EXTI_EMR1_EM15_Pos (15U) |
#define | EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) |
#define | EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk |
#define | EXTI_EMR1_EM16_Pos (16U) |
#define | EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) |
#define | EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk |
#define | EXTI_EMR1_EM17_Pos (17U) |
#define | EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) |
#define | EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk |
#define | EXTI_EMR1_EM18_Pos (18U) |
#define | EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) |
#define | EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk |
#define | EXTI_EMR1_EM20_Pos (20U) |
#define | EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) |
#define | EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk |
#define | EXTI_EMR1_EM21_Pos (21U) |
#define | EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) |
#define | EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk |
#define | EXTI_EMR1_EM22_Pos (22U) |
#define | EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) |
#define | EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk |
#define | EXTI_EMR1_EM23_Pos (23U) |
#define | EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) |
#define | EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk |
#define | EXTI_EMR1_EM24_Pos (24U) |
#define | EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) |
#define | EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk |
#define | EXTI_EMR1_EM25_Pos (25U) |
#define | EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) |
#define | EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk |
#define | EXTI_EMR1_EM26_Pos (26U) |
#define | EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) |
#define | EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk |
#define | EXTI_EMR1_EM27_Pos (27U) |
#define | EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) |
#define | EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk |
#define | EXTI_EMR1_EM28_Pos (28U) |
#define | EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) |
#define | EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk |
#define | EXTI_EMR1_EM29_Pos (29U) |
#define | EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) |
#define | EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk |
#define | EXTI_EMR1_EM30_Pos (30U) |
#define | EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) |
#define | EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk |
#define | EXTI_EMR1_EM31_Pos (31U) |
#define | EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) |
#define | EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk |
#define | EXTI_PR1_PR_Pos (0U) |
#define | EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) |
#define | EXTI_PR1_PR EXTI_PR1_PR_Msk |
#define | EXTI_PR1_PR0_Pos (0U) |
#define | EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) |
#define | EXTI_PR1_PR0 EXTI_PR1_PR0_Msk |
#define | EXTI_PR1_PR1_Pos (1U) |
#define | EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) |
#define | EXTI_PR1_PR1 EXTI_PR1_PR1_Msk |
#define | EXTI_PR1_PR2_Pos (2U) |
#define | EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) |
#define | EXTI_PR1_PR2 EXTI_PR1_PR2_Msk |
#define | EXTI_PR1_PR3_Pos (3U) |
#define | EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) |
#define | EXTI_PR1_PR3 EXTI_PR1_PR3_Msk |
#define | EXTI_PR1_PR4_Pos (4U) |
#define | EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) |
#define | EXTI_PR1_PR4 EXTI_PR1_PR4_Msk |
#define | EXTI_PR1_PR5_Pos (5U) |
#define | EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) |
#define | EXTI_PR1_PR5 EXTI_PR1_PR5_Msk |
#define | EXTI_PR1_PR6_Pos (6U) |
#define | EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) |
#define | EXTI_PR1_PR6 EXTI_PR1_PR6_Msk |
#define | EXTI_PR1_PR7_Pos (7U) |
#define | EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) |
#define | EXTI_PR1_PR7 EXTI_PR1_PR7_Msk |
#define | EXTI_PR1_PR8_Pos (8U) |
#define | EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) |
#define | EXTI_PR1_PR8 EXTI_PR1_PR8_Msk |
#define | EXTI_PR1_PR9_Pos (9U) |
#define | EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) |
#define | EXTI_PR1_PR9 EXTI_PR1_PR9_Msk |
#define | EXTI_PR1_PR10_Pos (10U) |
#define | EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) |
#define | EXTI_PR1_PR10 EXTI_PR1_PR10_Msk |
#define | EXTI_PR1_PR11_Pos (11U) |
#define | EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) |
#define | EXTI_PR1_PR11 EXTI_PR1_PR11_Msk |
#define | EXTI_PR1_PR12_Pos (12U) |
#define | EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) |
#define | EXTI_PR1_PR12 EXTI_PR1_PR12_Msk |
#define | EXTI_PR1_PR13_Pos (13U) |
#define | EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) |
#define | EXTI_PR1_PR13 EXTI_PR1_PR13_Msk |
#define | EXTI_PR1_PR14_Pos (14U) |
#define | EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) |
#define | EXTI_PR1_PR14 EXTI_PR1_PR14_Msk |
#define | EXTI_PR1_PR15_Pos (15U) |
#define | EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) |
#define | EXTI_PR1_PR15 EXTI_PR1_PR15_Msk |
#define | EXTI_PR1_PR16_Pos (16U) |
#define | EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) |
#define | EXTI_PR1_PR16 EXTI_PR1_PR16_Msk |
#define | EXTI_PR1_PR17_Pos (17U) |
#define | EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) |
#define | EXTI_PR1_PR17 EXTI_PR1_PR17_Msk |
#define | EXTI_PR1_PR18_Pos (18U) |
#define | EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) |
#define | EXTI_PR1_PR18 EXTI_PR1_PR18_Msk |
#define | EXTI_PR1_PR19_Pos (19U) |
#define | EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) |
#define | EXTI_PR1_PR19 EXTI_PR1_PR19_Msk |
#define | EXTI_PR1_PR20_Pos (20U) |
#define | EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) |
#define | EXTI_PR1_PR20 EXTI_PR1_PR20_Msk |
#define | EXTI_PR1_PR21_Pos (21U) |
#define | EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) |
#define | EXTI_PR1_PR21 EXTI_PR1_PR21_Msk |
#define | EXTI_IMR2_IM_Pos (0U) |
#define | EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) |
#define | EXTI_IMR2_IM EXTI_IMR2_IM_Msk |
#define | EXTI_IMR2_IM32_Pos (0U) |
#define | EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) |
#define | EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk |
#define | EXTI_IMR2_IM33_Pos (1U) |
#define | EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) |
#define | EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk |
#define | EXTI_IMR2_IM34_Pos (2U) |
#define | EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) |
#define | EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk |
#define | EXTI_IMR2_IM35_Pos (3U) |
#define | EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) |
#define | EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk |
#define | EXTI_IMR2_IM36_Pos (4U) |
#define | EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) |
#define | EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk |
#define | EXTI_IMR2_IM37_Pos (5U) |
#define | EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) |
#define | EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk |
#define | EXTI_IMR2_IM38_Pos (6U) |
#define | EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) |
#define | EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk |
#define | EXTI_IMR2_IM39_Pos (7U) |
#define | EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) |
#define | EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk |
#define | EXTI_IMR2_IM40_Pos (8U) |
#define | EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) |
#define | EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk |
#define | EXTI_IMR2_IM41_Pos (9U) |
#define | EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) |
#define | EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk |
#define | EXTI_IMR2_IM42_Pos (10U) |
#define | EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) |
#define | EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk |
#define | EXTI_IMR2_IM43_Pos (11U) |
#define | EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) |
#define | EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk |
#define | EXTI_IMR2_IM44_Pos (12U) |
#define | EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) |
#define | EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk |
#define | EXTI_IMR2_IM46_Pos (14U) |
#define | EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) |
#define | EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk |
#define | EXTI_IMR2_IM47_Pos (15U) |
#define | EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) |
#define | EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk |
#define | EXTI_IMR2_IM48_Pos (16U) |
#define | EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) |
#define | EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk |
#define | EXTI_IMR2_IM49_Pos (17U) |
#define | EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) |
#define | EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk |
#define | EXTI_IMR2_IM50_Pos (18U) |
#define | EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) |
#define | EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk |
#define | EXTI_IMR2_IM51_Pos (19U) |
#define | EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) |
#define | EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk |
#define | EXTI_IMR2_IM52_Pos (20U) |
#define | EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) |
#define | EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk |
#define | EXTI_IMR2_IM53_Pos (21U) |
#define | EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) |
#define | EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk |
#define | EXTI_IMR2_IM54_Pos (22U) |
#define | EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) |
#define | EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk |
#define | EXTI_IMR2_IM55_Pos (23U) |
#define | EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) |
#define | EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk |
#define | EXTI_IMR2_IM56_Pos (24U) |
#define | EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) |
#define | EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk |
#define | EXTI_IMR2_IM57_Pos (25U) |
#define | EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) |
#define | EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk |
#define | EXTI_IMR2_IM58_Pos (26U) |
#define | EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) |
#define | EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk |
#define | EXTI_IMR2_IM59_Pos (27U) |
#define | EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) |
#define | EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk |
#define | EXTI_IMR2_IM60_Pos (28U) |
#define | EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) |
#define | EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk |
#define | EXTI_IMR2_IM61_Pos (29U) |
#define | EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) |
#define | EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk |
#define | EXTI_IMR2_IM62_Pos (30U) |
#define | EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) |
#define | EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk |
#define | EXTI_IMR2_IM63_Pos (31U) |
#define | EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) |
#define | EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk |
#define | EXTI_EMR2_EM_Pos (0U) |
#define | EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) |
#define | EXTI_EMR2_EM EXTI_EMR2_EM_Msk |
#define | EXTI_EMR2_EM32_Pos (0U) |
#define | EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) |
#define | EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk |
#define | EXTI_EMR2_EM33_Pos (1U) |
#define | EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) |
#define | EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk |
#define | EXTI_EMR2_EM34_Pos (2U) |
#define | EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) |
#define | EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk |
#define | EXTI_EMR2_EM35_Pos (3U) |
#define | EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) |
#define | EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk |
#define | EXTI_EMR2_EM36_Pos (4U) |
#define | EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) |
#define | EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk |
#define | EXTI_EMR2_EM37_Pos (5U) |
#define | EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) |
#define | EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk |
#define | EXTI_EMR2_EM38_Pos (6U) |
#define | EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) |
#define | EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk |
#define | EXTI_EMR2_EM39_Pos (7U) |
#define | EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) |
#define | EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk |
#define | EXTI_EMR2_EM40_Pos (8U) |
#define | EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) |
#define | EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk |
#define | EXTI_EMR2_EM41_Pos (9U) |
#define | EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) |
#define | EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk |
#define | EXTI_EMR2_EM42_Pos (10U) |
#define | EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) |
#define | EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk |
#define | EXTI_EMR2_EM43_Pos (11U) |
#define | EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) |
#define | EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk |
#define | EXTI_EMR2_EM44_Pos (12U) |
#define | EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) |
#define | EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk |
#define | EXTI_EMR2_EM46_Pos (14U) |
#define | EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) |
#define | EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk |
#define | EXTI_EMR2_EM47_Pos (15U) |
#define | EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) |
#define | EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk |
#define | EXTI_EMR2_EM48_Pos (16U) |
#define | EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) |
#define | EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk |
#define | EXTI_EMR2_EM49_Pos (17U) |
#define | EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) |
#define | EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk |
#define | EXTI_EMR2_EM50_Pos (18U) |
#define | EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) |
#define | EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk |
#define | EXTI_EMR2_EM51_Pos (19U) |
#define | EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) |
#define | EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk |
#define | EXTI_EMR2_EM52_Pos (20U) |
#define | EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) |
#define | EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk |
#define | EXTI_EMR2_EM53_Pos (21U) |
#define | EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) |
#define | EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk |
#define | EXTI_EMR2_EM54_Pos (22U) |
#define | EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) |
#define | EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk |
#define | EXTI_EMR2_EM55_Pos (23U) |
#define | EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) |
#define | EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk |
#define | EXTI_EMR2_EM56_Pos (24U) |
#define | EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) |
#define | EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk |
#define | EXTI_EMR2_EM57_Pos (25U) |
#define | EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) |
#define | EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk |
#define | EXTI_EMR2_EM58_Pos (26U) |
#define | EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) |
#define | EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk |
#define | EXTI_EMR2_EM59_Pos (27U) |
#define | EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) |
#define | EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk |
#define | EXTI_EMR2_EM60_Pos (28U) |
#define | EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) |
#define | EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk |
#define | EXTI_EMR2_EM61_Pos (29U) |
#define | EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) |
#define | EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk |
#define | EXTI_EMR2_EM62_Pos (30U) |
#define | EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) |
#define | EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk |
#define | EXTI_EMR2_EM63_Pos (31U) |
#define | EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) |
#define | EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk |
#define | EXTI_PR2_PR_Pos (17U) |
#define | EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) |
#define | EXTI_PR2_PR EXTI_PR2_PR_Msk |
#define | EXTI_PR2_PR49_Pos (17U) |
#define | EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) |
#define | EXTI_PR2_PR49 EXTI_PR2_PR49_Msk |
#define | EXTI_PR2_PR51_Pos (19U) |
#define | EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) |
#define | EXTI_PR2_PR51 EXTI_PR2_PR51_Msk |
#define | EXTI_IMR3_IM_Pos (0U) |
#define | EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) |
#define | EXTI_IMR3_IM EXTI_IMR3_IM_Msk |
#define | EXTI_IMR3_IM64_Pos (0U) |
#define | EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) |
#define | EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk |
#define | EXTI_IMR3_IM65_Pos (1U) |
#define | EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) |
#define | EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk |
#define | EXTI_IMR3_IM66_Pos (2U) |
#define | EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) |
#define | EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk |
#define | EXTI_IMR3_IM67_Pos (3U) |
#define | EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) |
#define | EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk |
#define | EXTI_IMR3_IM68_Pos (4U) |
#define | EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) |
#define | EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk |
#define | EXTI_IMR3_IM69_Pos (5U) |
#define | EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) |
#define | EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk |
#define | EXTI_IMR3_IM70_Pos (6U) |
#define | EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) |
#define | EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk |
#define | EXTI_IMR3_IM71_Pos (7U) |
#define | EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) |
#define | EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk |
#define | EXTI_IMR3_IM72_Pos (8U) |
#define | EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) |
#define | EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk |
#define | EXTI_IMR3_IM73_Pos (9U) |
#define | EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) |
#define | EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk |
#define | EXTI_IMR3_IM74_Pos (10U) |
#define | EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) |
#define | EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk |
#define | EXTI_IMR3_IM75_Pos (11U) |
#define | EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) |
#define | EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk |
#define | EXTI_IMR3_IM76_Pos (12U) |
#define | EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) |
#define | EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk |
#define | EXTI_IMR3_IM77_Pos (13U) |
#define | EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) |
#define | EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk |
#define | EXTI_IMR3_IM78_Pos (14U) |
#define | EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) |
#define | EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk |
#define | EXTI_IMR3_IM79_Pos (15U) |
#define | EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) |
#define | EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk |
#define | EXTI_IMR3_IM80_Pos (16U) |
#define | EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) |
#define | EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk |
#define | EXTI_IMR3_IM82_Pos (18U) |
#define | EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) |
#define | EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk |
#define | EXTI_IMR3_IM84_Pos (20U) |
#define | EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) |
#define | EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk |
#define | EXTI_IMR3_IM85_Pos (21U) |
#define | EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) |
#define | EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk |
#define | EXTI_IMR3_IM86_Pos (22U) |
#define | EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) |
#define | EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk |
#define | EXTI_IMR3_IM87_Pos (23U) |
#define | EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) |
#define | EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk |
#define | EXTI_EMR3_EM_Pos (0U) |
#define | EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) |
#define | EXTI_EMR3_EM EXTI_EMR3_EM_Msk |
#define | EXTI_EMR3_EM64_Pos (0U) |
#define | EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) |
#define | EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk |
#define | EXTI_EMR3_EM65_Pos (1U) |
#define | EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) |
#define | EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk |
#define | EXTI_EMR3_EM66_Pos (2U) |
#define | EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) |
#define | EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk |
#define | EXTI_EMR3_EM67_Pos (3U) |
#define | EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) |
#define | EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk |
#define | EXTI_EMR3_EM68_Pos (4U) |
#define | EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) |
#define | EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk |
#define | EXTI_EMR3_EM69_Pos (5U) |
#define | EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) |
#define | EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk |
#define | EXTI_EMR3_EM70_Pos (6U) |
#define | EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) |
#define | EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk |
#define | EXTI_EMR3_EM71_Pos (7U) |
#define | EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) |
#define | EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk |
#define | EXTI_EMR3_EM72_Pos (8U) |
#define | EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) |
#define | EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk |
#define | EXTI_EMR3_EM73_Pos (9U) |
#define | EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) |
#define | EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk |
#define | EXTI_EMR3_EM74_Pos (10U) |
#define | EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) |
#define | EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk |
#define | EXTI_EMR3_EM75_Pos (11U) |
#define | EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) |
#define | EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk |
#define | EXTI_EMR3_EM76_Pos (12U) |
#define | EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) |
#define | EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk |
#define | EXTI_EMR3_EM77_Pos (13U) |
#define | EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) |
#define | EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk |
#define | EXTI_EMR3_EM78_Pos (14U) |
#define | EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) |
#define | EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk |
#define | EXTI_EMR3_EM79_Pos (15U) |
#define | EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) |
#define | EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk |
#define | EXTI_EMR3_EM80_Pos (16U) |
#define | EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) |
#define | EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk |
#define | EXTI_EMR3_EM81_Pos (17U) |
#define | EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) |
#define | EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk |
#define | EXTI_EMR3_EM82_Pos (18U) |
#define | EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) |
#define | EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk |
#define | EXTI_EMR3_EM84_Pos (20U) |
#define | EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) |
#define | EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk |
#define | EXTI_EMR3_EM85_Pos (21U) |
#define | EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) |
#define | EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk |
#define | EXTI_EMR3_EM86_Pos (22U) |
#define | EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) |
#define | EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk |
#define | EXTI_EMR3_EM87_Pos (23U) |
#define | EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) |
#define | EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk |
#define | EXTI_PR3_PR_Pos (18U) |
#define | EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) |
#define | EXTI_PR3_PR EXTI_PR3_PR_Msk |
#define | EXTI_PR3_PR82_Pos (18U) |
#define | EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) |
#define | EXTI_PR3_PR82 EXTI_PR3_PR82_Msk |
#define | EXTI_PR3_PR84_Pos (20U) |
#define | EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) |
#define | EXTI_PR3_PR84 EXTI_PR3_PR84_Msk |
#define | EXTI_PR3_PR85_Pos (21U) |
#define | EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) |
#define | EXTI_PR3_PR85 EXTI_PR3_PR85_Msk |
#define | EXTI_PR3_PR86_Pos (22U) |
#define | EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) |
#define | EXTI_PR3_PR86 EXTI_PR3_PR86_Msk |
#define | FLASH_SIZE_DATA_REGISTER 0x1FF1E880U |
#define | FLASH_SECTOR_TOTAL 8U /* 8 sectors */ |
#define | FLASH_SIZE |
#define | FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */ |
#define | FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ |
#define | FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ |
#define | FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */ |
#define | DUAL_BANK /* Dual-bank Flash */ |
#define | FLASH_ACR_LATENCY_Pos (0U) |
#define | FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) |
#define | FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk |
#define | FLASH_ACR_LATENCY_0WS (0x00000000UL) |
#define | FLASH_ACR_LATENCY_1WS (0x00000001UL) |
#define | FLASH_ACR_LATENCY_2WS (0x00000002UL) |
#define | FLASH_ACR_LATENCY_3WS (0x00000003UL) |
#define | FLASH_ACR_LATENCY_4WS (0x00000004UL) |
#define | FLASH_ACR_LATENCY_5WS (0x00000005UL) |
#define | FLASH_ACR_LATENCY_6WS (0x00000006UL) |
#define | FLASH_ACR_LATENCY_7WS (0x00000007UL) |
#define | FLASH_ACR_WRHIGHFREQ_Pos (4U) |
#define | FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) |
#define | FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk |
#define | FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) |
#define | FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) |
#define | FLASH_ACR_LATENCY_8WS (0x00000008UL) |
#define | FLASH_ACR_LATENCY_9WS (0x00000009UL) |
#define | FLASH_ACR_LATENCY_10WS (0x0000000AUL) |
#define | FLASH_ACR_LATENCY_11WS (0x0000000BUL) |
#define | FLASH_ACR_LATENCY_12WS (0x0000000CUL) |
#define | FLASH_ACR_LATENCY_13WS (0x0000000DUL) |
#define | FLASH_ACR_LATENCY_14WS (0x0000000EUL) |
#define | FLASH_ACR_LATENCY_15WS (0x0000000FUL) |
#define | FLASH_CR_LOCK_Pos (0U) |
#define | FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) |
#define | FLASH_CR_LOCK FLASH_CR_LOCK_Msk |
#define | FLASH_CR_PG_Pos (1U) |
#define | FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) |
#define | FLASH_CR_PG FLASH_CR_PG_Msk |
#define | FLASH_CR_SER_Pos (2U) |
#define | FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) |
#define | FLASH_CR_SER FLASH_CR_SER_Msk |
#define | FLASH_CR_BER_Pos (3U) |
#define | FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) |
#define | FLASH_CR_BER FLASH_CR_BER_Msk |
#define | FLASH_CR_PSIZE_Pos (4U) |
#define | FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) |
#define | FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk |
#define | FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) |
#define | FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) |
#define | FLASH_CR_FW_Pos (6U) |
#define | FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) |
#define | FLASH_CR_FW FLASH_CR_FW_Msk |
#define | FLASH_CR_START_Pos (7U) |
#define | FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) |
#define | FLASH_CR_START FLASH_CR_START_Msk |
#define | FLASH_CR_SNB_Pos (8U) |
#define | FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) |
#define | FLASH_CR_SNB FLASH_CR_SNB_Msk |
#define | FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) |
#define | FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) |
#define | FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) |
#define | FLASH_CR_CRC_EN_Pos (15U) |
#define | FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) |
#define | FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk |
#define | FLASH_CR_EOPIE_Pos (16U) |
#define | FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) |
#define | FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk |
#define | FLASH_CR_WRPERRIE_Pos (17U) |
#define | FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) |
#define | FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk |
#define | FLASH_CR_PGSERRIE_Pos (18U) |
#define | FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) |
#define | FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk |
#define | FLASH_CR_STRBERRIE_Pos (19U) |
#define | FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) |
#define | FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk |
#define | FLASH_CR_INCERRIE_Pos (21U) |
#define | FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) |
#define | FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk |
#define | FLASH_CR_OPERRIE_Pos (22U) |
#define | FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) |
#define | FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk |
#define | FLASH_CR_RDPERRIE_Pos (23U) |
#define | FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) |
#define | FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk |
#define | FLASH_CR_RDSERRIE_Pos (24U) |
#define | FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) |
#define | FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk |
#define | FLASH_CR_SNECCERRIE_Pos (25U) |
#define | FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) |
#define | FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk |
#define | FLASH_CR_DBECCERRIE_Pos (26U) |
#define | FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) |
#define | FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk |
#define | FLASH_CR_CRCENDIE_Pos (27U) |
#define | FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) |
#define | FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk |
#define | FLASH_CR_CRCRDERRIE_Pos (28U) |
#define | FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) |
#define | FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk |
#define | FLASH_SR_BSY_Pos (0U) |
#define | FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) |
#define | FLASH_SR_BSY FLASH_SR_BSY_Msk |
#define | FLASH_SR_WBNE_Pos (1U) |
#define | FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) |
#define | FLASH_SR_WBNE FLASH_SR_WBNE_Msk |
#define | FLASH_SR_QW_Pos (2U) |
#define | FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) |
#define | FLASH_SR_QW FLASH_SR_QW_Msk |
#define | FLASH_SR_CRC_BUSY_Pos (3U) |
#define | FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) |
#define | FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk |
#define | FLASH_SR_EOP_Pos (16U) |
#define | FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) |
#define | FLASH_SR_EOP FLASH_SR_EOP_Msk |
#define | FLASH_SR_WRPERR_Pos (17U) |
#define | FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) |
#define | FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk |
#define | FLASH_SR_PGSERR_Pos (18U) |
#define | FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) |
#define | FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk |
#define | FLASH_SR_STRBERR_Pos (19U) |
#define | FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) |
#define | FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk |
#define | FLASH_SR_INCERR_Pos (21U) |
#define | FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) |
#define | FLASH_SR_INCERR FLASH_SR_INCERR_Msk |
#define | FLASH_SR_OPERR_Pos (22U) |
#define | FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) |
#define | FLASH_SR_OPERR FLASH_SR_OPERR_Msk |
#define | FLASH_SR_RDPERR_Pos (23U) |
#define | FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) |
#define | FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk |
#define | FLASH_SR_RDSERR_Pos (24U) |
#define | FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) |
#define | FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk |
#define | FLASH_SR_SNECCERR_Pos (25U) |
#define | FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) |
#define | FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk |
#define | FLASH_SR_DBECCERR_Pos (26U) |
#define | FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) |
#define | FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk |
#define | FLASH_SR_CRCEND_Pos (27U) |
#define | FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) |
#define | FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk |
#define | FLASH_SR_CRCRDERR_Pos (28U) |
#define | FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) |
#define | FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk |
#define | FLASH_CCR_CLR_EOP_Pos (16U) |
#define | FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) |
#define | FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk |
#define | FLASH_CCR_CLR_WRPERR_Pos (17U) |
#define | FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) |
#define | FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk |
#define | FLASH_CCR_CLR_PGSERR_Pos (18U) |
#define | FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) |
#define | FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk |
#define | FLASH_CCR_CLR_STRBERR_Pos (19U) |
#define | FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) |
#define | FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk |
#define | FLASH_CCR_CLR_INCERR_Pos (21U) |
#define | FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) |
#define | FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk |
#define | FLASH_CCR_CLR_OPERR_Pos (22U) |
#define | FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) |
#define | FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk |
#define | FLASH_CCR_CLR_RDPERR_Pos (23U) |
#define | FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) |
#define | FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk |
#define | FLASH_CCR_CLR_RDSERR_Pos (24U) |
#define | FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) |
#define | FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk |
#define | FLASH_CCR_CLR_SNECCERR_Pos (25U) |
#define | FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) |
#define | FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk |
#define | FLASH_CCR_CLR_DBECCERR_Pos (26U) |
#define | FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) |
#define | FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk |
#define | FLASH_CCR_CLR_CRCEND_Pos (27U) |
#define | FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) |
#define | FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk |
#define | FLASH_CCR_CLR_CRCRDERR_Pos (28U) |
#define | FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) |
#define | FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk |
#define | FLASH_OPTCR_OPTLOCK_Pos (0U) |
#define | FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) |
#define | FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk |
#define | FLASH_OPTCR_OPTSTART_Pos (1U) |
#define | FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) |
#define | FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk |
#define | FLASH_OPTCR_MER_Pos (4U) |
#define | FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) |
#define | FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk |
#define | FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) |
#define | FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) |
#define | FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk |
#define | FLASH_OPTCR_SWAP_BANK_Pos (31U) |
#define | FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) |
#define | FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk |
#define | FLASH_OPTSR_OPT_BUSY_Pos (0U) |
#define | FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) |
#define | FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk |
#define | FLASH_OPTSR_BOR_LEV_Pos (2U) |
#define | FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) |
#define | FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk |
#define | FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) |
#define | FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) |
#define | FLASH_OPTSR_IWDG1_SW_Pos (4U) |
#define | FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) |
#define | FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk |
#define | FLASH_OPTSR_NRST_STOP_D1_Pos (6U) |
#define | FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) |
#define | FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk |
#define | FLASH_OPTSR_NRST_STBY_D1_Pos (7U) |
#define | FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) |
#define | FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk |
#define | FLASH_OPTSR_RDP_Pos (8U) |
#define | FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) |
#define | FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk |
#define | FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) |
#define | FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) |
#define | FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk |
#define | FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) |
#define | FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) |
#define | FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk |
#define | FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) |
#define | FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) |
#define | FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk |
#define | FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) |
#define | FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) |
#define | FLASH_OPTSR_SECURITY_Pos (21U) |
#define | FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) |
#define | FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk |
#define | FLASH_OPTSR_IO_HSLV_Pos (29U) |
#define | FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) |
#define | FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk |
#define | FLASH_OPTSR_OPTCHANGEERR_Pos (30U) |
#define | FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) |
#define | FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk |
#define | FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) |
#define | FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) |
#define | FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk |
#define | FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) |
#define | FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) |
#define | FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk |
#define | FLASH_PRAR_PROT_AREA_START_Pos (0U) |
#define | FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) |
#define | FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk |
#define | FLASH_PRAR_PROT_AREA_END_Pos (16U) |
#define | FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) |
#define | FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk |
#define | FLASH_PRAR_DMEP_Pos (31U) |
#define | FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) |
#define | FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk |
#define | FLASH_SCAR_SEC_AREA_START_Pos (0U) |
#define | FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) |
#define | FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk |
#define | FLASH_SCAR_SEC_AREA_END_Pos (16U) |
#define | FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) |
#define | FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk |
#define | FLASH_SCAR_DMES_Pos (31U) |
#define | FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) |
#define | FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk |
#define | FLASH_WPSN_WRPSN_Pos (0U) |
#define | FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) |
#define | FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk |
#define | FLASH_BOOT_ADD0_Pos (0U) |
#define | FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) |
#define | FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk |
#define | FLASH_BOOT_ADD1_Pos (16U) |
#define | FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) |
#define | FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk |
#define | FLASH_CRCCR_CRC_SECT_Pos (0U) |
#define | FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) |
#define | FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk |
#define | FLASH_CRCCR_CRC_BY_SECT_Pos (8U) |
#define | FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) |
#define | FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk |
#define | FLASH_CRCCR_ADD_SECT_Pos (9U) |
#define | FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) |
#define | FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk |
#define | FLASH_CRCCR_CLEAN_SECT_Pos (10U) |
#define | FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) |
#define | FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk |
#define | FLASH_CRCCR_START_CRC_Pos (16U) |
#define | FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) |
#define | FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk |
#define | FLASH_CRCCR_CLEAN_CRC_Pos (17U) |
#define | FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) |
#define | FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk |
#define | FLASH_CRCCR_CRC_BURST_Pos (20U) |
#define | FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) |
#define | FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk |
#define | FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) |
#define | FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) |
#define | FLASH_CRCCR_ALL_BANK_Pos (22U) |
#define | FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) |
#define | FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk |
#define | FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) |
#define | FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) |
#define | FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk |
#define | FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) |
#define | FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) |
#define | FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk |
#define | FLASH_CRCDATA_CRC_DATA_Pos (0U) |
#define | FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) |
#define | FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk |
#define | FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) |
#define | FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) |
#define | FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk |
#define | FMC_BCR1_CCLKEN_Pos (20U) |
#define | FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) |
#define | FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk |
#define | FMC_BCR1_WFDIS_Pos (21U) |
#define | FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) |
#define | FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk |
#define | FMC_BCR1_BMAP_Pos (24U) |
#define | FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) |
#define | FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk |
#define | FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) |
#define | FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) |
#define | FMC_BCR1_FMCEN_Pos (31U) |
#define | FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) |
#define | FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk |
#define | FMC_BCRx_MBKEN_Pos (0U) |
#define | FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) |
#define | FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk |
#define | FMC_BCRx_MUXEN_Pos (1U) |
#define | FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) |
#define | FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk |
#define | FMC_BCRx_MTYP_Pos (2U) |
#define | FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) |
#define | FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk |
#define | FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) |
#define | FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) |
#define | FMC_BCRx_MWID_Pos (4U) |
#define | FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) |
#define | FMC_BCRx_MWID FMC_BCRx_MWID_Msk |
#define | FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) |
#define | FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) |
#define | FMC_BCRx_FACCEN_Pos (6U) |
#define | FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) |
#define | FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk |
#define | FMC_BCRx_BURSTEN_Pos (8U) |
#define | FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) |
#define | FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk |
#define | FMC_BCRx_WAITPOL_Pos (9U) |
#define | FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) |
#define | FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk |
#define | FMC_BCRx_WAITCFG_Pos (11U) |
#define | FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) |
#define | FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk |
#define | FMC_BCRx_WREN_Pos (12U) |
#define | FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) |
#define | FMC_BCRx_WREN FMC_BCRx_WREN_Msk |
#define | FMC_BCRx_WAITEN_Pos (13U) |
#define | FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) |
#define | FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk |
#define | FMC_BCRx_EXTMOD_Pos (14U) |
#define | FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) |
#define | FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk |
#define | FMC_BCRx_ASYNCWAIT_Pos (15U) |
#define | FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) |
#define | FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk |
#define | FMC_BCRx_CPSIZE_Pos (16U) |
#define | FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) |
#define | FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk |
#define | FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) |
#define | FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) |
#define | FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) |
#define | FMC_BCRx_CBURSTRW_Pos (19U) |
#define | FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) |
#define | FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk |
#define | FMC_BTRx_ADDSET_Pos (0U) |
#define | FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) |
#define | FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk |
#define | FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) |
#define | FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) |
#define | FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) |
#define | FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) |
#define | FMC_BTRx_ADDHLD_Pos (4U) |
#define | FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) |
#define | FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk |
#define | FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) |
#define | FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) |
#define | FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) |
#define | FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) |
#define | FMC_BTRx_DATAST_Pos (8U) |
#define | FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk |
#define | FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) |
#define | FMC_BTRx_BUSTURN_Pos (16U) |
#define | FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) |
#define | FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk |
#define | FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) |
#define | FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) |
#define | FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) |
#define | FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) |
#define | FMC_BTRx_CLKDIV_Pos (20U) |
#define | FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) |
#define | FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk |
#define | FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) |
#define | FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) |
#define | FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) |
#define | FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) |
#define | FMC_BTRx_DATLAT_Pos (24U) |
#define | FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) |
#define | FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk |
#define | FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) |
#define | FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) |
#define | FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) |
#define | FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) |
#define | FMC_BTRx_ACCMOD_Pos (28U) |
#define | FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) |
#define | FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk |
#define | FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) |
#define | FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) |
#define | FMC_BWTRx_ADDSET_Pos (0U) |
#define | FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) |
#define | FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk |
#define | FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) |
#define | FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) |
#define | FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) |
#define | FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) |
#define | FMC_BWTRx_ADDHLD_Pos (4U) |
#define | FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) |
#define | FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk |
#define | FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) |
#define | FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) |
#define | FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) |
#define | FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) |
#define | FMC_BWTRx_DATAST_Pos (8U) |
#define | FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk |
#define | FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) |
#define | FMC_BWTRx_BUSTURN_Pos (16U) |
#define | FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) |
#define | FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk |
#define | FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) |
#define | FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) |
#define | FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) |
#define | FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) |
#define | FMC_BWTRx_ACCMOD_Pos (28U) |
#define | FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) |
#define | FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk |
#define | FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) |
#define | FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) |
#define | FMC_PCR_PWAITEN_Pos (1U) |
#define | FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) |
#define | FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk |
#define | FMC_PCR_PBKEN_Pos (2U) |
#define | FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) |
#define | FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk |
#define | FMC_PCR_PWID_Pos (4U) |
#define | FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) |
#define | FMC_PCR_PWID FMC_PCR_PWID_Msk |
#define | FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) |
#define | FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) |
#define | FMC_PCR_ECCEN_Pos (6U) |
#define | FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) |
#define | FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk |
#define | FMC_PCR_TCLR_Pos (9U) |
#define | FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) |
#define | FMC_PCR_TCLR FMC_PCR_TCLR_Msk |
#define | FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) |
#define | FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) |
#define | FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) |
#define | FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) |
#define | FMC_PCR_TAR_Pos (13U) |
#define | FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) |
#define | FMC_PCR_TAR FMC_PCR_TAR_Msk |
#define | FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) |
#define | FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) |
#define | FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) |
#define | FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) |
#define | FMC_PCR_ECCPS_Pos (17U) |
#define | FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) |
#define | FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk |
#define | FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) |
#define | FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) |
#define | FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) |
#define | FMC_SR_IRS_Pos (0U) |
#define | FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) |
#define | FMC_SR_IRS FMC_SR_IRS_Msk |
#define | FMC_SR_ILS_Pos (1U) |
#define | FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) |
#define | FMC_SR_ILS FMC_SR_ILS_Msk |
#define | FMC_SR_IFS_Pos (2U) |
#define | FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) |
#define | FMC_SR_IFS FMC_SR_IFS_Msk |
#define | FMC_SR_IREN_Pos (3U) |
#define | FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) |
#define | FMC_SR_IREN FMC_SR_IREN_Msk |
#define | FMC_SR_ILEN_Pos (4U) |
#define | FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) |
#define | FMC_SR_ILEN FMC_SR_ILEN_Msk |
#define | FMC_SR_IFEN_Pos (5U) |
#define | FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) |
#define | FMC_SR_IFEN FMC_SR_IFEN_Msk |
#define | FMC_SR_FEMPT_Pos (6U) |
#define | FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) |
#define | FMC_SR_FEMPT FMC_SR_FEMPT_Msk |
#define | FMC_PMEM_MEMSET_Pos (0U) |
#define | FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk |
#define | FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) |
#define | FMC_PMEM_MEMWAIT_Pos (8U) |
#define | FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk |
#define | FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) |
#define | FMC_PMEM_MEMHOLD_Pos (16U) |
#define | FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk |
#define | FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) |
#define | FMC_PMEM_MEMHIZ_Pos (24U) |
#define | FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk |
#define | FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) |
#define | FMC_PATT_ATTSET_Pos (0U) |
#define | FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk |
#define | FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) |
#define | FMC_PATT_ATTWAIT_Pos (8U) |
#define | FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk |
#define | FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) |
#define | FMC_PATT_ATTHOLD_Pos (16U) |
#define | FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk |
#define | FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) |
#define | FMC_PATT_ATTHIZ_Pos (24U) |
#define | FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk |
#define | FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) |
#define | FMC_ECCR3_ECC3_Pos (0U) |
#define | FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) |
#define | FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk |
#define | FMC_SDCRx_NC_Pos (0U) |
#define | FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) |
#define | FMC_SDCRx_NC FMC_SDCRx_NC_Msk |
#define | FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) |
#define | FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) |
#define | FMC_SDCRx_NR_Pos (2U) |
#define | FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) |
#define | FMC_SDCRx_NR FMC_SDCRx_NR_Msk |
#define | FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) |
#define | FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) |
#define | FMC_SDCRx_MWID_Pos (4U) |
#define | FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) |
#define | FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk |
#define | FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) |
#define | FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) |
#define | FMC_SDCRx_NB_Pos (6U) |
#define | FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) |
#define | FMC_SDCRx_NB FMC_SDCRx_NB_Msk |
#define | FMC_SDCRx_CAS_Pos (7U) |
#define | FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) |
#define | FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk |
#define | FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) |
#define | FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) |
#define | FMC_SDCRx_WP_Pos (9U) |
#define | FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) |
#define | FMC_SDCRx_WP FMC_SDCRx_WP_Msk |
#define | FMC_SDCRx_SDCLK_Pos (10U) |
#define | FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) |
#define | FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk |
#define | FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) |
#define | FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) |
#define | FMC_SDCRx_RBURST_Pos (12U) |
#define | FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) |
#define | FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk |
#define | FMC_SDCRx_RPIPE_Pos (13U) |
#define | FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) |
#define | FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk |
#define | FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) |
#define | FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) |
#define | FMC_SDTRx_TMRD_Pos (0U) |
#define | FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) |
#define | FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk |
#define | FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) |
#define | FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) |
#define | FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) |
#define | FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) |
#define | FMC_SDTRx_TXSR_Pos (4U) |
#define | FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) |
#define | FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk |
#define | FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) |
#define | FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) |
#define | FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) |
#define | FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) |
#define | FMC_SDTRx_TRAS_Pos (8U) |
#define | FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) |
#define | FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk |
#define | FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) |
#define | FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) |
#define | FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) |
#define | FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) |
#define | FMC_SDTRx_TRC_Pos (12U) |
#define | FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) |
#define | FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk |
#define | FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) |
#define | FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) |
#define | FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) |
#define | FMC_SDTRx_TWR_Pos (16U) |
#define | FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) |
#define | FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk |
#define | FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) |
#define | FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) |
#define | FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) |
#define | FMC_SDTRx_TRP_Pos (20U) |
#define | FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) |
#define | FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk |
#define | FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) |
#define | FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) |
#define | FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) |
#define | FMC_SDTRx_TRCD_Pos (24U) |
#define | FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) |
#define | FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk |
#define | FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) |
#define | FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) |
#define | FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) |
#define | FMC_SDCMR_MODE_Pos (0U) |
#define | FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) |
#define | FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk |
#define | FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) |
#define | FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) |
#define | FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) |
#define | FMC_SDCMR_CTB2_Pos (3U) |
#define | FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) |
#define | FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk |
#define | FMC_SDCMR_CTB1_Pos (4U) |
#define | FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) |
#define | FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk |
#define | FMC_SDCMR_NRFS_Pos (5U) |
#define | FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) |
#define | FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk |
#define | FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) |
#define | FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) |
#define | FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) |
#define | FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) |
#define | FMC_SDCMR_MRD_Pos (9U) |
#define | FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) |
#define | FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk |
#define | FMC_SDRTR_CRE_Pos (0U) |
#define | FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) |
#define | FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk |
#define | FMC_SDRTR_COUNT_Pos (1U) |
#define | FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) |
#define | FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk |
#define | FMC_SDRTR_REIE_Pos (14U) |
#define | FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) |
#define | FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk |
#define | FMC_SDSR_RE_Pos (0U) |
#define | FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) |
#define | FMC_SDSR_RE FMC_SDSR_RE_Msk |
#define | FMC_SDSR_MODES1_Pos (1U) |
#define | FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) |
#define | FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk |
#define | FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) |
#define | FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) |
#define | FMC_SDSR_MODES2_Pos (3U) |
#define | FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) |
#define | FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk |
#define | FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) |
#define | FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) |
#define | GPIO_MODER_MODE0_Pos (0U) |
#define | GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) |
#define | GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk |
#define | GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) |
#define | GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) |
#define | GPIO_MODER_MODE1_Pos (2U) |
#define | GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) |
#define | GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk |
#define | GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) |
#define | GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) |
#define | GPIO_MODER_MODE2_Pos (4U) |
#define | GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) |
#define | GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk |
#define | GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) |
#define | GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) |
#define | GPIO_MODER_MODE3_Pos (6U) |
#define | GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) |
#define | GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk |
#define | GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) |
#define | GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) |
#define | GPIO_MODER_MODE4_Pos (8U) |
#define | GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) |
#define | GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk |
#define | GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) |
#define | GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) |
#define | GPIO_MODER_MODE5_Pos (10U) |
#define | GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) |
#define | GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk |
#define | GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) |
#define | GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) |
#define | GPIO_MODER_MODE6_Pos (12U) |
#define | GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) |
#define | GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk |
#define | GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) |
#define | GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) |
#define | GPIO_MODER_MODE7_Pos (14U) |
#define | GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) |
#define | GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk |
#define | GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) |
#define | GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) |
#define | GPIO_MODER_MODE8_Pos (16U) |
#define | GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) |
#define | GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk |
#define | GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) |
#define | GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) |
#define | GPIO_MODER_MODE9_Pos (18U) |
#define | GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) |
#define | GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk |
#define | GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) |
#define | GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) |
#define | GPIO_MODER_MODE10_Pos (20U) |
#define | GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) |
#define | GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk |
#define | GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) |
#define | GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) |
#define | GPIO_MODER_MODE11_Pos (22U) |
#define | GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) |
#define | GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk |
#define | GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) |
#define | GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) |
#define | GPIO_MODER_MODE12_Pos (24U) |
#define | GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) |
#define | GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk |
#define | GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) |
#define | GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) |
#define | GPIO_MODER_MODE13_Pos (26U) |
#define | GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) |
#define | GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk |
#define | GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) |
#define | GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) |
#define | GPIO_MODER_MODE14_Pos (28U) |
#define | GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) |
#define | GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk |
#define | GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) |
#define | GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) |
#define | GPIO_MODER_MODE15_Pos (30U) |
#define | GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) |
#define | GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk |
#define | GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) |
#define | GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) |
#define | GPIO_OTYPER_OT0_Pos (0U) |
#define | GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) |
#define | GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk |
#define | GPIO_OTYPER_OT1_Pos (1U) |
#define | GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) |
#define | GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk |
#define | GPIO_OTYPER_OT2_Pos (2U) |
#define | GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) |
#define | GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk |
#define | GPIO_OTYPER_OT3_Pos (3U) |
#define | GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) |
#define | GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk |
#define | GPIO_OTYPER_OT4_Pos (4U) |
#define | GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) |
#define | GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk |
#define | GPIO_OTYPER_OT5_Pos (5U) |
#define | GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) |
#define | GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk |
#define | GPIO_OTYPER_OT6_Pos (6U) |
#define | GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) |
#define | GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk |
#define | GPIO_OTYPER_OT7_Pos (7U) |
#define | GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) |
#define | GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk |
#define | GPIO_OTYPER_OT8_Pos (8U) |
#define | GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) |
#define | GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk |
#define | GPIO_OTYPER_OT9_Pos (9U) |
#define | GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) |
#define | GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk |
#define | GPIO_OTYPER_OT10_Pos (10U) |
#define | GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) |
#define | GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk |
#define | GPIO_OTYPER_OT11_Pos (11U) |
#define | GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) |
#define | GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk |
#define | GPIO_OTYPER_OT12_Pos (12U) |
#define | GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) |
#define | GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk |
#define | GPIO_OTYPER_OT13_Pos (13U) |
#define | GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) |
#define | GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk |
#define | GPIO_OTYPER_OT14_Pos (14U) |
#define | GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) |
#define | GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk |
#define | GPIO_OTYPER_OT15_Pos (15U) |
#define | GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) |
#define | GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk |
#define | GPIO_OSPEEDR_OSPEED0_Pos (0U) |
#define | GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) |
#define | GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk |
#define | GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) |
#define | GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) |
#define | GPIO_OSPEEDR_OSPEED1_Pos (2U) |
#define | GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) |
#define | GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk |
#define | GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) |
#define | GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) |
#define | GPIO_OSPEEDR_OSPEED2_Pos (4U) |
#define | GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) |
#define | GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk |
#define | GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) |
#define | GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) |
#define | GPIO_OSPEEDR_OSPEED3_Pos (6U) |
#define | GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) |
#define | GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk |
#define | GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) |
#define | GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) |
#define | GPIO_OSPEEDR_OSPEED4_Pos (8U) |
#define | GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) |
#define | GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk |
#define | GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) |
#define | GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) |
#define | GPIO_OSPEEDR_OSPEED5_Pos (10U) |
#define | GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) |
#define | GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk |
#define | GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) |
#define | GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) |
#define | GPIO_OSPEEDR_OSPEED6_Pos (12U) |
#define | GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) |
#define | GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk |
#define | GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) |
#define | GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) |
#define | GPIO_OSPEEDR_OSPEED7_Pos (14U) |
#define | GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) |
#define | GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk |
#define | GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) |
#define | GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) |
#define | GPIO_OSPEEDR_OSPEED8_Pos (16U) |
#define | GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) |
#define | GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk |
#define | GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) |
#define | GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) |
#define | GPIO_OSPEEDR_OSPEED9_Pos (18U) |
#define | GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) |
#define | GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk |
#define | GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) |
#define | GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) |
#define | GPIO_OSPEEDR_OSPEED10_Pos (20U) |
#define | GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) |
#define | GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk |
#define | GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) |
#define | GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) |
#define | GPIO_OSPEEDR_OSPEED11_Pos (22U) |
#define | GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) |
#define | GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk |
#define | GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) |
#define | GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) |
#define | GPIO_OSPEEDR_OSPEED12_Pos (24U) |
#define | GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) |
#define | GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk |
#define | GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) |
#define | GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) |
#define | GPIO_OSPEEDR_OSPEED13_Pos (26U) |
#define | GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) |
#define | GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk |
#define | GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) |
#define | GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) |
#define | GPIO_OSPEEDR_OSPEED14_Pos (28U) |
#define | GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) |
#define | GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk |
#define | GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) |
#define | GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) |
#define | GPIO_OSPEEDR_OSPEED15_Pos (30U) |
#define | GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) |
#define | GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk |
#define | GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) |
#define | GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) |
#define | GPIO_PUPDR_PUPD0_Pos (0U) |
#define | GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) |
#define | GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk |
#define | GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) |
#define | GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) |
#define | GPIO_PUPDR_PUPD1_Pos (2U) |
#define | GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) |
#define | GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk |
#define | GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) |
#define | GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) |
#define | GPIO_PUPDR_PUPD2_Pos (4U) |
#define | GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) |
#define | GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk |
#define | GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) |
#define | GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) |
#define | GPIO_PUPDR_PUPD3_Pos (6U) |
#define | GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) |
#define | GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk |
#define | GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) |
#define | GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) |
#define | GPIO_PUPDR_PUPD4_Pos (8U) |
#define | GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) |
#define | GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk |
#define | GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) |
#define | GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) |
#define | GPIO_PUPDR_PUPD5_Pos (10U) |
#define | GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) |
#define | GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk |
#define | GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) |
#define | GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) |
#define | GPIO_PUPDR_PUPD6_Pos (12U) |
#define | GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) |
#define | GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk |
#define | GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) |
#define | GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) |
#define | GPIO_PUPDR_PUPD7_Pos (14U) |
#define | GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) |
#define | GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk |
#define | GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) |
#define | GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) |
#define | GPIO_PUPDR_PUPD8_Pos (16U) |
#define | GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) |
#define | GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk |
#define | GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) |
#define | GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) |
#define | GPIO_PUPDR_PUPD9_Pos (18U) |
#define | GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) |
#define | GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk |
#define | GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) |
#define | GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) |
#define | GPIO_PUPDR_PUPD10_Pos (20U) |
#define | GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) |
#define | GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk |
#define | GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) |
#define | GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) |
#define | GPIO_PUPDR_PUPD11_Pos (22U) |
#define | GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) |
#define | GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk |
#define | GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) |
#define | GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) |
#define | GPIO_PUPDR_PUPD12_Pos (24U) |
#define | GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) |
#define | GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk |
#define | GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) |
#define | GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) |
#define | GPIO_PUPDR_PUPD13_Pos (26U) |
#define | GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) |
#define | GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk |
#define | GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) |
#define | GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) |
#define | GPIO_PUPDR_PUPD14_Pos (28U) |
#define | GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) |
#define | GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk |
#define | GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) |
#define | GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) |
#define | GPIO_PUPDR_PUPD15_Pos (30U) |
#define | GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) |
#define | GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk |
#define | GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) |
#define | GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) |
#define | GPIO_IDR_ID0_Pos (0U) |
#define | GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) |
#define | GPIO_IDR_ID0 GPIO_IDR_ID0_Msk |
#define | GPIO_IDR_ID1_Pos (1U) |
#define | GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) |
#define | GPIO_IDR_ID1 GPIO_IDR_ID1_Msk |
#define | GPIO_IDR_ID2_Pos (2U) |
#define | GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) |
#define | GPIO_IDR_ID2 GPIO_IDR_ID2_Msk |
#define | GPIO_IDR_ID3_Pos (3U) |
#define | GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) |
#define | GPIO_IDR_ID3 GPIO_IDR_ID3_Msk |
#define | GPIO_IDR_ID4_Pos (4U) |
#define | GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) |
#define | GPIO_IDR_ID4 GPIO_IDR_ID4_Msk |
#define | GPIO_IDR_ID5_Pos (5U) |
#define | GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) |
#define | GPIO_IDR_ID5 GPIO_IDR_ID5_Msk |
#define | GPIO_IDR_ID6_Pos (6U) |
#define | GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) |
#define | GPIO_IDR_ID6 GPIO_IDR_ID6_Msk |
#define | GPIO_IDR_ID7_Pos (7U) |
#define | GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) |
#define | GPIO_IDR_ID7 GPIO_IDR_ID7_Msk |
#define | GPIO_IDR_ID8_Pos (8U) |
#define | GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) |
#define | GPIO_IDR_ID8 GPIO_IDR_ID8_Msk |
#define | GPIO_IDR_ID9_Pos (9U) |
#define | GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) |
#define | GPIO_IDR_ID9 GPIO_IDR_ID9_Msk |
#define | GPIO_IDR_ID10_Pos (10U) |
#define | GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) |
#define | GPIO_IDR_ID10 GPIO_IDR_ID10_Msk |
#define | GPIO_IDR_ID11_Pos (11U) |
#define | GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) |
#define | GPIO_IDR_ID11 GPIO_IDR_ID11_Msk |
#define | GPIO_IDR_ID12_Pos (12U) |
#define | GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) |
#define | GPIO_IDR_ID12 GPIO_IDR_ID12_Msk |
#define | GPIO_IDR_ID13_Pos (13U) |
#define | GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) |
#define | GPIO_IDR_ID13 GPIO_IDR_ID13_Msk |
#define | GPIO_IDR_ID14_Pos (14U) |
#define | GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) |
#define | GPIO_IDR_ID14 GPIO_IDR_ID14_Msk |
#define | GPIO_IDR_ID15_Pos (15U) |
#define | GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) |
#define | GPIO_IDR_ID15 GPIO_IDR_ID15_Msk |
#define | GPIO_ODR_OD0_Pos (0U) |
#define | GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) |
#define | GPIO_ODR_OD0 GPIO_ODR_OD0_Msk |
#define | GPIO_ODR_OD1_Pos (1U) |
#define | GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) |
#define | GPIO_ODR_OD1 GPIO_ODR_OD1_Msk |
#define | GPIO_ODR_OD2_Pos (2U) |
#define | GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) |
#define | GPIO_ODR_OD2 GPIO_ODR_OD2_Msk |
#define | GPIO_ODR_OD3_Pos (3U) |
#define | GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) |
#define | GPIO_ODR_OD3 GPIO_ODR_OD3_Msk |
#define | GPIO_ODR_OD4_Pos (4U) |
#define | GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) |
#define | GPIO_ODR_OD4 GPIO_ODR_OD4_Msk |
#define | GPIO_ODR_OD5_Pos (5U) |
#define | GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) |
#define | GPIO_ODR_OD5 GPIO_ODR_OD5_Msk |
#define | GPIO_ODR_OD6_Pos (6U) |
#define | GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) |
#define | GPIO_ODR_OD6 GPIO_ODR_OD6_Msk |
#define | GPIO_ODR_OD7_Pos (7U) |
#define | GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) |
#define | GPIO_ODR_OD7 GPIO_ODR_OD7_Msk |
#define | GPIO_ODR_OD8_Pos (8U) |
#define | GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) |
#define | GPIO_ODR_OD8 GPIO_ODR_OD8_Msk |
#define | GPIO_ODR_OD9_Pos (9U) |
#define | GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) |
#define | GPIO_ODR_OD9 GPIO_ODR_OD9_Msk |
#define | GPIO_ODR_OD10_Pos (10U) |
#define | GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) |
#define | GPIO_ODR_OD10 GPIO_ODR_OD10_Msk |
#define | GPIO_ODR_OD11_Pos (11U) |
#define | GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) |
#define | GPIO_ODR_OD11 GPIO_ODR_OD11_Msk |
#define | GPIO_ODR_OD12_Pos (12U) |
#define | GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) |
#define | GPIO_ODR_OD12 GPIO_ODR_OD12_Msk |
#define | GPIO_ODR_OD13_Pos (13U) |
#define | GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) |
#define | GPIO_ODR_OD13 GPIO_ODR_OD13_Msk |
#define | GPIO_ODR_OD14_Pos (14U) |
#define | GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) |
#define | GPIO_ODR_OD14 GPIO_ODR_OD14_Msk |
#define | GPIO_ODR_OD15_Pos (15U) |
#define | GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) |
#define | GPIO_ODR_OD15 GPIO_ODR_OD15_Msk |
#define | GPIO_BSRR_BS0_Pos (0U) |
#define | GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) |
#define | GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk |
#define | GPIO_BSRR_BS1_Pos (1U) |
#define | GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) |
#define | GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk |
#define | GPIO_BSRR_BS2_Pos (2U) |
#define | GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) |
#define | GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk |
#define | GPIO_BSRR_BS3_Pos (3U) |
#define | GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) |
#define | GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk |
#define | GPIO_BSRR_BS4_Pos (4U) |
#define | GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) |
#define | GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk |
#define | GPIO_BSRR_BS5_Pos (5U) |
#define | GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) |
#define | GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk |
#define | GPIO_BSRR_BS6_Pos (6U) |
#define | GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) |
#define | GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk |
#define | GPIO_BSRR_BS7_Pos (7U) |
#define | GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) |
#define | GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk |
#define | GPIO_BSRR_BS8_Pos (8U) |
#define | GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) |
#define | GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk |
#define | GPIO_BSRR_BS9_Pos (9U) |
#define | GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) |
#define | GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk |
#define | GPIO_BSRR_BS10_Pos (10U) |
#define | GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) |
#define | GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk |
#define | GPIO_BSRR_BS11_Pos (11U) |
#define | GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) |
#define | GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk |
#define | GPIO_BSRR_BS12_Pos (12U) |
#define | GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) |
#define | GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk |
#define | GPIO_BSRR_BS13_Pos (13U) |
#define | GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) |
#define | GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk |
#define | GPIO_BSRR_BS14_Pos (14U) |
#define | GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) |
#define | GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk |
#define | GPIO_BSRR_BS15_Pos (15U) |
#define | GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) |
#define | GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk |
#define | GPIO_BSRR_BR0_Pos (16U) |
#define | GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) |
#define | GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk |
#define | GPIO_BSRR_BR1_Pos (17U) |
#define | GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) |
#define | GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk |
#define | GPIO_BSRR_BR2_Pos (18U) |
#define | GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) |
#define | GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk |
#define | GPIO_BSRR_BR3_Pos (19U) |
#define | GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) |
#define | GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk |
#define | GPIO_BSRR_BR4_Pos (20U) |
#define | GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) |
#define | GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk |
#define | GPIO_BSRR_BR5_Pos (21U) |
#define | GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) |
#define | GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk |
#define | GPIO_BSRR_BR6_Pos (22U) |
#define | GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) |
#define | GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk |
#define | GPIO_BSRR_BR7_Pos (23U) |
#define | GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) |
#define | GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk |
#define | GPIO_BSRR_BR8_Pos (24U) |
#define | GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) |
#define | GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk |
#define | GPIO_BSRR_BR9_Pos (25U) |
#define | GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) |
#define | GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk |
#define | GPIO_BSRR_BR10_Pos (26U) |
#define | GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) |
#define | GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk |
#define | GPIO_BSRR_BR11_Pos (27U) |
#define | GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) |
#define | GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk |
#define | GPIO_BSRR_BR12_Pos (28U) |
#define | GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) |
#define | GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk |
#define | GPIO_BSRR_BR13_Pos (29U) |
#define | GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) |
#define | GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk |
#define | GPIO_BSRR_BR14_Pos (30U) |
#define | GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) |
#define | GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk |
#define | GPIO_BSRR_BR15_Pos (31U) |
#define | GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) |
#define | GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk |
#define | GPIO_LCKR_LCK0_Pos (0U) |
#define | GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) |
#define | GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
#define | GPIO_LCKR_LCK1_Pos (1U) |
#define | GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) |
#define | GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
#define | GPIO_LCKR_LCK2_Pos (2U) |
#define | GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) |
#define | GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
#define | GPIO_LCKR_LCK3_Pos (3U) |
#define | GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) |
#define | GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
#define | GPIO_LCKR_LCK4_Pos (4U) |
#define | GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) |
#define | GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
#define | GPIO_LCKR_LCK5_Pos (5U) |
#define | GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) |
#define | GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
#define | GPIO_LCKR_LCK6_Pos (6U) |
#define | GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) |
#define | GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
#define | GPIO_LCKR_LCK7_Pos (7U) |
#define | GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) |
#define | GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
#define | GPIO_LCKR_LCK8_Pos (8U) |
#define | GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) |
#define | GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
#define | GPIO_LCKR_LCK9_Pos (9U) |
#define | GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) |
#define | GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
#define | GPIO_LCKR_LCK10_Pos (10U) |
#define | GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) |
#define | GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
#define | GPIO_LCKR_LCK11_Pos (11U) |
#define | GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) |
#define | GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
#define | GPIO_LCKR_LCK12_Pos (12U) |
#define | GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) |
#define | GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
#define | GPIO_LCKR_LCK13_Pos (13U) |
#define | GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) |
#define | GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
#define | GPIO_LCKR_LCK14_Pos (14U) |
#define | GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) |
#define | GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
#define | GPIO_LCKR_LCK15_Pos (15U) |
#define | GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) |
#define | GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
#define | GPIO_LCKR_LCKK_Pos (16U) |
#define | GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) |
#define | GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
#define | GPIO_AFRL_AFSEL0_Pos (0U) |
#define | GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) |
#define | GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk |
#define | GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) |
#define | GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) |
#define | GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) |
#define | GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) |
#define | GPIO_AFRL_AFSEL1_Pos (4U) |
#define | GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) |
#define | GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk |
#define | GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) |
#define | GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) |
#define | GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) |
#define | GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) |
#define | GPIO_AFRL_AFSEL2_Pos (8U) |
#define | GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) |
#define | GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk |
#define | GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) |
#define | GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) |
#define | GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) |
#define | GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) |
#define | GPIO_AFRL_AFSEL3_Pos (12U) |
#define | GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) |
#define | GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk |
#define | GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) |
#define | GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) |
#define | GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) |
#define | GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) |
#define | GPIO_AFRL_AFSEL4_Pos (16U) |
#define | GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) |
#define | GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk |
#define | GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) |
#define | GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) |
#define | GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) |
#define | GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) |
#define | GPIO_AFRL_AFSEL5_Pos (20U) |
#define | GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) |
#define | GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk |
#define | GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) |
#define | GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) |
#define | GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) |
#define | GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) |
#define | GPIO_AFRL_AFSEL6_Pos (24U) |
#define | GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) |
#define | GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
#define | GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) |
#define | GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) |
#define | GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) |
#define | GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) |
#define | GPIO_AFRL_AFSEL7_Pos (28U) |
#define | GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) |
#define | GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
#define | GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) |
#define | GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) |
#define | GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) |
#define | GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) |
#define | GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
#define | GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 |
#define | GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 |
#define | GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 |
#define | GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 |
#define | GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 |
#define | GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 |
#define | GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 |
#define | GPIO_AFRH_AFSEL8_Pos (0U) |
#define | GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) |
#define | GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk |
#define | GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) |
#define | GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) |
#define | GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) |
#define | GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) |
#define | GPIO_AFRH_AFSEL9_Pos (4U) |
#define | GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) |
#define | GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk |
#define | GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) |
#define | GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) |
#define | GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) |
#define | GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) |
#define | GPIO_AFRH_AFSEL10_Pos (8U) |
#define | GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) |
#define | GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk |
#define | GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) |
#define | GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) |
#define | GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) |
#define | GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) |
#define | GPIO_AFRH_AFSEL11_Pos (12U) |
#define | GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) |
#define | GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk |
#define | GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) |
#define | GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) |
#define | GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) |
#define | GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) |
#define | GPIO_AFRH_AFSEL12_Pos (16U) |
#define | GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) |
#define | GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk |
#define | GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) |
#define | GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) |
#define | GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) |
#define | GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) |
#define | GPIO_AFRH_AFSEL13_Pos (20U) |
#define | GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) |
#define | GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk |
#define | GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) |
#define | GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) |
#define | GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) |
#define | GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) |
#define | GPIO_AFRH_AFSEL14_Pos (24U) |
#define | GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) |
#define | GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk |
#define | GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) |
#define | GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) |
#define | GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) |
#define | GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) |
#define | GPIO_AFRH_AFSEL15_Pos (28U) |
#define | GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) |
#define | GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk |
#define | GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) |
#define | GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) |
#define | GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) |
#define | GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) |
#define | GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 |
#define | GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 |
#define | GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 |
#define | GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 |
#define | GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 |
#define | GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 |
#define | GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 |
#define | GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 |
#define | HSEM_R_PROCID_Pos (0U) |
#define | HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) |
#define | HSEM_R_PROCID HSEM_R_PROCID_Msk |
#define | HSEM_R_COREID_Pos (8U) |
#define | HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) |
#define | HSEM_R_COREID HSEM_R_COREID_Msk |
#define | HSEM_R_LOCK_Pos (31U) |
#define | HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) |
#define | HSEM_R_LOCK HSEM_R_LOCK_Msk |
#define | HSEM_RLR_PROCID_Pos (0U) |
#define | HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) |
#define | HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk |
#define | HSEM_RLR_COREID_Pos (8U) |
#define | HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) |
#define | HSEM_RLR_COREID HSEM_RLR_COREID_Msk |
#define | HSEM_RLR_LOCK_Pos (31U) |
#define | HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) |
#define | HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk |
#define | HSEM_C1IER_ISE0_Pos (0U) |
#define | HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) |
#define | HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk |
#define | HSEM_C1IER_ISE1_Pos (1U) |
#define | HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) |
#define | HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk |
#define | HSEM_C1IER_ISE2_Pos (2U) |
#define | HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) |
#define | HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk |
#define | HSEM_C1IER_ISE3_Pos (3U) |
#define | HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) |
#define | HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk |
#define | HSEM_C1IER_ISE4_Pos (4U) |
#define | HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) |
#define | HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk |
#define | HSEM_C1IER_ISE5_Pos (5U) |
#define | HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) |
#define | HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk |
#define | HSEM_C1IER_ISE6_Pos (6U) |
#define | HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) |
#define | HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk |
#define | HSEM_C1IER_ISE7_Pos (7U) |
#define | HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) |
#define | HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk |
#define | HSEM_C1IER_ISE8_Pos (8U) |
#define | HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) |
#define | HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk |
#define | HSEM_C1IER_ISE9_Pos (9U) |
#define | HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) |
#define | HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk |
#define | HSEM_C1IER_ISE10_Pos (10U) |
#define | HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) |
#define | HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk |
#define | HSEM_C1IER_ISE11_Pos (11U) |
#define | HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) |
#define | HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk |
#define | HSEM_C1IER_ISE12_Pos (12U) |
#define | HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) |
#define | HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk |
#define | HSEM_C1IER_ISE13_Pos (13U) |
#define | HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) |
#define | HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk |
#define | HSEM_C1IER_ISE14_Pos (14U) |
#define | HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) |
#define | HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk |
#define | HSEM_C1IER_ISE15_Pos (15U) |
#define | HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) |
#define | HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk |
#define | HSEM_C1IER_ISE16_Pos (16U) |
#define | HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) |
#define | HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk |
#define | HSEM_C1IER_ISE17_Pos (17U) |
#define | HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) |
#define | HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk |
#define | HSEM_C1IER_ISE18_Pos (18U) |
#define | HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) |
#define | HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk |
#define | HSEM_C1IER_ISE19_Pos (19U) |
#define | HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) |
#define | HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk |
#define | HSEM_C1IER_ISE20_Pos (20U) |
#define | HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) |
#define | HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk |
#define | HSEM_C1IER_ISE21_Pos (21U) |
#define | HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) |
#define | HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk |
#define | HSEM_C1IER_ISE22_Pos (22U) |
#define | HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) |
#define | HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk |
#define | HSEM_C1IER_ISE23_Pos (23U) |
#define | HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) |
#define | HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk |
#define | HSEM_C1IER_ISE24_Pos (24U) |
#define | HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) |
#define | HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk |
#define | HSEM_C1IER_ISE25_Pos (25U) |
#define | HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) |
#define | HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk |
#define | HSEM_C1IER_ISE26_Pos (26U) |
#define | HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) |
#define | HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk |
#define | HSEM_C1IER_ISE27_Pos (27U) |
#define | HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) |
#define | HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk |
#define | HSEM_C1IER_ISE28_Pos (28U) |
#define | HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) |
#define | HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk |
#define | HSEM_C1IER_ISE29_Pos (29U) |
#define | HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) |
#define | HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk |
#define | HSEM_C1IER_ISE30_Pos (30U) |
#define | HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) |
#define | HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk |
#define | HSEM_C1IER_ISE31_Pos (31U) |
#define | HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) |
#define | HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk |
#define | HSEM_C1ICR_ISC0_Pos (0U) |
#define | HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) |
#define | HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk |
#define | HSEM_C1ICR_ISC1_Pos (1U) |
#define | HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) |
#define | HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk |
#define | HSEM_C1ICR_ISC2_Pos (2U) |
#define | HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) |
#define | HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk |
#define | HSEM_C1ICR_ISC3_Pos (3U) |
#define | HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) |
#define | HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk |
#define | HSEM_C1ICR_ISC4_Pos (4U) |
#define | HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) |
#define | HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk |
#define | HSEM_C1ICR_ISC5_Pos (5U) |
#define | HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) |
#define | HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk |
#define | HSEM_C1ICR_ISC6_Pos (6U) |
#define | HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) |
#define | HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk |
#define | HSEM_C1ICR_ISC7_Pos (7U) |
#define | HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) |
#define | HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk |
#define | HSEM_C1ICR_ISC8_Pos (8U) |
#define | HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) |
#define | HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk |
#define | HSEM_C1ICR_ISC9_Pos (9U) |
#define | HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) |
#define | HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk |
#define | HSEM_C1ICR_ISC10_Pos (10U) |
#define | HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) |
#define | HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk |
#define | HSEM_C1ICR_ISC11_Pos (11U) |
#define | HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) |
#define | HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk |
#define | HSEM_C1ICR_ISC12_Pos (12U) |
#define | HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) |
#define | HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk |
#define | HSEM_C1ICR_ISC13_Pos (13U) |
#define | HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) |
#define | HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk |
#define | HSEM_C1ICR_ISC14_Pos (14U) |
#define | HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) |
#define | HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk |
#define | HSEM_C1ICR_ISC15_Pos (15U) |
#define | HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) |
#define | HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk |
#define | HSEM_C1ICR_ISC16_Pos (16U) |
#define | HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) |
#define | HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk |
#define | HSEM_C1ICR_ISC17_Pos (17U) |
#define | HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) |
#define | HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk |
#define | HSEM_C1ICR_ISC18_Pos (18U) |
#define | HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) |
#define | HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk |
#define | HSEM_C1ICR_ISC19_Pos (19U) |
#define | HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) |
#define | HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk |
#define | HSEM_C1ICR_ISC20_Pos (20U) |
#define | HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) |
#define | HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk |
#define | HSEM_C1ICR_ISC21_Pos (21U) |
#define | HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) |
#define | HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk |
#define | HSEM_C1ICR_ISC22_Pos (22U) |
#define | HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) |
#define | HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk |
#define | HSEM_C1ICR_ISC23_Pos (23U) |
#define | HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) |
#define | HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk |
#define | HSEM_C1ICR_ISC24_Pos (24U) |
#define | HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) |
#define | HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk |
#define | HSEM_C1ICR_ISC25_Pos (25U) |
#define | HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) |
#define | HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk |
#define | HSEM_C1ICR_ISC26_Pos (26U) |
#define | HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) |
#define | HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk |
#define | HSEM_C1ICR_ISC27_Pos (27U) |
#define | HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) |
#define | HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk |
#define | HSEM_C1ICR_ISC28_Pos (28U) |
#define | HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) |
#define | HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk |
#define | HSEM_C1ICR_ISC29_Pos (29U) |
#define | HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) |
#define | HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk |
#define | HSEM_C1ICR_ISC30_Pos (30U) |
#define | HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) |
#define | HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk |
#define | HSEM_C1ICR_ISC31_Pos (31U) |
#define | HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) |
#define | HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk |
#define | HSEM_C1ISR_ISF0_Pos (0U) |
#define | HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) |
#define | HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk |
#define | HSEM_C1ISR_ISF1_Pos (1U) |
#define | HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) |
#define | HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk |
#define | HSEM_C1ISR_ISF2_Pos (2U) |
#define | HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) |
#define | HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk |
#define | HSEM_C1ISR_ISF3_Pos (3U) |
#define | HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) |
#define | HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk |
#define | HSEM_C1ISR_ISF4_Pos (4U) |
#define | HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) |
#define | HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk |
#define | HSEM_C1ISR_ISF5_Pos (5U) |
#define | HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) |
#define | HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk |
#define | HSEM_C1ISR_ISF6_Pos (6U) |
#define | HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) |
#define | HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk |
#define | HSEM_C1ISR_ISF7_Pos (7U) |
#define | HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) |
#define | HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk |
#define | HSEM_C1ISR_ISF8_Pos (8U) |
#define | HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) |
#define | HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk |
#define | HSEM_C1ISR_ISF9_Pos (9U) |
#define | HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) |
#define | HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk |
#define | HSEM_C1ISR_ISF10_Pos (10U) |
#define | HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) |
#define | HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk |
#define | HSEM_C1ISR_ISF11_Pos (11U) |
#define | HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) |
#define | HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk |
#define | HSEM_C1ISR_ISF12_Pos (12U) |
#define | HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) |
#define | HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk |
#define | HSEM_C1ISR_ISF13_Pos (13U) |
#define | HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) |
#define | HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk |
#define | HSEM_C1ISR_ISF14_Pos (14U) |
#define | HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) |
#define | HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk |
#define | HSEM_C1ISR_ISF15_Pos (15U) |
#define | HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) |
#define | HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk |
#define | HSEM_C1ISR_ISF16_Pos (16U) |
#define | HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) |
#define | HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk |
#define | HSEM_C1ISR_ISF17_Pos (17U) |
#define | HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) |
#define | HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk |
#define | HSEM_C1ISR_ISF18_Pos (18U) |
#define | HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) |
#define | HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk |
#define | HSEM_C1ISR_ISF19_Pos (19U) |
#define | HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) |
#define | HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk |
#define | HSEM_C1ISR_ISF20_Pos (20U) |
#define | HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) |
#define | HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk |
#define | HSEM_C1ISR_ISF21_Pos (21U) |
#define | HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) |
#define | HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk |
#define | HSEM_C1ISR_ISF22_Pos (22U) |
#define | HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) |
#define | HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk |
#define | HSEM_C1ISR_ISF23_Pos (23U) |
#define | HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) |
#define | HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk |
#define | HSEM_C1ISR_ISF24_Pos (24U) |
#define | HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) |
#define | HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk |
#define | HSEM_C1ISR_ISF25_Pos (25U) |
#define | HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) |
#define | HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk |
#define | HSEM_C1ISR_ISF26_Pos (26U) |
#define | HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) |
#define | HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk |
#define | HSEM_C1ISR_ISF27_Pos (27U) |
#define | HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) |
#define | HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk |
#define | HSEM_C1ISR_ISF28_Pos (28U) |
#define | HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) |
#define | HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk |
#define | HSEM_C1ISR_ISF29_Pos (29U) |
#define | HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) |
#define | HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk |
#define | HSEM_C1ISR_ISF30_Pos (30U) |
#define | HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) |
#define | HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk |
#define | HSEM_C1ISR_ISF31_Pos (31U) |
#define | HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) |
#define | HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk |
#define | HSEM_C1MISR_MISF0_Pos (0U) |
#define | HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) |
#define | HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk |
#define | HSEM_C1MISR_MISF1_Pos (1U) |
#define | HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) |
#define | HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk |
#define | HSEM_C1MISR_MISF2_Pos (2U) |
#define | HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) |
#define | HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk |
#define | HSEM_C1MISR_MISF3_Pos (3U) |
#define | HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) |
#define | HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk |
#define | HSEM_C1MISR_MISF4_Pos (4U) |
#define | HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) |
#define | HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk |
#define | HSEM_C1MISR_MISF5_Pos (5U) |
#define | HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) |
#define | HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk |
#define | HSEM_C1MISR_MISF6_Pos (6U) |
#define | HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) |
#define | HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk |
#define | HSEM_C1MISR_MISF7_Pos (7U) |
#define | HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) |
#define | HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk |
#define | HSEM_C1MISR_MISF8_Pos (8U) |
#define | HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) |
#define | HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk |
#define | HSEM_C1MISR_MISF9_Pos (9U) |
#define | HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) |
#define | HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk |
#define | HSEM_C1MISR_MISF10_Pos (10U) |
#define | HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) |
#define | HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk |
#define | HSEM_C1MISR_MISF11_Pos (11U) |
#define | HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) |
#define | HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk |
#define | HSEM_C1MISR_MISF12_Pos (12U) |
#define | HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) |
#define | HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk |
#define | HSEM_C1MISR_MISF13_Pos (13U) |
#define | HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) |
#define | HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk |
#define | HSEM_C1MISR_MISF14_Pos (14U) |
#define | HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) |
#define | HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk |
#define | HSEM_C1MISR_MISF15_Pos (15U) |
#define | HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) |
#define | HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk |
#define | HSEM_C1MISR_MISF16_Pos (16U) |
#define | HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) |
#define | HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk |
#define | HSEM_C1MISR_MISF17_Pos (17U) |
#define | HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) |
#define | HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk |
#define | HSEM_C1MISR_MISF18_Pos (18U) |
#define | HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) |
#define | HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk |
#define | HSEM_C1MISR_MISF19_Pos (19U) |
#define | HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) |
#define | HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk |
#define | HSEM_C1MISR_MISF20_Pos (20U) |
#define | HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) |
#define | HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk |
#define | HSEM_C1MISR_MISF21_Pos (21U) |
#define | HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) |
#define | HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk |
#define | HSEM_C1MISR_MISF22_Pos (22U) |
#define | HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) |
#define | HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk |
#define | HSEM_C1MISR_MISF23_Pos (23U) |
#define | HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) |
#define | HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk |
#define | HSEM_C1MISR_MISF24_Pos (24U) |
#define | HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) |
#define | HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk |
#define | HSEM_C1MISR_MISF25_Pos (25U) |
#define | HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) |
#define | HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk |
#define | HSEM_C1MISR_MISF26_Pos (26U) |
#define | HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) |
#define | HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk |
#define | HSEM_C1MISR_MISF27_Pos (27U) |
#define | HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) |
#define | HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk |
#define | HSEM_C1MISR_MISF28_Pos (28U) |
#define | HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) |
#define | HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk |
#define | HSEM_C1MISR_MISF29_Pos (29U) |
#define | HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) |
#define | HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk |
#define | HSEM_C1MISR_MISF30_Pos (30U) |
#define | HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) |
#define | HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk |
#define | HSEM_C1MISR_MISF31_Pos (31U) |
#define | HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) |
#define | HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk |
#define | HSEM_CR_COREID_Pos (8U) |
#define | HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) |
#define | HSEM_CR_COREID HSEM_CR_COREID_Msk |
#define | HSEM_CR_KEY_Pos (16U) |
#define | HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) |
#define | HSEM_CR_KEY HSEM_CR_KEY_Msk |
#define | HSEM_KEYR_KEY_Pos (16U) |
#define | HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) |
#define | HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk |
#define | I2C_CR1_PE_Pos (0U) |
#define | I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) |
#define | I2C_CR1_PE I2C_CR1_PE_Msk |
#define | I2C_CR1_TXIE_Pos (1U) |
#define | I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) |
#define | I2C_CR1_TXIE I2C_CR1_TXIE_Msk |
#define | I2C_CR1_RXIE_Pos (2U) |
#define | I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) |
#define | I2C_CR1_RXIE I2C_CR1_RXIE_Msk |
#define | I2C_CR1_ADDRIE_Pos (3U) |
#define | I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) |
#define | I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk |
#define | I2C_CR1_NACKIE_Pos (4U) |
#define | I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) |
#define | I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk |
#define | I2C_CR1_STOPIE_Pos (5U) |
#define | I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) |
#define | I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk |
#define | I2C_CR1_TCIE_Pos (6U) |
#define | I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) |
#define | I2C_CR1_TCIE I2C_CR1_TCIE_Msk |
#define | I2C_CR1_ERRIE_Pos (7U) |
#define | I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) |
#define | I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk |
#define | I2C_CR1_DNF_Pos (8U) |
#define | I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) |
#define | I2C_CR1_DNF I2C_CR1_DNF_Msk |
#define | I2C_CR1_ANFOFF_Pos (12U) |
#define | I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) |
#define | I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk |
#define | I2C_CR1_TXDMAEN_Pos (14U) |
#define | I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) |
#define | I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk |
#define | I2C_CR1_RXDMAEN_Pos (15U) |
#define | I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) |
#define | I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk |
#define | I2C_CR1_SBC_Pos (16U) |
#define | I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) |
#define | I2C_CR1_SBC I2C_CR1_SBC_Msk |
#define | I2C_CR1_NOSTRETCH_Pos (17U) |
#define | I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) |
#define | I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk |
#define | I2C_CR1_WUPEN_Pos (18U) |
#define | I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) |
#define | I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk |
#define | I2C_CR1_GCEN_Pos (19U) |
#define | I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) |
#define | I2C_CR1_GCEN I2C_CR1_GCEN_Msk |
#define | I2C_CR1_SMBHEN_Pos (20U) |
#define | I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) |
#define | I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk |
#define | I2C_CR1_SMBDEN_Pos (21U) |
#define | I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) |
#define | I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk |
#define | I2C_CR1_ALERTEN_Pos (22U) |
#define | I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) |
#define | I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk |
#define | I2C_CR1_PECEN_Pos (23U) |
#define | I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) |
#define | I2C_CR1_PECEN I2C_CR1_PECEN_Msk |
#define | I2C_CR2_SADD_Pos (0U) |
#define | I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) |
#define | I2C_CR2_SADD I2C_CR2_SADD_Msk |
#define | I2C_CR2_RD_WRN_Pos (10U) |
#define | I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) |
#define | I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk |
#define | I2C_CR2_ADD10_Pos (11U) |
#define | I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) |
#define | I2C_CR2_ADD10 I2C_CR2_ADD10_Msk |
#define | I2C_CR2_HEAD10R_Pos (12U) |
#define | I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) |
#define | I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk |
#define | I2C_CR2_START_Pos (13U) |
#define | I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) |
#define | I2C_CR2_START I2C_CR2_START_Msk |
#define | I2C_CR2_STOP_Pos (14U) |
#define | I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) |
#define | I2C_CR2_STOP I2C_CR2_STOP_Msk |
#define | I2C_CR2_NACK_Pos (15U) |
#define | I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) |
#define | I2C_CR2_NACK I2C_CR2_NACK_Msk |
#define | I2C_CR2_NBYTES_Pos (16U) |
#define | I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) |
#define | I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk |
#define | I2C_CR2_RELOAD_Pos (24U) |
#define | I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) |
#define | I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk |
#define | I2C_CR2_AUTOEND_Pos (25U) |
#define | I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) |
#define | I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk |
#define | I2C_CR2_PECBYTE_Pos (26U) |
#define | I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) |
#define | I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk |
#define | I2C_OAR1_OA1_Pos (0U) |
#define | I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) |
#define | I2C_OAR1_OA1 I2C_OAR1_OA1_Msk |
#define | I2C_OAR1_OA1MODE_Pos (10U) |
#define | I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) |
#define | I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk |
#define | I2C_OAR1_OA1EN_Pos (15U) |
#define | I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) |
#define | I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk |
#define | I2C_OAR2_OA2_Pos (1U) |
#define | I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) |
#define | I2C_OAR2_OA2 I2C_OAR2_OA2_Msk |
#define | I2C_OAR2_OA2MSK_Pos (8U) |
#define | I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) |
#define | I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk |
#define | I2C_OAR2_OA2NOMASK 0x00000000UL |
#define | I2C_OAR2_OA2MASK01_Pos (8U) |
#define | I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) |
#define | I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk |
#define | I2C_OAR2_OA2MASK02_Pos (9U) |
#define | I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) |
#define | I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk |
#define | I2C_OAR2_OA2MASK03_Pos (8U) |
#define | I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) |
#define | I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk |
#define | I2C_OAR2_OA2MASK04_Pos (10U) |
#define | I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) |
#define | I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk |
#define | I2C_OAR2_OA2MASK05_Pos (8U) |
#define | I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) |
#define | I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk |
#define | I2C_OAR2_OA2MASK06_Pos (9U) |
#define | I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) |
#define | I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk |
#define | I2C_OAR2_OA2MASK07_Pos (8U) |
#define | I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) |
#define | I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk |
#define | I2C_OAR2_OA2EN_Pos (15U) |
#define | I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) |
#define | I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk |
#define | I2C_TIMINGR_SCLL_Pos (0U) |
#define | I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) |
#define | I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk |
#define | I2C_TIMINGR_SCLH_Pos (8U) |
#define | I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) |
#define | I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk |
#define | I2C_TIMINGR_SDADEL_Pos (16U) |
#define | I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) |
#define | I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk |
#define | I2C_TIMINGR_SCLDEL_Pos (20U) |
#define | I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) |
#define | I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk |
#define | I2C_TIMINGR_PRESC_Pos (28U) |
#define | I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) |
#define | I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk |
#define | I2C_TIMEOUTR_TIMEOUTA_Pos (0U) |
#define | I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) |
#define | I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk |
#define | I2C_TIMEOUTR_TIDLE_Pos (12U) |
#define | I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) |
#define | I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk |
#define | I2C_TIMEOUTR_TIMOUTEN_Pos (15U) |
#define | I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) |
#define | I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk |
#define | I2C_TIMEOUTR_TIMEOUTB_Pos (16U) |
#define | I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) |
#define | I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk |
#define | I2C_TIMEOUTR_TEXTEN_Pos (31U) |
#define | I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) |
#define | I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk |
#define | I2C_ISR_TXE_Pos (0U) |
#define | I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) |
#define | I2C_ISR_TXE I2C_ISR_TXE_Msk |
#define | I2C_ISR_TXIS_Pos (1U) |
#define | I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) |
#define | I2C_ISR_TXIS I2C_ISR_TXIS_Msk |
#define | I2C_ISR_RXNE_Pos (2U) |
#define | I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) |
#define | I2C_ISR_RXNE I2C_ISR_RXNE_Msk |
#define | I2C_ISR_ADDR_Pos (3U) |
#define | I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) |
#define | I2C_ISR_ADDR I2C_ISR_ADDR_Msk |
#define | I2C_ISR_NACKF_Pos (4U) |
#define | I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) |
#define | I2C_ISR_NACKF I2C_ISR_NACKF_Msk |
#define | I2C_ISR_STOPF_Pos (5U) |
#define | I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) |
#define | I2C_ISR_STOPF I2C_ISR_STOPF_Msk |
#define | I2C_ISR_TC_Pos (6U) |
#define | I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) |
#define | I2C_ISR_TC I2C_ISR_TC_Msk |
#define | I2C_ISR_TCR_Pos (7U) |
#define | I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) |
#define | I2C_ISR_TCR I2C_ISR_TCR_Msk |
#define | I2C_ISR_BERR_Pos (8U) |
#define | I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) |
#define | I2C_ISR_BERR I2C_ISR_BERR_Msk |
#define | I2C_ISR_ARLO_Pos (9U) |
#define | I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) |
#define | I2C_ISR_ARLO I2C_ISR_ARLO_Msk |
#define | I2C_ISR_OVR_Pos (10U) |
#define | I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) |
#define | I2C_ISR_OVR I2C_ISR_OVR_Msk |
#define | I2C_ISR_PECERR_Pos (11U) |
#define | I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) |
#define | I2C_ISR_PECERR I2C_ISR_PECERR_Msk |
#define | I2C_ISR_TIMEOUT_Pos (12U) |
#define | I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) |
#define | I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk |
#define | I2C_ISR_ALERT_Pos (13U) |
#define | I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) |
#define | I2C_ISR_ALERT I2C_ISR_ALERT_Msk |
#define | I2C_ISR_BUSY_Pos (15U) |
#define | I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) |
#define | I2C_ISR_BUSY I2C_ISR_BUSY_Msk |
#define | I2C_ISR_DIR_Pos (16U) |
#define | I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) |
#define | I2C_ISR_DIR I2C_ISR_DIR_Msk |
#define | I2C_ISR_ADDCODE_Pos (17U) |
#define | I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) |
#define | I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk |
#define | I2C_ICR_ADDRCF_Pos (3U) |
#define | I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) |
#define | I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk |
#define | I2C_ICR_NACKCF_Pos (4U) |
#define | I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) |
#define | I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk |
#define | I2C_ICR_STOPCF_Pos (5U) |
#define | I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) |
#define | I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk |
#define | I2C_ICR_BERRCF_Pos (8U) |
#define | I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) |
#define | I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk |
#define | I2C_ICR_ARLOCF_Pos (9U) |
#define | I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) |
#define | I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk |
#define | I2C_ICR_OVRCF_Pos (10U) |
#define | I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) |
#define | I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk |
#define | I2C_ICR_PECCF_Pos (11U) |
#define | I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) |
#define | I2C_ICR_PECCF I2C_ICR_PECCF_Msk |
#define | I2C_ICR_TIMOUTCF_Pos (12U) |
#define | I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) |
#define | I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk |
#define | I2C_ICR_ALERTCF_Pos (13U) |
#define | I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) |
#define | I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk |
#define | I2C_PECR_PEC_Pos (0U) |
#define | I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) |
#define | I2C_PECR_PEC I2C_PECR_PEC_Msk |
#define | I2C_RXDR_RXDATA_Pos (0U) |
#define | I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) |
#define | I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk |
#define | I2C_TXDR_TXDATA_Pos (0U) |
#define | I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) |
#define | I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk |
#define | IWDG_KR_KEY_Pos (0U) |
#define | IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) |
#define | IWDG_KR_KEY IWDG_KR_KEY_Msk |
#define | IWDG_PR_PR_Pos (0U) |
#define | IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) |
#define | IWDG_PR_PR IWDG_PR_PR_Msk |
#define | IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) |
#define | IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) |
#define | IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) |
#define | IWDG_RLR_RL_Pos (0U) |
#define | IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) |
#define | IWDG_RLR_RL IWDG_RLR_RL_Msk |
#define | IWDG_SR_PVU_Pos (0U) |
#define | IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) |
#define | IWDG_SR_PVU IWDG_SR_PVU_Msk |
#define | IWDG_SR_RVU_Pos (1U) |
#define | IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) |
#define | IWDG_SR_RVU IWDG_SR_RVU_Msk |
#define | IWDG_SR_WVU_Pos (2U) |
#define | IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) |
#define | IWDG_SR_WVU IWDG_SR_WVU_Msk |
#define | IWDG_WINR_WIN_Pos (0U) |
#define | IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) |
#define | IWDG_WINR_WIN IWDG_WINR_WIN_Msk |
#define | MDMA_GISR0_GIF0_Pos (0U) |
#define | MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) |
#define | MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk |
#define | MDMA_GISR0_GIF1_Pos (1U) |
#define | MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) |
#define | MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk |
#define | MDMA_GISR0_GIF2_Pos (2U) |
#define | MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) |
#define | MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk |
#define | MDMA_GISR0_GIF3_Pos (3U) |
#define | MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) |
#define | MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk |
#define | MDMA_GISR0_GIF4_Pos (4U) |
#define | MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) |
#define | MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk |
#define | MDMA_GISR0_GIF5_Pos (5U) |
#define | MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) |
#define | MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk |
#define | MDMA_GISR0_GIF6_Pos (6U) |
#define | MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) |
#define | MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk |
#define | MDMA_GISR0_GIF7_Pos (7U) |
#define | MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) |
#define | MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk |
#define | MDMA_GISR0_GIF8_Pos (8U) |
#define | MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) |
#define | MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk |
#define | MDMA_GISR0_GIF9_Pos (9U) |
#define | MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) |
#define | MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk |
#define | MDMA_GISR0_GIF10_Pos (10U) |
#define | MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) |
#define | MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk |
#define | MDMA_GISR0_GIF11_Pos (11U) |
#define | MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) |
#define | MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk |
#define | MDMA_GISR0_GIF12_Pos (12U) |
#define | MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) |
#define | MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk |
#define | MDMA_GISR0_GIF13_Pos (13U) |
#define | MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) |
#define | MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk |
#define | MDMA_GISR0_GIF14_Pos (14U) |
#define | MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) |
#define | MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk |
#define | MDMA_GISR0_GIF15_Pos (15U) |
#define | MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) |
#define | MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk |
#define | MDMA_CISR_TEIF_Pos (0U) |
#define | MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) |
#define | MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk |
#define | MDMA_CISR_CTCIF_Pos (1U) |
#define | MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) |
#define | MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk |
#define | MDMA_CISR_BRTIF_Pos (2U) |
#define | MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) |
#define | MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk |
#define | MDMA_CISR_BTIF_Pos (3U) |
#define | MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) |
#define | MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk |
#define | MDMA_CISR_TCIF_Pos (4U) |
#define | MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) |
#define | MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk |
#define | MDMA_CISR_CRQA_Pos (16U) |
#define | MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) |
#define | MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk |
#define | MDMA_CIFCR_CTEIF_Pos (0U) |
#define | MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) |
#define | MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk |
#define | MDMA_CIFCR_CCTCIF_Pos (1U) |
#define | MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) |
#define | MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk |
#define | MDMA_CIFCR_CBRTIF_Pos (2U) |
#define | MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) |
#define | MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk |
#define | MDMA_CIFCR_CBTIF_Pos (3U) |
#define | MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) |
#define | MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk |
#define | MDMA_CIFCR_CLTCIF_Pos (4U) |
#define | MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) |
#define | MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk |
#define | MDMA_CESR_TEA_Pos (0U) |
#define | MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) |
#define | MDMA_CESR_TEA MDMA_CESR_TEA_Msk |
#define | MDMA_CESR_TED_Pos (7U) |
#define | MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) |
#define | MDMA_CESR_TED MDMA_CESR_TED_Msk |
#define | MDMA_CESR_TELD_Pos (8U) |
#define | MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) |
#define | MDMA_CESR_TELD MDMA_CESR_TELD_Msk |
#define | MDMA_CESR_TEMD_Pos (9U) |
#define | MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) |
#define | MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk |
#define | MDMA_CESR_ASE_Pos (10U) |
#define | MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) |
#define | MDMA_CESR_ASE MDMA_CESR_ASE_Msk |
#define | MDMA_CESR_BSE_Pos (11U) |
#define | MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) |
#define | MDMA_CESR_BSE MDMA_CESR_BSE_Msk |
#define | MDMA_CCR_EN_Pos (0U) |
#define | MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) |
#define | MDMA_CCR_EN MDMA_CCR_EN_Msk |
#define | MDMA_CCR_TEIE_Pos (1U) |
#define | MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) |
#define | MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk |
#define | MDMA_CCR_CTCIE_Pos (2U) |
#define | MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) |
#define | MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk |
#define | MDMA_CCR_BRTIE_Pos (3U) |
#define | MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) |
#define | MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk |
#define | MDMA_CCR_BTIE_Pos (4U) |
#define | MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) |
#define | MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk |
#define | MDMA_CCR_TCIE_Pos (5U) |
#define | MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) |
#define | MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk |
#define | MDMA_CCR_PL_Pos (6U) |
#define | MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) |
#define | MDMA_CCR_PL MDMA_CCR_PL_Msk |
#define | MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) |
#define | MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) |
#define | MDMA_CCR_BEX_Pos (12U) |
#define | MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) |
#define | MDMA_CCR_BEX MDMA_CCR_BEX_Msk |
#define | MDMA_CCR_HEX_Pos (13U) |
#define | MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) |
#define | MDMA_CCR_HEX MDMA_CCR_HEX_Msk |
#define | MDMA_CCR_WEX_Pos (14U) |
#define | MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) |
#define | MDMA_CCR_WEX MDMA_CCR_WEX_Msk |
#define | MDMA_CCR_SWRQ_Pos (16U) |
#define | MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) |
#define | MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk |
#define | MDMA_CTCR_SINC_Pos (0U) |
#define | MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) |
#define | MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk |
#define | MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) |
#define | MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) |
#define | MDMA_CTCR_DINC_Pos (2U) |
#define | MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) |
#define | MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk |
#define | MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) |
#define | MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) |
#define | MDMA_CTCR_SSIZE_Pos (4U) |
#define | MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) |
#define | MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk |
#define | MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) |
#define | MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) |
#define | MDMA_CTCR_DSIZE_Pos (6U) |
#define | MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) |
#define | MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk |
#define | MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) |
#define | MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) |
#define | MDMA_CTCR_SINCOS_Pos (8U) |
#define | MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) |
#define | MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk |
#define | MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) |
#define | MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) |
#define | MDMA_CTCR_DINCOS_Pos (10U) |
#define | MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) |
#define | MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk |
#define | MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) |
#define | MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) |
#define | MDMA_CTCR_SBURST_Pos (12U) |
#define | MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) |
#define | MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk |
#define | MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) |
#define | MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) |
#define | MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) |
#define | MDMA_CTCR_DBURST_Pos (15U) |
#define | MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) |
#define | MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk |
#define | MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) |
#define | MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) |
#define | MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) |
#define | MDMA_CTCR_TLEN_Pos (18U) |
#define | MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) |
#define | MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk |
#define | MDMA_CTCR_PKE_Pos (25U) |
#define | MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) |
#define | MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk |
#define | MDMA_CTCR_PAM_Pos (26U) |
#define | MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) |
#define | MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk |
#define | MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) |
#define | MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) |
#define | MDMA_CTCR_TRGM_Pos (28U) |
#define | MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) |
#define | MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk |
#define | MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) |
#define | MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) |
#define | MDMA_CTCR_SWRM_Pos (30U) |
#define | MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) |
#define | MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk |
#define | MDMA_CTCR_BWM_Pos (31U) |
#define | MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) |
#define | MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk |
#define | MDMA_CBNDTR_BNDT_Pos (0U) |
#define | MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) |
#define | MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk |
#define | MDMA_CBNDTR_BRSUM_Pos (18U) |
#define | MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) |
#define | MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk |
#define | MDMA_CBNDTR_BRDUM_Pos (19U) |
#define | MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) |
#define | MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk |
#define | MDMA_CBNDTR_BRC_Pos (20U) |
#define | MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) |
#define | MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk |
#define | MDMA_CSAR_SAR_Pos (0U) |
#define | MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) |
#define | MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk |
#define | MDMA_CDAR_DAR_Pos (0U) |
#define | MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) |
#define | MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk |
#define | MDMA_CBRUR_SUV_Pos (0U) |
#define | MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) |
#define | MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk |
#define | MDMA_CBRUR_DUV_Pos (16U) |
#define | MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) |
#define | MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk |
#define | MDMA_CLAR_LAR_Pos (0U) |
#define | MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) |
#define | MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk |
#define | MDMA_CTBR_TSEL_Pos (0U) |
#define | MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) |
#define | MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk |
#define | MDMA_CTBR_SBUS_Pos (16U) |
#define | MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) |
#define | MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk |
#define | MDMA_CTBR_DBUS_Pos (17U) |
#define | MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) |
#define | MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk |
#define | MDMA_CMAR_MAR_Pos (0U) |
#define | MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) |
#define | MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk |
#define | MDMA_CMDR_MDR_Pos (0U) |
#define | MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) |
#define | MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk |
#define | OPAMP_CSR_OPAMPxEN_Pos (0U) |
#define | OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) |
#define | OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk |
#define | OPAMP_CSR_FORCEVP_Pos (1U) |
#define | OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) |
#define | OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk |
#define | OPAMP_CSR_VPSEL_Pos (2U) |
#define | OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) |
#define | OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk |
#define | OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) |
#define | OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) |
#define | OPAMP_CSR_VMSEL_Pos (5U) |
#define | OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) |
#define | OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk |
#define | OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) |
#define | OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) |
#define | OPAMP_CSR_OPAHSM_Pos (8U) |
#define | OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) |
#define | OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk |
#define | OPAMP_CSR_CALON_Pos (11U) |
#define | OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) |
#define | OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk |
#define | OPAMP_CSR_CALSEL_Pos (12U) |
#define | OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) |
#define | OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk |
#define | OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) |
#define | OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) |
#define | OPAMP_CSR_PGGAIN_Pos (14U) |
#define | OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) |
#define | OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk |
#define | OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) |
#define | OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) |
#define | OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) |
#define | OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) |
#define | OPAMP_CSR_USERTRIM_Pos (18U) |
#define | OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) |
#define | OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk |
#define | OPAMP_CSR_TSTREF_Pos (29U) |
#define | OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) |
#define | OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk |
#define | OPAMP_CSR_CALOUT_Pos (30U) |
#define | OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) |
#define | OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk |
#define | OPAMP1_CSR_OPAEN_Pos (0U) |
#define | OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) |
#define | OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk |
#define | OPAMP1_CSR_FORCEVP_Pos (1U) |
#define | OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) |
#define | OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk |
#define | OPAMP1_CSR_VPSEL_Pos (2U) |
#define | OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) |
#define | OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk |
#define | OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) |
#define | OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) |
#define | OPAMP1_CSR_VMSEL_Pos (5U) |
#define | OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) |
#define | OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk |
#define | OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) |
#define | OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) |
#define | OPAMP1_CSR_OPAHSM_Pos (8U) |
#define | OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) |
#define | OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk |
#define | OPAMP1_CSR_CALON_Pos (11U) |
#define | OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) |
#define | OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk |
#define | OPAMP1_CSR_CALSEL_Pos (12U) |
#define | OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) |
#define | OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk |
#define | OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) |
#define | OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) |
#define | OPAMP1_CSR_PGGAIN_Pos (14U) |
#define | OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) |
#define | OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk |
#define | OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) |
#define | OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) |
#define | OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) |
#define | OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) |
#define | OPAMP1_CSR_USERTRIM_Pos (18U) |
#define | OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) |
#define | OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk |
#define | OPAMP1_CSR_TSTREF_Pos (29U) |
#define | OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) |
#define | OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk |
#define | OPAMP1_CSR_CALOUT_Pos (30U) |
#define | OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) |
#define | OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk |
#define | OPAMP2_CSR_OPAEN_Pos (0U) |
#define | OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) |
#define | OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk |
#define | OPAMP2_CSR_FORCEVP_Pos (1U) |
#define | OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) |
#define | OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk |
#define | OPAMP2_CSR_VPSEL_Pos (2U) |
#define | OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) |
#define | OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk |
#define | OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) |
#define | OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) |
#define | OPAMP2_CSR_VMSEL_Pos (5U) |
#define | OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) |
#define | OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk |
#define | OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) |
#define | OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) |
#define | OPAMP2_CSR_OPAHSM_Pos (8U) |
#define | OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) |
#define | OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk |
#define | OPAMP2_CSR_CALON_Pos (11U) |
#define | OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) |
#define | OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk |
#define | OPAMP2_CSR_CALSEL_Pos (12U) |
#define | OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) |
#define | OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk |
#define | OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) |
#define | OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) |
#define | OPAMP2_CSR_PGGAIN_Pos (14U) |
#define | OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) |
#define | OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk |
#define | OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) |
#define | OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) |
#define | OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) |
#define | OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) |
#define | OPAMP2_CSR_USERTRIM_Pos (18U) |
#define | OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) |
#define | OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk |
#define | OPAMP2_CSR_TSTREF_Pos (29U) |
#define | OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) |
#define | OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk |
#define | OPAMP2_CSR_CALOUT_Pos (30U) |
#define | OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) |
#define | OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk |
#define | OPAMP_OTR_TRIMOFFSETN_Pos (0U) |
#define | OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) |
#define | OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk |
#define | OPAMP_OTR_TRIMOFFSETP_Pos (8U) |
#define | OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) |
#define | OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk |
#define | OPAMP1_OTR_TRIMOFFSETN_Pos (0U) |
#define | OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) |
#define | OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk |
#define | OPAMP1_OTR_TRIMOFFSETP_Pos (8U) |
#define | OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) |
#define | OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk |
#define | OPAMP2_OTR_TRIMOFFSETN_Pos (0U) |
#define | OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) |
#define | OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk |
#define | OPAMP2_OTR_TRIMOFFSETP_Pos (8U) |
#define | OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) |
#define | OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk |
#define | OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U) |
#define | OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) |
#define | OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk |
#define | OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U) |
#define | OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) |
#define | OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk |
#define | OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U) |
#define | OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) |
#define | OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk |
#define | OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U) |
#define | OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) |
#define | OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk |
#define | OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U) |
#define | OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) |
#define | OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk |
#define | OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U) |
#define | OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) |
#define | OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk |
#define | POWER_DOMAINS_NUMBER 3U |
#define | PWR_CR1_ALS_Pos (17U) |
#define | PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) |
#define | PWR_CR1_ALS PWR_CR1_ALS_Msk |
#define | PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) |
#define | PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) |
#define | PWR_CR1_AVDEN_Pos (16U) |
#define | PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) |
#define | PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk |
#define | PWR_CR1_SVOS_Pos (14U) |
#define | PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) |
#define | PWR_CR1_SVOS PWR_CR1_SVOS_Msk |
#define | PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) |
#define | PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) |
#define | PWR_CR1_FLPS_Pos (9U) |
#define | PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) |
#define | PWR_CR1_FLPS PWR_CR1_FLPS_Msk |
#define | PWR_CR1_DBP_Pos (8U) |
#define | PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) |
#define | PWR_CR1_DBP PWR_CR1_DBP_Msk |
#define | PWR_CR1_PLS_Pos (5U) |
#define | PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) |
#define | PWR_CR1_PLS PWR_CR1_PLS_Msk |
#define | PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) |
#define | PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) |
#define | PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) |
#define | PWR_CR1_PVDEN_Pos (4U) |
#define | PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) |
#define | PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk |
#define | PWR_CR1_LPDS_Pos (0U) |
#define | PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) |
#define | PWR_CR1_LPDS PWR_CR1_LPDS_Msk |
#define | PWR_CR1_PLS_LEV0 (0UL) |
#define | PWR_CR1_PLS_LEV1_Pos (5U) |
#define | PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) |
#define | PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk |
#define | PWR_CR1_PLS_LEV2_Pos (6U) |
#define | PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) |
#define | PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk |
#define | PWR_CR1_PLS_LEV3_Pos (5U) |
#define | PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) |
#define | PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk |
#define | PWR_CR1_PLS_LEV4_Pos (7U) |
#define | PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) |
#define | PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk |
#define | PWR_CR1_PLS_LEV5_Pos (5U) |
#define | PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) |
#define | PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk |
#define | PWR_CR1_PLS_LEV6_Pos (6U) |
#define | PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) |
#define | PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk |
#define | PWR_CR1_PLS_LEV7_Pos (5U) |
#define | PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) |
#define | PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk |
#define | PWR_CR1_ALS_LEV0 (0UL) |
#define | PWR_CR1_ALS_LEV1_Pos (17U) |
#define | PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) |
#define | PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk |
#define | PWR_CR1_ALS_LEV2_Pos (18U) |
#define | PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) |
#define | PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk |
#define | PWR_CR1_ALS_LEV3_Pos (17U) |
#define | PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) |
#define | PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk |
#define | PWR_CSR1_AVDO_Pos (16U) |
#define | PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) |
#define | PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk |
#define | PWR_CSR1_ACTVOS_Pos (14U) |
#define | PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) |
#define | PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk |
#define | PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) |
#define | PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) |
#define | PWR_CSR1_ACTVOSRDY_Pos (13U) |
#define | PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) |
#define | PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk |
#define | PWR_CSR1_PVDO_Pos (4U) |
#define | PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) |
#define | PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk |
#define | PWR_CR2_TEMPH_Pos (23U) |
#define | PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) |
#define | PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk |
#define | PWR_CR2_TEMPL_Pos (22U) |
#define | PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) |
#define | PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk |
#define | PWR_CR2_VBATH_Pos (21U) |
#define | PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) |
#define | PWR_CR2_VBATH PWR_CR2_VBATH_Msk |
#define | PWR_CR2_VBATL_Pos (20U) |
#define | PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) |
#define | PWR_CR2_VBATL PWR_CR2_VBATL_Msk |
#define | PWR_CR2_BRRDY_Pos (16U) |
#define | PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) |
#define | PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk |
#define | PWR_CR2_MONEN_Pos (4U) |
#define | PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) |
#define | PWR_CR2_MONEN PWR_CR2_MONEN_Msk |
#define | PWR_CR2_BREN_Pos (0U) |
#define | PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) |
#define | PWR_CR2_BREN PWR_CR2_BREN_Msk |
#define | PWR_CR3_USB33RDY_Pos (26U) |
#define | PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) |
#define | PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk |
#define | PWR_CR3_USBREGEN_Pos (25U) |
#define | PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) |
#define | PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk |
#define | PWR_CR3_USB33DEN_Pos (24U) |
#define | PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) |
#define | PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk |
#define | PWR_CR3_VBRS_Pos (9U) |
#define | PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) |
#define | PWR_CR3_VBRS PWR_CR3_VBRS_Msk |
#define | PWR_CR3_VBE_Pos (8U) |
#define | PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) |
#define | PWR_CR3_VBE PWR_CR3_VBE_Msk |
#define | PWR_CR3_SCUEN_Pos (2U) |
#define | PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos) |
#define | PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk |
#define | PWR_CR3_LDOEN_Pos (1U) |
#define | PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) |
#define | PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk |
#define | PWR_CR3_BYPASS_Pos (0U) |
#define | PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) |
#define | PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk |
#define | PWR_CPUCR_RUN_D3_Pos (11U) |
#define | PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) |
#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk |
#define | PWR_CPUCR_CSSF_Pos (9U) |
#define | PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) |
#define | PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk |
#define | PWR_CPUCR_SBF_D2_Pos (8U) |
#define | PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) |
#define | PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk |
#define | PWR_CPUCR_SBF_D1_Pos (7U) |
#define | PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) |
#define | PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk |
#define | PWR_CPUCR_SBF_Pos (6U) |
#define | PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) |
#define | PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk |
#define | PWR_CPUCR_STOPF_Pos (5U) |
#define | PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) |
#define | PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk |
#define | PWR_CPUCR_PDDS_D3_Pos (2U) |
#define | PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) |
#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk |
#define | PWR_CPUCR_PDDS_D2_Pos (1U) |
#define | PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) |
#define | PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk |
#define | PWR_CPUCR_PDDS_D1_Pos (0U) |
#define | PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) |
#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk |
#define | PWR_D3CR_VOS_Pos (14U) |
#define | PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) |
#define | PWR_D3CR_VOS PWR_D3CR_VOS_Msk |
#define | PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) |
#define | PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) |
#define | PWR_D3CR_VOSRDY_Pos (13U) |
#define | PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) |
#define | PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk |
#define | PWR_WKUPCR_WKUPC6_Pos (5U) |
#define | PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) |
#define | PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk |
#define | PWR_WKUPCR_WKUPC5_Pos (4U) |
#define | PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) |
#define | PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk |
#define | PWR_WKUPCR_WKUPC4_Pos (3U) |
#define | PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) |
#define | PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk |
#define | PWR_WKUPCR_WKUPC3_Pos (2U) |
#define | PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) |
#define | PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk |
#define | PWR_WKUPCR_WKUPC2_Pos (1U) |
#define | PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) |
#define | PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk |
#define | PWR_WKUPCR_WKUPC1_Pos (0U) |
#define | PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) |
#define | PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk |
#define | PWR_WKUPFR_WKUPF6_Pos (5U) |
#define | PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) |
#define | PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk |
#define | PWR_WKUPFR_WKUPF5_Pos (4U) |
#define | PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) |
#define | PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk |
#define | PWR_WKUPFR_WKUPF4_Pos (3U) |
#define | PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) |
#define | PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk |
#define | PWR_WKUPFR_WKUPF3_Pos (2U) |
#define | PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) |
#define | PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk |
#define | PWR_WKUPFR_WKUPF2_Pos (1U) |
#define | PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) |
#define | PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk |
#define | PWR_WKUPFR_WKUPF1_Pos (0U) |
#define | PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) |
#define | PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk |
#define | PWR_WKUPEPR_WKUPPUPD6_Pos (26U) |
#define | PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk |
#define | PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD5_Pos (24U) |
#define | PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk |
#define | PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD4_Pos (22U) |
#define | PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk |
#define | PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD3_Pos (20U) |
#define | PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk |
#define | PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD2_Pos (18U) |
#define | PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk |
#define | PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD1_Pos (16U) |
#define | PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk |
#define | PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) |
#define | PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) |
#define | PWR_WKUPEPR_WKUPP6_Pos (13U) |
#define | PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) |
#define | PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk |
#define | PWR_WKUPEPR_WKUPP5_Pos (12U) |
#define | PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) |
#define | PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk |
#define | PWR_WKUPEPR_WKUPP4_Pos (11U) |
#define | PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) |
#define | PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk |
#define | PWR_WKUPEPR_WKUPP3_Pos (10U) |
#define | PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) |
#define | PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk |
#define | PWR_WKUPEPR_WKUPP2_Pos (9U) |
#define | PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) |
#define | PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk |
#define | PWR_WKUPEPR_WKUPP1_Pos (8U) |
#define | PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) |
#define | PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk |
#define | PWR_WKUPEPR_WKUPEN6_Pos (5U) |
#define | PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) |
#define | PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk |
#define | PWR_WKUPEPR_WKUPEN5_Pos (4U) |
#define | PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) |
#define | PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk |
#define | PWR_WKUPEPR_WKUPEN4_Pos (3U) |
#define | PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) |
#define | PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk |
#define | PWR_WKUPEPR_WKUPEN3_Pos (2U) |
#define | PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) |
#define | PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk |
#define | PWR_WKUPEPR_WKUPEN2_Pos (1U) |
#define | PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) |
#define | PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk |
#define | PWR_WKUPEPR_WKUPEN1_Pos (0U) |
#define | PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) |
#define | PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk |
#define | PWR_WKUPEPR_WKUPEN_Pos (0U) |
#define | PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) |
#define | PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk |
#define | RCC_VER_X |
#define | RCC_CR_HSION_Pos (0U) |
#define | RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) |
#define | RCC_CR_HSION RCC_CR_HSION_Msk |
#define | RCC_CR_HSIKERON_Pos (1U) |
#define | RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) |
#define | RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk |
#define | RCC_CR_HSIRDY_Pos (2U) |
#define | RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) |
#define | RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk |
#define | RCC_CR_HSIDIV_Pos (3U) |
#define | RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) |
#define | RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk |
#define | RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) |
#define | RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) |
#define | RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) |
#define | RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) |
#define | RCC_CR_HSIDIVF_Pos (5U) |
#define | RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) |
#define | RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk |
#define | RCC_CR_CSION_Pos (7U) |
#define | RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) |
#define | RCC_CR_CSION RCC_CR_CSION_Msk |
#define | RCC_CR_CSIRDY_Pos (8U) |
#define | RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) |
#define | RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk |
#define | RCC_CR_CSIKERON_Pos (9U) |
#define | RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) |
#define | RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk |
#define | RCC_CR_HSI48ON_Pos (12U) |
#define | RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) |
#define | RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk |
#define | RCC_CR_HSI48RDY_Pos (13U) |
#define | RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) |
#define | RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk |
#define | RCC_CR_D1CKRDY_Pos (14U) |
#define | RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) |
#define | RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk |
#define | RCC_CR_D2CKRDY_Pos (15U) |
#define | RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) |
#define | RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk |
#define | RCC_CR_HSEON_Pos (16U) |
#define | RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) |
#define | RCC_CR_HSEON RCC_CR_HSEON_Msk |
#define | RCC_CR_HSERDY_Pos (17U) |
#define | RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) |
#define | RCC_CR_HSERDY RCC_CR_HSERDY_Msk |
#define | RCC_CR_HSEBYP_Pos (18U) |
#define | RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) |
#define | RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk |
#define | RCC_CR_CSSHSEON_Pos (19U) |
#define | RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) |
#define | RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk |
#define | RCC_CR_PLL1ON_Pos (24U) |
#define | RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) |
#define | RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk |
#define | RCC_CR_PLL1RDY_Pos (25U) |
#define | RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) |
#define | RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk |
#define | RCC_CR_PLL2ON_Pos (26U) |
#define | RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) |
#define | RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk |
#define | RCC_CR_PLL2RDY_Pos (27U) |
#define | RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) |
#define | RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk |
#define | RCC_CR_PLL3ON_Pos (28U) |
#define | RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) |
#define | RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk |
#define | RCC_CR_PLL3RDY_Pos (29U) |
#define | RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) |
#define | RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk |
#define | RCC_CR_PLLON_Pos (24U) |
#define | RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) |
#define | RCC_CR_PLLON RCC_CR_PLLON_Msk |
#define | RCC_CR_PLLRDY_Pos (25U) |
#define | RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) |
#define | RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk |
#define | RCC_HSICFGR_HSICAL_Pos (0U) |
#define | RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk |
#define | RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) |
#define | RCC_HSICFGR_HSITRIM_Pos (24U) |
#define | RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk |
#define | RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) |
#define | RCC_CRRCR_HSI48CAL_Pos (0U) |
#define | RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk |
#define | RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) |
#define | RCC_CSICFGR_CSICAL_Pos (0U) |
#define | RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk |
#define | RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) |
#define | RCC_CSICFGR_CSITRIM_Pos (24U) |
#define | RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk |
#define | RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) |
#define | RCC_CFGR_SW_Pos (0U) |
#define | RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) |
#define | RCC_CFGR_SW RCC_CFGR_SW_Msk |
#define | RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) |
#define | RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) |
#define | RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) |
#define | RCC_CFGR_SW_HSI (0x00000000UL) |
#define | RCC_CFGR_SW_CSI (0x00000001UL) |
#define | RCC_CFGR_SW_HSE (0x00000002UL) |
#define | RCC_CFGR_SW_PLL1 (0x00000003UL) |
#define | RCC_CFGR_SWS_Pos (3U) |
#define | RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) |
#define | RCC_CFGR_SWS RCC_CFGR_SWS_Msk |
#define | RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) |
#define | RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) |
#define | RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) |
#define | RCC_CFGR_SWS_HSI (0x00000000UL) |
#define | RCC_CFGR_SWS_CSI (0x00000008UL) |
#define | RCC_CFGR_SWS_HSE (0x00000010UL) |
#define | RCC_CFGR_SWS_PLL1 (0x00000018UL) |
#define | RCC_CFGR_STOPWUCK_Pos (6U) |
#define | RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) |
#define | RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk |
#define | RCC_CFGR_STOPKERWUCK_Pos (7U) |
#define | RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) |
#define | RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk |
#define | RCC_CFGR_RTCPRE_Pos (8U) |
#define | RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk |
#define | RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) |
#define | RCC_CFGR_HRTIMSEL_Pos (14U) |
#define | RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos) |
#define | RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk |
#define | RCC_CFGR_TIMPRE_Pos (15U) |
#define | RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) |
#define | RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk |
#define | RCC_CFGR_MCO1_Pos (22U) |
#define | RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos) |
#define | RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk |
#define | RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) |
#define | RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) |
#define | RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) |
#define | RCC_CFGR_MCO1PRE_Pos (18U) |
#define | RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) |
#define | RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk |
#define | RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) |
#define | RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) |
#define | RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) |
#define | RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) |
#define | RCC_CFGR_MCO2PRE_Pos (25U) |
#define | RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) |
#define | RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk |
#define | RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) |
#define | RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) |
#define | RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) |
#define | RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) |
#define | RCC_CFGR_MCO2_Pos (29U) |
#define | RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos) |
#define | RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk |
#define | RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) |
#define | RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) |
#define | RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) |
#define | RCC_D1CFGR_HPRE_Pos (0U) |
#define | RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) |
#define | RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk |
#define | RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) |
#define | RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) |
#define | RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) |
#define | RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) |
#define | RCC_D1CFGR_HPRE_DIV1 (0U) |
#define | RCC_D1CFGR_HPRE_DIV2_Pos (3U) |
#define | RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) |
#define | RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk |
#define | RCC_D1CFGR_HPRE_DIV4_Pos (0U) |
#define | RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) |
#define | RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk |
#define | RCC_D1CFGR_HPRE_DIV8_Pos (1U) |
#define | RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) |
#define | RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk |
#define | RCC_D1CFGR_HPRE_DIV16_Pos (0U) |
#define | RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) |
#define | RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk |
#define | RCC_D1CFGR_HPRE_DIV64_Pos (2U) |
#define | RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) |
#define | RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk |
#define | RCC_D1CFGR_HPRE_DIV128_Pos (0U) |
#define | RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) |
#define | RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk |
#define | RCC_D1CFGR_HPRE_DIV256_Pos (1U) |
#define | RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) |
#define | RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk |
#define | RCC_D1CFGR_HPRE_DIV512_Pos (0U) |
#define | RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) |
#define | RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk |
#define | RCC_D1CFGR_D1PPRE_Pos (4U) |
#define | RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) |
#define | RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk |
#define | RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) |
#define | RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) |
#define | RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) |
#define | RCC_D1CFGR_D1PPRE_DIV1 (0U) |
#define | RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) |
#define | RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) |
#define | RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk |
#define | RCC_D1CFGR_D1PPRE_DIV4_Pos (4U) |
#define | RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) |
#define | RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk |
#define | RCC_D1CFGR_D1PPRE_DIV8_Pos (5U) |
#define | RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) |
#define | RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk |
#define | RCC_D1CFGR_D1PPRE_DIV16_Pos (4U) |
#define | RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) |
#define | RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk |
#define | RCC_D1CFGR_D1CPRE_Pos (8U) |
#define | RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) |
#define | RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk |
#define | RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) |
#define | RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) |
#define | RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) |
#define | RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV1 (0U) |
#define | RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) |
#define | RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV4_Pos (8U) |
#define | RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV8_Pos (9U) |
#define | RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV16_Pos (8U) |
#define | RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV64_Pos (10U) |
#define | RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV128_Pos (8U) |
#define | RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV256_Pos (9U) |
#define | RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk |
#define | RCC_D1CFGR_D1CPRE_DIV512_Pos (8U) |
#define | RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) |
#define | RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk |
#define | RCC_D2CFGR_D2PPRE1_Pos (4U) |
#define | RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) |
#define | RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk |
#define | RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) |
#define | RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) |
#define | RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) |
#define | RCC_D2CFGR_D2PPRE1_DIV1 (0U) |
#define | RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) |
#define | RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) |
#define | RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk |
#define | RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U) |
#define | RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) |
#define | RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk |
#define | RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U) |
#define | RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) |
#define | RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk |
#define | RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U) |
#define | RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) |
#define | RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk |
#define | RCC_D2CFGR_D2PPRE2_Pos (8U) |
#define | RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) |
#define | RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk |
#define | RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) |
#define | RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) |
#define | RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) |
#define | RCC_D2CFGR_D2PPRE2_DIV1 (0U) |
#define | RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) |
#define | RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) |
#define | RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk |
#define | RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U) |
#define | RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) |
#define | RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk |
#define | RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U) |
#define | RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) |
#define | RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk |
#define | RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U) |
#define | RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) |
#define | RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk |
#define | RCC_D3CFGR_D3PPRE_Pos (4U) |
#define | RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) |
#define | RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk |
#define | RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) |
#define | RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) |
#define | RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) |
#define | RCC_D3CFGR_D3PPRE_DIV1 (0U) |
#define | RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) |
#define | RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) |
#define | RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk |
#define | RCC_D3CFGR_D3PPRE_DIV4_Pos (4U) |
#define | RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) |
#define | RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk |
#define | RCC_D3CFGR_D3PPRE_DIV8_Pos (5U) |
#define | RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) |
#define | RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk |
#define | RCC_D3CFGR_D3PPRE_DIV16_Pos (4U) |
#define | RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) |
#define | RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk |
#define | RCC_PLLCKSELR_PLLSRC_Pos (0U) |
#define | RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) |
#define | RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk |
#define | RCC_PLLCKSELR_PLLSRC_HSI (0U) |
#define | RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) |
#define | RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) |
#define | RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk |
#define | RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U) |
#define | RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) |
#define | RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk |
#define | RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U) |
#define | RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) |
#define | RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk |
#define | RCC_PLLCKSELR_DIVM1_Pos (4U) |
#define | RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk |
#define | RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) |
#define | RCC_PLLCKSELR_DIVM2_Pos (12U) |
#define | RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk |
#define | RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) |
#define | RCC_PLLCKSELR_DIVM3_Pos (20U) |
#define | RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk |
#define | RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) |
#define | RCC_PLLCFGR_PLL1FRACEN_Pos (0U) |
#define | RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) |
#define | RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk |
#define | RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) |
#define | RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) |
#define | RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk |
#define | RCC_PLLCFGR_PLL1RGE_Pos (2U) |
#define | RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) |
#define | RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk |
#define | RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) |
#define | RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) |
#define | RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) |
#define | RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) |
#define | RCC_PLLCFGR_PLL2FRACEN_Pos (4U) |
#define | RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) |
#define | RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk |
#define | RCC_PLLCFGR_PLL2VCOSEL_Pos (5U) |
#define | RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) |
#define | RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk |
#define | RCC_PLLCFGR_PLL2RGE_Pos (6U) |
#define | RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) |
#define | RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk |
#define | RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) |
#define | RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) |
#define | RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) |
#define | RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) |
#define | RCC_PLLCFGR_PLL3FRACEN_Pos (8U) |
#define | RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) |
#define | RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk |
#define | RCC_PLLCFGR_PLL3VCOSEL_Pos (9U) |
#define | RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) |
#define | RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk |
#define | RCC_PLLCFGR_PLL3RGE_Pos (10U) |
#define | RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) |
#define | RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk |
#define | RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) |
#define | RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) |
#define | RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) |
#define | RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) |
#define | RCC_PLLCFGR_DIVP1EN_Pos (16U) |
#define | RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) |
#define | RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk |
#define | RCC_PLLCFGR_DIVQ1EN_Pos (17U) |
#define | RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) |
#define | RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk |
#define | RCC_PLLCFGR_DIVR1EN_Pos (18U) |
#define | RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) |
#define | RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk |
#define | RCC_PLLCFGR_DIVP2EN_Pos (19U) |
#define | RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) |
#define | RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk |
#define | RCC_PLLCFGR_DIVQ2EN_Pos (20U) |
#define | RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) |
#define | RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk |
#define | RCC_PLLCFGR_DIVR2EN_Pos (21U) |
#define | RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) |
#define | RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk |
#define | RCC_PLLCFGR_DIVP3EN_Pos (22U) |
#define | RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) |
#define | RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk |
#define | RCC_PLLCFGR_DIVQ3EN_Pos (23U) |
#define | RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) |
#define | RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk |
#define | RCC_PLLCFGR_DIVR3EN_Pos (24U) |
#define | RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) |
#define | RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk |
#define | RCC_PLL1DIVR_N1_Pos (0U) |
#define | RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) |
#define | RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk |
#define | RCC_PLL1DIVR_P1_Pos (9U) |
#define | RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) |
#define | RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk |
#define | RCC_PLL1DIVR_Q1_Pos (16U) |
#define | RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) |
#define | RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk |
#define | RCC_PLL1DIVR_R1_Pos (24U) |
#define | RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) |
#define | RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk |
#define | RCC_PLL1FRACR_FRACN1_Pos (3U) |
#define | RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) |
#define | RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk |
#define | RCC_PLL2DIVR_N2_Pos (0U) |
#define | RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) |
#define | RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk |
#define | RCC_PLL2DIVR_P2_Pos (9U) |
#define | RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) |
#define | RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk |
#define | RCC_PLL2DIVR_Q2_Pos (16U) |
#define | RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) |
#define | RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk |
#define | RCC_PLL2DIVR_R2_Pos (24U) |
#define | RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) |
#define | RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk |
#define | RCC_PLL2FRACR_FRACN2_Pos (3U) |
#define | RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) |
#define | RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk |
#define | RCC_PLL3DIVR_N3_Pos (0U) |
#define | RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) |
#define | RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk |
#define | RCC_PLL3DIVR_P3_Pos (9U) |
#define | RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) |
#define | RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk |
#define | RCC_PLL3DIVR_Q3_Pos (16U) |
#define | RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) |
#define | RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk |
#define | RCC_PLL3DIVR_R3_Pos (24U) |
#define | RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) |
#define | RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk |
#define | RCC_PLL3FRACR_FRACN3_Pos (3U) |
#define | RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) |
#define | RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk |
#define | RCC_D1CCIPR_FMCSEL_Pos (0U) |
#define | RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) |
#define | RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk |
#define | RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) |
#define | RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) |
#define | RCC_D1CCIPR_QSPISEL_Pos (4U) |
#define | RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) |
#define | RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk |
#define | RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) |
#define | RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) |
#define | RCC_D1CCIPR_SDMMCSEL_Pos (16U) |
#define | RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) |
#define | RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk |
#define | RCC_D1CCIPR_CKPERSEL_Pos (28U) |
#define | RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) |
#define | RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk |
#define | RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) |
#define | RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) |
#define | RCC_D2CCIP1R_SAI1SEL_Pos (0U) |
#define | RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) |
#define | RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk |
#define | RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) |
#define | RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) |
#define | RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) |
#define | RCC_D2CCIP1R_SAI23SEL_Pos (6U) |
#define | RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) |
#define | RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk |
#define | RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) |
#define | RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) |
#define | RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) |
#define | RCC_D2CCIP1R_SPI123SEL_Pos (12U) |
#define | RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) |
#define | RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk |
#define | RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) |
#define | RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) |
#define | RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) |
#define | RCC_D2CCIP1R_SPI45SEL_Pos (16U) |
#define | RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) |
#define | RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk |
#define | RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) |
#define | RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) |
#define | RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) |
#define | RCC_D2CCIP1R_SPDIFSEL_Pos (20U) |
#define | RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) |
#define | RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk |
#define | RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) |
#define | RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) |
#define | RCC_D2CCIP1R_DFSDM1SEL_Pos (24U) |
#define | RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) |
#define | RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk |
#define | RCC_D2CCIP1R_FDCANSEL_Pos (28U) |
#define | RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) |
#define | RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk |
#define | RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) |
#define | RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) |
#define | RCC_D2CCIP1R_SWPSEL_Pos (31U) |
#define | RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) |
#define | RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk |
#define | RCC_D2CCIP2R_USART16SEL_Pos (3U) |
#define | RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) |
#define | RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk |
#define | RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) |
#define | RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) |
#define | RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) |
#define | RCC_D2CCIP2R_USART28SEL_Pos (0U) |
#define | RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) |
#define | RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk |
#define | RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) |
#define | RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) |
#define | RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) |
#define | RCC_D2CCIP2R_RNGSEL_Pos (8U) |
#define | RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) |
#define | RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk |
#define | RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) |
#define | RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) |
#define | RCC_D2CCIP2R_I2C123SEL_Pos (12U) |
#define | RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) |
#define | RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk |
#define | RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) |
#define | RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) |
#define | RCC_D2CCIP2R_USBSEL_Pos (20U) |
#define | RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) |
#define | RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk |
#define | RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) |
#define | RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) |
#define | RCC_D2CCIP2R_CECSEL_Pos (22U) |
#define | RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) |
#define | RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk |
#define | RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) |
#define | RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) |
#define | RCC_D2CCIP2R_LPTIM1SEL_Pos (28U) |
#define | RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) |
#define | RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk |
#define | RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) |
#define | RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) |
#define | RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) |
#define | RCC_D3CCIPR_LPUART1SEL_Pos (0U) |
#define | RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) |
#define | RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk |
#define | RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) |
#define | RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) |
#define | RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) |
#define | RCC_D3CCIPR_I2C4SEL_Pos (8U) |
#define | RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) |
#define | RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk |
#define | RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) |
#define | RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM2SEL_Pos (10U) |
#define | RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk |
#define | RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM345SEL_Pos (13U) |
#define | RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk |
#define | RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) |
#define | RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) |
#define | RCC_D3CCIPR_SAI4ASEL_Pos (21U) |
#define | RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) |
#define | RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk |
#define | RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) |
#define | RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) |
#define | RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) |
#define | RCC_D3CCIPR_SAI4BSEL_Pos (24U) |
#define | RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) |
#define | RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk |
#define | RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) |
#define | RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) |
#define | RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) |
#define | RCC_D3CCIPR_ADCSEL_Pos (16U) |
#define | RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) |
#define | RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk |
#define | RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) |
#define | RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) |
#define | RCC_D3CCIPR_SPI6SEL_Pos (28U) |
#define | RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) |
#define | RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk |
#define | RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) |
#define | RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) |
#define | RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) |
#define | RCC_CIER_LSIRDYIE_Pos (0U) |
#define | RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) |
#define | RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk |
#define | RCC_CIER_LSERDYIE_Pos (1U) |
#define | RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) |
#define | RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk |
#define | RCC_CIER_HSIRDYIE_Pos (2U) |
#define | RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) |
#define | RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk |
#define | RCC_CIER_HSERDYIE_Pos (3U) |
#define | RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) |
#define | RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk |
#define | RCC_CIER_CSIRDYIE_Pos (4U) |
#define | RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) |
#define | RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk |
#define | RCC_CIER_HSI48RDYIE_Pos (5U) |
#define | RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) |
#define | RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk |
#define | RCC_CIER_PLL1RDYIE_Pos (6U) |
#define | RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) |
#define | RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk |
#define | RCC_CIER_PLL2RDYIE_Pos (7U) |
#define | RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) |
#define | RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk |
#define | RCC_CIER_PLL3RDYIE_Pos (8U) |
#define | RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) |
#define | RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk |
#define | RCC_CIER_LSECSSIE_Pos (9U) |
#define | RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) |
#define | RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk |
#define | RCC_CIFR_LSIRDYF_Pos (0U) |
#define | RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) |
#define | RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk |
#define | RCC_CIFR_LSERDYF_Pos (1U) |
#define | RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) |
#define | RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk |
#define | RCC_CIFR_HSIRDYF_Pos (2U) |
#define | RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) |
#define | RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk |
#define | RCC_CIFR_HSERDYF_Pos (3U) |
#define | RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) |
#define | RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk |
#define | RCC_CIFR_CSIRDYF_Pos (4U) |
#define | RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) |
#define | RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk |
#define | RCC_CIFR_HSI48RDYF_Pos (5U) |
#define | RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) |
#define | RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk |
#define | RCC_CIFR_PLLRDYF_Pos (6U) |
#define | RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) |
#define | RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk |
#define | RCC_CIFR_PLL2RDYF_Pos (7U) |
#define | RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) |
#define | RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk |
#define | RCC_CIFR_PLL3RDYF_Pos (8U) |
#define | RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) |
#define | RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk |
#define | RCC_CIFR_LSECSSF_Pos (9U) |
#define | RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) |
#define | RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk |
#define | RCC_CIFR_HSECSSF_Pos (10U) |
#define | RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) |
#define | RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk |
#define | RCC_CICR_LSIRDYC_Pos (0U) |
#define | RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) |
#define | RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk |
#define | RCC_CICR_LSERDYC_Pos (1U) |
#define | RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) |
#define | RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk |
#define | RCC_CICR_HSIRDYC_Pos (2U) |
#define | RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) |
#define | RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk |
#define | RCC_CICR_HSERDYC_Pos (3U) |
#define | RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) |
#define | RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk |
#define | RCC_CICR_CSIRDYC_Pos (4U) |
#define | RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) |
#define | RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk |
#define | RCC_CICR_HSI48RDYC_Pos (5U) |
#define | RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) |
#define | RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk |
#define | RCC_CICR_PLLRDYC_Pos (6U) |
#define | RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) |
#define | RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk |
#define | RCC_CICR_PLL2RDYC_Pos (7U) |
#define | RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) |
#define | RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk |
#define | RCC_CICR_PLL3RDYC_Pos (8U) |
#define | RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) |
#define | RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk |
#define | RCC_CICR_LSECSSC_Pos (9U) |
#define | RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) |
#define | RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk |
#define | RCC_CICR_HSECSSC_Pos (10U) |
#define | RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) |
#define | RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk |
#define | RCC_BDCR_LSEON_Pos (0U) |
#define | RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) |
#define | RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk |
#define | RCC_BDCR_LSERDY_Pos (1U) |
#define | RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) |
#define | RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk |
#define | RCC_BDCR_LSEBYP_Pos (2U) |
#define | RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) |
#define | RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk |
#define | RCC_BDCR_LSEDRV_Pos (3U) |
#define | RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) |
#define | RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk |
#define | RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) |
#define | RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) |
#define | RCC_BDCR_LSECSSON_Pos (5U) |
#define | RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) |
#define | RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk |
#define | RCC_BDCR_LSECSSD_Pos (6U) |
#define | RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) |
#define | RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk |
#define | RCC_BDCR_RTCSEL_Pos (8U) |
#define | RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) |
#define | RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk |
#define | RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) |
#define | RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) |
#define | RCC_BDCR_RTCEN_Pos (15U) |
#define | RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) |
#define | RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk |
#define | RCC_BDCR_BDRST_Pos (16U) |
#define | RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) |
#define | RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk |
#define | RCC_CSR_LSION_Pos (0U) |
#define | RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) |
#define | RCC_CSR_LSION RCC_CSR_LSION_Msk |
#define | RCC_CSR_LSIRDY_Pos (1U) |
#define | RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) |
#define | RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk |
#define | RCC_AHB3ENR_MDMAEN_Pos (0U) |
#define | RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) |
#define | RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk |
#define | RCC_AHB3ENR_DMA2DEN_Pos (4U) |
#define | RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) |
#define | RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk |
#define | RCC_AHB3ENR_FMCEN_Pos (12U) |
#define | RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) |
#define | RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk |
#define | RCC_AHB3ENR_QSPIEN_Pos (14U) |
#define | RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) |
#define | RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk |
#define | RCC_AHB3ENR_SDMMC1EN_Pos (16U) |
#define | RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) |
#define | RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk |
#define | RCC_AHB1ENR_DMA1EN_Pos (0U) |
#define | RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) |
#define | RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk |
#define | RCC_AHB1ENR_DMA2EN_Pos (1U) |
#define | RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) |
#define | RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk |
#define | RCC_AHB1ENR_ADC12EN_Pos (5U) |
#define | RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) |
#define | RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk |
#define | RCC_AHB1ENR_ETH1MACEN_Pos (15U) |
#define | RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) |
#define | RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk |
#define | RCC_AHB1ENR_ETH1TXEN_Pos (16U) |
#define | RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) |
#define | RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk |
#define | RCC_AHB1ENR_ETH1RXEN_Pos (17U) |
#define | RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) |
#define | RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk |
#define | RCC_AHB1ENR_USB1OTGHSEN_Pos (25U) |
#define | RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) |
#define | RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk |
#define | RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U) |
#define | RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) |
#define | RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk |
#define | RCC_AHB1ENR_USB2OTGFSEN_Pos (27U) |
#define | RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) |
#define | RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk |
#define | RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U) |
#define | RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) |
#define | RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk |
#define | RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos |
#define | RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk |
#define | RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN |
#define | RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos |
#define | RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk |
#define | RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN |
#define | RCC_AHB2ENR_DCMIEN_Pos (0U) |
#define | RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) |
#define | RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk |
#define | RCC_AHB2ENR_RNGEN_Pos (6U) |
#define | RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) |
#define | RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk |
#define | RCC_AHB2ENR_SDMMC2EN_Pos (9U) |
#define | RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) |
#define | RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk |
#define | RCC_AHB2ENR_SRAM1EN_Pos (29U) |
#define | RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) |
#define | RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk |
#define | RCC_AHB2ENR_SRAM2EN_Pos (30U) |
#define | RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) |
#define | RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk |
#define | RCC_AHB2ENR_SRAM3EN_Pos (31U) |
#define | RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) |
#define | RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk |
#define | RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos |
#define | RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk |
#define | RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN |
#define | RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos |
#define | RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk |
#define | RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN |
#define | RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos |
#define | RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk |
#define | RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN |
#define | RCC_AHB4ENR_GPIOAEN_Pos (0U) |
#define | RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) |
#define | RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk |
#define | RCC_AHB4ENR_GPIOBEN_Pos (1U) |
#define | RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) |
#define | RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk |
#define | RCC_AHB4ENR_GPIOCEN_Pos (2U) |
#define | RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) |
#define | RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk |
#define | RCC_AHB4ENR_GPIODEN_Pos (3U) |
#define | RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) |
#define | RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk |
#define | RCC_AHB4ENR_GPIOEEN_Pos (4U) |
#define | RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) |
#define | RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk |
#define | RCC_AHB4ENR_GPIOFEN_Pos (5U) |
#define | RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) |
#define | RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk |
#define | RCC_AHB4ENR_GPIOGEN_Pos (6U) |
#define | RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) |
#define | RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk |
#define | RCC_AHB4ENR_GPIOHEN_Pos (7U) |
#define | RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) |
#define | RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk |
#define | RCC_AHB4ENR_GPIOIEN_Pos (8U) |
#define | RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) |
#define | RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk |
#define | RCC_AHB4ENR_GPIOJEN_Pos (9U) |
#define | RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) |
#define | RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk |
#define | RCC_AHB4ENR_GPIOKEN_Pos (10U) |
#define | RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) |
#define | RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk |
#define | RCC_AHB4ENR_CRCEN_Pos (19U) |
#define | RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) |
#define | RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk |
#define | RCC_AHB4ENR_BDMAEN_Pos (21U) |
#define | RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) |
#define | RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk |
#define | RCC_AHB4ENR_ADC3EN_Pos (24U) |
#define | RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) |
#define | RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk |
#define | RCC_AHB4ENR_HSEMEN_Pos (25U) |
#define | RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) |
#define | RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk |
#define | RCC_AHB4ENR_BKPRAMEN_Pos (28U) |
#define | RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) |
#define | RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk |
#define | RCC_APB3ENR_WWDG1EN_Pos (6U) |
#define | RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) |
#define | RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk |
#define | RCC_APB1LENR_TIM2EN_Pos (0U) |
#define | RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) |
#define | RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk |
#define | RCC_APB1LENR_TIM3EN_Pos (1U) |
#define | RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) |
#define | RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk |
#define | RCC_APB1LENR_TIM4EN_Pos (2U) |
#define | RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) |
#define | RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk |
#define | RCC_APB1LENR_TIM5EN_Pos (3U) |
#define | RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) |
#define | RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk |
#define | RCC_APB1LENR_TIM6EN_Pos (4U) |
#define | RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) |
#define | RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk |
#define | RCC_APB1LENR_TIM7EN_Pos (5U) |
#define | RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) |
#define | RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk |
#define | RCC_APB1LENR_TIM12EN_Pos (6U) |
#define | RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) |
#define | RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk |
#define | RCC_APB1LENR_TIM13EN_Pos (7U) |
#define | RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) |
#define | RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk |
#define | RCC_APB1LENR_TIM14EN_Pos (8U) |
#define | RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) |
#define | RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk |
#define | RCC_APB1LENR_LPTIM1EN_Pos (9U) |
#define | RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) |
#define | RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk |
#define | RCC_APB1LENR_SPI2EN_Pos (14U) |
#define | RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) |
#define | RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk |
#define | RCC_APB1LENR_SPI3EN_Pos (15U) |
#define | RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) |
#define | RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk |
#define | RCC_APB1LENR_SPDIFRXEN_Pos (16U) |
#define | RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) |
#define | RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk |
#define | RCC_APB1LENR_USART2EN_Pos (17U) |
#define | RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) |
#define | RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk |
#define | RCC_APB1LENR_USART3EN_Pos (18U) |
#define | RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) |
#define | RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk |
#define | RCC_APB1LENR_UART4EN_Pos (19U) |
#define | RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) |
#define | RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk |
#define | RCC_APB1LENR_UART5EN_Pos (20U) |
#define | RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) |
#define | RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk |
#define | RCC_APB1LENR_I2C1EN_Pos (21U) |
#define | RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) |
#define | RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk |
#define | RCC_APB1LENR_I2C2EN_Pos (22U) |
#define | RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) |
#define | RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk |
#define | RCC_APB1LENR_I2C3EN_Pos (23U) |
#define | RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) |
#define | RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk |
#define | RCC_APB1LENR_CECEN_Pos (27U) |
#define | RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) |
#define | RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk |
#define | RCC_APB1LENR_DAC12EN_Pos (29U) |
#define | RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) |
#define | RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk |
#define | RCC_APB1LENR_UART7EN_Pos (30U) |
#define | RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) |
#define | RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk |
#define | RCC_APB1LENR_UART8EN_Pos (31U) |
#define | RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) |
#define | RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk |
#define | RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos |
#define | RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk |
#define | RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN |
#define | RCC_APB1HENR_CRSEN_Pos (1U) |
#define | RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) |
#define | RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk |
#define | RCC_APB1HENR_SWPMIEN_Pos (2U) |
#define | RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) |
#define | RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk |
#define | RCC_APB1HENR_OPAMPEN_Pos (4U) |
#define | RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) |
#define | RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk |
#define | RCC_APB1HENR_MDIOSEN_Pos (5U) |
#define | RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) |
#define | RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk |
#define | RCC_APB1HENR_FDCANEN_Pos (8U) |
#define | RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) |
#define | RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk |
#define | RCC_APB2ENR_TIM1EN_Pos (0U) |
#define | RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) |
#define | RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk |
#define | RCC_APB2ENR_TIM8EN_Pos (1U) |
#define | RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) |
#define | RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk |
#define | RCC_APB2ENR_USART1EN_Pos (4U) |
#define | RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) |
#define | RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk |
#define | RCC_APB2ENR_USART6EN_Pos (5U) |
#define | RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) |
#define | RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk |
#define | RCC_APB2ENR_SPI1EN_Pos (12U) |
#define | RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) |
#define | RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk |
#define | RCC_APB2ENR_SPI4EN_Pos (13U) |
#define | RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) |
#define | RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk |
#define | RCC_APB2ENR_TIM15EN_Pos (16U) |
#define | RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) |
#define | RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk |
#define | RCC_APB2ENR_TIM16EN_Pos (17U) |
#define | RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) |
#define | RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk |
#define | RCC_APB2ENR_TIM17EN_Pos (18U) |
#define | RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) |
#define | RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk |
#define | RCC_APB2ENR_SPI5EN_Pos (20U) |
#define | RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) |
#define | RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk |
#define | RCC_APB2ENR_SAI1EN_Pos (22U) |
#define | RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) |
#define | RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk |
#define | RCC_APB2ENR_SAI2EN_Pos (23U) |
#define | RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) |
#define | RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk |
#define | RCC_APB2ENR_SAI3EN_Pos (24U) |
#define | RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) |
#define | RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk |
#define | RCC_APB2ENR_DFSDM1EN_Pos (28U) |
#define | RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) |
#define | RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk |
#define | RCC_APB2ENR_HRTIMEN_Pos (29U) |
#define | RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) |
#define | RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk |
#define | RCC_APB4ENR_SYSCFGEN_Pos (1U) |
#define | RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) |
#define | RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk |
#define | RCC_APB4ENR_LPUART1EN_Pos (3U) |
#define | RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) |
#define | RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk |
#define | RCC_APB4ENR_SPI6EN_Pos (5U) |
#define | RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) |
#define | RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk |
#define | RCC_APB4ENR_I2C4EN_Pos (7U) |
#define | RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) |
#define | RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk |
#define | RCC_APB4ENR_LPTIM2EN_Pos (9U) |
#define | RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) |
#define | RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk |
#define | RCC_APB4ENR_LPTIM3EN_Pos (10U) |
#define | RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) |
#define | RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk |
#define | RCC_APB4ENR_LPTIM4EN_Pos (11U) |
#define | RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) |
#define | RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk |
#define | RCC_APB4ENR_LPTIM5EN_Pos (12U) |
#define | RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) |
#define | RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk |
#define | RCC_APB4ENR_COMP12EN_Pos (14U) |
#define | RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) |
#define | RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk |
#define | RCC_APB4ENR_VREFEN_Pos (15U) |
#define | RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) |
#define | RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk |
#define | RCC_APB4ENR_RTCAPBEN_Pos (16U) |
#define | RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) |
#define | RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk |
#define | RCC_APB4ENR_SAI4EN_Pos (21U) |
#define | RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) |
#define | RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk |
#define | RCC_AHB3RSTR_MDMARST_Pos (0U) |
#define | RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) |
#define | RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk |
#define | RCC_AHB3RSTR_DMA2DRST_Pos (4U) |
#define | RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) |
#define | RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk |
#define | RCC_AHB3RSTR_FMCRST_Pos (12U) |
#define | RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) |
#define | RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk |
#define | RCC_AHB3RSTR_QSPIRST_Pos (14U) |
#define | RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) |
#define | RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk |
#define | RCC_AHB3RSTR_SDMMC1RST_Pos (16U) |
#define | RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) |
#define | RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk |
#define | RCC_AHB1RSTR_DMA1RST_Pos (0U) |
#define | RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) |
#define | RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk |
#define | RCC_AHB1RSTR_DMA2RST_Pos (1U) |
#define | RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) |
#define | RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk |
#define | RCC_AHB1RSTR_ADC12RST_Pos (5U) |
#define | RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) |
#define | RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk |
#define | RCC_AHB1RSTR_ETH1MACRST_Pos (15U) |
#define | RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) |
#define | RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk |
#define | RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U) |
#define | RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) |
#define | RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk |
#define | RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U) |
#define | RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) |
#define | RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk |
#define | RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos |
#define | RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk |
#define | RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST |
#define | RCC_AHB2RSTR_DCMIRST_Pos (0U) |
#define | RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) |
#define | RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk |
#define | RCC_AHB2RSTR_RNGRST_Pos (6U) |
#define | RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) |
#define | RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk |
#define | RCC_AHB2RSTR_SDMMC2RST_Pos (9U) |
#define | RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) |
#define | RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk |
#define | RCC_AHB4RSTR_GPIOARST_Pos (0U) |
#define | RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) |
#define | RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk |
#define | RCC_AHB4RSTR_GPIOBRST_Pos (1U) |
#define | RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) |
#define | RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk |
#define | RCC_AHB4RSTR_GPIOCRST_Pos (2U) |
#define | RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) |
#define | RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk |
#define | RCC_AHB4RSTR_GPIODRST_Pos (3U) |
#define | RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) |
#define | RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk |
#define | RCC_AHB4RSTR_GPIOERST_Pos (4U) |
#define | RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) |
#define | RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk |
#define | RCC_AHB4RSTR_GPIOFRST_Pos (5U) |
#define | RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) |
#define | RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk |
#define | RCC_AHB4RSTR_GPIOGRST_Pos (6U) |
#define | RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) |
#define | RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk |
#define | RCC_AHB4RSTR_GPIOHRST_Pos (7U) |
#define | RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) |
#define | RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk |
#define | RCC_AHB4RSTR_GPIOIRST_Pos (8U) |
#define | RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) |
#define | RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk |
#define | RCC_AHB4RSTR_GPIOJRST_Pos (9U) |
#define | RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) |
#define | RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk |
#define | RCC_AHB4RSTR_GPIOKRST_Pos (10U) |
#define | RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) |
#define | RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk |
#define | RCC_AHB4RSTR_CRCRST_Pos (19U) |
#define | RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) |
#define | RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk |
#define | RCC_AHB4RSTR_BDMARST_Pos (21U) |
#define | RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) |
#define | RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk |
#define | RCC_AHB4RSTR_ADC3RST_Pos (24U) |
#define | RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) |
#define | RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk |
#define | RCC_AHB4RSTR_HSEMRST_Pos (25U) |
#define | RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) |
#define | RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk |
#define | RCC_APB1LRSTR_TIM2RST_Pos (0U) |
#define | RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) |
#define | RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk |
#define | RCC_APB1LRSTR_TIM3RST_Pos (1U) |
#define | RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) |
#define | RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk |
#define | RCC_APB1LRSTR_TIM4RST_Pos (2U) |
#define | RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) |
#define | RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk |
#define | RCC_APB1LRSTR_TIM5RST_Pos (3U) |
#define | RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) |
#define | RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk |
#define | RCC_APB1LRSTR_TIM6RST_Pos (4U) |
#define | RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) |
#define | RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk |
#define | RCC_APB1LRSTR_TIM7RST_Pos (5U) |
#define | RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) |
#define | RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk |
#define | RCC_APB1LRSTR_TIM12RST_Pos (6U) |
#define | RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) |
#define | RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk |
#define | RCC_APB1LRSTR_TIM13RST_Pos (7U) |
#define | RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) |
#define | RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk |
#define | RCC_APB1LRSTR_TIM14RST_Pos (8U) |
#define | RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) |
#define | RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk |
#define | RCC_APB1LRSTR_LPTIM1RST_Pos (9U) |
#define | RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) |
#define | RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk |
#define | RCC_APB1LRSTR_SPI2RST_Pos (14U) |
#define | RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) |
#define | RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk |
#define | RCC_APB1LRSTR_SPI3RST_Pos (15U) |
#define | RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) |
#define | RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk |
#define | RCC_APB1LRSTR_SPDIFRXRST_Pos (16U) |
#define | RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) |
#define | RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk |
#define | RCC_APB1LRSTR_USART2RST_Pos (17U) |
#define | RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) |
#define | RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk |
#define | RCC_APB1LRSTR_USART3RST_Pos (18U) |
#define | RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) |
#define | RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk |
#define | RCC_APB1LRSTR_UART4RST_Pos (19U) |
#define | RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) |
#define | RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk |
#define | RCC_APB1LRSTR_UART5RST_Pos (20U) |
#define | RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) |
#define | RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk |
#define | RCC_APB1LRSTR_I2C1RST_Pos (21U) |
#define | RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) |
#define | RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk |
#define | RCC_APB1LRSTR_I2C2RST_Pos (22U) |
#define | RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) |
#define | RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk |
#define | RCC_APB1LRSTR_I2C3RST_Pos (23U) |
#define | RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) |
#define | RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk |
#define | RCC_APB1LRSTR_CECRST_Pos (27U) |
#define | RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) |
#define | RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk |
#define | RCC_APB1LRSTR_DAC12RST_Pos (29U) |
#define | RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) |
#define | RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk |
#define | RCC_APB1LRSTR_UART7RST_Pos (30U) |
#define | RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) |
#define | RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk |
#define | RCC_APB1LRSTR_UART8RST_Pos (31U) |
#define | RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) |
#define | RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk |
#define | RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos |
#define | RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk |
#define | RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST |
#define | RCC_APB1HRSTR_CRSRST_Pos (1U) |
#define | RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) |
#define | RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk |
#define | RCC_APB1HRSTR_SWPMIRST_Pos (2U) |
#define | RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) |
#define | RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk |
#define | RCC_APB1HRSTR_OPAMPRST_Pos (4U) |
#define | RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) |
#define | RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk |
#define | RCC_APB1HRSTR_MDIOSRST_Pos (5U) |
#define | RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) |
#define | RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk |
#define | RCC_APB1HRSTR_FDCANRST_Pos (8U) |
#define | RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) |
#define | RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk |
#define | RCC_APB2RSTR_TIM1RST_Pos (0U) |
#define | RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) |
#define | RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk |
#define | RCC_APB2RSTR_TIM8RST_Pos (1U) |
#define | RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) |
#define | RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk |
#define | RCC_APB2RSTR_USART1RST_Pos (4U) |
#define | RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) |
#define | RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk |
#define | RCC_APB2RSTR_USART6RST_Pos (5U) |
#define | RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) |
#define | RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk |
#define | RCC_APB2RSTR_SPI1RST_Pos (12U) |
#define | RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) |
#define | RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk |
#define | RCC_APB2RSTR_SPI4RST_Pos (13U) |
#define | RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) |
#define | RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk |
#define | RCC_APB2RSTR_TIM15RST_Pos (16U) |
#define | RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) |
#define | RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk |
#define | RCC_APB2RSTR_TIM16RST_Pos (17U) |
#define | RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) |
#define | RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk |
#define | RCC_APB2RSTR_TIM17RST_Pos (18U) |
#define | RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) |
#define | RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk |
#define | RCC_APB2RSTR_SPI5RST_Pos (20U) |
#define | RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) |
#define | RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk |
#define | RCC_APB2RSTR_SAI1RST_Pos (22U) |
#define | RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) |
#define | RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk |
#define | RCC_APB2RSTR_SAI2RST_Pos (23U) |
#define | RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) |
#define | RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk |
#define | RCC_APB2RSTR_SAI3RST_Pos (24U) |
#define | RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) |
#define | RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk |
#define | RCC_APB2RSTR_DFSDM1RST_Pos (28U) |
#define | RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) |
#define | RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk |
#define | RCC_APB2RSTR_HRTIMRST_Pos (29U) |
#define | RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) |
#define | RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk |
#define | RCC_APB4RSTR_SYSCFGRST_Pos (1U) |
#define | RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) |
#define | RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk |
#define | RCC_APB4RSTR_LPUART1RST_Pos (3U) |
#define | RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) |
#define | RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk |
#define | RCC_APB4RSTR_SPI6RST_Pos (5U) |
#define | RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) |
#define | RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk |
#define | RCC_APB4RSTR_I2C4RST_Pos (7U) |
#define | RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) |
#define | RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk |
#define | RCC_APB4RSTR_LPTIM2RST_Pos (9U) |
#define | RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) |
#define | RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk |
#define | RCC_APB4RSTR_LPTIM3RST_Pos (10U) |
#define | RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) |
#define | RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk |
#define | RCC_APB4RSTR_LPTIM4RST_Pos (11U) |
#define | RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) |
#define | RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk |
#define | RCC_APB4RSTR_LPTIM5RST_Pos (12U) |
#define | RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) |
#define | RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk |
#define | RCC_APB4RSTR_COMP12RST_Pos (14U) |
#define | RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) |
#define | RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk |
#define | RCC_APB4RSTR_VREFRST_Pos (15U) |
#define | RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) |
#define | RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk |
#define | RCC_APB4RSTR_SAI4RST_Pos (21U) |
#define | RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) |
#define | RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk |
#define | RCC_GCR_WW1RSC_Pos (0U) |
#define | RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) |
#define | RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk |
#define | RCC_D3AMR_BDMAAMEN_Pos (0U) |
#define | RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) |
#define | RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk |
#define | RCC_D3AMR_LPUART1AMEN_Pos (3U) |
#define | RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) |
#define | RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk |
#define | RCC_D3AMR_SPI6AMEN_Pos (5U) |
#define | RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) |
#define | RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk |
#define | RCC_D3AMR_I2C4AMEN_Pos (7U) |
#define | RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) |
#define | RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk |
#define | RCC_D3AMR_LPTIM2AMEN_Pos (9U) |
#define | RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) |
#define | RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk |
#define | RCC_D3AMR_LPTIM3AMEN_Pos (10U) |
#define | RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) |
#define | RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk |
#define | RCC_D3AMR_LPTIM4AMEN_Pos (11U) |
#define | RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) |
#define | RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk |
#define | RCC_D3AMR_LPTIM5AMEN_Pos (12U) |
#define | RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) |
#define | RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk |
#define | RCC_D3AMR_COMP12AMEN_Pos (14U) |
#define | RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) |
#define | RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk |
#define | RCC_D3AMR_VREFAMEN_Pos (15U) |
#define | RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) |
#define | RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk |
#define | RCC_D3AMR_RTCAMEN_Pos (16U) |
#define | RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) |
#define | RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk |
#define | RCC_D3AMR_CRCAMEN_Pos (19U) |
#define | RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) |
#define | RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk |
#define | RCC_D3AMR_SAI4AMEN_Pos (21U) |
#define | RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) |
#define | RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk |
#define | RCC_D3AMR_ADC3AMEN_Pos (24U) |
#define | RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) |
#define | RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk |
#define | RCC_D3AMR_BKPRAMAMEN_Pos (28U) |
#define | RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) |
#define | RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk |
#define | RCC_D3AMR_SRAM4AMEN_Pos (29U) |
#define | RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) |
#define | RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk |
#define | RCC_AHB3LPENR_MDMALPEN_Pos (0U) |
#define | RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) |
#define | RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk |
#define | RCC_AHB3LPENR_DMA2DLPEN_Pos (4U) |
#define | RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) |
#define | RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk |
#define | RCC_AHB3LPENR_FLASHLPEN_Pos (8U) |
#define | RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) |
#define | RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk |
#define | RCC_AHB3LPENR_FMCLPEN_Pos (12U) |
#define | RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) |
#define | RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk |
#define | RCC_AHB3LPENR_QSPILPEN_Pos (14U) |
#define | RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) |
#define | RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk |
#define | RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U) |
#define | RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) |
#define | RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk |
#define | RCC_AHB3LPENR_DTCM1LPEN_Pos (28U) |
#define | RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) |
#define | RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk |
#define | RCC_AHB3LPENR_DTCM2LPEN_Pos (29U) |
#define | RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) |
#define | RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk |
#define | RCC_AHB3LPENR_ITCMLPEN_Pos (30U) |
#define | RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) |
#define | RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk |
#define | RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U) |
#define | RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) |
#define | RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk |
#define | RCC_AHB1LPENR_DMA1LPEN_Pos (0U) |
#define | RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) |
#define | RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk |
#define | RCC_AHB1LPENR_DMA2LPEN_Pos (1U) |
#define | RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) |
#define | RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk |
#define | RCC_AHB1LPENR_ADC12LPEN_Pos (5U) |
#define | RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) |
#define | RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk |
#define | RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) |
#define | RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) |
#define | RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk |
#define | RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) |
#define | RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) |
#define | RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk |
#define | RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) |
#define | RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) |
#define | RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk |
#define | RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U) |
#define | RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) |
#define | RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk |
#define | RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U) |
#define | RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) |
#define | RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk |
#define | RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U) |
#define | RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) |
#define | RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk |
#define | RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U) |
#define | RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) |
#define | RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk |
#define | RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos |
#define | RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk |
#define | RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN |
#define | RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos |
#define | RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk |
#define | RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN |
#define | RCC_AHB2LPENR_DCMILPEN_Pos (0U) |
#define | RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) |
#define | RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk |
#define | RCC_AHB2LPENR_RNGLPEN_Pos (6U) |
#define | RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) |
#define | RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk |
#define | RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) |
#define | RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) |
#define | RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk |
#define | RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) |
#define | RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) |
#define | RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk |
#define | RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) |
#define | RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) |
#define | RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk |
#define | RCC_AHB2LPENR_SRAM3LPEN_Pos (31U) |
#define | RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) |
#define | RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk |
#define | RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos |
#define | RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk |
#define | RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN |
#define | RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos |
#define | RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk |
#define | RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN |
#define | RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos |
#define | RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk |
#define | RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN |
#define | RCC_AHB4LPENR_GPIOALPEN_Pos (0U) |
#define | RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk |
#define | RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) |
#define | RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk |
#define | RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) |
#define | RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk |
#define | RCC_AHB4LPENR_GPIODLPEN_Pos (3U) |
#define | RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk |
#define | RCC_AHB4LPENR_GPIOELPEN_Pos (4U) |
#define | RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk |
#define | RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) |
#define | RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk |
#define | RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) |
#define | RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk |
#define | RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) |
#define | RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk |
#define | RCC_AHB4LPENR_GPIOILPEN_Pos (8U) |
#define | RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk |
#define | RCC_AHB4LPENR_GPIOJLPEN_Pos (9U) |
#define | RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk |
#define | RCC_AHB4LPENR_GPIOKLPEN_Pos (10U) |
#define | RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) |
#define | RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk |
#define | RCC_AHB4LPENR_CRCLPEN_Pos (19U) |
#define | RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) |
#define | RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk |
#define | RCC_AHB4LPENR_BDMALPEN_Pos (21U) |
#define | RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) |
#define | RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk |
#define | RCC_AHB4LPENR_ADC3LPEN_Pos (24U) |
#define | RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) |
#define | RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk |
#define | RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) |
#define | RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) |
#define | RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk |
#define | RCC_AHB4LPENR_SRAM4LPEN_Pos (29U) |
#define | RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) |
#define | RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk |
#define | RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos |
#define | RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk |
#define | RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN |
#define | RCC_APB3LPENR_WWDG1LPEN_Pos (6U) |
#define | RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) |
#define | RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk |
#define | RCC_APB1LLPENR_TIM2LPEN_Pos (0U) |
#define | RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk |
#define | RCC_APB1LLPENR_TIM3LPEN_Pos (1U) |
#define | RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk |
#define | RCC_APB1LLPENR_TIM4LPEN_Pos (2U) |
#define | RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk |
#define | RCC_APB1LLPENR_TIM5LPEN_Pos (3U) |
#define | RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk |
#define | RCC_APB1LLPENR_TIM6LPEN_Pos (4U) |
#define | RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk |
#define | RCC_APB1LLPENR_TIM7LPEN_Pos (5U) |
#define | RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk |
#define | RCC_APB1LLPENR_TIM12LPEN_Pos (6U) |
#define | RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk |
#define | RCC_APB1LLPENR_TIM13LPEN_Pos (7U) |
#define | RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk |
#define | RCC_APB1LLPENR_TIM14LPEN_Pos (8U) |
#define | RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) |
#define | RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk |
#define | RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U) |
#define | RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) |
#define | RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk |
#define | RCC_APB1LLPENR_SPI2LPEN_Pos (14U) |
#define | RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) |
#define | RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk |
#define | RCC_APB1LLPENR_SPI3LPEN_Pos (15U) |
#define | RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) |
#define | RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk |
#define | RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U) |
#define | RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) |
#define | RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk |
#define | RCC_APB1LLPENR_USART2LPEN_Pos (17U) |
#define | RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) |
#define | RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk |
#define | RCC_APB1LLPENR_USART3LPEN_Pos (18U) |
#define | RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) |
#define | RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk |
#define | RCC_APB1LLPENR_UART4LPEN_Pos (19U) |
#define | RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) |
#define | RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk |
#define | RCC_APB1LLPENR_UART5LPEN_Pos (20U) |
#define | RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) |
#define | RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk |
#define | RCC_APB1LLPENR_I2C1LPEN_Pos (21U) |
#define | RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) |
#define | RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk |
#define | RCC_APB1LLPENR_I2C2LPEN_Pos (22U) |
#define | RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) |
#define | RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk |
#define | RCC_APB1LLPENR_I2C3LPEN_Pos (23U) |
#define | RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) |
#define | RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk |
#define | RCC_APB1LLPENR_CECLPEN_Pos (27U) |
#define | RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) |
#define | RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk |
#define | RCC_APB1LLPENR_DAC12LPEN_Pos (29U) |
#define | RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) |
#define | RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk |
#define | RCC_APB1LLPENR_UART7LPEN_Pos (30U) |
#define | RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) |
#define | RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk |
#define | RCC_APB1LLPENR_UART8LPEN_Pos (31U) |
#define | RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) |
#define | RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk |
#define | RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos |
#define | RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk |
#define | RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN |
#define | RCC_APB1HLPENR_CRSLPEN_Pos (1U) |
#define | RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) |
#define | RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk |
#define | RCC_APB1HLPENR_SWPMILPEN_Pos (2U) |
#define | RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) |
#define | RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk |
#define | RCC_APB1HLPENR_OPAMPLPEN_Pos (4U) |
#define | RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) |
#define | RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk |
#define | RCC_APB1HLPENR_MDIOSLPEN_Pos (5U) |
#define | RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) |
#define | RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk |
#define | RCC_APB1HLPENR_FDCANLPEN_Pos (8U) |
#define | RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) |
#define | RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk |
#define | RCC_APB2LPENR_TIM1LPEN_Pos (0U) |
#define | RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) |
#define | RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk |
#define | RCC_APB2LPENR_TIM8LPEN_Pos (1U) |
#define | RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) |
#define | RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk |
#define | RCC_APB2LPENR_USART1LPEN_Pos (4U) |
#define | RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) |
#define | RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk |
#define | RCC_APB2LPENR_USART6LPEN_Pos (5U) |
#define | RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) |
#define | RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk |
#define | RCC_APB2LPENR_SPI1LPEN_Pos (12U) |
#define | RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) |
#define | RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk |
#define | RCC_APB2LPENR_SPI4LPEN_Pos (13U) |
#define | RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) |
#define | RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk |
#define | RCC_APB2LPENR_TIM15LPEN_Pos (16U) |
#define | RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) |
#define | RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk |
#define | RCC_APB2LPENR_TIM16LPEN_Pos (17U) |
#define | RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) |
#define | RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk |
#define | RCC_APB2LPENR_TIM17LPEN_Pos (18U) |
#define | RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) |
#define | RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk |
#define | RCC_APB2LPENR_SPI5LPEN_Pos (20U) |
#define | RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) |
#define | RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk |
#define | RCC_APB2LPENR_SAI1LPEN_Pos (22U) |
#define | RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) |
#define | RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk |
#define | RCC_APB2LPENR_SAI2LPEN_Pos (23U) |
#define | RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) |
#define | RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk |
#define | RCC_APB2LPENR_SAI3LPEN_Pos (24U) |
#define | RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) |
#define | RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk |
#define | RCC_APB2LPENR_DFSDM1LPEN_Pos (28U) |
#define | RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) |
#define | RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk |
#define | RCC_APB2LPENR_HRTIMLPEN_Pos (29U) |
#define | RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) |
#define | RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk |
#define | RCC_APB4LPENR_SYSCFGLPEN_Pos (1U) |
#define | RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) |
#define | RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk |
#define | RCC_APB4LPENR_LPUART1LPEN_Pos (3U) |
#define | RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) |
#define | RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk |
#define | RCC_APB4LPENR_SPI6LPEN_Pos (5U) |
#define | RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) |
#define | RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk |
#define | RCC_APB4LPENR_I2C4LPEN_Pos (7U) |
#define | RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) |
#define | RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk |
#define | RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) |
#define | RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) |
#define | RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk |
#define | RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) |
#define | RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) |
#define | RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk |
#define | RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) |
#define | RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) |
#define | RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk |
#define | RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) |
#define | RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) |
#define | RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk |
#define | RCC_APB4LPENR_COMP12LPEN_Pos (14U) |
#define | RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) |
#define | RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk |
#define | RCC_APB4LPENR_VREFLPEN_Pos (15U) |
#define | RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) |
#define | RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk |
#define | RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) |
#define | RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) |
#define | RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk |
#define | RCC_APB4LPENR_SAI4LPEN_Pos (21U) |
#define | RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) |
#define | RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk |
#define | RCC_RSR_RMVF_Pos (16U) |
#define | RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) |
#define | RCC_RSR_RMVF RCC_RSR_RMVF_Msk |
#define | RCC_RSR_CPURSTF_Pos (17U) |
#define | RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos) |
#define | RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk |
#define | RCC_RSR_D1RSTF_Pos (19U) |
#define | RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) |
#define | RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk |
#define | RCC_RSR_D2RSTF_Pos (20U) |
#define | RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) |
#define | RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk |
#define | RCC_RSR_BORRSTF_Pos (21U) |
#define | RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) |
#define | RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk |
#define | RCC_RSR_PINRSTF_Pos (22U) |
#define | RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) |
#define | RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk |
#define | RCC_RSR_PORRSTF_Pos (23U) |
#define | RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) |
#define | RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk |
#define | RCC_RSR_SFTRSTF_Pos (24U) |
#define | RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) |
#define | RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk |
#define | RCC_RSR_IWDG1RSTF_Pos (26U) |
#define | RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) |
#define | RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk |
#define | RCC_RSR_WWDG1RSTF_Pos (28U) |
#define | RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) |
#define | RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk |
#define | RCC_RSR_LPWRRSTF_Pos (30U) |
#define | RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) |
#define | RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk |
#define | RNG_CR_RNGEN_Pos (2U) |
#define | RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) |
#define | RNG_CR_RNGEN RNG_CR_RNGEN_Msk |
#define | RNG_CR_IE_Pos (3U) |
#define | RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) |
#define | RNG_CR_IE RNG_CR_IE_Msk |
#define | RNG_CR_CED_Pos (5U) |
#define | RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) |
#define | RNG_CR_CED RNG_CR_CED_Msk |
#define | RNG_SR_DRDY_Pos (0U) |
#define | RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) |
#define | RNG_SR_DRDY RNG_SR_DRDY_Msk |
#define | RNG_SR_CECS_Pos (1U) |
#define | RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) |
#define | RNG_SR_CECS RNG_SR_CECS_Msk |
#define | RNG_SR_SECS_Pos (2U) |
#define | RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) |
#define | RNG_SR_SECS RNG_SR_SECS_Msk |
#define | RNG_SR_CEIS_Pos (5U) |
#define | RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) |
#define | RNG_SR_CEIS RNG_SR_CEIS_Msk |
#define | RNG_SR_SEIS_Pos (6U) |
#define | RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) |
#define | RNG_SR_SEIS RNG_SR_SEIS_Msk |
#define | RTC_TR_PM_Pos (22U) |
#define | RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) |
#define | RTC_TR_PM RTC_TR_PM_Msk |
#define | RTC_TR_HT_Pos (20U) |
#define | RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) |
#define | RTC_TR_HT RTC_TR_HT_Msk |
#define | RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) |
#define | RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) |
#define | RTC_TR_HU_Pos (16U) |
#define | RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) |
#define | RTC_TR_HU RTC_TR_HU_Msk |
#define | RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) |
#define | RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) |
#define | RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) |
#define | RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) |
#define | RTC_TR_MNT_Pos (12U) |
#define | RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) |
#define | RTC_TR_MNT RTC_TR_MNT_Msk |
#define | RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) |
#define | RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) |
#define | RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) |
#define | RTC_TR_MNU_Pos (8U) |
#define | RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) |
#define | RTC_TR_MNU RTC_TR_MNU_Msk |
#define | RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) |
#define | RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) |
#define | RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) |
#define | RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) |
#define | RTC_TR_ST_Pos (4U) |
#define | RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) |
#define | RTC_TR_ST RTC_TR_ST_Msk |
#define | RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) |
#define | RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) |
#define | RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) |
#define | RTC_TR_SU_Pos (0U) |
#define | RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) |
#define | RTC_TR_SU RTC_TR_SU_Msk |
#define | RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) |
#define | RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) |
#define | RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) |
#define | RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) |
#define | RTC_DR_YT_Pos (20U) |
#define | RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) |
#define | RTC_DR_YT RTC_DR_YT_Msk |
#define | RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) |
#define | RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) |
#define | RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) |
#define | RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) |
#define | RTC_DR_YU_Pos (16U) |
#define | RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) |
#define | RTC_DR_YU RTC_DR_YU_Msk |
#define | RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) |
#define | RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) |
#define | RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) |
#define | RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) |
#define | RTC_DR_WDU_Pos (13U) |
#define | RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) |
#define | RTC_DR_WDU RTC_DR_WDU_Msk |
#define | RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) |
#define | RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) |
#define | RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) |
#define | RTC_DR_MT_Pos (12U) |
#define | RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) |
#define | RTC_DR_MT RTC_DR_MT_Msk |
#define | RTC_DR_MU_Pos (8U) |
#define | RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) |
#define | RTC_DR_MU RTC_DR_MU_Msk |
#define | RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) |
#define | RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) |
#define | RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) |
#define | RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) |
#define | RTC_DR_DT_Pos (4U) |
#define | RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) |
#define | RTC_DR_DT RTC_DR_DT_Msk |
#define | RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) |
#define | RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) |
#define | RTC_DR_DU_Pos (0U) |
#define | RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) |
#define | RTC_DR_DU RTC_DR_DU_Msk |
#define | RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) |
#define | RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) |
#define | RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) |
#define | RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) |
#define | RTC_CR_ITSE_Pos (24U) |
#define | RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) |
#define | RTC_CR_ITSE RTC_CR_ITSE_Msk |
#define | RTC_CR_COE_Pos (23U) |
#define | RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) |
#define | RTC_CR_COE RTC_CR_COE_Msk |
#define | RTC_CR_OSEL_Pos (21U) |
#define | RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) |
#define | RTC_CR_OSEL RTC_CR_OSEL_Msk |
#define | RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) |
#define | RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) |
#define | RTC_CR_POL_Pos (20U) |
#define | RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) |
#define | RTC_CR_POL RTC_CR_POL_Msk |
#define | RTC_CR_COSEL_Pos (19U) |
#define | RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) |
#define | RTC_CR_COSEL RTC_CR_COSEL_Msk |
#define | RTC_CR_BKP_Pos (18U) |
#define | RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) |
#define | RTC_CR_BKP RTC_CR_BKP_Msk |
#define | RTC_CR_SUB1H_Pos (17U) |
#define | RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) |
#define | RTC_CR_SUB1H RTC_CR_SUB1H_Msk |
#define | RTC_CR_ADD1H_Pos (16U) |
#define | RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) |
#define | RTC_CR_ADD1H RTC_CR_ADD1H_Msk |
#define | RTC_CR_TSIE_Pos (15U) |
#define | RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) |
#define | RTC_CR_TSIE RTC_CR_TSIE_Msk |
#define | RTC_CR_WUTIE_Pos (14U) |
#define | RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) |
#define | RTC_CR_WUTIE RTC_CR_WUTIE_Msk |
#define | RTC_CR_ALRBIE_Pos (13U) |
#define | RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) |
#define | RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk |
#define | RTC_CR_ALRAIE_Pos (12U) |
#define | RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) |
#define | RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk |
#define | RTC_CR_TSE_Pos (11U) |
#define | RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) |
#define | RTC_CR_TSE RTC_CR_TSE_Msk |
#define | RTC_CR_WUTE_Pos (10U) |
#define | RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) |
#define | RTC_CR_WUTE RTC_CR_WUTE_Msk |
#define | RTC_CR_ALRBE_Pos (9U) |
#define | RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) |
#define | RTC_CR_ALRBE RTC_CR_ALRBE_Msk |
#define | RTC_CR_ALRAE_Pos (8U) |
#define | RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) |
#define | RTC_CR_ALRAE RTC_CR_ALRAE_Msk |
#define | RTC_CR_FMT_Pos (6U) |
#define | RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) |
#define | RTC_CR_FMT RTC_CR_FMT_Msk |
#define | RTC_CR_BYPSHAD_Pos (5U) |
#define | RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) |
#define | RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk |
#define | RTC_CR_REFCKON_Pos (4U) |
#define | RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) |
#define | RTC_CR_REFCKON RTC_CR_REFCKON_Msk |
#define | RTC_CR_TSEDGE_Pos (3U) |
#define | RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) |
#define | RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk |
#define | RTC_CR_WUCKSEL_Pos (0U) |
#define | RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) |
#define | RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk |
#define | RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) |
#define | RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) |
#define | RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) |
#define | RTC_ISR_ITSF_Pos (17U) |
#define | RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) |
#define | RTC_ISR_ITSF RTC_ISR_ITSF_Msk |
#define | RTC_ISR_RECALPF_Pos (16U) |
#define | RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) |
#define | RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk |
#define | RTC_ISR_TAMP3F_Pos (15U) |
#define | RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) |
#define | RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk |
#define | RTC_ISR_TAMP2F_Pos (14U) |
#define | RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) |
#define | RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk |
#define | RTC_ISR_TAMP1F_Pos (13U) |
#define | RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) |
#define | RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk |
#define | RTC_ISR_TSOVF_Pos (12U) |
#define | RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) |
#define | RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk |
#define | RTC_ISR_TSF_Pos (11U) |
#define | RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) |
#define | RTC_ISR_TSF RTC_ISR_TSF_Msk |
#define | RTC_ISR_WUTF_Pos (10U) |
#define | RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) |
#define | RTC_ISR_WUTF RTC_ISR_WUTF_Msk |
#define | RTC_ISR_ALRBF_Pos (9U) |
#define | RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) |
#define | RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk |
#define | RTC_ISR_ALRAF_Pos (8U) |
#define | RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) |
#define | RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk |
#define | RTC_ISR_INIT_Pos (7U) |
#define | RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) |
#define | RTC_ISR_INIT RTC_ISR_INIT_Msk |
#define | RTC_ISR_INITF_Pos (6U) |
#define | RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) |
#define | RTC_ISR_INITF RTC_ISR_INITF_Msk |
#define | RTC_ISR_RSF_Pos (5U) |
#define | RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) |
#define | RTC_ISR_RSF RTC_ISR_RSF_Msk |
#define | RTC_ISR_INITS_Pos (4U) |
#define | RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) |
#define | RTC_ISR_INITS RTC_ISR_INITS_Msk |
#define | RTC_ISR_SHPF_Pos (3U) |
#define | RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) |
#define | RTC_ISR_SHPF RTC_ISR_SHPF_Msk |
#define | RTC_ISR_WUTWF_Pos (2U) |
#define | RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) |
#define | RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk |
#define | RTC_ISR_ALRBWF_Pos (1U) |
#define | RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) |
#define | RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk |
#define | RTC_ISR_ALRAWF_Pos (0U) |
#define | RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) |
#define | RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk |
#define | RTC_PRER_PREDIV_A_Pos (16U) |
#define | RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) |
#define | RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk |
#define | RTC_PRER_PREDIV_S_Pos (0U) |
#define | RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) |
#define | RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk |
#define | RTC_WUTR_WUT_Pos (0U) |
#define | RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) |
#define | RTC_WUTR_WUT RTC_WUTR_WUT_Msk |
#define | RTC_ALRMAR_MSK4_Pos (31U) |
#define | RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) |
#define | RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk |
#define | RTC_ALRMAR_WDSEL_Pos (30U) |
#define | RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) |
#define | RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk |
#define | RTC_ALRMAR_DT_Pos (28U) |
#define | RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) |
#define | RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk |
#define | RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) |
#define | RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) |
#define | RTC_ALRMAR_DU_Pos (24U) |
#define | RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) |
#define | RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk |
#define | RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) |
#define | RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) |
#define | RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) |
#define | RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) |
#define | RTC_ALRMAR_MSK3_Pos (23U) |
#define | RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) |
#define | RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk |
#define | RTC_ALRMAR_PM_Pos (22U) |
#define | RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) |
#define | RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk |
#define | RTC_ALRMAR_HT_Pos (20U) |
#define | RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) |
#define | RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk |
#define | RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) |
#define | RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) |
#define | RTC_ALRMAR_HU_Pos (16U) |
#define | RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) |
#define | RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk |
#define | RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) |
#define | RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) |
#define | RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) |
#define | RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) |
#define | RTC_ALRMAR_MSK2_Pos (15U) |
#define | RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) |
#define | RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk |
#define | RTC_ALRMAR_MNT_Pos (12U) |
#define | RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) |
#define | RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk |
#define | RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) |
#define | RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) |
#define | RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) |
#define | RTC_ALRMAR_MNU_Pos (8U) |
#define | RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) |
#define | RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk |
#define | RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) |
#define | RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) |
#define | RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) |
#define | RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) |
#define | RTC_ALRMAR_MSK1_Pos (7U) |
#define | RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) |
#define | RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk |
#define | RTC_ALRMAR_ST_Pos (4U) |
#define | RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) |
#define | RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk |
#define | RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) |
#define | RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) |
#define | RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) |
#define | RTC_ALRMAR_SU_Pos (0U) |
#define | RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) |
#define | RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk |
#define | RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) |
#define | RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) |
#define | RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) |
#define | RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) |
#define | RTC_ALRMBR_MSK4_Pos (31U) |
#define | RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) |
#define | RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk |
#define | RTC_ALRMBR_WDSEL_Pos (30U) |
#define | RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) |
#define | RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk |
#define | RTC_ALRMBR_DT_Pos (28U) |
#define | RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) |
#define | RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk |
#define | RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) |
#define | RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) |
#define | RTC_ALRMBR_DU_Pos (24U) |
#define | RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) |
#define | RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk |
#define | RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) |
#define | RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) |
#define | RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) |
#define | RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) |
#define | RTC_ALRMBR_MSK3_Pos (23U) |
#define | RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) |
#define | RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk |
#define | RTC_ALRMBR_PM_Pos (22U) |
#define | RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) |
#define | RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk |
#define | RTC_ALRMBR_HT_Pos (20U) |
#define | RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) |
#define | RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk |
#define | RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) |
#define | RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) |
#define | RTC_ALRMBR_HU_Pos (16U) |
#define | RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) |
#define | RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk |
#define | RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) |
#define | RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) |
#define | RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) |
#define | RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) |
#define | RTC_ALRMBR_MSK2_Pos (15U) |
#define | RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) |
#define | RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk |
#define | RTC_ALRMBR_MNT_Pos (12U) |
#define | RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) |
#define | RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk |
#define | RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) |
#define | RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) |
#define | RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) |
#define | RTC_ALRMBR_MNU_Pos (8U) |
#define | RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) |
#define | RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk |
#define | RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) |
#define | RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) |
#define | RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) |
#define | RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) |
#define | RTC_ALRMBR_MSK1_Pos (7U) |
#define | RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) |
#define | RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk |
#define | RTC_ALRMBR_ST_Pos (4U) |
#define | RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) |
#define | RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk |
#define | RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) |
#define | RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) |
#define | RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) |
#define | RTC_ALRMBR_SU_Pos (0U) |
#define | RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) |
#define | RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk |
#define | RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) |
#define | RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) |
#define | RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) |
#define | RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) |
#define | RTC_WPR_KEY_Pos (0U) |
#define | RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) |
#define | RTC_WPR_KEY RTC_WPR_KEY_Msk |
#define | RTC_SSR_SS_Pos (0U) |
#define | RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) |
#define | RTC_SSR_SS RTC_SSR_SS_Msk |
#define | RTC_SHIFTR_SUBFS_Pos (0U) |
#define | RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) |
#define | RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk |
#define | RTC_SHIFTR_ADD1S_Pos (31U) |
#define | RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) |
#define | RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk |
#define | RTC_TSTR_PM_Pos (22U) |
#define | RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) |
#define | RTC_TSTR_PM RTC_TSTR_PM_Msk |
#define | RTC_TSTR_HT_Pos (20U) |
#define | RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) |
#define | RTC_TSTR_HT RTC_TSTR_HT_Msk |
#define | RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) |
#define | RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) |
#define | RTC_TSTR_HU_Pos (16U) |
#define | RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) |
#define | RTC_TSTR_HU RTC_TSTR_HU_Msk |
#define | RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) |
#define | RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) |
#define | RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) |
#define | RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) |
#define | RTC_TSTR_MNT_Pos (12U) |
#define | RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) |
#define | RTC_TSTR_MNT RTC_TSTR_MNT_Msk |
#define | RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) |
#define | RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) |
#define | RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) |
#define | RTC_TSTR_MNU_Pos (8U) |
#define | RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) |
#define | RTC_TSTR_MNU RTC_TSTR_MNU_Msk |
#define | RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) |
#define | RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) |
#define | RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) |
#define | RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) |
#define | RTC_TSTR_ST_Pos (4U) |
#define | RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) |
#define | RTC_TSTR_ST RTC_TSTR_ST_Msk |
#define | RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) |
#define | RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) |
#define | RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) |
#define | RTC_TSTR_SU_Pos (0U) |
#define | RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) |
#define | RTC_TSTR_SU RTC_TSTR_SU_Msk |
#define | RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) |
#define | RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) |
#define | RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) |
#define | RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) |
#define | RTC_TSDR_WDU_Pos (13U) |
#define | RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) |
#define | RTC_TSDR_WDU RTC_TSDR_WDU_Msk |
#define | RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) |
#define | RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) |
#define | RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) |
#define | RTC_TSDR_MT_Pos (12U) |
#define | RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) |
#define | RTC_TSDR_MT RTC_TSDR_MT_Msk |
#define | RTC_TSDR_MU_Pos (8U) |
#define | RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) |
#define | RTC_TSDR_MU RTC_TSDR_MU_Msk |
#define | RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) |
#define | RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) |
#define | RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) |
#define | RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) |
#define | RTC_TSDR_DT_Pos (4U) |
#define | RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) |
#define | RTC_TSDR_DT RTC_TSDR_DT_Msk |
#define | RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) |
#define | RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) |
#define | RTC_TSDR_DU_Pos (0U) |
#define | RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) |
#define | RTC_TSDR_DU RTC_TSDR_DU_Msk |
#define | RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) |
#define | RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) |
#define | RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) |
#define | RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) |
#define | RTC_TSSSR_SS_Pos (0U) |
#define | RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) |
#define | RTC_TSSSR_SS RTC_TSSSR_SS_Msk |
#define | RTC_CALR_CALP_Pos (15U) |
#define | RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) |
#define | RTC_CALR_CALP RTC_CALR_CALP_Msk |
#define | RTC_CALR_CALW8_Pos (14U) |
#define | RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) |
#define | RTC_CALR_CALW8 RTC_CALR_CALW8_Msk |
#define | RTC_CALR_CALW16_Pos (13U) |
#define | RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) |
#define | RTC_CALR_CALW16 RTC_CALR_CALW16_Msk |
#define | RTC_CALR_CALM_Pos (0U) |
#define | RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM RTC_CALR_CALM_Msk |
#define | RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) |
#define | RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) |
#define | RTC_TAMPCR_TAMP3MF_Pos (24U) |
#define | RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) |
#define | RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk |
#define | RTC_TAMPCR_TAMP3NOERASE_Pos (23U) |
#define | RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) |
#define | RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk |
#define | RTC_TAMPCR_TAMP3IE_Pos (22U) |
#define | RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) |
#define | RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk |
#define | RTC_TAMPCR_TAMP2MF_Pos (21U) |
#define | RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) |
#define | RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk |
#define | RTC_TAMPCR_TAMP2NOERASE_Pos (20U) |
#define | RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) |
#define | RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk |
#define | RTC_TAMPCR_TAMP2IE_Pos (19U) |
#define | RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) |
#define | RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk |
#define | RTC_TAMPCR_TAMP1MF_Pos (18U) |
#define | RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) |
#define | RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk |
#define | RTC_TAMPCR_TAMP1NOERASE_Pos (17U) |
#define | RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) |
#define | RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk |
#define | RTC_TAMPCR_TAMP1IE_Pos (16U) |
#define | RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) |
#define | RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk |
#define | RTC_TAMPCR_TAMPPUDIS_Pos (15U) |
#define | RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) |
#define | RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk |
#define | RTC_TAMPCR_TAMPPRCH_Pos (13U) |
#define | RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) |
#define | RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk |
#define | RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) |
#define | RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) |
#define | RTC_TAMPCR_TAMPFLT_Pos (11U) |
#define | RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) |
#define | RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk |
#define | RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) |
#define | RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) |
#define | RTC_TAMPCR_TAMPFREQ_Pos (8U) |
#define | RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) |
#define | RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk |
#define | RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) |
#define | RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) |
#define | RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) |
#define | RTC_TAMPCR_TAMPTS_Pos (7U) |
#define | RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) |
#define | RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk |
#define | RTC_TAMPCR_TAMP3TRG_Pos (6U) |
#define | RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) |
#define | RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk |
#define | RTC_TAMPCR_TAMP3E_Pos (5U) |
#define | RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) |
#define | RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk |
#define | RTC_TAMPCR_TAMP2TRG_Pos (4U) |
#define | RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) |
#define | RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk |
#define | RTC_TAMPCR_TAMP2E_Pos (3U) |
#define | RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) |
#define | RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk |
#define | RTC_TAMPCR_TAMPIE_Pos (2U) |
#define | RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) |
#define | RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk |
#define | RTC_TAMPCR_TAMP1TRG_Pos (1U) |
#define | RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) |
#define | RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk |
#define | RTC_TAMPCR_TAMP1E_Pos (0U) |
#define | RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) |
#define | RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk |
#define | RTC_ALRMASSR_MASKSS_Pos (24U) |
#define | RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) |
#define | RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk |
#define | RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) |
#define | RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) |
#define | RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) |
#define | RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) |
#define | RTC_ALRMASSR_SS_Pos (0U) |
#define | RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) |
#define | RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk |
#define | RTC_ALRMBSSR_MASKSS_Pos (24U) |
#define | RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) |
#define | RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk |
#define | RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) |
#define | RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) |
#define | RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) |
#define | RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) |
#define | RTC_ALRMBSSR_SS_Pos (0U) |
#define | RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) |
#define | RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk |
#define | RTC_OR_OUT_RMP_Pos (1U) |
#define | RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) |
#define | RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk |
#define | RTC_OR_ALARMOUTTYPE_Pos (0U) |
#define | RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) |
#define | RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk |
#define | RTC_BKP0R_Pos (0U) |
#define | RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) |
#define | RTC_BKP0R RTC_BKP0R_Msk |
#define | RTC_BKP1R_Pos (0U) |
#define | RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) |
#define | RTC_BKP1R RTC_BKP1R_Msk |
#define | RTC_BKP2R_Pos (0U) |
#define | RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) |
#define | RTC_BKP2R RTC_BKP2R_Msk |
#define | RTC_BKP3R_Pos (0U) |
#define | RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) |
#define | RTC_BKP3R RTC_BKP3R_Msk |
#define | RTC_BKP4R_Pos (0U) |
#define | RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) |
#define | RTC_BKP4R RTC_BKP4R_Msk |
#define | RTC_BKP5R_Pos (0U) |
#define | RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) |
#define | RTC_BKP5R RTC_BKP5R_Msk |
#define | RTC_BKP6R_Pos (0U) |
#define | RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) |
#define | RTC_BKP6R RTC_BKP6R_Msk |
#define | RTC_BKP7R_Pos (0U) |
#define | RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) |
#define | RTC_BKP7R RTC_BKP7R_Msk |
#define | RTC_BKP8R_Pos (0U) |
#define | RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) |
#define | RTC_BKP8R RTC_BKP8R_Msk |
#define | RTC_BKP9R_Pos (0U) |
#define | RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) |
#define | RTC_BKP9R RTC_BKP9R_Msk |
#define | RTC_BKP10R_Pos (0U) |
#define | RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) |
#define | RTC_BKP10R RTC_BKP10R_Msk |
#define | RTC_BKP11R_Pos (0U) |
#define | RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) |
#define | RTC_BKP11R RTC_BKP11R_Msk |
#define | RTC_BKP12R_Pos (0U) |
#define | RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) |
#define | RTC_BKP12R RTC_BKP12R_Msk |
#define | RTC_BKP13R_Pos (0U) |
#define | RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) |
#define | RTC_BKP13R RTC_BKP13R_Msk |
#define | RTC_BKP14R_Pos (0U) |
#define | RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) |
#define | RTC_BKP14R RTC_BKP14R_Msk |
#define | RTC_BKP15R_Pos (0U) |
#define | RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) |
#define | RTC_BKP15R RTC_BKP15R_Msk |
#define | RTC_BKP16R_Pos (0U) |
#define | RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) |
#define | RTC_BKP16R RTC_BKP16R_Msk |
#define | RTC_BKP17R_Pos (0U) |
#define | RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) |
#define | RTC_BKP17R RTC_BKP17R_Msk |
#define | RTC_BKP18R_Pos (0U) |
#define | RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) |
#define | RTC_BKP18R RTC_BKP18R_Msk |
#define | RTC_BKP19R_Pos (0U) |
#define | RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) |
#define | RTC_BKP19R RTC_BKP19R_Msk |
#define | RTC_BKP20R_Pos (0U) |
#define | RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) |
#define | RTC_BKP20R RTC_BKP20R_Msk |
#define | RTC_BKP21R_Pos (0U) |
#define | RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) |
#define | RTC_BKP21R RTC_BKP21R_Msk |
#define | RTC_BKP22R_Pos (0U) |
#define | RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) |
#define | RTC_BKP22R RTC_BKP22R_Msk |
#define | RTC_BKP23R_Pos (0U) |
#define | RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) |
#define | RTC_BKP23R RTC_BKP23R_Msk |
#define | RTC_BKP24R_Pos (0U) |
#define | RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) |
#define | RTC_BKP24R RTC_BKP24R_Msk |
#define | RTC_BKP25R_Pos (0U) |
#define | RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) |
#define | RTC_BKP25R RTC_BKP25R_Msk |
#define | RTC_BKP26R_Pos (0U) |
#define | RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) |
#define | RTC_BKP26R RTC_BKP26R_Msk |
#define | RTC_BKP27R_Pos (0U) |
#define | RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) |
#define | RTC_BKP27R RTC_BKP27R_Msk |
#define | RTC_BKP28R_Pos (0U) |
#define | RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) |
#define | RTC_BKP28R RTC_BKP28R_Msk |
#define | RTC_BKP29R_Pos (0U) |
#define | RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) |
#define | RTC_BKP29R RTC_BKP29R_Msk |
#define | RTC_BKP30R_Pos (0U) |
#define | RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) |
#define | RTC_BKP30R RTC_BKP30R_Msk |
#define | RTC_BKP31R_Pos (0U) |
#define | RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) |
#define | RTC_BKP31R RTC_BKP31R_Msk |
#define | RTC_BKP_NUMBER_Pos (5U) |
#define | RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) |
#define | RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk |
#define | SPDIFRX_CR_SPDIFEN_Pos (0U) |
#define | SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) |
#define | SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk |
#define | SPDIFRX_CR_RXDMAEN_Pos (2U) |
#define | SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) |
#define | SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk |
#define | SPDIFRX_CR_RXSTEO_Pos (3U) |
#define | SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) |
#define | SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk |
#define | SPDIFRX_CR_DRFMT_Pos (4U) |
#define | SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) |
#define | SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk |
#define | SPDIFRX_CR_PMSK_Pos (6U) |
#define | SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) |
#define | SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk |
#define | SPDIFRX_CR_VMSK_Pos (7U) |
#define | SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) |
#define | SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk |
#define | SPDIFRX_CR_CUMSK_Pos (8U) |
#define | SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) |
#define | SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk |
#define | SPDIFRX_CR_PTMSK_Pos (9U) |
#define | SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) |
#define | SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk |
#define | SPDIFRX_CR_CBDMAEN_Pos (10U) |
#define | SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) |
#define | SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk |
#define | SPDIFRX_CR_CHSEL_Pos (11U) |
#define | SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) |
#define | SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk |
#define | SPDIFRX_CR_NBTR_Pos (12U) |
#define | SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) |
#define | SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk |
#define | SPDIFRX_CR_WFA_Pos (14U) |
#define | SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) |
#define | SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk |
#define | SPDIFRX_CR_INSEL_Pos (16U) |
#define | SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) |
#define | SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk |
#define | SPDIFRX_CR_CKSEN_Pos (20U) |
#define | SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) |
#define | SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk |
#define | SPDIFRX_CR_CKSBKPEN_Pos (21U) |
#define | SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) |
#define | SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk |
#define | SPDIFRX_IMR_RXNEIE_Pos (0U) |
#define | SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) |
#define | SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk |
#define | SPDIFRX_IMR_CSRNEIE_Pos (1U) |
#define | SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) |
#define | SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk |
#define | SPDIFRX_IMR_PERRIE_Pos (2U) |
#define | SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) |
#define | SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk |
#define | SPDIFRX_IMR_OVRIE_Pos (3U) |
#define | SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) |
#define | SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk |
#define | SPDIFRX_IMR_SBLKIE_Pos (4U) |
#define | SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) |
#define | SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk |
#define | SPDIFRX_IMR_SYNCDIE_Pos (5U) |
#define | SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) |
#define | SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk |
#define | SPDIFRX_IMR_IFEIE_Pos (6U) |
#define | SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) |
#define | SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk |
#define | SPDIFRX_SR_RXNE_Pos (0U) |
#define | SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) |
#define | SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk |
#define | SPDIFRX_SR_CSRNE_Pos (1U) |
#define | SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) |
#define | SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk |
#define | SPDIFRX_SR_PERR_Pos (2U) |
#define | SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) |
#define | SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk |
#define | SPDIFRX_SR_OVR_Pos (3U) |
#define | SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) |
#define | SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk |
#define | SPDIFRX_SR_SBD_Pos (4U) |
#define | SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) |
#define | SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk |
#define | SPDIFRX_SR_SYNCD_Pos (5U) |
#define | SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) |
#define | SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk |
#define | SPDIFRX_SR_FERR_Pos (6U) |
#define | SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) |
#define | SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk |
#define | SPDIFRX_SR_SERR_Pos (7U) |
#define | SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) |
#define | SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk |
#define | SPDIFRX_SR_TERR_Pos (8U) |
#define | SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) |
#define | SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk |
#define | SPDIFRX_SR_WIDTH5_Pos (16U) |
#define | SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) |
#define | SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk |
#define | SPDIFRX_IFCR_PERRCF_Pos (2U) |
#define | SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) |
#define | SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk |
#define | SPDIFRX_IFCR_OVRCF_Pos (3U) |
#define | SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) |
#define | SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk |
#define | SPDIFRX_IFCR_SBDCF_Pos (4U) |
#define | SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) |
#define | SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk |
#define | SPDIFRX_IFCR_SYNCDCF_Pos (5U) |
#define | SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) |
#define | SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk |
#define | SPDIFRX_DR0_DR_Pos (0U) |
#define | SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) |
#define | SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk |
#define | SPDIFRX_DR0_PE_Pos (24U) |
#define | SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) |
#define | SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk |
#define | SPDIFRX_DR0_V_Pos (25U) |
#define | SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) |
#define | SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk |
#define | SPDIFRX_DR0_U_Pos (26U) |
#define | SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) |
#define | SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk |
#define | SPDIFRX_DR0_C_Pos (27U) |
#define | SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) |
#define | SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk |
#define | SPDIFRX_DR0_PT_Pos (28U) |
#define | SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) |
#define | SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk |
#define | SPDIFRX_DR1_DR_Pos (8U) |
#define | SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) |
#define | SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk |
#define | SPDIFRX_DR1_PT_Pos (4U) |
#define | SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) |
#define | SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk |
#define | SPDIFRX_DR1_C_Pos (3U) |
#define | SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) |
#define | SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk |
#define | SPDIFRX_DR1_U_Pos (2U) |
#define | SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) |
#define | SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk |
#define | SPDIFRX_DR1_V_Pos (1U) |
#define | SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) |
#define | SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk |
#define | SPDIFRX_DR1_PE_Pos (0U) |
#define | SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) |
#define | SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk |
#define | SPDIFRX_DR1_DRNL1_Pos (16U) |
#define | SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) |
#define | SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk |
#define | SPDIFRX_DR1_DRNL2_Pos (0U) |
#define | SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) |
#define | SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk |
#define | SPDIFRX_CSR_USR_Pos (0U) |
#define | SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) |
#define | SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk |
#define | SPDIFRX_CSR_CS_Pos (16U) |
#define | SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) |
#define | SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk |
#define | SPDIFRX_CSR_SOB_Pos (24U) |
#define | SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) |
#define | SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk |
#define | SPDIFRX_DIR_THI_Pos (0U) |
#define | SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) |
#define | SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk |
#define | SPDIFRX_DIR_TLO_Pos (16U) |
#define | SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) |
#define | SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk |
#define | SPDIFRX_VERR_MINREV_Pos (0U) |
#define | SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) |
#define | SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk |
#define | SPDIFRX_VERR_MAJREV_Pos (4U) |
#define | SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) |
#define | SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk |
#define | SPDIFRX_IDR_ID_Pos (0U) |
#define | SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) |
#define | SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk |
#define | SPDIFRX_SIDR_SID_Pos (0U) |
#define | SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) |
#define | SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk |
#define | SAI_VER_V2_X |
#define | SAI_GCR_SYNCIN_Pos (0U) |
#define | SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) |
#define | SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk |
#define | SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) |
#define | SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) |
#define | SAI_GCR_SYNCOUT_Pos (4U) |
#define | SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) |
#define | SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk |
#define | SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) |
#define | SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) |
#define | SAI_xCR1_MODE_Pos (0U) |
#define | SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) |
#define | SAI_xCR1_MODE SAI_xCR1_MODE_Msk |
#define | SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) |
#define | SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) |
#define | SAI_xCR1_PRTCFG_Pos (2U) |
#define | SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) |
#define | SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk |
#define | SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) |
#define | SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) |
#define | SAI_xCR1_DS_Pos (5U) |
#define | SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) |
#define | SAI_xCR1_DS SAI_xCR1_DS_Msk |
#define | SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) |
#define | SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) |
#define | SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) |
#define | SAI_xCR1_LSBFIRST_Pos (8U) |
#define | SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) |
#define | SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk |
#define | SAI_xCR1_CKSTR_Pos (9U) |
#define | SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) |
#define | SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk |
#define | SAI_xCR1_SYNCEN_Pos (10U) |
#define | SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) |
#define | SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk |
#define | SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) |
#define | SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) |
#define | SAI_xCR1_MONO_Pos (12U) |
#define | SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) |
#define | SAI_xCR1_MONO SAI_xCR1_MONO_Msk |
#define | SAI_xCR1_OUTDRIV_Pos (13U) |
#define | SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) |
#define | SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk |
#define | SAI_xCR1_SAIEN_Pos (16U) |
#define | SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) |
#define | SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk |
#define | SAI_xCR1_DMAEN_Pos (17U) |
#define | SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) |
#define | SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk |
#define | SAI_xCR1_NODIV_Pos (19U) |
#define | SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) |
#define | SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk |
#define | SAI_xCR1_MCKDIV_Pos (20U) |
#define | SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk |
#define | SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) |
#define | SAI_xCR1_MCKEN_Pos (27U) |
#define | SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) |
#define | SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk |
#define | SAI_xCR1_OSR_Pos (26U) |
#define | SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) |
#define | SAI_xCR1_OSR SAI_xCR1_OSR_Msk |
#define | SAI_xCR1_NOMCK SAI_xCR1_NODIV |
#define | SAI_xCR2_FTH_Pos (0U) |
#define | SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) |
#define | SAI_xCR2_FTH SAI_xCR2_FTH_Msk |
#define | SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) |
#define | SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) |
#define | SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) |
#define | SAI_xCR2_FFLUSH_Pos (3U) |
#define | SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) |
#define | SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk |
#define | SAI_xCR2_TRIS_Pos (4U) |
#define | SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) |
#define | SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk |
#define | SAI_xCR2_MUTE_Pos (5U) |
#define | SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) |
#define | SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk |
#define | SAI_xCR2_MUTEVAL_Pos (6U) |
#define | SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) |
#define | SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk |
#define | SAI_xCR2_MUTECNT_Pos (7U) |
#define | SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk |
#define | SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) |
#define | SAI_xCR2_CPL_Pos (13U) |
#define | SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) |
#define | SAI_xCR2_CPL SAI_xCR2_CPL_Msk |
#define | SAI_xCR2_COMP_Pos (14U) |
#define | SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) |
#define | SAI_xCR2_COMP SAI_xCR2_COMP_Msk |
#define | SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) |
#define | SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) |
#define | SAI_xFRCR_FRL_Pos (0U) |
#define | SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk |
#define | SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) |
#define | SAI_xFRCR_FSALL_Pos (8U) |
#define | SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk |
#define | SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) |
#define | SAI_xFRCR_FSDEF_Pos (16U) |
#define | SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) |
#define | SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk |
#define | SAI_xFRCR_FSPOL_Pos (17U) |
#define | SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) |
#define | SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk |
#define | SAI_xFRCR_FSOFF_Pos (18U) |
#define | SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) |
#define | SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk |
#define | SAI_xFRCR_FSPO SAI_xFRCR_FSPOL |
#define | SAI_xSLOTR_FBOFF_Pos (0U) |
#define | SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) |
#define | SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk |
#define | SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) |
#define | SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) |
#define | SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) |
#define | SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) |
#define | SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) |
#define | SAI_xSLOTR_SLOTSZ_Pos (6U) |
#define | SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) |
#define | SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk |
#define | SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) |
#define | SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) |
#define | SAI_xSLOTR_NBSLOT_Pos (8U) |
#define | SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) |
#define | SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk |
#define | SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) |
#define | SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) |
#define | SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) |
#define | SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) |
#define | SAI_xSLOTR_SLOTEN_Pos (16U) |
#define | SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) |
#define | SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk |
#define | SAI_xIMR_OVRUDRIE_Pos (0U) |
#define | SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) |
#define | SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk |
#define | SAI_xIMR_MUTEDETIE_Pos (1U) |
#define | SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) |
#define | SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk |
#define | SAI_xIMR_WCKCFGIE_Pos (2U) |
#define | SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) |
#define | SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk |
#define | SAI_xIMR_FREQIE_Pos (3U) |
#define | SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) |
#define | SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk |
#define | SAI_xIMR_CNRDYIE_Pos (4U) |
#define | SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) |
#define | SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk |
#define | SAI_xIMR_AFSDETIE_Pos (5U) |
#define | SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) |
#define | SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk |
#define | SAI_xIMR_LFSDETIE_Pos (6U) |
#define | SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) |
#define | SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk |
#define | SAI_xSR_OVRUDR_Pos (0U) |
#define | SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) |
#define | SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk |
#define | SAI_xSR_MUTEDET_Pos (1U) |
#define | SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) |
#define | SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk |
#define | SAI_xSR_WCKCFG_Pos (2U) |
#define | SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) |
#define | SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk |
#define | SAI_xSR_FREQ_Pos (3U) |
#define | SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) |
#define | SAI_xSR_FREQ SAI_xSR_FREQ_Msk |
#define | SAI_xSR_CNRDY_Pos (4U) |
#define | SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) |
#define | SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk |
#define | SAI_xSR_AFSDET_Pos (5U) |
#define | SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) |
#define | SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk |
#define | SAI_xSR_LFSDET_Pos (6U) |
#define | SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) |
#define | SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk |
#define | SAI_xSR_FLVL_Pos (16U) |
#define | SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) |
#define | SAI_xSR_FLVL SAI_xSR_FLVL_Msk |
#define | SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) |
#define | SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) |
#define | SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) |
#define | SAI_xCLRFR_COVRUDR_Pos (0U) |
#define | SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) |
#define | SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk |
#define | SAI_xCLRFR_CMUTEDET_Pos (1U) |
#define | SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) |
#define | SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk |
#define | SAI_xCLRFR_CWCKCFG_Pos (2U) |
#define | SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) |
#define | SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk |
#define | SAI_xCLRFR_CFREQ_Pos (3U) |
#define | SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) |
#define | SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk |
#define | SAI_xCLRFR_CCNRDY_Pos (4U) |
#define | SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) |
#define | SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk |
#define | SAI_xCLRFR_CAFSDET_Pos (5U) |
#define | SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) |
#define | SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk |
#define | SAI_xCLRFR_CLFSDET_Pos (6U) |
#define | SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) |
#define | SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk |
#define | SAI_xDR_DATA_Pos (0U) |
#define | SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) |
#define | SAI_xDR_DATA SAI_xDR_DATA_Msk |
#define | SAI_PDMCR_PDMEN_Pos (0U) |
#define | SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) |
#define | SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk |
#define | SAI_PDMCR_MICNBR_Pos (4U) |
#define | SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) |
#define | SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk |
#define | SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) |
#define | SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) |
#define | SAI_PDMCR_CKEN1_Pos (8U) |
#define | SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) |
#define | SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk |
#define | SAI_PDMCR_CKEN2_Pos (9U) |
#define | SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) |
#define | SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk |
#define | SAI_PDMCR_CKEN3_Pos (10U) |
#define | SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) |
#define | SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk |
#define | SAI_PDMCR_CKEN4_Pos (11U) |
#define | SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) |
#define | SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk |
#define | SAI_PDMDLY_DLYM1L_Pos (0U) |
#define | SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) |
#define | SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk |
#define | SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) |
#define | SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) |
#define | SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) |
#define | SAI_PDMDLY_DLYM1R_Pos (4U) |
#define | SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) |
#define | SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk |
#define | SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) |
#define | SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) |
#define | SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) |
#define | SAI_PDMDLY_DLYM2L_Pos (8U) |
#define | SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) |
#define | SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk |
#define | SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) |
#define | SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) |
#define | SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) |
#define | SAI_PDMDLY_DLYM2R_Pos (12U) |
#define | SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) |
#define | SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk |
#define | SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) |
#define | SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) |
#define | SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) |
#define | SAI_PDMDLY_DLYM3L_Pos (16U) |
#define | SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) |
#define | SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk |
#define | SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) |
#define | SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) |
#define | SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) |
#define | SAI_PDMDLY_DLYM3R_Pos (20U) |
#define | SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) |
#define | SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk |
#define | SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) |
#define | SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) |
#define | SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) |
#define | SAI_PDMDLY_DLYM4L_Pos (24U) |
#define | SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) |
#define | SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk |
#define | SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) |
#define | SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) |
#define | SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) |
#define | SAI_PDMDLY_DLYM4R_Pos (28U) |
#define | SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) |
#define | SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk |
#define | SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) |
#define | SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) |
#define | SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) |
#define | SDMMC_POWER_PWRCTRL_Pos (0U) |
#define | SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) |
#define | SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk |
#define | SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) |
#define | SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) |
#define | SDMMC_POWER_VSWITCH_Pos (2U) |
#define | SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) |
#define | SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk |
#define | SDMMC_POWER_VSWITCHEN_Pos (3U) |
#define | SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) |
#define | SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk |
#define | SDMMC_POWER_DIRPOL_Pos (4U) |
#define | SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) |
#define | SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk |
#define | SDMMC_CLKCR_CLKDIV_Pos (0U) |
#define | SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) |
#define | SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk |
#define | SDMMC_CLKCR_PWRSAV_Pos (12U) |
#define | SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) |
#define | SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk |
#define | SDMMC_CLKCR_WIDBUS_Pos (14U) |
#define | SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) |
#define | SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk |
#define | SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) |
#define | SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) |
#define | SDMMC_CLKCR_NEGEDGE_Pos (16U) |
#define | SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) |
#define | SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk |
#define | SDMMC_CLKCR_HWFC_EN_Pos (17U) |
#define | SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) |
#define | SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk |
#define | SDMMC_CLKCR_DDR_Pos (18U) |
#define | SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) |
#define | SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk |
#define | SDMMC_CLKCR_BUSSPEED_Pos (19U) |
#define | SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) |
#define | SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk |
#define | SDMMC_CLKCR_SELCLKRX_Pos (20U) |
#define | SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) |
#define | SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk |
#define | SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) |
#define | SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) |
#define | SDMMC_ARG_CMDARG_Pos (0U) |
#define | SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) |
#define | SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk |
#define | SDMMC_CMD_CMDINDEX_Pos (0U) |
#define | SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) |
#define | SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk |
#define | SDMMC_CMD_CMDTRANS_Pos (6U) |
#define | SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) |
#define | SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk |
#define | SDMMC_CMD_CMDSTOP_Pos (7U) |
#define | SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) |
#define | SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk |
#define | SDMMC_CMD_WAITRESP_Pos (8U) |
#define | SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) |
#define | SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk |
#define | SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) |
#define | SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) |
#define | SDMMC_CMD_WAITINT_Pos (10U) |
#define | SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) |
#define | SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk |
#define | SDMMC_CMD_WAITPEND_Pos (11U) |
#define | SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) |
#define | SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk |
#define | SDMMC_CMD_CPSMEN_Pos (12U) |
#define | SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) |
#define | SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk |
#define | SDMMC_CMD_DTHOLD_Pos (13U) |
#define | SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) |
#define | SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk |
#define | SDMMC_CMD_BOOTMODE_Pos (14U) |
#define | SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) |
#define | SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk |
#define | SDMMC_CMD_BOOTEN_Pos (15U) |
#define | SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) |
#define | SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk |
#define | SDMMC_CMD_CMDSUSPEND_Pos (16U) |
#define | SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) |
#define | SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk |
#define | SDMMC_RESPCMD_RESPCMD_Pos (0U) |
#define | SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) |
#define | SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk |
#define | SDMMC_RESP0_CARDSTATUS0_Pos (0U) |
#define | SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) |
#define | SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk |
#define | SDMMC_RESP1_CARDSTATUS1_Pos (0U) |
#define | SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) |
#define | SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk |
#define | SDMMC_RESP2_CARDSTATUS2_Pos (0U) |
#define | SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) |
#define | SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk |
#define | SDMMC_RESP3_CARDSTATUS3_Pos (0U) |
#define | SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) |
#define | SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk |
#define | SDMMC_RESP4_CARDSTATUS4_Pos (0U) |
#define | SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) |
#define | SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk |
#define | SDMMC_DTIMER_DATATIME_Pos (0U) |
#define | SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) |
#define | SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk |
#define | SDMMC_DLEN_DATALENGTH_Pos (0U) |
#define | SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) |
#define | SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk |
#define | SDMMC_DCTRL_DTEN_Pos (0U) |
#define | SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) |
#define | SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk |
#define | SDMMC_DCTRL_DTDIR_Pos (1U) |
#define | SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) |
#define | SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk |
#define | SDMMC_DCTRL_DTMODE_Pos (2U) |
#define | SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) |
#define | SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk |
#define | SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) |
#define | SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) |
#define | SDMMC_DCTRL_DBLOCKSIZE_Pos (4U) |
#define | SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
#define | SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk |
#define | SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
#define | SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
#define | SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
#define | SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
#define | SDMMC_DCTRL_RWSTART_Pos (8U) |
#define | SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) |
#define | SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk |
#define | SDMMC_DCTRL_RWSTOP_Pos (9U) |
#define | SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) |
#define | SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk |
#define | SDMMC_DCTRL_RWMOD_Pos (10U) |
#define | SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) |
#define | SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk |
#define | SDMMC_DCTRL_SDIOEN_Pos (11U) |
#define | SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) |
#define | SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk |
#define | SDMMC_DCTRL_BOOTACKEN_Pos (12U) |
#define | SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) |
#define | SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk |
#define | SDMMC_DCTRL_FIFORST_Pos (13U) |
#define | SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) |
#define | SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk |
#define | SDMMC_DCOUNT_DATACOUNT_Pos (0U) |
#define | SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) |
#define | SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk |
#define | SDMMC_STA_CCRCFAIL_Pos (0U) |
#define | SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) |
#define | SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk |
#define | SDMMC_STA_DCRCFAIL_Pos (1U) |
#define | SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) |
#define | SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk |
#define | SDMMC_STA_CTIMEOUT_Pos (2U) |
#define | SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) |
#define | SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk |
#define | SDMMC_STA_DTIMEOUT_Pos (3U) |
#define | SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) |
#define | SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk |
#define | SDMMC_STA_TXUNDERR_Pos (4U) |
#define | SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) |
#define | SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk |
#define | SDMMC_STA_RXOVERR_Pos (5U) |
#define | SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) |
#define | SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk |
#define | SDMMC_STA_CMDREND_Pos (6U) |
#define | SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) |
#define | SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk |
#define | SDMMC_STA_CMDSENT_Pos (7U) |
#define | SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) |
#define | SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk |
#define | SDMMC_STA_DATAEND_Pos (8U) |
#define | SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) |
#define | SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk |
#define | SDMMC_STA_DHOLD_Pos (9U) |
#define | SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) |
#define | SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk |
#define | SDMMC_STA_DBCKEND_Pos (10U) |
#define | SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) |
#define | SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk |
#define | SDMMC_STA_DABORT_Pos (11U) |
#define | SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) |
#define | SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk |
#define | SDMMC_STA_DPSMACT_Pos (12U) |
#define | SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) |
#define | SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk |
#define | SDMMC_STA_CPSMACT_Pos (13U) |
#define | SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) |
#define | SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk |
#define | SDMMC_STA_TXFIFOHE_Pos (14U) |
#define | SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) |
#define | SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk |
#define | SDMMC_STA_RXFIFOHF_Pos (15U) |
#define | SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) |
#define | SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk |
#define | SDMMC_STA_TXFIFOF_Pos (16U) |
#define | SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) |
#define | SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk |
#define | SDMMC_STA_RXFIFOF_Pos (17U) |
#define | SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) |
#define | SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk |
#define | SDMMC_STA_TXFIFOE_Pos (18U) |
#define | SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) |
#define | SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk |
#define | SDMMC_STA_RXFIFOE_Pos (19U) |
#define | SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) |
#define | SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk |
#define | SDMMC_STA_BUSYD0_Pos (20U) |
#define | SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) |
#define | SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk |
#define | SDMMC_STA_BUSYD0END_Pos (21U) |
#define | SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) |
#define | SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk |
#define | SDMMC_STA_SDIOIT_Pos (22U) |
#define | SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) |
#define | SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk |
#define | SDMMC_STA_ACKFAIL_Pos (23U) |
#define | SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) |
#define | SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk |
#define | SDMMC_STA_ACKTIMEOUT_Pos (24U) |
#define | SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) |
#define | SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk |
#define | SDMMC_STA_VSWEND_Pos (25U) |
#define | SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) |
#define | SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk |
#define | SDMMC_STA_CKSTOP_Pos (26U) |
#define | SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) |
#define | SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk |
#define | SDMMC_STA_IDMATE_Pos (27U) |
#define | SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) |
#define | SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk |
#define | SDMMC_STA_IDMABTC_Pos (28U) |
#define | SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) |
#define | SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk |
#define | SDMMC_ICR_CCRCFAILC_Pos (0U) |
#define | SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) |
#define | SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk |
#define | SDMMC_ICR_DCRCFAILC_Pos (1U) |
#define | SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) |
#define | SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk |
#define | SDMMC_ICR_CTIMEOUTC_Pos (2U) |
#define | SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) |
#define | SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk |
#define | SDMMC_ICR_DTIMEOUTC_Pos (3U) |
#define | SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) |
#define | SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk |
#define | SDMMC_ICR_TXUNDERRC_Pos (4U) |
#define | SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) |
#define | SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk |
#define | SDMMC_ICR_RXOVERRC_Pos (5U) |
#define | SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) |
#define | SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk |
#define | SDMMC_ICR_CMDRENDC_Pos (6U) |
#define | SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) |
#define | SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk |
#define | SDMMC_ICR_CMDSENTC_Pos (7U) |
#define | SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) |
#define | SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk |
#define | SDMMC_ICR_DATAENDC_Pos (8U) |
#define | SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) |
#define | SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk |
#define | SDMMC_ICR_DHOLDC_Pos (9U) |
#define | SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) |
#define | SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk |
#define | SDMMC_ICR_DBCKENDC_Pos (10U) |
#define | SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) |
#define | SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk |
#define | SDMMC_ICR_DABORTC_Pos (11U) |
#define | SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) |
#define | SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk |
#define | SDMMC_ICR_BUSYD0ENDC_Pos (21U) |
#define | SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) |
#define | SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk |
#define | SDMMC_ICR_SDIOITC_Pos (22U) |
#define | SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) |
#define | SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk |
#define | SDMMC_ICR_ACKFAILC_Pos (23U) |
#define | SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) |
#define | SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk |
#define | SDMMC_ICR_ACKTIMEOUTC_Pos (24U) |
#define | SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) |
#define | SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk |
#define | SDMMC_ICR_VSWENDC_Pos (25U) |
#define | SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) |
#define | SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk |
#define | SDMMC_ICR_CKSTOPC_Pos (26U) |
#define | SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) |
#define | SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk |
#define | SDMMC_ICR_IDMATEC_Pos (27U) |
#define | SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) |
#define | SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk |
#define | SDMMC_ICR_IDMABTCC_Pos (28U) |
#define | SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) |
#define | SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk |
#define | SDMMC_MASK_CCRCFAILIE_Pos (0U) |
#define | SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) |
#define | SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk |
#define | SDMMC_MASK_DCRCFAILIE_Pos (1U) |
#define | SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) |
#define | SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk |
#define | SDMMC_MASK_CTIMEOUTIE_Pos (2U) |
#define | SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) |
#define | SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk |
#define | SDMMC_MASK_DTIMEOUTIE_Pos (3U) |
#define | SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) |
#define | SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk |
#define | SDMMC_MASK_TXUNDERRIE_Pos (4U) |
#define | SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) |
#define | SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk |
#define | SDMMC_MASK_RXOVERRIE_Pos (5U) |
#define | SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) |
#define | SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk |
#define | SDMMC_MASK_CMDRENDIE_Pos (6U) |
#define | SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) |
#define | SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk |
#define | SDMMC_MASK_CMDSENTIE_Pos (7U) |
#define | SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) |
#define | SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk |
#define | SDMMC_MASK_DATAENDIE_Pos (8U) |
#define | SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) |
#define | SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk |
#define | SDMMC_MASK_DHOLDIE_Pos (9U) |
#define | SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) |
#define | SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk |
#define | SDMMC_MASK_DBCKENDIE_Pos (10U) |
#define | SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) |
#define | SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk |
#define | SDMMC_MASK_DABORTIE_Pos (11U) |
#define | SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) |
#define | SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk |
#define | SDMMC_MASK_TXFIFOHEIE_Pos (14U) |
#define | SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) |
#define | SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk |
#define | SDMMC_MASK_RXFIFOHFIE_Pos (15U) |
#define | SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) |
#define | SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk |
#define | SDMMC_MASK_RXFIFOFIE_Pos (17U) |
#define | SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) |
#define | SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk |
#define | SDMMC_MASK_TXFIFOEIE_Pos (18U) |
#define | SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) |
#define | SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk |
#define | SDMMC_MASK_BUSYD0ENDIE_Pos (21U) |
#define | SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) |
#define | SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk |
#define | SDMMC_MASK_SDIOITIE_Pos (22U) |
#define | SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) |
#define | SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk |
#define | SDMMC_MASK_ACKFAILIE_Pos (23U) |
#define | SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) |
#define | SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk |
#define | SDMMC_MASK_ACKTIMEOUTIE_Pos (24U) |
#define | SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) |
#define | SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk |
#define | SDMMC_MASK_VSWENDIE_Pos (25U) |
#define | SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) |
#define | SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk |
#define | SDMMC_MASK_CKSTOPIE_Pos (26U) |
#define | SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) |
#define | SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk |
#define | SDMMC_MASK_IDMABTCIE_Pos (28U) |
#define | SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) |
#define | SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk |
#define | SDMMC_ACKTIME_ACKTIME_Pos (0U) |
#define | SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) |
#define | SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk |
#define | SDMMC_FIFO_FIFODATA_Pos (0U) |
#define | SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) |
#define | SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk |
#define | SDMMC_IDMA_IDMAEN_Pos (0U) |
#define | SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) |
#define | SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk |
#define | SDMMC_IDMA_IDMABMODE_Pos (1U) |
#define | SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) |
#define | SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk |
#define | SDMMC_IDMA_IDMABACT_Pos (2U) |
#define | SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) |
#define | SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk |
#define | SDMMC_IDMABSIZE_IDMABNDT_Pos (5U) |
#define | SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) |
#define | SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk |
#define | SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) |
#define | SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) |
#define | DLYB_CR_DEN_Pos (0U) |
#define | DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) |
#define | DLYB_CR_DEN DLYB_CR_DEN_Msk |
#define | DLYB_CR_SEN_Pos (1U) |
#define | DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) |
#define | DLYB_CR_SEN DLYB_CR_SEN_Msk |
#define | DLYB_CFGR_SEL_Pos (0U) |
#define | DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) |
#define | DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk |
#define | DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) |
#define | DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) |
#define | DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) |
#define | DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) |
#define | DLYB_CFGR_UNIT_Pos (8U) |
#define | DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk |
#define | DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) |
#define | DLYB_CFGR_LNG_Pos (16U) |
#define | DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk |
#define | DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) |
#define | DLYB_CFGR_LNGF_Pos (31U) |
#define | DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) |
#define | DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk |
#define | SPI_CR1_SPE_Pos (0U) |
#define | SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) |
#define | SPI_CR1_SPE SPI_CR1_SPE_Msk |
#define | SPI_CR1_MASRX_Pos (8U) |
#define | SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) |
#define | SPI_CR1_MASRX SPI_CR1_MASRX_Msk |
#define | SPI_CR1_CSTART_Pos (9U) |
#define | SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) |
#define | SPI_CR1_CSTART SPI_CR1_CSTART_Msk |
#define | SPI_CR1_CSUSP_Pos (10U) |
#define | SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) |
#define | SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk |
#define | SPI_CR1_HDDIR_Pos (11U) |
#define | SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) |
#define | SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk |
#define | SPI_CR1_SSI_Pos (12U) |
#define | SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) |
#define | SPI_CR1_SSI SPI_CR1_SSI_Msk |
#define | SPI_CR1_CRC33_17_Pos (13U) |
#define | SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) |
#define | SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk |
#define | SPI_CR1_RCRCINI_Pos (14U) |
#define | SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) |
#define | SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk |
#define | SPI_CR1_TCRCINI_Pos (15U) |
#define | SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) |
#define | SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk |
#define | SPI_CR1_IOLOCK_Pos (16U) |
#define | SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) |
#define | SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk |
#define | SPI_CR2_TSER_Pos (16U) |
#define | SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) |
#define | SPI_CR2_TSER SPI_CR2_TSER_Msk |
#define | SPI_CR2_TSIZE_Pos (0U) |
#define | SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) |
#define | SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk |
#define | SPI_CFG1_DSIZE_Pos (0U) |
#define | SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) |
#define | SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk |
#define | SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) |
#define | SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) |
#define | SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) |
#define | SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) |
#define | SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) |
#define | SPI_CFG1_FTHLV_Pos (5U) |
#define | SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) |
#define | SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk |
#define | SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) |
#define | SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) |
#define | SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) |
#define | SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) |
#define | SPI_CFG1_UDRCFG_Pos (9U) |
#define | SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) |
#define | SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk |
#define | SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) |
#define | SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) |
#define | SPI_CFG1_UDRDET_Pos (11U) |
#define | SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) |
#define | SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk |
#define | SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) |
#define | SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) |
#define | SPI_CFG1_RXDMAEN_Pos (14U) |
#define | SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) |
#define | SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk |
#define | SPI_CFG1_TXDMAEN_Pos (15U) |
#define | SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) |
#define | SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk |
#define | SPI_CFG1_CRCSIZE_Pos (16U) |
#define | SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) |
#define | SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk |
#define | SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) |
#define | SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) |
#define | SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) |
#define | SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) |
#define | SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) |
#define | SPI_CFG1_CRCEN_Pos (22U) |
#define | SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) |
#define | SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk |
#define | SPI_CFG1_MBR_Pos (28U) |
#define | SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) |
#define | SPI_CFG1_MBR SPI_CFG1_MBR_Msk |
#define | SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) |
#define | SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) |
#define | SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) |
#define | SPI_CFG2_MSSI_Pos (0U) |
#define | SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) |
#define | SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk |
#define | SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) |
#define | SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) |
#define | SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) |
#define | SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) |
#define | SPI_CFG2_MIDI_Pos (4U) |
#define | SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) |
#define | SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk |
#define | SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) |
#define | SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) |
#define | SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) |
#define | SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) |
#define | SPI_CFG2_IOSWP_Pos (15U) |
#define | SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) |
#define | SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk |
#define | SPI_CFG2_COMM_Pos (17U) |
#define | SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) |
#define | SPI_CFG2_COMM SPI_CFG2_COMM_Msk |
#define | SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) |
#define | SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) |
#define | SPI_CFG2_SP_Pos (19U) |
#define | SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) |
#define | SPI_CFG2_SP SPI_CFG2_SP_Msk |
#define | SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) |
#define | SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) |
#define | SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) |
#define | SPI_CFG2_MASTER_Pos (22U) |
#define | SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) |
#define | SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk |
#define | SPI_CFG2_LSBFRST_Pos (23U) |
#define | SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) |
#define | SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk |
#define | SPI_CFG2_CPHA_Pos (24U) |
#define | SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) |
#define | SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk |
#define | SPI_CFG2_CPOL_Pos (25U) |
#define | SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) |
#define | SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk |
#define | SPI_CFG2_SSM_Pos (26U) |
#define | SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) |
#define | SPI_CFG2_SSM SPI_CFG2_SSM_Msk |
#define | SPI_CFG2_SSIOP_Pos (28U) |
#define | SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) |
#define | SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk |
#define | SPI_CFG2_SSOE_Pos (29U) |
#define | SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) |
#define | SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk |
#define | SPI_CFG2_SSOM_Pos (30U) |
#define | SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) |
#define | SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk |
#define | SPI_CFG2_AFCNTR_Pos (31U) |
#define | SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) |
#define | SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk |
#define | SPI_IER_RXPIE_Pos (0U) |
#define | SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) |
#define | SPI_IER_RXPIE SPI_IER_RXPIE_Msk |
#define | SPI_IER_TXPIE_Pos (1U) |
#define | SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) |
#define | SPI_IER_TXPIE SPI_IER_TXPIE_Msk |
#define | SPI_IER_DXPIE_Pos (2U) |
#define | SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) |
#define | SPI_IER_DXPIE SPI_IER_DXPIE_Msk |
#define | SPI_IER_EOTIE_Pos (3U) |
#define | SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) |
#define | SPI_IER_EOTIE SPI_IER_EOTIE_Msk |
#define | SPI_IER_TXTFIE_Pos (4U) |
#define | SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) |
#define | SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk |
#define | SPI_IER_UDRIE_Pos (5U) |
#define | SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) |
#define | SPI_IER_UDRIE SPI_IER_UDRIE_Msk |
#define | SPI_IER_OVRIE_Pos (6U) |
#define | SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) |
#define | SPI_IER_OVRIE SPI_IER_OVRIE_Msk |
#define | SPI_IER_CRCEIE_Pos (7U) |
#define | SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) |
#define | SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk |
#define | SPI_IER_TIFREIE_Pos (8U) |
#define | SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) |
#define | SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk |
#define | SPI_IER_MODFIE_Pos (9U) |
#define | SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) |
#define | SPI_IER_MODFIE SPI_IER_MODFIE_Msk |
#define | SPI_IER_TSERFIE_Pos (10U) |
#define | SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) |
#define | SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk |
#define | SPI_SR_RXP_Pos (0U) |
#define | SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) |
#define | SPI_SR_RXP SPI_SR_RXP_Msk |
#define | SPI_SR_TXP_Pos (1U) |
#define | SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) |
#define | SPI_SR_TXP SPI_SR_TXP_Msk |
#define | SPI_SR_DXP_Pos (2U) |
#define | SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) |
#define | SPI_SR_DXP SPI_SR_DXP_Msk |
#define | SPI_SR_EOT_Pos (3U) |
#define | SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) |
#define | SPI_SR_EOT SPI_SR_EOT_Msk |
#define | SPI_SR_TXTF_Pos (4U) |
#define | SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) |
#define | SPI_SR_TXTF SPI_SR_TXTF_Msk |
#define | SPI_SR_UDR_Pos (5U) |
#define | SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) |
#define | SPI_SR_UDR SPI_SR_UDR_Msk |
#define | SPI_SR_OVR_Pos (6U) |
#define | SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) |
#define | SPI_SR_OVR SPI_SR_OVR_Msk |
#define | SPI_SR_CRCE_Pos (7U) |
#define | SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) |
#define | SPI_SR_CRCE SPI_SR_CRCE_Msk |
#define | SPI_SR_TIFRE_Pos (8U) |
#define | SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) |
#define | SPI_SR_TIFRE SPI_SR_TIFRE_Msk |
#define | SPI_SR_MODF_Pos (9U) |
#define | SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) |
#define | SPI_SR_MODF SPI_SR_MODF_Msk |
#define | SPI_SR_TSERF_Pos (10U) |
#define | SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) |
#define | SPI_SR_TSERF SPI_SR_TSERF_Msk |
#define | SPI_SR_SUSP_Pos (11U) |
#define | SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) |
#define | SPI_SR_SUSP SPI_SR_SUSP_Msk |
#define | SPI_SR_TXC_Pos (12U) |
#define | SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) |
#define | SPI_SR_TXC SPI_SR_TXC_Msk |
#define | SPI_SR_RXPLVL_Pos (13U) |
#define | SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) |
#define | SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk |
#define | SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) |
#define | SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) |
#define | SPI_SR_RXWNE_Pos (15U) |
#define | SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) |
#define | SPI_SR_RXWNE SPI_SR_RXWNE_Msk |
#define | SPI_SR_CTSIZE_Pos (16U) |
#define | SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) |
#define | SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk |
#define | SPI_IFCR_EOTC_Pos (3U) |
#define | SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) |
#define | SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk |
#define | SPI_IFCR_TXTFC_Pos (4U) |
#define | SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) |
#define | SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk |
#define | SPI_IFCR_UDRC_Pos (5U) |
#define | SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) |
#define | SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk |
#define | SPI_IFCR_OVRC_Pos (6U) |
#define | SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) |
#define | SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk |
#define | SPI_IFCR_CRCEC_Pos (7U) |
#define | SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) |
#define | SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk |
#define | SPI_IFCR_TIFREC_Pos (8U) |
#define | SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) |
#define | SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk |
#define | SPI_IFCR_MODFC_Pos (9U) |
#define | SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) |
#define | SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk |
#define | SPI_IFCR_TSERFC_Pos (10U) |
#define | SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) |
#define | SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk |
#define | SPI_IFCR_SUSPC_Pos (11U) |
#define | SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) |
#define | SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk |
#define | SPI_TXDR_TXDR_Pos (0U) |
#define | SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) |
#define | SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */ |
#define | SPI_RXDR_RXDR_Pos (0U) |
#define | SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) |
#define | SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */ |
#define | SPI_CRCPOLY_CRCPOLY_Pos (0U) |
#define | SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) |
#define | SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */ |
#define | SPI_TXCRC_TXCRC_Pos (0U) |
#define | SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) |
#define | SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */ |
#define | SPI_RXCRC_RXCRC_Pos (0U) |
#define | SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) |
#define | SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */ |
#define | SPI_UDRDR_UDRDR_Pos (0U) |
#define | SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) |
#define | SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */ |
#define | SPI_I2SCFGR_I2SMOD_Pos (0U) |
#define | SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) |
#define | SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk |
#define | SPI_I2SCFGR_I2SCFG_Pos (1U) |
#define | SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) |
#define | SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk |
#define | SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) |
#define | SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) |
#define | SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) |
#define | SPI_I2SCFGR_I2SSTD_Pos (4U) |
#define | SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) |
#define | SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk |
#define | SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) |
#define | SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) |
#define | SPI_I2SCFGR_PCMSYNC_Pos (7U) |
#define | SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) |
#define | SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk |
#define | SPI_I2SCFGR_DATLEN_Pos (8U) |
#define | SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) |
#define | SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk |
#define | SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) |
#define | SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) |
#define | SPI_I2SCFGR_CHLEN_Pos (10U) |
#define | SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) |
#define | SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk |
#define | SPI_I2SCFGR_CKPOL_Pos (11U) |
#define | SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) |
#define | SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk |
#define | SPI_I2SCFGR_FIXCH_Pos (12U) |
#define | SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) |
#define | SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk |
#define | SPI_I2SCFGR_WSINV_Pos (13U) |
#define | SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) |
#define | SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk |
#define | SPI_I2SCFGR_DATFMT_Pos (14U) |
#define | SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) |
#define | SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk |
#define | SPI_I2SCFGR_I2SDIV_Pos (16U) |
#define | SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) |
#define | SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk |
#define | SPI_I2SCFGR_ODD_Pos (24U) |
#define | SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) |
#define | SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk |
#define | SPI_I2SCFGR_MCKOE_Pos (25U) |
#define | SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) |
#define | SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk |
#define | QUADSPI_CR_EN_Pos (0U) |
#define | QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) |
#define | QUADSPI_CR_EN QUADSPI_CR_EN_Msk |
#define | QUADSPI_CR_ABORT_Pos (1U) |
#define | QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) |
#define | QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk |
#define | QUADSPI_CR_DMAEN_Pos (2U) |
#define | QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) |
#define | QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk |
#define | QUADSPI_CR_TCEN_Pos (3U) |
#define | QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) |
#define | QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk |
#define | QUADSPI_CR_SSHIFT_Pos (4U) |
#define | QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) |
#define | QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk |
#define | QUADSPI_CR_DFM_Pos (6U) |
#define | QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) |
#define | QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk |
#define | QUADSPI_CR_FSEL_Pos (7U) |
#define | QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) |
#define | QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk |
#define | QUADSPI_CR_FTHRES_Pos (8U) |
#define | QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) |
#define | QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk |
#define | QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) |
#define | QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) |
#define | QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) |
#define | QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) |
#define | QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) |
#define | QUADSPI_CR_TEIE_Pos (16U) |
#define | QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) |
#define | QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk |
#define | QUADSPI_CR_TCIE_Pos (17U) |
#define | QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) |
#define | QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk |
#define | QUADSPI_CR_FTIE_Pos (18U) |
#define | QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) |
#define | QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk |
#define | QUADSPI_CR_SMIE_Pos (19U) |
#define | QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) |
#define | QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk |
#define | QUADSPI_CR_TOIE_Pos (20U) |
#define | QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) |
#define | QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk |
#define | QUADSPI_CR_APMS_Pos (22U) |
#define | QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) |
#define | QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk |
#define | QUADSPI_CR_PMM_Pos (23U) |
#define | QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) |
#define | QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk |
#define | QUADSPI_CR_PRESCALER_Pos (24U) |
#define | QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk |
#define | QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) |
#define | QUADSPI_DCR_CKMODE_Pos (0U) |
#define | QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) |
#define | QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk |
#define | QUADSPI_DCR_CSHT_Pos (8U) |
#define | QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) |
#define | QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk |
#define | QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) |
#define | QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) |
#define | QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) |
#define | QUADSPI_DCR_FSIZE_Pos (16U) |
#define | QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) |
#define | QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk |
#define | QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) |
#define | QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) |
#define | QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) |
#define | QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) |
#define | QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) |
#define | QUADSPI_SR_TEF_Pos (0U) |
#define | QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) |
#define | QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk |
#define | QUADSPI_SR_TCF_Pos (1U) |
#define | QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) |
#define | QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk |
#define | QUADSPI_SR_FTF_Pos (2U) |
#define | QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) |
#define | QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk |
#define | QUADSPI_SR_SMF_Pos (3U) |
#define | QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) |
#define | QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk |
#define | QUADSPI_SR_TOF_Pos (4U) |
#define | QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) |
#define | QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk |
#define | QUADSPI_SR_BUSY_Pos (5U) |
#define | QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) |
#define | QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk |
#define | QUADSPI_SR_FLEVEL_Pos (8U) |
#define | QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk |
#define | QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) |
#define | QUADSPI_FCR_CTEF_Pos (0U) |
#define | QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) |
#define | QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk |
#define | QUADSPI_FCR_CTCF_Pos (1U) |
#define | QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) |
#define | QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk |
#define | QUADSPI_FCR_CSMF_Pos (3U) |
#define | QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) |
#define | QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk |
#define | QUADSPI_FCR_CTOF_Pos (4U) |
#define | QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) |
#define | QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk |
#define | QUADSPI_DLR_DL_Pos (0U) |
#define | QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) |
#define | QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk |
#define | QUADSPI_CCR_INSTRUCTION_Pos (0U) |
#define | QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk |
#define | QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) |
#define | QUADSPI_CCR_IMODE_Pos (8U) |
#define | QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) |
#define | QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk |
#define | QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) |
#define | QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) |
#define | QUADSPI_CCR_ADMODE_Pos (10U) |
#define | QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) |
#define | QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk |
#define | QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) |
#define | QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) |
#define | QUADSPI_CCR_ADSIZE_Pos (12U) |
#define | QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) |
#define | QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk |
#define | QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) |
#define | QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) |
#define | QUADSPI_CCR_ABMODE_Pos (14U) |
#define | QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) |
#define | QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk |
#define | QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) |
#define | QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) |
#define | QUADSPI_CCR_ABSIZE_Pos (16U) |
#define | QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) |
#define | QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk |
#define | QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) |
#define | QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) |
#define | QUADSPI_CCR_DCYC_Pos (18U) |
#define | QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) |
#define | QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk |
#define | QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) |
#define | QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) |
#define | QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) |
#define | QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) |
#define | QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) |
#define | QUADSPI_CCR_DMODE_Pos (24U) |
#define | QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) |
#define | QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk |
#define | QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) |
#define | QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) |
#define | QUADSPI_CCR_FMODE_Pos (26U) |
#define | QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) |
#define | QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk |
#define | QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) |
#define | QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) |
#define | QUADSPI_CCR_SIOO_Pos (28U) |
#define | QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) |
#define | QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk |
#define | QUADSPI_CCR_DHHC_Pos (30U) |
#define | QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) |
#define | QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk |
#define | QUADSPI_CCR_DDRM_Pos (31U) |
#define | QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) |
#define | QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk |
#define | QUADSPI_AR_ADDRESS_Pos (0U) |
#define | QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) |
#define | QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk |
#define | QUADSPI_ABR_ALTERNATE_Pos (0U) |
#define | QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) |
#define | QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk |
#define | QUADSPI_DR_DATA_Pos (0U) |
#define | QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) |
#define | QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk |
#define | QUADSPI_PSMKR_MASK_Pos (0U) |
#define | QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) |
#define | QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk |
#define | QUADSPI_PSMAR_MATCH_Pos (0U) |
#define | QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) |
#define | QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk |
#define | QUADSPI_PIR_INTERVAL_Pos (0U) |
#define | QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) |
#define | QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk |
#define | QUADSPI_LPTR_TIMEOUT_Pos (0U) |
#define | QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) |
#define | QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk |
#define | SYSCFG_PMCR_I2C1_FMP_Pos (0U) |
#define | SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) |
#define | SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk |
#define | SYSCFG_PMCR_I2C2_FMP_Pos (1U) |
#define | SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) |
#define | SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk |
#define | SYSCFG_PMCR_I2C3_FMP_Pos (2U) |
#define | SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) |
#define | SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk |
#define | SYSCFG_PMCR_I2C4_FMP_Pos (3U) |
#define | SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) |
#define | SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk |
#define | SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U) |
#define | SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) |
#define | SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk |
#define | SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U) |
#define | SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) |
#define | SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk |
#define | SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U) |
#define | SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) |
#define | SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk |
#define | SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U) |
#define | SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) |
#define | SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk |
#define | SYSCFG_PMCR_BOOSTEN_Pos (8U) |
#define | SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) |
#define | SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk |
#define | SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U) |
#define | SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) |
#define | SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk |
#define | SYSCFG_PMCR_EPIS_SEL_Pos (21U) |
#define | SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) |
#define | SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk |
#define | SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) |
#define | SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) |
#define | SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) |
#define | SYSCFG_PMCR_PA0SO_Pos (24U) |
#define | SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) |
#define | SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk |
#define | SYSCFG_PMCR_PA1SO_Pos (25U) |
#define | SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) |
#define | SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk |
#define | SYSCFG_PMCR_PC2SO_Pos (26U) |
#define | SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) |
#define | SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk |
#define | SYSCFG_PMCR_PC3SO_Pos (27U) |
#define | SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) |
#define | SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk |
#define | SYSCFG_EXTICR1_EXTI0_Pos (0U) |
#define | SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) |
#define | SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk |
#define | SYSCFG_EXTICR1_EXTI1_Pos (4U) |
#define | SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) |
#define | SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk |
#define | SYSCFG_EXTICR1_EXTI2_Pos (8U) |
#define | SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) |
#define | SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk |
#define | SYSCFG_EXTICR1_EXTI3_Pos (12U) |
#define | SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) |
#define | SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk |
#define | SYSCFG_EXTICR1_EXTI0_PA (0U) |
EXTI0 configuration. | |
#define | SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) |
#define | SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) |
#define | SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) |
#define | SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) |
#define | SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) |
#define | SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) |
#define | SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) |
#define | SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) |
#define | SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) |
#define | SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) |
#define | SYSCFG_EXTICR1_EXTI1_PA (0U) |
EXTI1 configuration. | |
#define | SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) |
#define | SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) |
#define | SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) |
#define | SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) |
#define | SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) |
#define | SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) |
#define | SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) |
#define | SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) |
#define | SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) |
#define | SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) |
#define | SYSCFG_EXTICR1_EXTI2_PA (0U) |
EXTI2 configuration. | |
#define | SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) |
#define | SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) |
#define | SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) |
#define | SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) |
#define | SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) |
#define | SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) |
#define | SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) |
#define | SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) |
#define | SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) |
#define | SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) |
#define | SYSCFG_EXTICR1_EXTI3_PA (0U) |
EXTI3 configuration. | |
#define | SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) |
#define | SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) |
#define | SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) |
#define | SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) |
#define | SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) |
#define | SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) |
#define | SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) |
#define | SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) |
#define | SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) |
#define | SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) |
#define | SYSCFG_EXTICR2_EXTI4_Pos (0U) |
#define | SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) |
#define | SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk |
#define | SYSCFG_EXTICR2_EXTI5_Pos (4U) |
#define | SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) |
#define | SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk |
#define | SYSCFG_EXTICR2_EXTI6_Pos (8U) |
#define | SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) |
#define | SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk |
#define | SYSCFG_EXTICR2_EXTI7_Pos (12U) |
#define | SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) |
#define | SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk |
#define | SYSCFG_EXTICR2_EXTI4_PA (0U) |
EXTI4 configuration. | |
#define | SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) |
#define | SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) |
#define | SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) |
#define | SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) |
#define | SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) |
#define | SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) |
#define | SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) |
#define | SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) |
#define | SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) |
#define | SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) |
#define | SYSCFG_EXTICR2_EXTI5_PA (0U) |
EXTI5 configuration. | |
#define | SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) |
#define | SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) |
#define | SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) |
#define | SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) |
#define | SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) |
#define | SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) |
#define | SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) |
#define | SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) |
#define | SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) |
#define | SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) |
#define | SYSCFG_EXTICR2_EXTI6_PA (0U) |
EXTI6 configuration. | |
#define | SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) |
#define | SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) |
#define | SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) |
#define | SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) |
#define | SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) |
#define | SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) |
#define | SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) |
#define | SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) |
#define | SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) |
#define | SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) |
#define | SYSCFG_EXTICR2_EXTI7_PA (0U) |
EXTI7 configuration. | |
#define | SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) |
#define | SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) |
#define | SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) |
#define | SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) |
#define | SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) |
#define | SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) |
#define | SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) |
#define | SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) |
#define | SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) |
#define | SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) |
#define | SYSCFG_EXTICR3_EXTI8_Pos (0U) |
#define | SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) |
#define | SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk |
#define | SYSCFG_EXTICR3_EXTI9_Pos (4U) |
#define | SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) |
#define | SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk |
#define | SYSCFG_EXTICR3_EXTI10_Pos (8U) |
#define | SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) |
#define | SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk |
#define | SYSCFG_EXTICR3_EXTI11_Pos (12U) |
#define | SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) |
#define | SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk |
#define | SYSCFG_EXTICR3_EXTI8_PA (0U) |
EXTI8 configuration. | |
#define | SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) |
#define | SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) |
#define | SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) |
#define | SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) |
#define | SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) |
#define | SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) |
#define | SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) |
#define | SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) |
#define | SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) |
#define | SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) |
#define | SYSCFG_EXTICR3_EXTI9_PA (0U) |
EXTI9 configuration. | |
#define | SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) |
#define | SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) |
#define | SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) |
#define | SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) |
#define | SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) |
#define | SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) |
#define | SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) |
#define | SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) |
#define | SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) |
#define | SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) |
#define | SYSCFG_EXTICR3_EXTI10_PA (0U) |
EXTI10 configuration. | |
#define | SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) |
#define | SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) |
#define | SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) |
#define | SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) |
#define | SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) |
#define | SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) |
#define | SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) |
#define | SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) |
#define | SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) |
#define | SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) |
#define | SYSCFG_EXTICR3_EXTI11_PA (0U) |
EXTI11 configuration. | |
#define | SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) |
#define | SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) |
#define | SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) |
#define | SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) |
#define | SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) |
#define | SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) |
#define | SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) |
#define | SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) |
#define | SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) |
#define | SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) |
#define | SYSCFG_EXTICR4_EXTI12_Pos (0U) |
#define | SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) |
#define | SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk |
#define | SYSCFG_EXTICR4_EXTI13_Pos (4U) |
#define | SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) |
#define | SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk |
#define | SYSCFG_EXTICR4_EXTI14_Pos (8U) |
#define | SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) |
#define | SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk |
#define | SYSCFG_EXTICR4_EXTI15_Pos (12U) |
#define | SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) |
#define | SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk |
#define | SYSCFG_EXTICR4_EXTI12_PA (0U) |
EXTI12 configuration. | |
#define | SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) |
#define | SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) |
#define | SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) |
#define | SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) |
#define | SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) |
#define | SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) |
#define | SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) |
#define | SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) |
#define | SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) |
#define | SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) |
#define | SYSCFG_EXTICR4_EXTI13_PA (0U) |
EXTI13 configuration. | |
#define | SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) |
#define | SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) |
#define | SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) |
#define | SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) |
#define | SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) |
#define | SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) |
#define | SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) |
#define | SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) |
#define | SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) |
#define | SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) |
#define | SYSCFG_EXTICR4_EXTI14_PA (0U) |
EXTI14 configuration. | |
#define | SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) |
#define | SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) |
#define | SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) |
#define | SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) |
#define | SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) |
#define | SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) |
#define | SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) |
#define | SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) |
#define | SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) |
#define | SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) |
#define | SYSCFG_EXTICR4_EXTI15_PA (0U) |
EXTI15 configuration. | |
#define | SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) |
#define | SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) |
#define | SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) |
#define | SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) |
#define | SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) |
#define | SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) |
#define | SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) |
#define | SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) |
#define | SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) |
#define | SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) |
#define | SYSCFG_CFGR_PVDL_Pos (2U) |
#define | SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) |
#define | SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk |
#define | SYSCFG_CFGR_FLASHL_Pos (3U) |
#define | SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) |
#define | SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk |
#define | SYSCFG_CFGR_CM7L_Pos (6U) |
#define | SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) |
#define | SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk |
#define | SYSCFG_CFGR_BKRAML_Pos (7U) |
#define | SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) |
#define | SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk |
#define | SYSCFG_CFGR_SRAM4L_Pos (9U) |
#define | SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) |
#define | SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk |
#define | SYSCFG_CFGR_SRAM3L_Pos (10U) |
#define | SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) |
#define | SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk |
#define | SYSCFG_CFGR_SRAM2L_Pos (11U) |
#define | SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) |
#define | SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk |
#define | SYSCFG_CFGR_SRAM1L_Pos (12U) |
#define | SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) |
#define | SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk |
#define | SYSCFG_CFGR_DTCML_Pos (13U) |
#define | SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) |
#define | SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk |
#define | SYSCFG_CFGR_ITCML_Pos (14U) |
#define | SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) |
#define | SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk |
#define | SYSCFG_CFGR_AXISRAML_Pos (15U) |
#define | SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) |
#define | SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk |
#define | SYSCFG_CCCSR_EN_Pos (0U) |
#define | SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) |
#define | SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk |
#define | SYSCFG_CCCSR_CS_Pos (1U) |
#define | SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) |
#define | SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk |
#define | SYSCFG_CCCSR_READY_Pos (8U) |
#define | SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) |
#define | SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk |
#define | SYSCFG_CCCSR_HSLV_Pos (16U) |
#define | SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) |
#define | SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk |
#define | SYSCFG_CCVR_NCV_Pos (0U) |
#define | SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) |
#define | SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk |
#define | SYSCFG_CCVR_PCV_Pos (4U) |
#define | SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) |
#define | SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk |
#define | SYSCFG_CCCR_NCC_Pos (0U) |
#define | SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) |
#define | SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk |
#define | SYSCFG_CCCR_PCC_Pos (4U) |
#define | SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) |
#define | SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk |
#define | SYSCFG_PWRCR_ODEN_Pos (0U) |
#define | SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) |
#define | SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk |
#define | SYSCFG_PKGR_PKG_Pos (0U) |
#define | SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) |
#define | SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk |
#define | SYSCFG_UR0_BKS_Pos (0U) |
#define | SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) |
#define | SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk |
#define | SYSCFG_UR0_RDP_Pos (16U) |
#define | SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) |
#define | SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk |
#define | SYSCFG_UR2_BORH_Pos (0U) |
#define | SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) |
#define | SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk |
#define | SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) |
#define | SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) |
#define | SYSCFG_UR2_BOOT_ADD0_Pos (16U) |
#define | SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) |
#define | SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk |
#define | SYSCFG_UR3_BOOT_ADD1_Pos (0U) |
#define | SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) |
#define | SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk |
#define | SYSCFG_UR4_MEPAD_BANK1_Pos (16U) |
#define | SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) |
#define | SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk |
#define | SYSCFG_UR5_MESAD_BANK1_Pos (0U) |
#define | SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) |
#define | SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk |
#define | SYSCFG_UR5_WRPN_BANK1_Pos (16U) |
#define | SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) |
#define | SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk |
#define | SYSCFG_UR6_PABEG_BANK1_Pos (0U) |
#define | SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) |
#define | SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk |
#define | SYSCFG_UR6_PAEND_BANK1_Pos (16U) |
#define | SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) |
#define | SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk |
#define | SYSCFG_UR7_SABEG_BANK1_Pos (0U) |
#define | SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) |
#define | SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk |
#define | SYSCFG_UR7_SAEND_BANK1_Pos (16U) |
#define | SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) |
#define | SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk |
#define | SYSCFG_UR8_MEPAD_BANK2_Pos (0U) |
#define | SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) |
#define | SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk |
#define | SYSCFG_UR8_MESAD_BANK2_Pos (16U) |
#define | SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) |
#define | SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk |
#define | SYSCFG_UR9_WRPN_BANK2_Pos (0U) |
#define | SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) |
#define | SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk |
#define | SYSCFG_UR9_PABEG_BANK2_Pos (16U) |
#define | SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) |
#define | SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk |
#define | SYSCFG_UR10_PAEND_BANK2_Pos (0U) |
#define | SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) |
#define | SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk |
#define | SYSCFG_UR10_SABEG_BANK2_Pos (16U) |
#define | SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) |
#define | SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk |
#define | SYSCFG_UR11_SAEND_BANK2_Pos (0U) |
#define | SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) |
#define | SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk |
#define | SYSCFG_UR11_IWDG1M_Pos (16U) |
#define | SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) |
#define | SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk |
#define | SYSCFG_UR12_SECURE_Pos (16U) |
#define | SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) |
#define | SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk |
#define | SYSCFG_UR13_SDRS_Pos (0U) |
#define | SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) |
#define | SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk |
#define | SYSCFG_UR13_D1SBRST_Pos (16U) |
#define | SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) |
#define | SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk |
#define | SYSCFG_UR14_D1STPRST_Pos (0U) |
#define | SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) |
#define | SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk |
#define | SYSCFG_UR15_FZIWDGSTB_Pos (16U) |
#define | SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) |
#define | SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk |
#define | SYSCFG_UR16_FZIWDGSTP_Pos (0U) |
#define | SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) |
#define | SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk |
#define | SYSCFG_UR16_PKP_Pos (16U) |
#define | SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) |
#define | SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk |
#define | SYSCFG_UR17_IOHSLV_Pos (0U) |
#define | SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) |
#define | SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk |
#define | TIM_BREAK_INPUT_SUPPORT |
#define | TIM_CR1_CEN_Pos (0U) |
#define | TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) |
#define | TIM_CR1_CEN TIM_CR1_CEN_Msk |
#define | TIM_CR1_UDIS_Pos (1U) |
#define | TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) |
#define | TIM_CR1_UDIS TIM_CR1_UDIS_Msk |
#define | TIM_CR1_URS_Pos (2U) |
#define | TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) |
#define | TIM_CR1_URS TIM_CR1_URS_Msk |
#define | TIM_CR1_OPM_Pos (3U) |
#define | TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) |
#define | TIM_CR1_OPM TIM_CR1_OPM_Msk |
#define | TIM_CR1_DIR_Pos (4U) |
#define | TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) |
#define | TIM_CR1_DIR TIM_CR1_DIR_Msk |
#define | TIM_CR1_CMS_Pos (5U) |
#define | TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) |
#define | TIM_CR1_CMS TIM_CR1_CMS_Msk |
#define | TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) |
#define | TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) |
#define | TIM_CR1_ARPE_Pos (7U) |
#define | TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) |
#define | TIM_CR1_ARPE TIM_CR1_ARPE_Msk |
#define | TIM_CR1_CKD_Pos (8U) |
#define | TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) |
#define | TIM_CR1_CKD TIM_CR1_CKD_Msk |
#define | TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) |
#define | TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) |
#define | TIM_CR1_UIFREMAP_Pos (11U) |
#define | TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) |
#define | TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk |
#define | TIM_CR2_CCPC_Pos (0U) |
#define | TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) |
#define | TIM_CR2_CCPC TIM_CR2_CCPC_Msk |
#define | TIM_CR2_CCUS_Pos (2U) |
#define | TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) |
#define | TIM_CR2_CCUS TIM_CR2_CCUS_Msk |
#define | TIM_CR2_CCDS_Pos (3U) |
#define | TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) |
#define | TIM_CR2_CCDS TIM_CR2_CCDS_Msk |
#define | TIM_CR2_MMS_Pos (4U) |
#define | TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) |
#define | TIM_CR2_MMS TIM_CR2_MMS_Msk |
#define | TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) |
#define | TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) |
#define | TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) |
#define | TIM_CR2_TI1S_Pos (7U) |
#define | TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) |
#define | TIM_CR2_TI1S TIM_CR2_TI1S_Msk |
#define | TIM_CR2_OIS1_Pos (8U) |
#define | TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) |
#define | TIM_CR2_OIS1 TIM_CR2_OIS1_Msk |
#define | TIM_CR2_OIS1N_Pos (9U) |
#define | TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) |
#define | TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk |
#define | TIM_CR2_OIS2_Pos (10U) |
#define | TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) |
#define | TIM_CR2_OIS2 TIM_CR2_OIS2_Msk |
#define | TIM_CR2_OIS2N_Pos (11U) |
#define | TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) |
#define | TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk |
#define | TIM_CR2_OIS3_Pos (12U) |
#define | TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) |
#define | TIM_CR2_OIS3 TIM_CR2_OIS3_Msk |
#define | TIM_CR2_OIS3N_Pos (13U) |
#define | TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) |
#define | TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk |
#define | TIM_CR2_OIS4_Pos (14U) |
#define | TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) |
#define | TIM_CR2_OIS4 TIM_CR2_OIS4_Msk |
#define | TIM_CR2_OIS5_Pos (16U) |
#define | TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) |
#define | TIM_CR2_OIS5 TIM_CR2_OIS5_Msk |
#define | TIM_CR2_OIS6_Pos (18U) |
#define | TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) |
#define | TIM_CR2_OIS6 TIM_CR2_OIS6_Msk |
#define | TIM_CR2_MMS2_Pos (20U) |
#define | TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) |
#define | TIM_CR2_MMS2 TIM_CR2_MMS2_Msk |
#define | TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) |
#define | TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) |
#define | TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) |
#define | TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) |
#define | TIM_SMCR_SMS_Pos (0U) |
#define | TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) |
#define | TIM_SMCR_SMS TIM_SMCR_SMS_Msk |
#define | TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) |
#define | TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) |
#define | TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) |
#define | TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) |
#define | TIM_SMCR_TS_Pos (4U) |
#define | TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) |
#define | TIM_SMCR_TS TIM_SMCR_TS_Msk |
#define | TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) |
#define | TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) |
#define | TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) |
#define | TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) |
#define | TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) |
#define | TIM_SMCR_MSM_Pos (7U) |
#define | TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) |
#define | TIM_SMCR_MSM TIM_SMCR_MSM_Msk |
#define | TIM_SMCR_ETF_Pos (8U) |
#define | TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) |
#define | TIM_SMCR_ETF TIM_SMCR_ETF_Msk |
#define | TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) |
#define | TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) |
#define | TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) |
#define | TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) |
#define | TIM_SMCR_ETPS_Pos (12U) |
#define | TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) |
#define | TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk |
#define | TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) |
#define | TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) |
#define | TIM_SMCR_ECE_Pos (14U) |
#define | TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) |
#define | TIM_SMCR_ECE TIM_SMCR_ECE_Msk |
#define | TIM_SMCR_ETP_Pos (15U) |
#define | TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) |
#define | TIM_SMCR_ETP TIM_SMCR_ETP_Msk |
#define | TIM_DIER_UIE_Pos (0U) |
#define | TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) |
#define | TIM_DIER_UIE TIM_DIER_UIE_Msk |
#define | TIM_DIER_CC1IE_Pos (1U) |
#define | TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) |
#define | TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk |
#define | TIM_DIER_CC2IE_Pos (2U) |
#define | TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) |
#define | TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk |
#define | TIM_DIER_CC3IE_Pos (3U) |
#define | TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) |
#define | TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk |
#define | TIM_DIER_CC4IE_Pos (4U) |
#define | TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) |
#define | TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk |
#define | TIM_DIER_COMIE_Pos (5U) |
#define | TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) |
#define | TIM_DIER_COMIE TIM_DIER_COMIE_Msk |
#define | TIM_DIER_TIE_Pos (6U) |
#define | TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) |
#define | TIM_DIER_TIE TIM_DIER_TIE_Msk |
#define | TIM_DIER_BIE_Pos (7U) |
#define | TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) |
#define | TIM_DIER_BIE TIM_DIER_BIE_Msk |
#define | TIM_DIER_UDE_Pos (8U) |
#define | TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) |
#define | TIM_DIER_UDE TIM_DIER_UDE_Msk |
#define | TIM_DIER_CC1DE_Pos (9U) |
#define | TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) |
#define | TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk |
#define | TIM_DIER_CC2DE_Pos (10U) |
#define | TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) |
#define | TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk |
#define | TIM_DIER_CC3DE_Pos (11U) |
#define | TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) |
#define | TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk |
#define | TIM_DIER_CC4DE_Pos (12U) |
#define | TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) |
#define | TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk |
#define | TIM_DIER_COMDE_Pos (13U) |
#define | TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) |
#define | TIM_DIER_COMDE TIM_DIER_COMDE_Msk |
#define | TIM_DIER_TDE_Pos (14U) |
#define | TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) |
#define | TIM_DIER_TDE TIM_DIER_TDE_Msk |
#define | TIM_SR_UIF_Pos (0U) |
#define | TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) |
#define | TIM_SR_UIF TIM_SR_UIF_Msk |
#define | TIM_SR_CC1IF_Pos (1U) |
#define | TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) |
#define | TIM_SR_CC1IF TIM_SR_CC1IF_Msk |
#define | TIM_SR_CC2IF_Pos (2U) |
#define | TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) |
#define | TIM_SR_CC2IF TIM_SR_CC2IF_Msk |
#define | TIM_SR_CC3IF_Pos (3U) |
#define | TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) |
#define | TIM_SR_CC3IF TIM_SR_CC3IF_Msk |
#define | TIM_SR_CC4IF_Pos (4U) |
#define | TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) |
#define | TIM_SR_CC4IF TIM_SR_CC4IF_Msk |
#define | TIM_SR_COMIF_Pos (5U) |
#define | TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) |
#define | TIM_SR_COMIF TIM_SR_COMIF_Msk |
#define | TIM_SR_TIF_Pos (6U) |
#define | TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) |
#define | TIM_SR_TIF TIM_SR_TIF_Msk |
#define | TIM_SR_BIF_Pos (7U) |
#define | TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) |
#define | TIM_SR_BIF TIM_SR_BIF_Msk |
#define | TIM_SR_B2IF_Pos (8U) |
#define | TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) |
#define | TIM_SR_B2IF TIM_SR_B2IF_Msk |
#define | TIM_SR_CC1OF_Pos (9U) |
#define | TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) |
#define | TIM_SR_CC1OF TIM_SR_CC1OF_Msk |
#define | TIM_SR_CC2OF_Pos (10U) |
#define | TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) |
#define | TIM_SR_CC2OF TIM_SR_CC2OF_Msk |
#define | TIM_SR_CC3OF_Pos (11U) |
#define | TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) |
#define | TIM_SR_CC3OF TIM_SR_CC3OF_Msk |
#define | TIM_SR_CC4OF_Pos (12U) |
#define | TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) |
#define | TIM_SR_CC4OF TIM_SR_CC4OF_Msk |
#define | TIM_SR_CC5IF_Pos (16U) |
#define | TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) |
#define | TIM_SR_CC5IF TIM_SR_CC5IF_Msk |
#define | TIM_SR_CC6IF_Pos (17U) |
#define | TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) |
#define | TIM_SR_CC6IF TIM_SR_CC6IF_Msk |
#define | TIM_SR_SBIF_Pos (13U) |
#define | TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) |
#define | TIM_SR_SBIF TIM_SR_SBIF_Msk |
#define | TIM_EGR_UG_Pos (0U) |
#define | TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) |
#define | TIM_EGR_UG TIM_EGR_UG_Msk |
#define | TIM_EGR_CC1G_Pos (1U) |
#define | TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) |
#define | TIM_EGR_CC1G TIM_EGR_CC1G_Msk |
#define | TIM_EGR_CC2G_Pos (2U) |
#define | TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) |
#define | TIM_EGR_CC2G TIM_EGR_CC2G_Msk |
#define | TIM_EGR_CC3G_Pos (3U) |
#define | TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) |
#define | TIM_EGR_CC3G TIM_EGR_CC3G_Msk |
#define | TIM_EGR_CC4G_Pos (4U) |
#define | TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) |
#define | TIM_EGR_CC4G TIM_EGR_CC4G_Msk |
#define | TIM_EGR_COMG_Pos (5U) |
#define | TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) |
#define | TIM_EGR_COMG TIM_EGR_COMG_Msk |
#define | TIM_EGR_TG_Pos (6U) |
#define | TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) |
#define | TIM_EGR_TG TIM_EGR_TG_Msk |
#define | TIM_EGR_BG_Pos (7U) |
#define | TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) |
#define | TIM_EGR_BG TIM_EGR_BG_Msk |
#define | TIM_EGR_B2G_Pos (8U) |
#define | TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) |
#define | TIM_EGR_B2G TIM_EGR_B2G_Msk |
#define | TIM_CCMR1_CC1S_Pos (0U) |
#define | TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) |
#define | TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk |
#define | TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) |
#define | TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) |
#define | TIM_CCMR1_OC1FE_Pos (2U) |
#define | TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) |
#define | TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk |
#define | TIM_CCMR1_OC1PE_Pos (3U) |
#define | TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) |
#define | TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk |
#define | TIM_CCMR1_OC1M_Pos (4U) |
#define | TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) |
#define | TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk |
#define | TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) |
#define | TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) |
#define | TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) |
#define | TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) |
#define | TIM_CCMR1_OC1CE_Pos (7U) |
#define | TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) |
#define | TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk |
#define | TIM_CCMR1_CC2S_Pos (8U) |
#define | TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) |
#define | TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk |
#define | TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) |
#define | TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) |
#define | TIM_CCMR1_OC2FE_Pos (10U) |
#define | TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) |
#define | TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk |
#define | TIM_CCMR1_OC2PE_Pos (11U) |
#define | TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) |
#define | TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk |
#define | TIM_CCMR1_OC2M_Pos (12U) |
#define | TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) |
#define | TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk |
#define | TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) |
#define | TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) |
#define | TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) |
#define | TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) |
#define | TIM_CCMR1_OC2CE_Pos (15U) |
#define | TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) |
#define | TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk |
#define | TIM_CCMR1_IC1PSC_Pos (2U) |
#define | TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) |
#define | TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk |
#define | TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) |
#define | TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) |
#define | TIM_CCMR1_IC1F_Pos (4U) |
#define | TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) |
#define | TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk |
#define | TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) |
#define | TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) |
#define | TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) |
#define | TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) |
#define | TIM_CCMR1_IC2PSC_Pos (10U) |
#define | TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) |
#define | TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk |
#define | TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) |
#define | TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) |
#define | TIM_CCMR1_IC2F_Pos (12U) |
#define | TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) |
#define | TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk |
#define | TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) |
#define | TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) |
#define | TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) |
#define | TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) |
#define | TIM_CCMR2_CC3S_Pos (0U) |
#define | TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) |
#define | TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk |
#define | TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) |
#define | TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) |
#define | TIM_CCMR2_OC3FE_Pos (2U) |
#define | TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) |
#define | TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk |
#define | TIM_CCMR2_OC3PE_Pos (3U) |
#define | TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) |
#define | TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk |
#define | TIM_CCMR2_OC3M_Pos (4U) |
#define | TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) |
#define | TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk |
#define | TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) |
#define | TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) |
#define | TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) |
#define | TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) |
#define | TIM_CCMR2_OC3CE_Pos (7U) |
#define | TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) |
#define | TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk |
#define | TIM_CCMR2_CC4S_Pos (8U) |
#define | TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) |
#define | TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk |
#define | TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) |
#define | TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) |
#define | TIM_CCMR2_OC4FE_Pos (10U) |
#define | TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) |
#define | TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk |
#define | TIM_CCMR2_OC4PE_Pos (11U) |
#define | TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) |
#define | TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk |
#define | TIM_CCMR2_OC4M_Pos (12U) |
#define | TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) |
#define | TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk |
#define | TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) |
#define | TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) |
#define | TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) |
#define | TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) |
#define | TIM_CCMR2_OC4CE_Pos (15U) |
#define | TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) |
#define | TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk |
#define | TIM_CCMR2_IC3PSC_Pos (2U) |
#define | TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) |
#define | TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk |
#define | TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) |
#define | TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) |
#define | TIM_CCMR2_IC3F_Pos (4U) |
#define | TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) |
#define | TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk |
#define | TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) |
#define | TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) |
#define | TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) |
#define | TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) |
#define | TIM_CCMR2_IC4PSC_Pos (10U) |
#define | TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) |
#define | TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk |
#define | TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) |
#define | TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) |
#define | TIM_CCMR2_IC4F_Pos (12U) |
#define | TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) |
#define | TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk |
#define | TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) |
#define | TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) |
#define | TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) |
#define | TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) |
#define | TIM_CCER_CC1E_Pos (0U) |
#define | TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) |
#define | TIM_CCER_CC1E TIM_CCER_CC1E_Msk |
#define | TIM_CCER_CC1P_Pos (1U) |
#define | TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) |
#define | TIM_CCER_CC1P TIM_CCER_CC1P_Msk |
#define | TIM_CCER_CC1NE_Pos (2U) |
#define | TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) |
#define | TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk |
#define | TIM_CCER_CC1NP_Pos (3U) |
#define | TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) |
#define | TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk |
#define | TIM_CCER_CC2E_Pos (4U) |
#define | TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) |
#define | TIM_CCER_CC2E TIM_CCER_CC2E_Msk |
#define | TIM_CCER_CC2P_Pos (5U) |
#define | TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) |
#define | TIM_CCER_CC2P TIM_CCER_CC2P_Msk |
#define | TIM_CCER_CC2NE_Pos (6U) |
#define | TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) |
#define | TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk |
#define | TIM_CCER_CC2NP_Pos (7U) |
#define | TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) |
#define | TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk |
#define | TIM_CCER_CC3E_Pos (8U) |
#define | TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) |
#define | TIM_CCER_CC3E TIM_CCER_CC3E_Msk |
#define | TIM_CCER_CC3P_Pos (9U) |
#define | TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) |
#define | TIM_CCER_CC3P TIM_CCER_CC3P_Msk |
#define | TIM_CCER_CC3NE_Pos (10U) |
#define | TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) |
#define | TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk |
#define | TIM_CCER_CC3NP_Pos (11U) |
#define | TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) |
#define | TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk |
#define | TIM_CCER_CC4E_Pos (12U) |
#define | TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) |
#define | TIM_CCER_CC4E TIM_CCER_CC4E_Msk |
#define | TIM_CCER_CC4P_Pos (13U) |
#define | TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) |
#define | TIM_CCER_CC4P TIM_CCER_CC4P_Msk |
#define | TIM_CCER_CC4NP_Pos (15U) |
#define | TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) |
#define | TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk |
#define | TIM_CCER_CC5E_Pos (16U) |
#define | TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) |
#define | TIM_CCER_CC5E TIM_CCER_CC5E_Msk |
#define | TIM_CCER_CC5P_Pos (17U) |
#define | TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) |
#define | TIM_CCER_CC5P TIM_CCER_CC5P_Msk |
#define | TIM_CCER_CC6E_Pos (20U) |
#define | TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) |
#define | TIM_CCER_CC6E TIM_CCER_CC6E_Msk |
#define | TIM_CCER_CC6P_Pos (21U) |
#define | TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) |
#define | TIM_CCER_CC6P TIM_CCER_CC6P_Msk |
#define | TIM_CNT_CNT_Pos (0U) |
#define | TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) |
#define | TIM_CNT_CNT TIM_CNT_CNT_Msk |
#define | TIM_CNT_UIFCPY_Pos (31U) |
#define | TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) |
#define | TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk |
#define | TIM_PSC_PSC_Pos (0U) |
#define | TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) |
#define | TIM_PSC_PSC TIM_PSC_PSC_Msk |
#define | TIM_ARR_ARR_Pos (0U) |
#define | TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) |
#define | TIM_ARR_ARR TIM_ARR_ARR_Msk |
#define | TIM_RCR_REP_Pos (0U) |
#define | TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) |
#define | TIM_RCR_REP TIM_RCR_REP_Msk |
#define | TIM_CCR1_CCR1_Pos (0U) |
#define | TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) |
#define | TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk |
#define | TIM_CCR2_CCR2_Pos (0U) |
#define | TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) |
#define | TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk |
#define | TIM_CCR3_CCR3_Pos (0U) |
#define | TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) |
#define | TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk |
#define | TIM_CCR4_CCR4_Pos (0U) |
#define | TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) |
#define | TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk |
#define | TIM_CCR5_CCR5_Pos (0U) |
#define | TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) |
#define | TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk |
#define | TIM_CCR5_GC5C1_Pos (29U) |
#define | TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) |
#define | TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk |
#define | TIM_CCR5_GC5C2_Pos (30U) |
#define | TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) |
#define | TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk |
#define | TIM_CCR5_GC5C3_Pos (31U) |
#define | TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) |
#define | TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk |
#define | TIM_CCR6_CCR6_Pos (0U) |
#define | TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) |
#define | TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk |
#define | TIM_BDTR_DTG_Pos (0U) |
#define | TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG TIM_BDTR_DTG_Msk |
#define | TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) |
#define | TIM_BDTR_LOCK_Pos (8U) |
#define | TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) |
#define | TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk |
#define | TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) |
#define | TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) |
#define | TIM_BDTR_OSSI_Pos (10U) |
#define | TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) |
#define | TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk |
#define | TIM_BDTR_OSSR_Pos (11U) |
#define | TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) |
#define | TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk |
#define | TIM_BDTR_BKE_Pos (12U) |
#define | TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) |
#define | TIM_BDTR_BKE TIM_BDTR_BKE_Msk |
#define | TIM_BDTR_BKP_Pos (13U) |
#define | TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) |
#define | TIM_BDTR_BKP TIM_BDTR_BKP_Msk |
#define | TIM_BDTR_AOE_Pos (14U) |
#define | TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) |
#define | TIM_BDTR_AOE TIM_BDTR_AOE_Msk |
#define | TIM_BDTR_MOE_Pos (15U) |
#define | TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) |
#define | TIM_BDTR_MOE TIM_BDTR_MOE_Msk |
#define | TIM_BDTR_BKF_Pos (16U) |
#define | TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) |
#define | TIM_BDTR_BKF TIM_BDTR_BKF_Msk |
#define | TIM_BDTR_BK2F_Pos (20U) |
#define | TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) |
#define | TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk |
#define | TIM_BDTR_BK2E_Pos (24U) |
#define | TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) |
#define | TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk |
#define | TIM_BDTR_BK2P_Pos (25U) |
#define | TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) |
#define | TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk |
#define | TIM_DCR_DBA_Pos (0U) |
#define | TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) |
#define | TIM_DCR_DBA TIM_DCR_DBA_Msk |
#define | TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) |
#define | TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) |
#define | TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) |
#define | TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) |
#define | TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) |
#define | TIM_DCR_DBL_Pos (8U) |
#define | TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) |
#define | TIM_DCR_DBL TIM_DCR_DBL_Msk |
#define | TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) |
#define | TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) |
#define | TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) |
#define | TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) |
#define | TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) |
#define | TIM_DMAR_DMAB_Pos (0U) |
#define | TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) |
#define | TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk |
#define | TIM_CCMR3_OC5FE_Pos (2U) |
#define | TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) |
#define | TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk |
#define | TIM_CCMR3_OC5PE_Pos (3U) |
#define | TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) |
#define | TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk |
#define | TIM_CCMR3_OC5M_Pos (4U) |
#define | TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) |
#define | TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk |
#define | TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) |
#define | TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) |
#define | TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) |
#define | TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) |
#define | TIM_CCMR3_OC5CE_Pos (7U) |
#define | TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) |
#define | TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk |
#define | TIM_CCMR3_OC6FE_Pos (10U) |
#define | TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) |
#define | TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk |
#define | TIM_CCMR3_OC6PE_Pos (11U) |
#define | TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) |
#define | TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk |
#define | TIM_CCMR3_OC6M_Pos (12U) |
#define | TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) |
#define | TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk |
#define | TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) |
#define | TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) |
#define | TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) |
#define | TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) |
#define | TIM_CCMR3_OC6CE_Pos (15U) |
#define | TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) |
#define | TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk |
#define | TIM1_AF1_BKINE_Pos (0U) |
#define | TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) |
#define | TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk |
#define | TIM1_AF1_BKCMP1E_Pos (1U) |
#define | TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) |
#define | TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk |
#define | TIM1_AF1_BKCMP2E_Pos (2U) |
#define | TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) |
#define | TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk |
#define | TIM1_AF1_BKDF1BK0E_Pos (8U) |
#define | TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) |
#define | TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk |
#define | TIM1_AF1_BKINP_Pos (9U) |
#define | TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) |
#define | TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk |
#define | TIM1_AF1_BKCMP1P_Pos (10U) |
#define | TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) |
#define | TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk |
#define | TIM1_AF1_BKCMP2P_Pos (11U) |
#define | TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) |
#define | TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk |
#define | TIM1_AF1_ETRSEL_Pos (14U) |
#define | TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) |
#define | TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk |
#define | TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) |
#define | TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) |
#define | TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) |
#define | TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) |
#define | TIM1_AF2_BK2INE_Pos (0U) |
#define | TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) |
#define | TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk |
#define | TIM1_AF2_BK2CMP1E_Pos (1U) |
#define | TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) |
#define | TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk |
#define | TIM1_AF2_BK2CMP2E_Pos (2U) |
#define | TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) |
#define | TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk |
#define | TIM1_AF2_BK2DFBK1E_Pos (8U) |
#define | TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) |
#define | TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk |
#define | TIM1_AF2_BK2INP_Pos (9U) |
#define | TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) |
#define | TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk |
#define | TIM1_AF2_BK2CMP1P_Pos (10U) |
#define | TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) |
#define | TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk |
#define | TIM1_AF2_BK2CMP2P_Pos (11U) |
#define | TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) |
#define | TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk |
#define | TIM_TISEL_TI1SEL_Pos (0U) |
#define | TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) |
#define | TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk |
#define | TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) |
#define | TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) |
#define | TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) |
#define | TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) |
#define | TIM_TISEL_TI2SEL_Pos (8U) |
#define | TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) |
#define | TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk |
#define | TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) |
#define | TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) |
#define | TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) |
#define | TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) |
#define | TIM_TISEL_TI3SEL_Pos (16U) |
#define | TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) |
#define | TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk |
#define | TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) |
#define | TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) |
#define | TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) |
#define | TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) |
#define | TIM_TISEL_TI4SEL_Pos (24U) |
#define | TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) |
#define | TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk |
#define | TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) |
#define | TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) |
#define | TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) |
#define | TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) |
#define | TIM8_AF1_BKINE_Pos (0U) |
#define | TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) |
#define | TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk |
#define | TIM8_AF1_BKCMP1E_Pos (1U) |
#define | TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) |
#define | TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk |
#define | TIM8_AF1_BKCMP2E_Pos (2U) |
#define | TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) |
#define | TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk |
#define | TIM8_AF1_BKDFBK2E_Pos (8U) |
#define | TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) |
#define | TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk |
#define | TIM8_AF1_BKINP_Pos (9U) |
#define | TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) |
#define | TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk |
#define | TIM8_AF1_BKCMP1P_Pos (10U) |
#define | TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) |
#define | TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk |
#define | TIM8_AF1_BKCMP2P_Pos (11U) |
#define | TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) |
#define | TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk |
#define | TIM8_AF1_ETRSEL_Pos (14U) |
#define | TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) |
#define | TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk |
#define | TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) |
#define | TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) |
#define | TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) |
#define | TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) |
#define | TIM8_AF2_BK2INE_Pos (0U) |
#define | TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) |
#define | TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk |
#define | TIM8_AF2_BK2CMP1E_Pos (1U) |
#define | TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) |
#define | TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk |
#define | TIM8_AF2_BK2CMP2E_Pos (2U) |
#define | TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) |
#define | TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk |
#define | TIM8_AF2_BK2DFBK3E_Pos (8U) |
#define | TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) |
#define | TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk |
#define | TIM8_AF2_BK2INP_Pos (9U) |
#define | TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) |
#define | TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk |
#define | TIM8_AF2_BK2CMP1P_Pos (10U) |
#define | TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) |
#define | TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk |
#define | TIM8_AF2_BK2CMP2P_Pos (11U) |
#define | TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) |
#define | TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk |
#define | TIM2_AF1_ETRSEL_Pos (14U) |
#define | TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) |
#define | TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk |
#define | TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) |
#define | TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) |
#define | TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) |
#define | TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) |
#define | TIM3_AF1_ETRSEL_Pos (14U) |
#define | TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) |
#define | TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk |
#define | TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) |
#define | TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) |
#define | TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) |
#define | TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) |
#define | TIM5_AF1_ETRSEL_Pos (14U) |
#define | TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) |
#define | TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk |
#define | TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) |
#define | TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) |
#define | TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) |
#define | TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) |
#define | TIM15_AF1_BKINE_Pos (0U) |
#define | TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) |
#define | TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk |
#define | TIM15_AF1_BKCMP1E_Pos (1U) |
#define | TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) |
#define | TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk |
#define | TIM15_AF1_BKCMP2E_Pos (2U) |
#define | TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) |
#define | TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk |
#define | TIM15_AF1_BKDF1BK2E_Pos (8U) |
#define | TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) |
#define | TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk |
#define | TIM15_AF1_BKINP_Pos (9U) |
#define | TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) |
#define | TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk |
#define | TIM15_AF1_BKCMP1P_Pos (10U) |
#define | TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) |
#define | TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk |
#define | TIM15_AF1_BKCMP2P_Pos (11U) |
#define | TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) |
#define | TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk |
#define | TIM16_AF1_BKINE_Pos (0U) |
#define | TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) |
#define | TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk |
#define | TIM16_AF1_BKCMP1E_Pos (1U) |
#define | TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) |
#define | TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk |
#define | TIM16_AF1_BKCMP2E_Pos (2U) |
#define | TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) |
#define | TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk |
#define | TIM16_AF1_BKDF1BK2E_Pos (8U) |
#define | TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) |
#define | TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk |
#define | TIM16_AF1_BKINP_Pos (9U) |
#define | TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) |
#define | TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk |
#define | TIM16_AF1_BKCMP1P_Pos (10U) |
#define | TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) |
#define | TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk |
#define | TIM16_AF1_BKCMP2P_Pos (11U) |
#define | TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) |
#define | TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk |
#define | TIM17_AF1_BKINE_Pos (0U) |
#define | TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) |
#define | TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk |
#define | TIM17_AF1_BKCMP1E_Pos (1U) |
#define | TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) |
#define | TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk |
#define | TIM17_AF1_BKCMP2E_Pos (2U) |
#define | TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) |
#define | TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk |
#define | TIM17_AF1_BKDF1BK2E_Pos (8U) |
#define | TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) |
#define | TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk |
#define | TIM17_AF1_BKINP_Pos (9U) |
#define | TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) |
#define | TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk |
#define | TIM17_AF1_BKCMP1P_Pos (10U) |
#define | TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) |
#define | TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk |
#define | TIM17_AF1_BKCMP2P_Pos (11U) |
#define | TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) |
#define | TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk |
#define | LPTIM_ISR_CMPM_Pos (0U) |
#define | LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) |
#define | LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk |
#define | LPTIM_ISR_ARRM_Pos (1U) |
#define | LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) |
#define | LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk |
#define | LPTIM_ISR_EXTTRIG_Pos (2U) |
#define | LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) |
#define | LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk |
#define | LPTIM_ISR_CMPOK_Pos (3U) |
#define | LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) |
#define | LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk |
#define | LPTIM_ISR_ARROK_Pos (4U) |
#define | LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) |
#define | LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk |
#define | LPTIM_ISR_UP_Pos (5U) |
#define | LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) |
#define | LPTIM_ISR_UP LPTIM_ISR_UP_Msk |
#define | LPTIM_ISR_DOWN_Pos (6U) |
#define | LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) |
#define | LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk |
#define | LPTIM_ICR_CMPMCF_Pos (0U) |
#define | LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) |
#define | LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk |
#define | LPTIM_ICR_ARRMCF_Pos (1U) |
#define | LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) |
#define | LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk |
#define | LPTIM_ICR_EXTTRIGCF_Pos (2U) |
#define | LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) |
#define | LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk |
#define | LPTIM_ICR_CMPOKCF_Pos (3U) |
#define | LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) |
#define | LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk |
#define | LPTIM_ICR_ARROKCF_Pos (4U) |
#define | LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) |
#define | LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk |
#define | LPTIM_ICR_UPCF_Pos (5U) |
#define | LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) |
#define | LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk |
#define | LPTIM_ICR_DOWNCF_Pos (6U) |
#define | LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) |
#define | LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk |
#define | LPTIM_IER_CMPMIE_Pos (0U) |
#define | LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) |
#define | LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk |
#define | LPTIM_IER_ARRMIE_Pos (1U) |
#define | LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) |
#define | LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk |
#define | LPTIM_IER_EXTTRIGIE_Pos (2U) |
#define | LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) |
#define | LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk |
#define | LPTIM_IER_CMPOKIE_Pos (3U) |
#define | LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) |
#define | LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk |
#define | LPTIM_IER_ARROKIE_Pos (4U) |
#define | LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) |
#define | LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk |
#define | LPTIM_IER_UPIE_Pos (5U) |
#define | LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) |
#define | LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk |
#define | LPTIM_IER_DOWNIE_Pos (6U) |
#define | LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) |
#define | LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk |
#define | LPTIM_CFGR_CKSEL_Pos (0U) |
#define | LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) |
#define | LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk |
#define | LPTIM_CFGR_CKPOL_Pos (1U) |
#define | LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) |
#define | LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk |
#define | LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) |
#define | LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) |
#define | LPTIM_CFGR_CKFLT_Pos (3U) |
#define | LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) |
#define | LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk |
#define | LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) |
#define | LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) |
#define | LPTIM_CFGR_TRGFLT_Pos (6U) |
#define | LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) |
#define | LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk |
#define | LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) |
#define | LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) |
#define | LPTIM_CFGR_PRESC_Pos (9U) |
#define | LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) |
#define | LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk |
#define | LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) |
#define | LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) |
#define | LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) |
#define | LPTIM_CFGR_TRIGSEL_Pos (13U) |
#define | LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) |
#define | LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk |
#define | LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) |
#define | LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) |
#define | LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) |
#define | LPTIM_CFGR_TRIGEN_Pos (17U) |
#define | LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) |
#define | LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk |
#define | LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) |
#define | LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) |
#define | LPTIM_CFGR_TIMOUT_Pos (19U) |
#define | LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) |
#define | LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk |
#define | LPTIM_CFGR_WAVE_Pos (20U) |
#define | LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) |
#define | LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk |
#define | LPTIM_CFGR_WAVPOL_Pos (21U) |
#define | LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) |
#define | LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk |
#define | LPTIM_CFGR_PRELOAD_Pos (22U) |
#define | LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) |
#define | LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk |
#define | LPTIM_CFGR_COUNTMODE_Pos (23U) |
#define | LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) |
#define | LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk |
#define | LPTIM_CFGR_ENC_Pos (24U) |
#define | LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) |
#define | LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk |
#define | LPTIM_CR_ENABLE_Pos (0U) |
#define | LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) |
#define | LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk |
#define | LPTIM_CR_SNGSTRT_Pos (1U) |
#define | LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) |
#define | LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk |
#define | LPTIM_CR_CNTSTRT_Pos (2U) |
#define | LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) |
#define | LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk |
#define | LPTIM_CR_COUNTRST_Pos (3U) |
#define | LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) |
#define | LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk |
#define | LPTIM_CR_RSTARE_Pos (4U) |
#define | LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) |
#define | LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk |
#define | LPTIM_CMP_CMP_Pos (0U) |
#define | LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) |
#define | LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk |
#define | LPTIM_ARR_ARR_Pos (0U) |
#define | LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) |
#define | LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk |
#define | LPTIM_CNT_CNT_Pos (0U) |
#define | LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) |
#define | LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk |
#define | LPTIM_CFGR2_IN1SEL_Pos (0U) |
#define | LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) |
#define | LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk |
#define | LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) |
#define | LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) |
#define | LPTIM_CFGR2_IN2SEL_Pos (4U) |
#define | LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) |
#define | LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk |
#define | LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) |
#define | LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) |
#define | COMP_SR_C1VAL_Pos (0U) |
#define | COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) |
#define | COMP_SR_C1VAL COMP_SR_C1VAL_Msk |
#define | COMP_SR_C2VAL_Pos (1U) |
#define | COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) |
#define | COMP_SR_C2VAL COMP_SR_C2VAL_Msk |
#define | COMP_SR_C1IF_Pos (16U) |
#define | COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) |
#define | COMP_SR_C1IF COMP_SR_C1IF_Msk |
#define | COMP_SR_C2IF_Pos (17U) |
#define | COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) |
#define | COMP_SR_C2IF COMP_SR_C2IF_Msk |
#define | COMP_ICFR_C1IF_Pos (16U) |
#define | COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) |
#define | COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk |
#define | COMP_ICFR_C2IF_Pos (17U) |
#define | COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) |
#define | COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk |
#define | COMP_OR_AFOPA6_Pos (0U) |
#define | COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) |
#define | COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk |
#define | COMP_OR_AFOPA8_Pos (1U) |
#define | COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) |
#define | COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk |
#define | COMP_OR_AFOPB12_Pos (2U) |
#define | COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) |
#define | COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk |
#define | COMP_OR_AFOPE6_Pos (3U) |
#define | COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) |
#define | COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk |
#define | COMP_OR_AFOPE15_Pos (4U) |
#define | COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) |
#define | COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk |
#define | COMP_OR_AFOPG2_Pos (5U) |
#define | COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) |
#define | COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk |
#define | COMP_OR_AFOPG3_Pos (6U) |
#define | COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) |
#define | COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk |
#define | COMP_OR_AFOPG4_Pos (7U) |
#define | COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) |
#define | COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk |
#define | COMP_OR_AFOPI1_Pos (8U) |
#define | COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) |
#define | COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk |
#define | COMP_OR_AFOPI4_Pos (9U) |
#define | COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) |
#define | COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk |
#define | COMP_OR_AFOPK2_Pos (10U) |
#define | COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) |
#define | COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk |
#define | COMP_CFGRx_EN_Pos (0U) |
#define | COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) |
#define | COMP_CFGRx_EN COMP_CFGRx_EN_Msk |
#define | COMP_CFGRx_BRGEN_Pos (1U) |
#define | COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) |
#define | COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk |
#define | COMP_CFGRx_SCALEN_Pos (2U) |
#define | COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) |
#define | COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk |
#define | COMP_CFGRx_POLARITY_Pos (3U) |
#define | COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) |
#define | COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk |
#define | COMP_CFGRx_WINMODE_Pos (4U) |
#define | COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) |
#define | COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk |
#define | COMP_CFGRx_ITEN_Pos (6U) |
#define | COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) |
#define | COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk |
#define | COMP_CFGRx_HYST_Pos (8U) |
#define | COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) |
#define | COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk |
#define | COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) |
#define | COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) |
#define | COMP_CFGRx_PWRMODE_Pos (12U) |
#define | COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) |
#define | COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk |
#define | COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) |
#define | COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) |
#define | COMP_CFGRx_INMSEL_Pos (16U) |
#define | COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) |
#define | COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk |
#define | COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) |
#define | COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) |
#define | COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) |
#define | COMP_CFGRx_INPSEL_Pos (20U) |
#define | COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) |
#define | COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk |
#define | COMP_CFGRx_BLANKING_Pos (24U) |
#define | COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) |
#define | COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk |
#define | COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) |
#define | COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) |
#define | COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) |
#define | COMP_CFGRx_LOCK_Pos (31U) |
#define | COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) |
#define | COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk |
#define | USART_CR1_UE_Pos (0U) |
#define | USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) |
#define | USART_CR1_UE USART_CR1_UE_Msk |
#define | USART_CR1_UESM_Pos (1U) |
#define | USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) |
#define | USART_CR1_UESM USART_CR1_UESM_Msk |
#define | USART_CR1_RE_Pos (2U) |
#define | USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) |
#define | USART_CR1_RE USART_CR1_RE_Msk |
#define | USART_CR1_TE_Pos (3U) |
#define | USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) |
#define | USART_CR1_TE USART_CR1_TE_Msk |
#define | USART_CR1_IDLEIE_Pos (4U) |
#define | USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) |
#define | USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk |
#define | USART_CR1_RXNEIE_RXFNEIE_Pos (5U) |
#define | USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) |
#define | USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk |
#define | USART_CR1_TCIE_Pos (6U) |
#define | USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) |
#define | USART_CR1_TCIE USART_CR1_TCIE_Msk |
#define | USART_CR1_TXEIE_TXFNFIE_Pos (7U) |
#define | USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) |
#define | USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk |
#define | USART_CR1_PEIE_Pos (8U) |
#define | USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) |
#define | USART_CR1_PEIE USART_CR1_PEIE_Msk |
#define | USART_CR1_PS_Pos (9U) |
#define | USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) |
#define | USART_CR1_PS USART_CR1_PS_Msk |
#define | USART_CR1_PCE_Pos (10U) |
#define | USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) |
#define | USART_CR1_PCE USART_CR1_PCE_Msk |
#define | USART_CR1_WAKE_Pos (11U) |
#define | USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) |
#define | USART_CR1_WAKE USART_CR1_WAKE_Msk |
#define | USART_CR1_M_Pos (12U) |
#define | USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) |
#define | USART_CR1_M USART_CR1_M_Msk |
#define | USART_CR1_M0_Pos (12U) |
#define | USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) |
#define | USART_CR1_M0 USART_CR1_M0_Msk |
#define | USART_CR1_MME_Pos (13U) |
#define | USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) |
#define | USART_CR1_MME USART_CR1_MME_Msk |
#define | USART_CR1_CMIE_Pos (14U) |
#define | USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) |
#define | USART_CR1_CMIE USART_CR1_CMIE_Msk |
#define | USART_CR1_OVER8_Pos (15U) |
#define | USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) |
#define | USART_CR1_OVER8 USART_CR1_OVER8_Msk |
#define | USART_CR1_DEDT_Pos (16U) |
#define | USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) |
#define | USART_CR1_DEDT USART_CR1_DEDT_Msk |
#define | USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) |
#define | USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) |
#define | USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) |
#define | USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) |
#define | USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) |
#define | USART_CR1_DEAT_Pos (21U) |
#define | USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) |
#define | USART_CR1_DEAT USART_CR1_DEAT_Msk |
#define | USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) |
#define | USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) |
#define | USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) |
#define | USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) |
#define | USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) |
#define | USART_CR1_RTOIE_Pos (26U) |
#define | USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) |
#define | USART_CR1_RTOIE USART_CR1_RTOIE_Msk |
#define | USART_CR1_EOBIE_Pos (27U) |
#define | USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) |
#define | USART_CR1_EOBIE USART_CR1_EOBIE_Msk |
#define | USART_CR1_M1_Pos (28U) |
#define | USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) |
#define | USART_CR1_M1 USART_CR1_M1_Msk |
#define | USART_CR1_FIFOEN_Pos (29U) |
#define | USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) |
#define | USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk |
#define | USART_CR1_TXFEIE_Pos (30U) |
#define | USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) |
#define | USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk |
#define | USART_CR1_RXFFIE_Pos (31U) |
#define | USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) |
#define | USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk |
#define | USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE |
#define | USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE |
#define | USART_CR2_SLVEN_Pos (0U) |
#define | USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) |
#define | USART_CR2_SLVEN USART_CR2_SLVEN_Msk |
#define | USART_CR2_DIS_NSS_Pos (3U) |
#define | USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) |
#define | USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk |
#define | USART_CR2_ADDM7_Pos (4U) |
#define | USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) |
#define | USART_CR2_ADDM7 USART_CR2_ADDM7_Msk |
#define | USART_CR2_LBDL_Pos (5U) |
#define | USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) |
#define | USART_CR2_LBDL USART_CR2_LBDL_Msk |
#define | USART_CR2_LBDIE_Pos (6U) |
#define | USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) |
#define | USART_CR2_LBDIE USART_CR2_LBDIE_Msk |
#define | USART_CR2_LBCL_Pos (8U) |
#define | USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) |
#define | USART_CR2_LBCL USART_CR2_LBCL_Msk |
#define | USART_CR2_CPHA_Pos (9U) |
#define | USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) |
#define | USART_CR2_CPHA USART_CR2_CPHA_Msk |
#define | USART_CR2_CPOL_Pos (10U) |
#define | USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) |
#define | USART_CR2_CPOL USART_CR2_CPOL_Msk |
#define | USART_CR2_CLKEN_Pos (11U) |
#define | USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) |
#define | USART_CR2_CLKEN USART_CR2_CLKEN_Msk |
#define | USART_CR2_STOP_Pos (12U) |
#define | USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) |
#define | USART_CR2_STOP USART_CR2_STOP_Msk |
#define | USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) |
#define | USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) |
#define | USART_CR2_LINEN_Pos (14U) |
#define | USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) |
#define | USART_CR2_LINEN USART_CR2_LINEN_Msk |
#define | USART_CR2_SWAP_Pos (15U) |
#define | USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) |
#define | USART_CR2_SWAP USART_CR2_SWAP_Msk |
#define | USART_CR2_RXINV_Pos (16U) |
#define | USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) |
#define | USART_CR2_RXINV USART_CR2_RXINV_Msk |
#define | USART_CR2_TXINV_Pos (17U) |
#define | USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) |
#define | USART_CR2_TXINV USART_CR2_TXINV_Msk |
#define | USART_CR2_DATAINV_Pos (18U) |
#define | USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) |
#define | USART_CR2_DATAINV USART_CR2_DATAINV_Msk |
#define | USART_CR2_MSBFIRST_Pos (19U) |
#define | USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) |
#define | USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk |
#define | USART_CR2_ABREN_Pos (20U) |
#define | USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) |
#define | USART_CR2_ABREN USART_CR2_ABREN_Msk |
#define | USART_CR2_ABRMODE_Pos (21U) |
#define | USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) |
#define | USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk |
#define | USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) |
#define | USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) |
#define | USART_CR2_RTOEN_Pos (23U) |
#define | USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) |
#define | USART_CR2_RTOEN USART_CR2_RTOEN_Msk |
#define | USART_CR2_ADD_Pos (24U) |
#define | USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) |
#define | USART_CR2_ADD USART_CR2_ADD_Msk |
#define | USART_CR3_EIE_Pos (0U) |
#define | USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) |
#define | USART_CR3_EIE USART_CR3_EIE_Msk |
#define | USART_CR3_IREN_Pos (1U) |
#define | USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) |
#define | USART_CR3_IREN USART_CR3_IREN_Msk |
#define | USART_CR3_IRLP_Pos (2U) |
#define | USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) |
#define | USART_CR3_IRLP USART_CR3_IRLP_Msk |
#define | USART_CR3_HDSEL_Pos (3U) |
#define | USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) |
#define | USART_CR3_HDSEL USART_CR3_HDSEL_Msk |
#define | USART_CR3_NACK_Pos (4U) |
#define | USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) |
#define | USART_CR3_NACK USART_CR3_NACK_Msk |
#define | USART_CR3_SCEN_Pos (5U) |
#define | USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) |
#define | USART_CR3_SCEN USART_CR3_SCEN_Msk |
#define | USART_CR3_DMAR_Pos (6U) |
#define | USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) |
#define | USART_CR3_DMAR USART_CR3_DMAR_Msk |
#define | USART_CR3_DMAT_Pos (7U) |
#define | USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) |
#define | USART_CR3_DMAT USART_CR3_DMAT_Msk |
#define | USART_CR3_RTSE_Pos (8U) |
#define | USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) |
#define | USART_CR3_RTSE USART_CR3_RTSE_Msk |
#define | USART_CR3_CTSE_Pos (9U) |
#define | USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) |
#define | USART_CR3_CTSE USART_CR3_CTSE_Msk |
#define | USART_CR3_CTSIE_Pos (10U) |
#define | USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) |
#define | USART_CR3_CTSIE USART_CR3_CTSIE_Msk |
#define | USART_CR3_ONEBIT_Pos (11U) |
#define | USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) |
#define | USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk |
#define | USART_CR3_OVRDIS_Pos (12U) |
#define | USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) |
#define | USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk |
#define | USART_CR3_DDRE_Pos (13U) |
#define | USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) |
#define | USART_CR3_DDRE USART_CR3_DDRE_Msk |
#define | USART_CR3_DEM_Pos (14U) |
#define | USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) |
#define | USART_CR3_DEM USART_CR3_DEM_Msk |
#define | USART_CR3_DEP_Pos (15U) |
#define | USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) |
#define | USART_CR3_DEP USART_CR3_DEP_Msk |
#define | USART_CR3_SCARCNT_Pos (17U) |
#define | USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) |
#define | USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk |
#define | USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) |
#define | USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) |
#define | USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) |
#define | USART_CR3_WUS_Pos (20U) |
#define | USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) |
#define | USART_CR3_WUS USART_CR3_WUS_Msk |
#define | USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) |
#define | USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) |
#define | USART_CR3_WUFIE_Pos (22U) |
#define | USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) |
#define | USART_CR3_WUFIE USART_CR3_WUFIE_Msk |
#define | USART_CR3_TXFTIE_Pos (23U) |
#define | USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) |
#define | USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk |
#define | USART_CR3_TCBGTIE_Pos (24U) |
#define | USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) |
#define | USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk |
#define | USART_CR3_RXFTCFG_Pos (25U) |
#define | USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) |
#define | USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk |
#define | USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) |
#define | USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) |
#define | USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) |
#define | USART_CR3_RXFTIE_Pos (28U) |
#define | USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) |
#define | USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk |
#define | USART_CR3_TXFTCFG_Pos (29U) |
#define | USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) |
#define | USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk |
#define | USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) |
#define | USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) |
#define | USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) |
#define | USART_BRR_DIV_FRACTION_Pos (0U) |
#define | USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) |
#define | USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk |
#define | USART_BRR_DIV_MANTISSA_Pos (4U) |
#define | USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) |
#define | USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk |
#define | USART_GTPR_PSC_Pos (0U) |
#define | USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) |
#define | USART_GTPR_PSC USART_GTPR_PSC_Msk |
#define | USART_GTPR_GT_Pos (8U) |
#define | USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) |
#define | USART_GTPR_GT USART_GTPR_GT_Msk |
#define | USART_RTOR_RTO_Pos (0U) |
#define | USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) |
#define | USART_RTOR_RTO USART_RTOR_RTO_Msk |
#define | USART_RTOR_BLEN_Pos (24U) |
#define | USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) |
#define | USART_RTOR_BLEN USART_RTOR_BLEN_Msk |
#define | USART_RQR_ABRRQ_Pos (0U) |
#define | USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) |
#define | USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk |
#define | USART_RQR_SBKRQ_Pos (1U) |
#define | USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) |
#define | USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk |
#define | USART_RQR_MMRQ_Pos (2U) |
#define | USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) |
#define | USART_RQR_MMRQ USART_RQR_MMRQ_Msk |
#define | USART_RQR_RXFRQ_Pos (3U) |
#define | USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) |
#define | USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk |
#define | USART_RQR_TXFRQ_Pos (4U) |
#define | USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) |
#define | USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk |
#define | USART_ISR_PE_Pos (0U) |
#define | USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) |
#define | USART_ISR_PE USART_ISR_PE_Msk |
#define | USART_ISR_FE_Pos (1U) |
#define | USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) |
#define | USART_ISR_FE USART_ISR_FE_Msk |
#define | USART_ISR_NE_Pos (2U) |
#define | USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) |
#define | USART_ISR_NE USART_ISR_NE_Msk |
#define | USART_ISR_ORE_Pos (3U) |
#define | USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) |
#define | USART_ISR_ORE USART_ISR_ORE_Msk |
#define | USART_ISR_IDLE_Pos (4U) |
#define | USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) |
#define | USART_ISR_IDLE USART_ISR_IDLE_Msk |
#define | USART_ISR_RXNE_RXFNE_Pos (5U) |
#define | USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) |
#define | USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk |
#define | USART_ISR_TC_Pos (6U) |
#define | USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) |
#define | USART_ISR_TC USART_ISR_TC_Msk |
#define | USART_ISR_TXE_TXFNF_Pos (7U) |
#define | USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) |
#define | USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk |
#define | USART_ISR_LBDF_Pos (8U) |
#define | USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) |
#define | USART_ISR_LBDF USART_ISR_LBDF_Msk |
#define | USART_ISR_CTSIF_Pos (9U) |
#define | USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) |
#define | USART_ISR_CTSIF USART_ISR_CTSIF_Msk |
#define | USART_ISR_CTS_Pos (10U) |
#define | USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) |
#define | USART_ISR_CTS USART_ISR_CTS_Msk |
#define | USART_ISR_RTOF_Pos (11U) |
#define | USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) |
#define | USART_ISR_RTOF USART_ISR_RTOF_Msk |
#define | USART_ISR_EOBF_Pos (12U) |
#define | USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) |
#define | USART_ISR_EOBF USART_ISR_EOBF_Msk |
#define | USART_ISR_UDR_Pos (13U) |
#define | USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) |
#define | USART_ISR_UDR USART_ISR_UDR_Msk |
#define | USART_ISR_ABRE_Pos (14U) |
#define | USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) |
#define | USART_ISR_ABRE USART_ISR_ABRE_Msk |
#define | USART_ISR_ABRF_Pos (15U) |
#define | USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) |
#define | USART_ISR_ABRF USART_ISR_ABRF_Msk |
#define | USART_ISR_BUSY_Pos (16U) |
#define | USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) |
#define | USART_ISR_BUSY USART_ISR_BUSY_Msk |
#define | USART_ISR_CMF_Pos (17U) |
#define | USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) |
#define | USART_ISR_CMF USART_ISR_CMF_Msk |
#define | USART_ISR_SBKF_Pos (18U) |
#define | USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) |
#define | USART_ISR_SBKF USART_ISR_SBKF_Msk |
#define | USART_ISR_RWU_Pos (19U) |
#define | USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) |
#define | USART_ISR_RWU USART_ISR_RWU_Msk |
#define | USART_ISR_WUF_Pos (20U) |
#define | USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) |
#define | USART_ISR_WUF USART_ISR_WUF_Msk |
#define | USART_ISR_TEACK_Pos (21U) |
#define | USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) |
#define | USART_ISR_TEACK USART_ISR_TEACK_Msk |
#define | USART_ISR_REACK_Pos (22U) |
#define | USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) |
#define | USART_ISR_REACK USART_ISR_REACK_Msk |
#define | USART_ISR_TXFE_Pos (23U) |
#define | USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) |
#define | USART_ISR_TXFE USART_ISR_TXFE_Msk |
#define | USART_ISR_RXFF_Pos (24U) |
#define | USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) |
#define | USART_ISR_RXFF USART_ISR_RXFF_Msk |
#define | USART_ISR_TCBGT_Pos (25U) |
#define | USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) |
#define | USART_ISR_TCBGT USART_ISR_TCBGT_Msk |
#define | USART_ISR_RXFT_Pos (26U) |
#define | USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) |
#define | USART_ISR_RXFT USART_ISR_RXFT_Msk |
#define | USART_ISR_TXFT_Pos (27U) |
#define | USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) |
#define | USART_ISR_TXFT USART_ISR_TXFT_Msk |
#define | USART_ICR_PECF_Pos (0U) |
#define | USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) |
#define | USART_ICR_PECF USART_ICR_PECF_Msk |
#define | USART_ICR_FECF_Pos (1U) |
#define | USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) |
#define | USART_ICR_FECF USART_ICR_FECF_Msk |
#define | USART_ICR_NECF_Pos (2U) |
#define | USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) |
#define | USART_ICR_NECF USART_ICR_NECF_Msk |
#define | USART_ICR_ORECF_Pos (3U) |
#define | USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) |
#define | USART_ICR_ORECF USART_ICR_ORECF_Msk |
#define | USART_ICR_IDLECF_Pos (4U) |
#define | USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) |
#define | USART_ICR_IDLECF USART_ICR_IDLECF_Msk |
#define | USART_ICR_TXFECF_Pos (5U) |
#define | USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) |
#define | USART_ICR_TXFECF USART_ICR_TXFECF_Msk |
#define | USART_ICR_TCCF_Pos (6U) |
#define | USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) |
#define | USART_ICR_TCCF USART_ICR_TCCF_Msk |
#define | USART_ICR_TCBGTCF_Pos (7U) |
#define | USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) |
#define | USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk |
#define | USART_ICR_LBDCF_Pos (8U) |
#define | USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) |
#define | USART_ICR_LBDCF USART_ICR_LBDCF_Msk |
#define | USART_ICR_CTSCF_Pos (9U) |
#define | USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) |
#define | USART_ICR_CTSCF USART_ICR_CTSCF_Msk |
#define | USART_ICR_RTOCF_Pos (11U) |
#define | USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) |
#define | USART_ICR_RTOCF USART_ICR_RTOCF_Msk |
#define | USART_ICR_EOBCF_Pos (12U) |
#define | USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) |
#define | USART_ICR_EOBCF USART_ICR_EOBCF_Msk |
#define | USART_ICR_UDRCF_Pos (13U) |
#define | USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) |
#define | USART_ICR_UDRCF USART_ICR_UDRCF_Msk |
#define | USART_ICR_CMCF_Pos (17U) |
#define | USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) |
#define | USART_ICR_CMCF USART_ICR_CMCF_Msk |
#define | USART_ICR_WUCF_Pos (20U) |
#define | USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) |
#define | USART_ICR_WUCF USART_ICR_WUCF_Msk |
#define | USART_RDR_RDR_Pos (0U) |
#define | USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) |
#define | USART_RDR_RDR USART_RDR_RDR_Msk |
#define | USART_TDR_TDR_Pos (0U) |
#define | USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) |
#define | USART_TDR_TDR USART_TDR_TDR_Msk |
#define | USART_PRESC_PRESCALER_Pos (0U) |
#define | USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) |
#define | USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk |
#define | USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) |
#define | USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) |
#define | USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) |
#define | USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) |
#define | SWPMI_CR_RXDMA_Pos (0U) |
#define | SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) |
#define | SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk |
#define | SWPMI_CR_TXDMA_Pos (1U) |
#define | SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) |
#define | SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk |
#define | SWPMI_CR_RXMODE_Pos (2U) |
#define | SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) |
#define | SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk |
#define | SWPMI_CR_TXMODE_Pos (3U) |
#define | SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) |
#define | SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk |
#define | SWPMI_CR_LPBK_Pos (4U) |
#define | SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) |
#define | SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk |
#define | SWPMI_CR_SWPACT_Pos (5U) |
#define | SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) |
#define | SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk |
#define | SWPMI_CR_DEACT_Pos (10U) |
#define | SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) |
#define | SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk |
#define | SWPMI_CR_SWPEN_Pos (11U) |
#define | SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) |
#define | SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk |
#define | SWPMI_BRR_BR_Pos (0U) |
#define | SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) |
#define | SWPMI_BRR_BR SWPMI_BRR_BR_Msk |
#define | SWPMI_ISR_RXBFF_Pos (0U) |
#define | SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) |
#define | SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk |
#define | SWPMI_ISR_TXBEF_Pos (1U) |
#define | SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) |
#define | SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk |
#define | SWPMI_ISR_RXBERF_Pos (2U) |
#define | SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) |
#define | SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk |
#define | SWPMI_ISR_RXOVRF_Pos (3U) |
#define | SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) |
#define | SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk |
#define | SWPMI_ISR_TXUNRF_Pos (4U) |
#define | SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) |
#define | SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk |
#define | SWPMI_ISR_RXNE_Pos (5U) |
#define | SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) |
#define | SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk |
#define | SWPMI_ISR_TXE_Pos (6U) |
#define | SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) |
#define | SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk |
#define | SWPMI_ISR_TCF_Pos (7U) |
#define | SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) |
#define | SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk |
#define | SWPMI_ISR_SRF_Pos (8U) |
#define | SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) |
#define | SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk |
#define | SWPMI_ISR_SUSP_Pos (9U) |
#define | SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) |
#define | SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk |
#define | SWPMI_ISR_DEACTF_Pos (10U) |
#define | SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) |
#define | SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk |
#define | SWPMI_ISR_RDYF_Pos (11U) |
#define | SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) |
#define | SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk |
#define | SWPMI_ICR_CRXBFF_Pos (0U) |
#define | SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) |
#define | SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk |
#define | SWPMI_ICR_CTXBEF_Pos (1U) |
#define | SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) |
#define | SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk |
#define | SWPMI_ICR_CRXBERF_Pos (2U) |
#define | SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) |
#define | SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk |
#define | SWPMI_ICR_CRXOVRF_Pos (3U) |
#define | SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) |
#define | SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk |
#define | SWPMI_ICR_CTXUNRF_Pos (4U) |
#define | SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) |
#define | SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk |
#define | SWPMI_ICR_CTCF_Pos (7U) |
#define | SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) |
#define | SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk |
#define | SWPMI_ICR_CSRF_Pos (8U) |
#define | SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) |
#define | SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk |
#define | SWPMI_ICR_CRDYF_Pos (11U) |
#define | SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) |
#define | SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk |
#define | SWPMI_IER_RXBFIE_Pos (0U) |
#define | SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) |
#define | SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk |
#define | SWPMI_IER_TXBEIE_Pos (1U) |
#define | SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) |
#define | SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk |
#define | SWPMI_IER_RXBERIE_Pos (2U) |
#define | SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) |
#define | SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk |
#define | SWPMI_IER_RXOVRIE_Pos (3U) |
#define | SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) |
#define | SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk |
#define | SWPMI_IER_TXUNRIE_Pos (4U) |
#define | SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) |
#define | SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk |
#define | SWPMI_IER_RIE_Pos (5U) |
#define | SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) |
#define | SWPMI_IER_RIE SWPMI_IER_RIE_Msk |
#define | SWPMI_IER_TIE_Pos (6U) |
#define | SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) |
#define | SWPMI_IER_TIE SWPMI_IER_TIE_Msk |
#define | SWPMI_IER_TCIE_Pos (7U) |
#define | SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) |
#define | SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk |
#define | SWPMI_IER_SRIE_Pos (8U) |
#define | SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) |
#define | SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk |
#define | SWPMI_IER_RDYIE_Pos (11U) |
#define | SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) |
#define | SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk |
#define | SWPMI_RFL_RFL_Pos (0U) |
#define | SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) |
#define | SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk |
#define | SWPMI_RFL_RFL_0_1 (0x00000003U) |
#define | SWPMI_TDR_TD_Pos (0U) |
#define | SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) |
#define | SWPMI_TDR_TD SWPMI_TDR_TD_Msk |
#define | SWPMI_RDR_RD_Pos (0U) |
#define | SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) |
#define | SWPMI_RDR_RD SWPMI_RDR_RD_Msk |
#define | SWPMI_OR_TBYP_Pos (0U) |
#define | SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) |
#define | SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk |
#define | SWPMI_OR_CLASS_Pos (1U) |
#define | SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) |
#define | SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk |
#define | WWDG_CR_T_Pos (0U) |
#define | WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T WWDG_CR_T_Msk |
#define | WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) |
#define | WWDG_CR_WDGA_Pos (7U) |
#define | WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) |
#define | WWDG_CR_WDGA WWDG_CR_WDGA_Msk |
#define | WWDG_CFR_W_Pos (0U) |
#define | WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W WWDG_CFR_W_Msk |
#define | WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) |
#define | WWDG_CFR_EWI_Pos (9U) |
#define | WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) |
#define | WWDG_CFR_EWI WWDG_CFR_EWI_Msk |
#define | WWDG_CFR_WDGTB_Pos (11U) |
#define | WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) |
#define | WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk |
#define | WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) |
#define | WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) |
#define | WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) |
#define | WWDG_SR_EWIF_Pos (0U) |
#define | WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) |
#define | WWDG_SR_EWIF WWDG_SR_EWIF_Msk |
#define | STM32H7_DEV_ID 0x450UL |
#define | DBGMCU_IDCODE_DEV_ID_Pos (0U) |
#define | DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) |
#define | DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk |
#define | DBGMCU_IDCODE_REV_ID_Pos (16U) |
#define | DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) |
#define | DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk |
#define | DBGMCU_CR_DBG_SLEEPD1_Pos (0U) |
#define | DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) |
#define | DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk |
#define | DBGMCU_CR_DBG_STOPD1_Pos (1U) |
#define | DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) |
#define | DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk |
#define | DBGMCU_CR_DBG_STANDBYD1_Pos (2U) |
#define | DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) |
#define | DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk |
#define | DBGMCU_CR_DBG_TRACECKEN_Pos (20U) |
#define | DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) |
#define | DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk |
#define | DBGMCU_CR_DBG_CKD1EN_Pos (21U) |
#define | DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) |
#define | DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk |
#define | DBGMCU_CR_DBG_CKD3EN_Pos (22U) |
#define | DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) |
#define | DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk |
#define | DBGMCU_CR_DBG_TRGOEN_Pos (28U) |
#define | DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) |
#define | DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk |
#define | DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U) |
#define | DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) |
#define | DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk |
#define | DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U) |
#define | DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk |
#define | DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U) |
#define | DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk |
#define | DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U) |
#define | DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk |
#define | DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U) |
#define | DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk |
#define | DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U) |
#define | DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) |
#define | DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk |
#define | DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U) |
#define | DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) |
#define | DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk |
#define | DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U) |
#define | DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) |
#define | DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk |
#define | DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U) |
#define | DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) |
#define | DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk |
#define | DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U) |
#define | DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) |
#define | DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk |
#define | DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U) |
#define | DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) |
#define | DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk |
#define | DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U) |
#define | DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) |
#define | DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk |
#define | DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U) |
#define | DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) |
#define | DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk |
#define | DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U) |
#define | DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) |
#define | DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk |
#define | DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk |
#define | DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk |
#define | DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk |
#define | DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) |
#define | DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk |
#define | DBGMCU_APB4FZ1_DBG_RTC_Pos (16U) |
#define | DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) |
#define | DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk |
#define | DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U) |
#define | DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) |
#define | DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk |
#define | HRTIM_MCR_CK_PSC_Pos (0U) |
#define | HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) |
#define | HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk |
#define | HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) |
#define | HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) |
#define | HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) |
#define | HRTIM_MCR_CONT_Pos (3U) |
#define | HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) |
#define | HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk |
#define | HRTIM_MCR_RETRIG_Pos (4U) |
#define | HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) |
#define | HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk |
#define | HRTIM_MCR_HALF_Pos (5U) |
#define | HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) |
#define | HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk |
#define | HRTIM_MCR_SYNC_IN_Pos (8U) |
#define | HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) |
#define | HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk |
#define | HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) |
#define | HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) |
#define | HRTIM_MCR_SYNCRSTM_Pos (10U) |
#define | HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) |
#define | HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk |
#define | HRTIM_MCR_SYNCSTRTM_Pos (11U) |
#define | HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) |
#define | HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk |
#define | HRTIM_MCR_SYNC_OUT_Pos (12U) |
#define | HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) |
#define | HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk |
#define | HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) |
#define | HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) |
#define | HRTIM_MCR_SYNC_SRC_Pos (14U) |
#define | HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) |
#define | HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk |
#define | HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) |
#define | HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) |
#define | HRTIM_MCR_MCEN_Pos (16U) |
#define | HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) |
#define | HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk |
#define | HRTIM_MCR_TACEN_Pos (17U) |
#define | HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) |
#define | HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk |
#define | HRTIM_MCR_TBCEN_Pos (18U) |
#define | HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) |
#define | HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk |
#define | HRTIM_MCR_TCCEN_Pos (19U) |
#define | HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) |
#define | HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk |
#define | HRTIM_MCR_TDCEN_Pos (20U) |
#define | HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) |
#define | HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk |
#define | HRTIM_MCR_TECEN_Pos (21U) |
#define | HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) |
#define | HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk |
#define | HRTIM_MCR_DACSYNC_Pos (25U) |
#define | HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) |
#define | HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk |
#define | HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) |
#define | HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) |
#define | HRTIM_MCR_PREEN_Pos (27U) |
#define | HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) |
#define | HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk |
#define | HRTIM_MCR_MREPU_Pos (29U) |
#define | HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) |
#define | HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk |
#define | HRTIM_MCR_BRSTDMA_Pos (30U) |
#define | HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) |
#define | HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk |
#define | HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) |
#define | HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) |
#define | HRTIM_MISR_MCMP1_Pos (0U) |
#define | HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) |
#define | HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk |
#define | HRTIM_MISR_MCMP2_Pos (1U) |
#define | HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) |
#define | HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk |
#define | HRTIM_MISR_MCMP3_Pos (2U) |
#define | HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) |
#define | HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk |
#define | HRTIM_MISR_MCMP4_Pos (3U) |
#define | HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) |
#define | HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk |
#define | HRTIM_MISR_MREP_Pos (4U) |
#define | HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) |
#define | HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk |
#define | HRTIM_MISR_SYNC_Pos (5U) |
#define | HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) |
#define | HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk |
#define | HRTIM_MISR_MUPD_Pos (6U) |
#define | HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) |
#define | HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk |
#define | HRTIM_MICR_MCMP1_Pos (0U) |
#define | HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) |
#define | HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk |
#define | HRTIM_MICR_MCMP2_Pos (1U) |
#define | HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) |
#define | HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk |
#define | HRTIM_MICR_MCMP3_Pos (2U) |
#define | HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) |
#define | HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk |
#define | HRTIM_MICR_MCMP4_Pos (3U) |
#define | HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) |
#define | HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk |
#define | HRTIM_MICR_MREP_Pos (4U) |
#define | HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) |
#define | HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk |
#define | HRTIM_MICR_SYNC_Pos (5U) |
#define | HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) |
#define | HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk |
#define | HRTIM_MICR_MUPD_Pos (6U) |
#define | HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) |
#define | HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk |
#define | HRTIM_MDIER_MCMP1IE_Pos (0U) |
#define | HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) |
#define | HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk |
#define | HRTIM_MDIER_MCMP2IE_Pos (1U) |
#define | HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) |
#define | HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk |
#define | HRTIM_MDIER_MCMP3IE_Pos (2U) |
#define | HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) |
#define | HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk |
#define | HRTIM_MDIER_MCMP4IE_Pos (3U) |
#define | HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) |
#define | HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk |
#define | HRTIM_MDIER_MREPIE_Pos (4U) |
#define | HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) |
#define | HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk |
#define | HRTIM_MDIER_SYNCIE_Pos (5U) |
#define | HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) |
#define | HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk |
#define | HRTIM_MDIER_MUPDIE_Pos (6U) |
#define | HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) |
#define | HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk |
#define | HRTIM_MDIER_MCMP1DE_Pos (16U) |
#define | HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) |
#define | HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk |
#define | HRTIM_MDIER_MCMP2DE_Pos (17U) |
#define | HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) |
#define | HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk |
#define | HRTIM_MDIER_MCMP3DE_Pos (18U) |
#define | HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) |
#define | HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk |
#define | HRTIM_MDIER_MCMP4DE_Pos (19U) |
#define | HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) |
#define | HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk |
#define | HRTIM_MDIER_MREPDE_Pos (20U) |
#define | HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) |
#define | HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk |
#define | HRTIM_MDIER_SYNCDE_Pos (21U) |
#define | HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) |
#define | HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk |
#define | HRTIM_MDIER_MUPDDE_Pos (22U) |
#define | HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) |
#define | HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk |
#define | HRTIM_MCNTR_MCNTR_Pos (0U) |
#define | HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) |
#define | HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk |
#define | HRTIM_MPER_MPER_Pos (0U) |
#define | HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) |
#define | HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk |
#define | HRTIM_MREP_MREP_Pos (0U) |
#define | HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) |
#define | HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk |
#define | HRTIM_MCMP1R_MCMP1R_Pos (0U) |
#define | HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) |
#define | HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk |
#define | HRTIM_MCMP1R_MCMP2R_Pos (0U) |
#define | HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) |
#define | HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk |
#define | HRTIM_MCMP1R_MCMP3R_Pos (0U) |
#define | HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) |
#define | HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk |
#define | HRTIM_MCMP1R_MCMP4R_Pos (0U) |
#define | HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) |
#define | HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk |
#define | HRTIM_TIMCR_CK_PSC_Pos (0U) |
#define | HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) |
#define | HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk |
#define | HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) |
#define | HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) |
#define | HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) |
#define | HRTIM_TIMCR_CONT_Pos (3U) |
#define | HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) |
#define | HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk |
#define | HRTIM_TIMCR_RETRIG_Pos (4U) |
#define | HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) |
#define | HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk |
#define | HRTIM_TIMCR_HALF_Pos (5U) |
#define | HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) |
#define | HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk |
#define | HRTIM_TIMCR_PSHPLL_Pos (6U) |
#define | HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) |
#define | HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk |
#define | HRTIM_TIMCR_SYNCRST_Pos (10U) |
#define | HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) |
#define | HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk |
#define | HRTIM_TIMCR_SYNCSTRT_Pos (11U) |
#define | HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) |
#define | HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk |
#define | HRTIM_TIMCR_DELCMP2_Pos (12U) |
#define | HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) |
#define | HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk |
#define | HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) |
#define | HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) |
#define | HRTIM_TIMCR_DELCMP4_Pos (14U) |
#define | HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) |
#define | HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk |
#define | HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) |
#define | HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) |
#define | HRTIM_TIMCR_TREPU_Pos (17U) |
#define | HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) |
#define | HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk |
#define | HRTIM_TIMCR_TRSTU_Pos (18U) |
#define | HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) |
#define | HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk |
#define | HRTIM_TIMCR_TAU_Pos (19U) |
#define | HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) |
#define | HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk |
#define | HRTIM_TIMCR_TBU_Pos (20U) |
#define | HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) |
#define | HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk |
#define | HRTIM_TIMCR_TCU_Pos (21U) |
#define | HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) |
#define | HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk |
#define | HRTIM_TIMCR_TDU_Pos (22U) |
#define | HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) |
#define | HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk |
#define | HRTIM_TIMCR_TEU_Pos (23U) |
#define | HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) |
#define | HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk |
#define | HRTIM_TIMCR_MSTU_Pos (24U) |
#define | HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) |
#define | HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk |
#define | HRTIM_TIMCR_DACSYNC_Pos (25U) |
#define | HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) |
#define | HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk |
#define | HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) |
#define | HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) |
#define | HRTIM_TIMCR_PREEN_Pos (27U) |
#define | HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) |
#define | HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk |
#define | HRTIM_TIMCR_UPDGAT_Pos (28U) |
#define | HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) |
#define | HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk |
#define | HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) |
#define | HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) |
#define | HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) |
#define | HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) |
#define | HRTIM_TIMISR_CMP1_Pos (0U) |
#define | HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) |
#define | HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk |
#define | HRTIM_TIMISR_CMP2_Pos (1U) |
#define | HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) |
#define | HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk |
#define | HRTIM_TIMISR_CMP3_Pos (2U) |
#define | HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) |
#define | HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk |
#define | HRTIM_TIMISR_CMP4_Pos (3U) |
#define | HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) |
#define | HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk |
#define | HRTIM_TIMISR_REP_Pos (4U) |
#define | HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) |
#define | HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk |
#define | HRTIM_TIMISR_UPD_Pos (6U) |
#define | HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) |
#define | HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk |
#define | HRTIM_TIMISR_CPT1_Pos (7U) |
#define | HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) |
#define | HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk |
#define | HRTIM_TIMISR_CPT2_Pos (8U) |
#define | HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) |
#define | HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk |
#define | HRTIM_TIMISR_SET1_Pos (9U) |
#define | HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) |
#define | HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk |
#define | HRTIM_TIMISR_RST1_Pos (10U) |
#define | HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) |
#define | HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk |
#define | HRTIM_TIMISR_SET2_Pos (11U) |
#define | HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) |
#define | HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk |
#define | HRTIM_TIMISR_RST2_Pos (12U) |
#define | HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) |
#define | HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk |
#define | HRTIM_TIMISR_RST_Pos (13U) |
#define | HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) |
#define | HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk |
#define | HRTIM_TIMISR_DLYPRT_Pos (14U) |
#define | HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) |
#define | HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk |
#define | HRTIM_TIMISR_CPPSTAT_Pos (16U) |
#define | HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) |
#define | HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk |
#define | HRTIM_TIMISR_IPPSTAT_Pos (17U) |
#define | HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) |
#define | HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk |
#define | HRTIM_TIMISR_O1STAT_Pos (18U) |
#define | HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) |
#define | HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk |
#define | HRTIM_TIMISR_O2STAT_Pos (19U) |
#define | HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) |
#define | HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk |
#define | HRTIM_TIMISR_O1CPY_Pos (20U) |
#define | HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) |
#define | HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk |
#define | HRTIM_TIMISR_O2CPY_Pos (21U) |
#define | HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) |
#define | HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk |
#define | HRTIM_TIMICR_CMP1C_Pos (0U) |
#define | HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) |
#define | HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk |
#define | HRTIM_TIMICR_CMP2C_Pos (1U) |
#define | HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) |
#define | HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk |
#define | HRTIM_TIMICR_CMP3C_Pos (2U) |
#define | HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) |
#define | HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk |
#define | HRTIM_TIMICR_CMP4C_Pos (3U) |
#define | HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) |
#define | HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk |
#define | HRTIM_TIMICR_REPC_Pos (4U) |
#define | HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) |
#define | HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk |
#define | HRTIM_TIMICR_UPDC_Pos (6U) |
#define | HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) |
#define | HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk |
#define | HRTIM_TIMICR_CPT1C_Pos (7U) |
#define | HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) |
#define | HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk |
#define | HRTIM_TIMICR_CPT2C_Pos (8U) |
#define | HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) |
#define | HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk |
#define | HRTIM_TIMICR_SET1C_Pos (9U) |
#define | HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) |
#define | HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk |
#define | HRTIM_TIMICR_RST1C_Pos (10U) |
#define | HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) |
#define | HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk |
#define | HRTIM_TIMICR_SET2C_Pos (11U) |
#define | HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) |
#define | HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk |
#define | HRTIM_TIMICR_RST2C_Pos (12U) |
#define | HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) |
#define | HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk |
#define | HRTIM_TIMICR_RSTC_Pos (13U) |
#define | HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) |
#define | HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk |
#define | HRTIM_TIMICR_DLYPRTC_Pos (14U) |
#define | HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) |
#define | HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk |
#define | HRTIM_TIMDIER_CMP1IE_Pos (0U) |
#define | HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) |
#define | HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk |
#define | HRTIM_TIMDIER_CMP2IE_Pos (1U) |
#define | HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) |
#define | HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk |
#define | HRTIM_TIMDIER_CMP3IE_Pos (2U) |
#define | HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) |
#define | HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk |
#define | HRTIM_TIMDIER_CMP4IE_Pos (3U) |
#define | HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) |
#define | HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk |
#define | HRTIM_TIMDIER_REPIE_Pos (4U) |
#define | HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) |
#define | HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk |
#define | HRTIM_TIMDIER_UPDIE_Pos (6U) |
#define | HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) |
#define | HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk |
#define | HRTIM_TIMDIER_CPT1IE_Pos (7U) |
#define | HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) |
#define | HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk |
#define | HRTIM_TIMDIER_CPT2IE_Pos (8U) |
#define | HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) |
#define | HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk |
#define | HRTIM_TIMDIER_SET1IE_Pos (9U) |
#define | HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) |
#define | HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk |
#define | HRTIM_TIMDIER_RST1IE_Pos (10U) |
#define | HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) |
#define | HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk |
#define | HRTIM_TIMDIER_SET2IE_Pos (11U) |
#define | HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) |
#define | HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk |
#define | HRTIM_TIMDIER_RST2IE_Pos (12U) |
#define | HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) |
#define | HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk |
#define | HRTIM_TIMDIER_RSTIE_Pos (13U) |
#define | HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) |
#define | HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk |
#define | HRTIM_TIMDIER_DLYPRTIE_Pos (14U) |
#define | HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) |
#define | HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk |
#define | HRTIM_TIMDIER_CMP1DE_Pos (16U) |
#define | HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) |
#define | HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk |
#define | HRTIM_TIMDIER_CMP2DE_Pos (17U) |
#define | HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) |
#define | HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk |
#define | HRTIM_TIMDIER_CMP3DE_Pos (18U) |
#define | HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) |
#define | HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk |
#define | HRTIM_TIMDIER_CMP4DE_Pos (19U) |
#define | HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) |
#define | HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk |
#define | HRTIM_TIMDIER_REPDE_Pos (20U) |
#define | HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) |
#define | HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk |
#define | HRTIM_TIMDIER_UPDDE_Pos (22U) |
#define | HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) |
#define | HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk |
#define | HRTIM_TIMDIER_CPT1DE_Pos (23U) |
#define | HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) |
#define | HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk |
#define | HRTIM_TIMDIER_CPT2DE_Pos (24U) |
#define | HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) |
#define | HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk |
#define | HRTIM_TIMDIER_SET1DE_Pos (25U) |
#define | HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) |
#define | HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk |
#define | HRTIM_TIMDIER_RST1DE_Pos (26U) |
#define | HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) |
#define | HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk |
#define | HRTIM_TIMDIER_SET2DE_Pos (27U) |
#define | HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) |
#define | HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk |
#define | HRTIM_TIMDIER_RST2DE_Pos (28U) |
#define | HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) |
#define | HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk |
#define | HRTIM_TIMDIER_RSTDE_Pos (29U) |
#define | HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) |
#define | HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk |
#define | HRTIM_TIMDIER_DLYPRTDE_Pos (30U) |
#define | HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) |
#define | HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk |
#define | HRTIM_CNTR_CNTR_Pos (0U) |
#define | HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) |
#define | HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk |
#define | HRTIM_PER_PER_Pos (0U) |
#define | HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) |
#define | HRTIM_PER_PER HRTIM_PER_PER_Msk |
#define | HRTIM_REP_REP_Pos (0U) |
#define | HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) |
#define | HRTIM_REP_REP HRTIM_REP_REP_Msk |
#define | HRTIM_CMP1R_CMP1R_Pos (0U) |
#define | HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) |
#define | HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk |
#define | HRTIM_CMP1CR_CMP1CR_Pos (0U) |
#define | HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) |
#define | HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk |
#define | HRTIM_CMP2R_CMP2R_Pos (0U) |
#define | HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) |
#define | HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk |
#define | HRTIM_CMP3R_CMP3R_Pos (0U) |
#define | HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) |
#define | HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk |
#define | HRTIM_CMP4R_CMP4R_Pos (0U) |
#define | HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) |
#define | HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk |
#define | HRTIM_CPT1R_CPT1R_Pos (0U) |
#define | HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) |
#define | HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk |
#define | HRTIM_CPT2R_CPT2R_Pos (0U) |
#define | HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) |
#define | HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk |
#define | HRTIM_DTR_DTR_Pos (0U) |
#define | HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk |
#define | HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) |
#define | HRTIM_DTR_SDTR_Pos (9U) |
#define | HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) |
#define | HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk |
#define | HRTIM_DTR_DTPRSC_Pos (10U) |
#define | HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) |
#define | HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk |
#define | HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) |
#define | HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) |
#define | HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) |
#define | HRTIM_DTR_DTRSLK_Pos (14U) |
#define | HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) |
#define | HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk |
#define | HRTIM_DTR_DTRLK_Pos (15U) |
#define | HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) |
#define | HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk |
#define | HRTIM_DTR_DTF_Pos (16U) |
#define | HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk |
#define | HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) |
#define | HRTIM_DTR_SDTF_Pos (25U) |
#define | HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) |
#define | HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk |
#define | HRTIM_DTR_DTFSLK_Pos (30U) |
#define | HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) |
#define | HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk |
#define | HRTIM_DTR_DTFLK_Pos (31U) |
#define | HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) |
#define | HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk |
#define | HRTIM_SET1R_SST_Pos (0U) |
#define | HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) |
#define | HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk |
#define | HRTIM_SET1R_RESYNC_Pos (1U) |
#define | HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) |
#define | HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk |
#define | HRTIM_SET1R_PER_Pos (2U) |
#define | HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) |
#define | HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk |
#define | HRTIM_SET1R_CMP1_Pos (3U) |
#define | HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) |
#define | HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk |
#define | HRTIM_SET1R_CMP2_Pos (4U) |
#define | HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) |
#define | HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk |
#define | HRTIM_SET1R_CMP3_Pos (5U) |
#define | HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) |
#define | HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk |
#define | HRTIM_SET1R_CMP4_Pos (6U) |
#define | HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) |
#define | HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk |
#define | HRTIM_SET1R_MSTPER_Pos (7U) |
#define | HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) |
#define | HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk |
#define | HRTIM_SET1R_MSTCMP1_Pos (8U) |
#define | HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) |
#define | HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk |
#define | HRTIM_SET1R_MSTCMP2_Pos (9U) |
#define | HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) |
#define | HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk |
#define | HRTIM_SET1R_MSTCMP3_Pos (10U) |
#define | HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) |
#define | HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk |
#define | HRTIM_SET1R_MSTCMP4_Pos (11U) |
#define | HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) |
#define | HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk |
#define | HRTIM_SET1R_TIMEVNT1_Pos (12U) |
#define | HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) |
#define | HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk |
#define | HRTIM_SET1R_TIMEVNT2_Pos (13U) |
#define | HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) |
#define | HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk |
#define | HRTIM_SET1R_TIMEVNT3_Pos (14U) |
#define | HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) |
#define | HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk |
#define | HRTIM_SET1R_TIMEVNT4_Pos (15U) |
#define | HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) |
#define | HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk |
#define | HRTIM_SET1R_TIMEVNT5_Pos (16U) |
#define | HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) |
#define | HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk |
#define | HRTIM_SET1R_TIMEVNT6_Pos (17U) |
#define | HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) |
#define | HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk |
#define | HRTIM_SET1R_TIMEVNT7_Pos (18U) |
#define | HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) |
#define | HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk |
#define | HRTIM_SET1R_TIMEVNT8_Pos (19U) |
#define | HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) |
#define | HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk |
#define | HRTIM_SET1R_TIMEVNT9_Pos (20U) |
#define | HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) |
#define | HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk |
#define | HRTIM_SET1R_EXTVNT1_Pos (21U) |
#define | HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) |
#define | HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk |
#define | HRTIM_SET1R_EXTVNT2_Pos (22U) |
#define | HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) |
#define | HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk |
#define | HRTIM_SET1R_EXTVNT3_Pos (23U) |
#define | HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) |
#define | HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk |
#define | HRTIM_SET1R_EXTVNT4_Pos (24U) |
#define | HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) |
#define | HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk |
#define | HRTIM_SET1R_EXTVNT5_Pos (25U) |
#define | HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) |
#define | HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk |
#define | HRTIM_SET1R_EXTVNT6_Pos (26U) |
#define | HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) |
#define | HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk |
#define | HRTIM_SET1R_EXTVNT7_Pos (27U) |
#define | HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) |
#define | HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk |
#define | HRTIM_SET1R_EXTVNT8_Pos (28U) |
#define | HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) |
#define | HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk |
#define | HRTIM_SET1R_EXTVNT9_Pos (29U) |
#define | HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) |
#define | HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk |
#define | HRTIM_SET1R_EXTVNT10_Pos (30U) |
#define | HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) |
#define | HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk |
#define | HRTIM_SET1R_UPDATE_Pos (31U) |
#define | HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) |
#define | HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk |
#define | HRTIM_RST1R_SRT_Pos (0U) |
#define | HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) |
#define | HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk |
#define | HRTIM_RST1R_RESYNC_Pos (1U) |
#define | HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) |
#define | HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk |
#define | HRTIM_RST1R_PER_Pos (2U) |
#define | HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) |
#define | HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk |
#define | HRTIM_RST1R_CMP1_Pos (3U) |
#define | HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) |
#define | HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk |
#define | HRTIM_RST1R_CMP2_Pos (4U) |
#define | HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) |
#define | HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk |
#define | HRTIM_RST1R_CMP3_Pos (5U) |
#define | HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) |
#define | HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk |
#define | HRTIM_RST1R_CMP4_Pos (6U) |
#define | HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) |
#define | HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk |
#define | HRTIM_RST1R_MSTPER_Pos (7U) |
#define | HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) |
#define | HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk |
#define | HRTIM_RST1R_MSTCMP1_Pos (8U) |
#define | HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) |
#define | HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk |
#define | HRTIM_RST1R_MSTCMP2_Pos (9U) |
#define | HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) |
#define | HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk |
#define | HRTIM_RST1R_MSTCMP3_Pos (10U) |
#define | HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) |
#define | HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk |
#define | HRTIM_RST1R_MSTCMP4_Pos (11U) |
#define | HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) |
#define | HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk |
#define | HRTIM_RST1R_TIMEVNT1_Pos (12U) |
#define | HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) |
#define | HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk |
#define | HRTIM_RST1R_TIMEVNT2_Pos (13U) |
#define | HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) |
#define | HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk |
#define | HRTIM_RST1R_TIMEVNT3_Pos (14U) |
#define | HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) |
#define | HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk |
#define | HRTIM_RST1R_TIMEVNT4_Pos (15U) |
#define | HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) |
#define | HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk |
#define | HRTIM_RST1R_TIMEVNT5_Pos (16U) |
#define | HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) |
#define | HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk |
#define | HRTIM_RST1R_TIMEVNT6_Pos (17U) |
#define | HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) |
#define | HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk |
#define | HRTIM_RST1R_TIMEVNT7_Pos (18U) |
#define | HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) |
#define | HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk |
#define | HRTIM_RST1R_TIMEVNT8_Pos (19U) |
#define | HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) |
#define | HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk |
#define | HRTIM_RST1R_TIMEVNT9_Pos (20U) |
#define | HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) |
#define | HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk |
#define | HRTIM_RST1R_EXTVNT1_Pos (21U) |
#define | HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) |
#define | HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk |
#define | HRTIM_RST1R_EXTVNT2_Pos (22U) |
#define | HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) |
#define | HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk |
#define | HRTIM_RST1R_EXTVNT3_Pos (23U) |
#define | HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) |
#define | HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk |
#define | HRTIM_RST1R_EXTVNT4_Pos (24U) |
#define | HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) |
#define | HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk |
#define | HRTIM_RST1R_EXTVNT5_Pos (25U) |
#define | HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) |
#define | HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk |
#define | HRTIM_RST1R_EXTVNT6_Pos (26U) |
#define | HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) |
#define | HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk |
#define | HRTIM_RST1R_EXTVNT7_Pos (27U) |
#define | HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) |
#define | HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk |
#define | HRTIM_RST1R_EXTVNT8_Pos (28U) |
#define | HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) |
#define | HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk |
#define | HRTIM_RST1R_EXTVNT9_Pos (29U) |
#define | HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) |
#define | HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk |
#define | HRTIM_RST1R_EXTVNT10_Pos (30U) |
#define | HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) |
#define | HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk |
#define | HRTIM_RST1R_UPDATE_Pos (31U) |
#define | HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) |
#define | HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk |
#define | HRTIM_SET2R_SST_Pos (0U) |
#define | HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) |
#define | HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk |
#define | HRTIM_SET2R_RESYNC_Pos (1U) |
#define | HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) |
#define | HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk |
#define | HRTIM_SET2R_PER_Pos (2U) |
#define | HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) |
#define | HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk |
#define | HRTIM_SET2R_CMP1_Pos (3U) |
#define | HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) |
#define | HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk |
#define | HRTIM_SET2R_CMP2_Pos (4U) |
#define | HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) |
#define | HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk |
#define | HRTIM_SET2R_CMP3_Pos (5U) |
#define | HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) |
#define | HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk |
#define | HRTIM_SET2R_CMP4_Pos (6U) |
#define | HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) |
#define | HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk |
#define | HRTIM_SET2R_MSTPER_Pos (7U) |
#define | HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) |
#define | HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk |
#define | HRTIM_SET2R_MSTCMP1_Pos (8U) |
#define | HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) |
#define | HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk |
#define | HRTIM_SET2R_MSTCMP2_Pos (9U) |
#define | HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) |
#define | HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk |
#define | HRTIM_SET2R_MSTCMP3_Pos (10U) |
#define | HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) |
#define | HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk |
#define | HRTIM_SET2R_MSTCMP4_Pos (11U) |
#define | HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) |
#define | HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk |
#define | HRTIM_SET2R_TIMEVNT1_Pos (12U) |
#define | HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) |
#define | HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk |
#define | HRTIM_SET2R_TIMEVNT2_Pos (13U) |
#define | HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) |
#define | HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk |
#define | HRTIM_SET2R_TIMEVNT3_Pos (14U) |
#define | HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) |
#define | HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk |
#define | HRTIM_SET2R_TIMEVNT4_Pos (15U) |
#define | HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) |
#define | HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk |
#define | HRTIM_SET2R_TIMEVNT5_Pos (16U) |
#define | HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) |
#define | HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk |
#define | HRTIM_SET2R_TIMEVNT6_Pos (17U) |
#define | HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) |
#define | HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk |
#define | HRTIM_SET2R_TIMEVNT7_Pos (18U) |
#define | HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) |
#define | HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk |
#define | HRTIM_SET2R_TIMEVNT8_Pos (19U) |
#define | HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) |
#define | HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk |
#define | HRTIM_SET2R_TIMEVNT9_Pos (20U) |
#define | HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) |
#define | HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk |
#define | HRTIM_SET2R_EXTVNT1_Pos (21U) |
#define | HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) |
#define | HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk |
#define | HRTIM_SET2R_EXTVNT2_Pos (22U) |
#define | HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) |
#define | HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk |
#define | HRTIM_SET2R_EXTVNT3_Pos (23U) |
#define | HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) |
#define | HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk |
#define | HRTIM_SET2R_EXTVNT4_Pos (24U) |
#define | HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) |
#define | HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk |
#define | HRTIM_SET2R_EXTVNT5_Pos (25U) |
#define | HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) |
#define | HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk |
#define | HRTIM_SET2R_EXTVNT6_Pos (26U) |
#define | HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) |
#define | HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk |
#define | HRTIM_SET2R_EXTVNT7_Pos (27U) |
#define | HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) |
#define | HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk |
#define | HRTIM_SET2R_EXTVNT8_Pos (28U) |
#define | HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) |
#define | HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk |
#define | HRTIM_SET2R_EXTVNT9_Pos (29U) |
#define | HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) |
#define | HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk |
#define | HRTIM_SET2R_EXTVNT10_Pos (30U) |
#define | HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) |
#define | HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk |
#define | HRTIM_SET2R_UPDATE_Pos (31U) |
#define | HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) |
#define | HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk |
#define | HRTIM_RST2R_SRT_Pos (0U) |
#define | HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) |
#define | HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk |
#define | HRTIM_RST2R_RESYNC_Pos (1U) |
#define | HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) |
#define | HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk |
#define | HRTIM_RST2R_PER_Pos (2U) |
#define | HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) |
#define | HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk |
#define | HRTIM_RST2R_CMP1_Pos (3U) |
#define | HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) |
#define | HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk |
#define | HRTIM_RST2R_CMP2_Pos (4U) |
#define | HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) |
#define | HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk |
#define | HRTIM_RST2R_CMP3_Pos (5U) |
#define | HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) |
#define | HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk |
#define | HRTIM_RST2R_CMP4_Pos (6U) |
#define | HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) |
#define | HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk |
#define | HRTIM_RST2R_MSTPER_Pos (7U) |
#define | HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) |
#define | HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk |
#define | HRTIM_RST2R_MSTCMP1_Pos (8U) |
#define | HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) |
#define | HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk |
#define | HRTIM_RST2R_MSTCMP2_Pos (9U) |
#define | HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) |
#define | HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk |
#define | HRTIM_RST2R_MSTCMP3_Pos (10U) |
#define | HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) |
#define | HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk |
#define | HRTIM_RST2R_MSTCMP4_Pos (11U) |
#define | HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) |
#define | HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk |
#define | HRTIM_RST2R_TIMEVNT1_Pos (12U) |
#define | HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) |
#define | HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk |
#define | HRTIM_RST2R_TIMEVNT2_Pos (13U) |
#define | HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) |
#define | HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk |
#define | HRTIM_RST2R_TIMEVNT3_Pos (14U) |
#define | HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) |
#define | HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk |
#define | HRTIM_RST2R_TIMEVNT4_Pos (15U) |
#define | HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) |
#define | HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk |
#define | HRTIM_RST2R_TIMEVNT5_Pos (16U) |
#define | HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) |
#define | HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk |
#define | HRTIM_RST2R_TIMEVNT6_Pos (17U) |
#define | HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) |
#define | HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk |
#define | HRTIM_RST2R_TIMEVNT7_Pos (18U) |
#define | HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) |
#define | HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk |
#define | HRTIM_RST2R_TIMEVNT8_Pos (19U) |
#define | HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) |
#define | HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk |
#define | HRTIM_RST2R_TIMEVNT9_Pos (20U) |
#define | HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) |
#define | HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk |
#define | HRTIM_RST2R_EXTVNT1_Pos (21U) |
#define | HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) |
#define | HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk |
#define | HRTIM_RST2R_EXTVNT2_Pos (22U) |
#define | HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) |
#define | HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk |
#define | HRTIM_RST2R_EXTVNT3_Pos (23U) |
#define | HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) |
#define | HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk |
#define | HRTIM_RST2R_EXTVNT4_Pos (24U) |
#define | HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) |
#define | HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk |
#define | HRTIM_RST2R_EXTVNT5_Pos (25U) |
#define | HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) |
#define | HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk |
#define | HRTIM_RST2R_EXTVNT6_Pos (26U) |
#define | HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) |
#define | HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk |
#define | HRTIM_RST2R_EXTVNT7_Pos (27U) |
#define | HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) |
#define | HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk |
#define | HRTIM_RST2R_EXTVNT8_Pos (28U) |
#define | HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) |
#define | HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk |
#define | HRTIM_RST2R_EXTVNT9_Pos (29U) |
#define | HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) |
#define | HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk |
#define | HRTIM_RST2R_EXTVNT10_Pos (30U) |
#define | HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) |
#define | HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk |
#define | HRTIM_RST2R_UPDATE_Pos (31U) |
#define | HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) |
#define | HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk |
#define | HRTIM_EEFR1_EE1LTCH_Pos (0U) |
#define | HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) |
#define | HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk |
#define | HRTIM_EEFR1_EE1FLTR_Pos (1U) |
#define | HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) |
#define | HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk |
#define | HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) |
#define | HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) |
#define | HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) |
#define | HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) |
#define | HRTIM_EEFR1_EE2LTCH_Pos (6U) |
#define | HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) |
#define | HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk |
#define | HRTIM_EEFR1_EE2FLTR_Pos (7U) |
#define | HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) |
#define | HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk |
#define | HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) |
#define | HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) |
#define | HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) |
#define | HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) |
#define | HRTIM_EEFR1_EE3LTCH_Pos (12U) |
#define | HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) |
#define | HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk |
#define | HRTIM_EEFR1_EE3FLTR_Pos (13U) |
#define | HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) |
#define | HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk |
#define | HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) |
#define | HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) |
#define | HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) |
#define | HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) |
#define | HRTIM_EEFR1_EE4LTCH_Pos (18U) |
#define | HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) |
#define | HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk |
#define | HRTIM_EEFR1_EE4FLTR_Pos (19U) |
#define | HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) |
#define | HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk |
#define | HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) |
#define | HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) |
#define | HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) |
#define | HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) |
#define | HRTIM_EEFR1_EE5LTCH_Pos (24U) |
#define | HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) |
#define | HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk |
#define | HRTIM_EEFR1_EE5FLTR_Pos (25U) |
#define | HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) |
#define | HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk |
#define | HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) |
#define | HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) |
#define | HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) |
#define | HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) |
#define | HRTIM_EEFR2_EE6LTCH_Pos (0U) |
#define | HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) |
#define | HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk |
#define | HRTIM_EEFR2_EE6FLTR_Pos (1U) |
#define | HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) |
#define | HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk |
#define | HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) |
#define | HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) |
#define | HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) |
#define | HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) |
#define | HRTIM_EEFR2_EE7LTCH_Pos (6U) |
#define | HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) |
#define | HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk |
#define | HRTIM_EEFR2_EE7FLTR_Pos (7U) |
#define | HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) |
#define | HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk |
#define | HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) |
#define | HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) |
#define | HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) |
#define | HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) |
#define | HRTIM_EEFR2_EE8LTCH_Pos (12U) |
#define | HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) |
#define | HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk |
#define | HRTIM_EEFR2_EE8FLTR_Pos (13U) |
#define | HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) |
#define | HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk |
#define | HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) |
#define | HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) |
#define | HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) |
#define | HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) |
#define | HRTIM_EEFR2_EE9LTCH_Pos (18U) |
#define | HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) |
#define | HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk |
#define | HRTIM_EEFR2_EE9FLTR_Pos (19U) |
#define | HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) |
#define | HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk |
#define | HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) |
#define | HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) |
#define | HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) |
#define | HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) |
#define | HRTIM_EEFR2_EE10LTCH_Pos (24U) |
#define | HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) |
#define | HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk |
#define | HRTIM_EEFR2_EE10FLTR_Pos (25U) |
#define | HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) |
#define | HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk |
#define | HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) |
#define | HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) |
#define | HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) |
#define | HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) |
#define | HRTIM_RSTR_UPDATE_Pos (1U) |
#define | HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) |
#define | HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk |
#define | HRTIM_RSTR_CMP2_Pos (2U) |
#define | HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) |
#define | HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk |
#define | HRTIM_RSTR_CMP4_Pos (3U) |
#define | HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) |
#define | HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk |
#define | HRTIM_RSTR_MSTPER_Pos (4U) |
#define | HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) |
#define | HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk |
#define | HRTIM_RSTR_MSTCMP1_Pos (5U) |
#define | HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) |
#define | HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk |
#define | HRTIM_RSTR_MSTCMP2_Pos (6U) |
#define | HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) |
#define | HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk |
#define | HRTIM_RSTR_MSTCMP3_Pos (7U) |
#define | HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) |
#define | HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk |
#define | HRTIM_RSTR_MSTCMP4_Pos (8U) |
#define | HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) |
#define | HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk |
#define | HRTIM_RSTR_EXTEVNT1_Pos (9U) |
#define | HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) |
#define | HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk |
#define | HRTIM_RSTR_EXTEVNT2_Pos (10U) |
#define | HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) |
#define | HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk |
#define | HRTIM_RSTR_EXTEVNT3_Pos (11U) |
#define | HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) |
#define | HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk |
#define | HRTIM_RSTR_EXTEVNT4_Pos (12U) |
#define | HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) |
#define | HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk |
#define | HRTIM_RSTR_EXTEVNT5_Pos (13U) |
#define | HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) |
#define | HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk |
#define | HRTIM_RSTR_EXTEVNT6_Pos (14U) |
#define | HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) |
#define | HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk |
#define | HRTIM_RSTR_EXTEVNT7_Pos (15U) |
#define | HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) |
#define | HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk |
#define | HRTIM_RSTR_EXTEVNT8_Pos (16U) |
#define | HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) |
#define | HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk |
#define | HRTIM_RSTR_EXTEVNT9_Pos (17U) |
#define | HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) |
#define | HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk |
#define | HRTIM_RSTR_EXTEVNT10_Pos (18U) |
#define | HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) |
#define | HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk |
#define | HRTIM_RSTR_TIMBCMP1_Pos (19U) |
#define | HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) |
#define | HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk |
#define | HRTIM_RSTR_TIMBCMP2_Pos (20U) |
#define | HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) |
#define | HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk |
#define | HRTIM_RSTR_TIMBCMP4_Pos (21U) |
#define | HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) |
#define | HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk |
#define | HRTIM_RSTR_TIMCCMP1_Pos (22U) |
#define | HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) |
#define | HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk |
#define | HRTIM_RSTR_TIMCCMP2_Pos (23U) |
#define | HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) |
#define | HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk |
#define | HRTIM_RSTR_TIMCCMP4_Pos (24U) |
#define | HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) |
#define | HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk |
#define | HRTIM_RSTR_TIMDCMP1_Pos (25U) |
#define | HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) |
#define | HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk |
#define | HRTIM_RSTR_TIMDCMP2_Pos (26U) |
#define | HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) |
#define | HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk |
#define | HRTIM_RSTR_TIMDCMP4_Pos (27U) |
#define | HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) |
#define | HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk |
#define | HRTIM_RSTR_TIMECMP1_Pos (28U) |
#define | HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) |
#define | HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk |
#define | HRTIM_RSTR_TIMECMP2_Pos (29U) |
#define | HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) |
#define | HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk |
#define | HRTIM_RSTR_TIMECMP4_Pos (30U) |
#define | HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) |
#define | HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk |
#define | HRTIM_RSTBR_TIMACMP1_Pos (19U) |
#define | HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) |
#define | HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk |
#define | HRTIM_RSTBR_TIMACMP2_Pos (20U) |
#define | HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) |
#define | HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk |
#define | HRTIM_RSTBR_TIMACMP4_Pos (21U) |
#define | HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) |
#define | HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk |
#define | HRTIM_RSTBR_TIMCCMP1_Pos (22U) |
#define | HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) |
#define | HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk |
#define | HRTIM_RSTBR_TIMCCMP2_Pos (23U) |
#define | HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) |
#define | HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk |
#define | HRTIM_RSTBR_TIMCCMP4_Pos (24U) |
#define | HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) |
#define | HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk |
#define | HRTIM_RSTBR_TIMDCMP1_Pos (25U) |
#define | HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) |
#define | HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk |
#define | HRTIM_RSTBR_TIMDCMP2_Pos (26U) |
#define | HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) |
#define | HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk |
#define | HRTIM_RSTBR_TIMDCMP4_Pos (27U) |
#define | HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) |
#define | HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk |
#define | HRTIM_RSTBR_TIMECMP1_Pos (28U) |
#define | HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) |
#define | HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk |
#define | HRTIM_RSTBR_TIMECMP2_Pos (29U) |
#define | HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) |
#define | HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk |
#define | HRTIM_RSTBR_TIMECMP4_Pos (30U) |
#define | HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) |
#define | HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk |
#define | HRTIM_RSTCR_TIMACMP1_Pos (19U) |
#define | HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) |
#define | HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk |
#define | HRTIM_RSTCR_TIMACMP2_Pos (20U) |
#define | HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) |
#define | HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk |
#define | HRTIM_RSTCR_TIMACMP4_Pos (21U) |
#define | HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) |
#define | HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk |
#define | HRTIM_RSTCR_TIMBCMP1_Pos (22U) |
#define | HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) |
#define | HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk |
#define | HRTIM_RSTCR_TIMBCMP2_Pos (23U) |
#define | HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) |
#define | HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk |
#define | HRTIM_RSTCR_TIMBCMP4_Pos (24U) |
#define | HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) |
#define | HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk |
#define | HRTIM_RSTCR_TIMDCMP1_Pos (25U) |
#define | HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) |
#define | HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk |
#define | HRTIM_RSTCR_TIMDCMP2_Pos (26U) |
#define | HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) |
#define | HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk |
#define | HRTIM_RSTCR_TIMDCMP4_Pos (27U) |
#define | HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) |
#define | HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk |
#define | HRTIM_RSTCR_TIMECMP1_Pos (28U) |
#define | HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) |
#define | HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk |
#define | HRTIM_RSTCR_TIMECMP2_Pos (29U) |
#define | HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) |
#define | HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk |
#define | HRTIM_RSTCR_TIMECMP4_Pos (30U) |
#define | HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) |
#define | HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk |
#define | HRTIM_RSTDR_TIMACMP1_Pos (19U) |
#define | HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) |
#define | HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk |
#define | HRTIM_RSTDR_TIMACMP2_Pos (20U) |
#define | HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) |
#define | HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk |
#define | HRTIM_RSTDR_TIMACMP4_Pos (21U) |
#define | HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) |
#define | HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk |
#define | HRTIM_RSTDR_TIMBCMP1_Pos (22U) |
#define | HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) |
#define | HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk |
#define | HRTIM_RSTDR_TIMBCMP2_Pos (23U) |
#define | HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) |
#define | HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk |
#define | HRTIM_RSTDR_TIMBCMP4_Pos (24U) |
#define | HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) |
#define | HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk |
#define | HRTIM_RSTDR_TIMCCMP1_Pos (25U) |
#define | HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) |
#define | HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk |
#define | HRTIM_RSTDR_TIMCCMP2_Pos (26U) |
#define | HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) |
#define | HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk |
#define | HRTIM_RSTDR_TIMCCMP4_Pos (27U) |
#define | HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) |
#define | HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk |
#define | HRTIM_RSTDR_TIMECMP1_Pos (28U) |
#define | HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) |
#define | HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk |
#define | HRTIM_RSTDR_TIMECMP2_Pos (29U) |
#define | HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) |
#define | HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk |
#define | HRTIM_RSTDR_TIMECMP4_Pos (30U) |
#define | HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) |
#define | HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk |
#define | HRTIM_RSTER_TIMACMP1_Pos (19U) |
#define | HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) |
#define | HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk |
#define | HRTIM_RSTER_TIMACMP2_Pos (20U) |
#define | HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) |
#define | HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk |
#define | HRTIM_RSTER_TIMACMP4_Pos (21U) |
#define | HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) |
#define | HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk |
#define | HRTIM_RSTER_TIMBCMP1_Pos (22U) |
#define | HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) |
#define | HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk |
#define | HRTIM_RSTER_TIMBCMP2_Pos (23U) |
#define | HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) |
#define | HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk |
#define | HRTIM_RSTER_TIMBCMP4_Pos (24U) |
#define | HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) |
#define | HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk |
#define | HRTIM_RSTER_TIMCCMP1_Pos (25U) |
#define | HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) |
#define | HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk |
#define | HRTIM_RSTER_TIMCCMP2_Pos (26U) |
#define | HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) |
#define | HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk |
#define | HRTIM_RSTER_TIMCCMP4_Pos (27U) |
#define | HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) |
#define | HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk |
#define | HRTIM_RSTER_TIMDCMP1_Pos (28U) |
#define | HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) |
#define | HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk |
#define | HRTIM_RSTER_TIMDCMP2_Pos (29U) |
#define | HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) |
#define | HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk |
#define | HRTIM_RSTER_TIMDCMP4_Pos (30U) |
#define | HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) |
#define | HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk |
#define | HRTIM_CHPR_CARFRQ_Pos (0U) |
#define | HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) |
#define | HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk |
#define | HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) |
#define | HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) |
#define | HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) |
#define | HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) |
#define | HRTIM_CHPR_CARDTY_Pos (4U) |
#define | HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) |
#define | HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk |
#define | HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) |
#define | HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) |
#define | HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) |
#define | HRTIM_CHPR_STRPW_Pos (7U) |
#define | HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) |
#define | HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk |
#define | HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) |
#define | HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) |
#define | HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) |
#define | HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) |
#define | HRTIM_CPT1CR_SWCPT_Pos (0U) |
#define | HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) |
#define | HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk |
#define | HRTIM_CPT1CR_UPDCPT_Pos (1U) |
#define | HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) |
#define | HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk |
#define | HRTIM_CPT1CR_EXEV1CPT_Pos (2U) |
#define | HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk |
#define | HRTIM_CPT1CR_EXEV2CPT_Pos (3U) |
#define | HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk |
#define | HRTIM_CPT1CR_EXEV3CPT_Pos (4U) |
#define | HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk |
#define | HRTIM_CPT1CR_EXEV4CPT_Pos (5U) |
#define | HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk |
#define | HRTIM_CPT1CR_EXEV5CPT_Pos (6U) |
#define | HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk |
#define | HRTIM_CPT1CR_EXEV6CPT_Pos (7U) |
#define | HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk |
#define | HRTIM_CPT1CR_EXEV7CPT_Pos (8U) |
#define | HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk |
#define | HRTIM_CPT1CR_EXEV8CPT_Pos (9U) |
#define | HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk |
#define | HRTIM_CPT1CR_EXEV9CPT_Pos (10U) |
#define | HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk |
#define | HRTIM_CPT1CR_EXEV10CPT_Pos (11U) |
#define | HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) |
#define | HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk |
#define | HRTIM_CPT1CR_TA1SET_Pos (12U) |
#define | HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) |
#define | HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk |
#define | HRTIM_CPT1CR_TA1RST_Pos (13U) |
#define | HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) |
#define | HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk |
#define | HRTIM_CPT1CR_TIMACMP1_Pos (14U) |
#define | HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) |
#define | HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk |
#define | HRTIM_CPT1CR_TIMACMP2_Pos (15U) |
#define | HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) |
#define | HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk |
#define | HRTIM_CPT1CR_TB1SET_Pos (16U) |
#define | HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) |
#define | HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk |
#define | HRTIM_CPT1CR_TB1RST_Pos (17U) |
#define | HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) |
#define | HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk |
#define | HRTIM_CPT1CR_TIMBCMP1_Pos (18U) |
#define | HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) |
#define | HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk |
#define | HRTIM_CPT1CR_TIMBCMP2_Pos (19U) |
#define | HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) |
#define | HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk |
#define | HRTIM_CPT1CR_TC1SET_Pos (20U) |
#define | HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) |
#define | HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk |
#define | HRTIM_CPT1CR_TC1RST_Pos (21U) |
#define | HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) |
#define | HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk |
#define | HRTIM_CPT1CR_TIMCCMP1_Pos (22U) |
#define | HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) |
#define | HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk |
#define | HRTIM_CPT1CR_TIMCCMP2_Pos (23U) |
#define | HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) |
#define | HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk |
#define | HRTIM_CPT1CR_TD1SET_Pos (24U) |
#define | HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) |
#define | HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk |
#define | HRTIM_CPT1CR_TD1RST_Pos (25U) |
#define | HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) |
#define | HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk |
#define | HRTIM_CPT1CR_TIMDCMP1_Pos (26U) |
#define | HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) |
#define | HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk |
#define | HRTIM_CPT1CR_TIMDCMP2_Pos (27U) |
#define | HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) |
#define | HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk |
#define | HRTIM_CPT1CR_TE1SET_Pos (28U) |
#define | HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) |
#define | HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk |
#define | HRTIM_CPT1CR_TE1RST_Pos (29U) |
#define | HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) |
#define | HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk |
#define | HRTIM_CPT1CR_TIMECMP1_Pos (30U) |
#define | HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) |
#define | HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk |
#define | HRTIM_CPT1CR_TIMECMP2_Pos (31U) |
#define | HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) |
#define | HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk |
#define | HRTIM_CPT2CR_SWCPT_Pos (0U) |
#define | HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) |
#define | HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk |
#define | HRTIM_CPT2CR_UPDCPT_Pos (1U) |
#define | HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) |
#define | HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk |
#define | HRTIM_CPT2CR_EXEV1CPT_Pos (2U) |
#define | HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk |
#define | HRTIM_CPT2CR_EXEV2CPT_Pos (3U) |
#define | HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk |
#define | HRTIM_CPT2CR_EXEV3CPT_Pos (4U) |
#define | HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk |
#define | HRTIM_CPT2CR_EXEV4CPT_Pos (5U) |
#define | HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk |
#define | HRTIM_CPT2CR_EXEV5CPT_Pos (6U) |
#define | HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk |
#define | HRTIM_CPT2CR_EXEV6CPT_Pos (7U) |
#define | HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk |
#define | HRTIM_CPT2CR_EXEV7CPT_Pos (8U) |
#define | HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk |
#define | HRTIM_CPT2CR_EXEV8CPT_Pos (9U) |
#define | HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk |
#define | HRTIM_CPT2CR_EXEV9CPT_Pos (10U) |
#define | HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk |
#define | HRTIM_CPT2CR_EXEV10CPT_Pos (11U) |
#define | HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) |
#define | HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk |
#define | HRTIM_CPT2CR_TA1SET_Pos (12U) |
#define | HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) |
#define | HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk |
#define | HRTIM_CPT2CR_TA1RST_Pos (13U) |
#define | HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) |
#define | HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk |
#define | HRTIM_CPT2CR_TIMACMP1_Pos (14U) |
#define | HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) |
#define | HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk |
#define | HRTIM_CPT2CR_TIMACMP2_Pos (15U) |
#define | HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) |
#define | HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk |
#define | HRTIM_CPT2CR_TB1SET_Pos (16U) |
#define | HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) |
#define | HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk |
#define | HRTIM_CPT2CR_TB1RST_Pos (17U) |
#define | HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) |
#define | HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk |
#define | HRTIM_CPT2CR_TIMBCMP1_Pos (18U) |
#define | HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) |
#define | HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk |
#define | HRTIM_CPT2CR_TIMBCMP2_Pos (19U) |
#define | HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) |
#define | HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk |
#define | HRTIM_CPT2CR_TC1SET_Pos (20U) |
#define | HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) |
#define | HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk |
#define | HRTIM_CPT2CR_TC1RST_Pos (21U) |
#define | HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) |
#define | HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk |
#define | HRTIM_CPT2CR_TIMCCMP1_Pos (22U) |
#define | HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) |
#define | HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk |
#define | HRTIM_CPT2CR_TIMCCMP2_Pos (23U) |
#define | HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) |
#define | HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk |
#define | HRTIM_CPT2CR_TD1SET_Pos (24U) |
#define | HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) |
#define | HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk |
#define | HRTIM_CPT2CR_TD1RST_Pos (25U) |
#define | HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) |
#define | HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk |
#define | HRTIM_CPT2CR_TIMDCMP1_Pos (26U) |
#define | HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) |
#define | HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk |
#define | HRTIM_CPT2CR_TIMDCMP2_Pos (27U) |
#define | HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) |
#define | HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk |
#define | HRTIM_CPT2CR_TE1SET_Pos (28U) |
#define | HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) |
#define | HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk |
#define | HRTIM_CPT2CR_TE1RST_Pos (29U) |
#define | HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) |
#define | HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk |
#define | HRTIM_CPT2CR_TIMECMP1_Pos (30U) |
#define | HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) |
#define | HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk |
#define | HRTIM_CPT2CR_TIMECMP2_Pos (31U) |
#define | HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) |
#define | HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk |
#define | HRTIM_OUTR_POL1_Pos (1U) |
#define | HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) |
#define | HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk |
#define | HRTIM_OUTR_IDLM1_Pos (2U) |
#define | HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) |
#define | HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk |
#define | HRTIM_OUTR_IDLES1_Pos (3U) |
#define | HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) |
#define | HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk |
#define | HRTIM_OUTR_FAULT1_Pos (4U) |
#define | HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) |
#define | HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk |
#define | HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) |
#define | HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) |
#define | HRTIM_OUTR_CHP1_Pos (6U) |
#define | HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) |
#define | HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk |
#define | HRTIM_OUTR_DIDL1_Pos (7U) |
#define | HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) |
#define | HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk |
#define | HRTIM_OUTR_DTEN_Pos (8U) |
#define | HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) |
#define | HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk |
#define | HRTIM_OUTR_DLYPRTEN_Pos (9U) |
#define | HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) |
#define | HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk |
#define | HRTIM_OUTR_DLYPRT_Pos (10U) |
#define | HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) |
#define | HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk |
#define | HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) |
#define | HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) |
#define | HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) |
#define | HRTIM_OUTR_POL2_Pos (17U) |
#define | HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) |
#define | HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk |
#define | HRTIM_OUTR_IDLM2_Pos (18U) |
#define | HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) |
#define | HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk |
#define | HRTIM_OUTR_IDLES2_Pos (19U) |
#define | HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) |
#define | HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk |
#define | HRTIM_OUTR_FAULT2_Pos (20U) |
#define | HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) |
#define | HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk |
#define | HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) |
#define | HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) |
#define | HRTIM_OUTR_CHP2_Pos (22U) |
#define | HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) |
#define | HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk |
#define | HRTIM_OUTR_DIDL2_Pos (23U) |
#define | HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) |
#define | HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk |
#define | HRTIM_FLTR_FLT1EN_Pos (0U) |
#define | HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) |
#define | HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk |
#define | HRTIM_FLTR_FLT2EN_Pos (1U) |
#define | HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) |
#define | HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk |
#define | HRTIM_FLTR_FLT3EN_Pos (2U) |
#define | HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) |
#define | HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk |
#define | HRTIM_FLTR_FLT4EN_Pos (3U) |
#define | HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) |
#define | HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk |
#define | HRTIM_FLTR_FLT5EN_Pos (4U) |
#define | HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) |
#define | HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk |
#define | HRTIM_FLTR_FLTLCK_Pos (31U) |
#define | HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) |
#define | HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk |
#define | HRTIM_CR1_MUDIS_Pos (0U) |
#define | HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) |
#define | HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk |
#define | HRTIM_CR1_TAUDIS_Pos (1U) |
#define | HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) |
#define | HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk |
#define | HRTIM_CR1_TBUDIS_Pos (2U) |
#define | HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) |
#define | HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk |
#define | HRTIM_CR1_TCUDIS_Pos (3U) |
#define | HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) |
#define | HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk |
#define | HRTIM_CR1_TDUDIS_Pos (4U) |
#define | HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) |
#define | HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk |
#define | HRTIM_CR1_TEUDIS_Pos (5U) |
#define | HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) |
#define | HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk |
#define | HRTIM_CR1_ADC1USRC_Pos (16U) |
#define | HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) |
#define | HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk |
#define | HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) |
#define | HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) |
#define | HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) |
#define | HRTIM_CR1_ADC2USRC_Pos (19U) |
#define | HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) |
#define | HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk |
#define | HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) |
#define | HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) |
#define | HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) |
#define | HRTIM_CR1_ADC3USRC_Pos (22U) |
#define | HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) |
#define | HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk |
#define | HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) |
#define | HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) |
#define | HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) |
#define | HRTIM_CR1_ADC4USRC_Pos (25U) |
#define | HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) |
#define | HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk |
#define | HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) |
#define | HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) |
#define | HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) |
#define | HRTIM_CR2_MSWU_Pos (0U) |
#define | HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) |
#define | HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk |
#define | HRTIM_CR2_TASWU_Pos (1U) |
#define | HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) |
#define | HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk |
#define | HRTIM_CR2_TBSWU_Pos (2U) |
#define | HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) |
#define | HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk |
#define | HRTIM_CR2_TCSWU_Pos (3U) |
#define | HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) |
#define | HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk |
#define | HRTIM_CR2_TDSWU_Pos (4U) |
#define | HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) |
#define | HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk |
#define | HRTIM_CR2_TESWU_Pos (5U) |
#define | HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) |
#define | HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk |
#define | HRTIM_CR2_MRST_Pos (8U) |
#define | HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) |
#define | HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk |
#define | HRTIM_CR2_TARST_Pos (9U) |
#define | HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) |
#define | HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk |
#define | HRTIM_CR2_TBRST_Pos (10U) |
#define | HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) |
#define | HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk |
#define | HRTIM_CR2_TCRST_Pos (11U) |
#define | HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) |
#define | HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk |
#define | HRTIM_CR2_TDRST_Pos (12U) |
#define | HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) |
#define | HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk |
#define | HRTIM_CR2_TERST_Pos (13U) |
#define | HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) |
#define | HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk |
#define | HRTIM_ISR_FLT1_Pos (0U) |
#define | HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) |
#define | HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk |
#define | HRTIM_ISR_FLT2_Pos (1U) |
#define | HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) |
#define | HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk |
#define | HRTIM_ISR_FLT3_Pos (2U) |
#define | HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) |
#define | HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk |
#define | HRTIM_ISR_FLT4_Pos (3U) |
#define | HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) |
#define | HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk |
#define | HRTIM_ISR_FLT5_Pos (4U) |
#define | HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) |
#define | HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk |
#define | HRTIM_ISR_SYSFLT_Pos (5U) |
#define | HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) |
#define | HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk |
#define | HRTIM_ISR_BMPER_Pos (17U) |
#define | HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) |
#define | HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk |
#define | HRTIM_ICR_FLT1C_Pos (0U) |
#define | HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) |
#define | HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk |
#define | HRTIM_ICR_FLT2C_Pos (1U) |
#define | HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) |
#define | HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk |
#define | HRTIM_ICR_FLT3C_Pos (2U) |
#define | HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) |
#define | HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk |
#define | HRTIM_ICR_FLT4C_Pos (3U) |
#define | HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) |
#define | HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk |
#define | HRTIM_ICR_FLT5C_Pos (4U) |
#define | HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) |
#define | HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk |
#define | HRTIM_ICR_SYSFLTC_Pos (5U) |
#define | HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) |
#define | HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk |
#define | HRTIM_ICR_BMPERC_Pos (17U) |
#define | HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) |
#define | HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk |
#define | HRTIM_IER_FLT1_Pos (0U) |
#define | HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) |
#define | HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk |
#define | HRTIM_IER_FLT2_Pos (1U) |
#define | HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) |
#define | HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk |
#define | HRTIM_IER_FLT3_Pos (2U) |
#define | HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) |
#define | HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk |
#define | HRTIM_IER_FLT4_Pos (3U) |
#define | HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) |
#define | HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk |
#define | HRTIM_IER_FLT5_Pos (4U) |
#define | HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) |
#define | HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk |
#define | HRTIM_IER_SYSFLT_Pos (5U) |
#define | HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) |
#define | HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk |
#define | HRTIM_IER_BMPER_Pos (17U) |
#define | HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) |
#define | HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk |
#define | HRTIM_OENR_TA1OEN_Pos (0U) |
#define | HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) |
#define | HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk |
#define | HRTIM_OENR_TA2OEN_Pos (1U) |
#define | HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) |
#define | HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk |
#define | HRTIM_OENR_TB1OEN_Pos (2U) |
#define | HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) |
#define | HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk |
#define | HRTIM_OENR_TB2OEN_Pos (3U) |
#define | HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) |
#define | HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk |
#define | HRTIM_OENR_TC1OEN_Pos (4U) |
#define | HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) |
#define | HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk |
#define | HRTIM_OENR_TC2OEN_Pos (5U) |
#define | HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) |
#define | HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk |
#define | HRTIM_OENR_TD1OEN_Pos (6U) |
#define | HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) |
#define | HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk |
#define | HRTIM_OENR_TD2OEN_Pos (7U) |
#define | HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) |
#define | HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk |
#define | HRTIM_OENR_TE1OEN_Pos (8U) |
#define | HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) |
#define | HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk |
#define | HRTIM_OENR_TE2OEN_Pos (9U) |
#define | HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) |
#define | HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk |
#define | HRTIM_ODISR_TA1ODIS_Pos (0U) |
#define | HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) |
#define | HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk |
#define | HRTIM_ODISR_TA2ODIS_Pos (1U) |
#define | HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) |
#define | HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk |
#define | HRTIM_ODISR_TB1ODIS_Pos (2U) |
#define | HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) |
#define | HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk |
#define | HRTIM_ODISR_TB2ODIS_Pos (3U) |
#define | HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) |
#define | HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk |
#define | HRTIM_ODISR_TC1ODIS_Pos (4U) |
#define | HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) |
#define | HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk |
#define | HRTIM_ODISR_TC2ODIS_Pos (5U) |
#define | HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) |
#define | HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk |
#define | HRTIM_ODISR_TD1ODIS_Pos (6U) |
#define | HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) |
#define | HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk |
#define | HRTIM_ODISR_TD2ODIS_Pos (7U) |
#define | HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) |
#define | HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk |
#define | HRTIM_ODISR_TE1ODIS_Pos (8U) |
#define | HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) |
#define | HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk |
#define | HRTIM_ODISR_TE2ODIS_Pos (9U) |
#define | HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) |
#define | HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk |
#define | HRTIM_ODSR_TA1ODS_Pos (0U) |
#define | HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) |
#define | HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk |
#define | HRTIM_ODSR_TA2ODS_Pos (1U) |
#define | HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) |
#define | HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk |
#define | HRTIM_ODSR_TB1ODS_Pos (2U) |
#define | HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) |
#define | HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk |
#define | HRTIM_ODSR_TB2ODS_Pos (3U) |
#define | HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) |
#define | HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk |
#define | HRTIM_ODSR_TC1ODS_Pos (4U) |
#define | HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) |
#define | HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk |
#define | HRTIM_ODSR_TC2ODS_Pos (5U) |
#define | HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) |
#define | HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk |
#define | HRTIM_ODSR_TD1ODS_Pos (6U) |
#define | HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) |
#define | HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk |
#define | HRTIM_ODSR_TD2ODS_Pos (7U) |
#define | HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) |
#define | HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk |
#define | HRTIM_ODSR_TE1ODS_Pos (8U) |
#define | HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) |
#define | HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk |
#define | HRTIM_ODSR_TE2ODS_Pos (9U) |
#define | HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) |
#define | HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk |
#define | HRTIM_BMCR_BME_Pos (0U) |
#define | HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) |
#define | HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk |
#define | HRTIM_BMCR_BMOM_Pos (1U) |
#define | HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) |
#define | HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk |
#define | HRTIM_BMCR_BMCLK_Pos (2U) |
#define | HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) |
#define | HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk |
#define | HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) |
#define | HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) |
#define | HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) |
#define | HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) |
#define | HRTIM_BMCR_BMPRSC_Pos (6U) |
#define | HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) |
#define | HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk |
#define | HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) |
#define | HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) |
#define | HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) |
#define | HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) |
#define | HRTIM_BMCR_BMPREN_Pos (10U) |
#define | HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) |
#define | HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk |
#define | HRTIM_BMCR_MTBM_Pos (16U) |
#define | HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) |
#define | HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk |
#define | HRTIM_BMCR_TABM_Pos (17U) |
#define | HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) |
#define | HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk |
#define | HRTIM_BMCR_TBBM_Pos (18U) |
#define | HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) |
#define | HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk |
#define | HRTIM_BMCR_TCBM_Pos (19U) |
#define | HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) |
#define | HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk |
#define | HRTIM_BMCR_TDBM_Pos (20U) |
#define | HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) |
#define | HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk |
#define | HRTIM_BMCR_TEBM_Pos (21U) |
#define | HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) |
#define | HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk |
#define | HRTIM_BMCR_BMSTAT_Pos (31U) |
#define | HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) |
#define | HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk |
#define | HRTIM_BMTRGR_SW_Pos (0U) |
#define | HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) |
#define | HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk |
#define | HRTIM_BMTRGR_MSTRST_Pos (1U) |
#define | HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) |
#define | HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk |
#define | HRTIM_BMTRGR_MSTREP_Pos (2U) |
#define | HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) |
#define | HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk |
#define | HRTIM_BMTRGR_MSTCMP1_Pos (3U) |
#define | HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) |
#define | HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk |
#define | HRTIM_BMTRGR_MSTCMP2_Pos (4U) |
#define | HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) |
#define | HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk |
#define | HRTIM_BMTRGR_MSTCMP3_Pos (5U) |
#define | HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) |
#define | HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk |
#define | HRTIM_BMTRGR_MSTCMP4_Pos (6U) |
#define | HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) |
#define | HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk |
#define | HRTIM_BMTRGR_TARST_Pos (7U) |
#define | HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) |
#define | HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk |
#define | HRTIM_BMTRGR_TAREP_Pos (8U) |
#define | HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) |
#define | HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk |
#define | HRTIM_BMTRGR_TACMP1_Pos (9U) |
#define | HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) |
#define | HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk |
#define | HRTIM_BMTRGR_TACMP2_Pos (10U) |
#define | HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) |
#define | HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk |
#define | HRTIM_BMTRGR_TBRST_Pos (11U) |
#define | HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) |
#define | HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk |
#define | HRTIM_BMTRGR_TBREP_Pos (12U) |
#define | HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) |
#define | HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk |
#define | HRTIM_BMTRGR_TBCMP1_Pos (13U) |
#define | HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) |
#define | HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk |
#define | HRTIM_BMTRGR_TBCMP2_Pos (14U) |
#define | HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) |
#define | HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk |
#define | HRTIM_BMTRGR_TCRST_Pos (15U) |
#define | HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) |
#define | HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk |
#define | HRTIM_BMTRGR_TCREP_Pos (16U) |
#define | HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) |
#define | HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk |
#define | HRTIM_BMTRGR_TCCMP1_Pos (17U) |
#define | HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) |
#define | HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk |
#define | HRTIM_BMTRGR_TCCMP2_Pos (18U) |
#define | HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) |
#define | HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk |
#define | HRTIM_BMTRGR_TDRST_Pos (19U) |
#define | HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) |
#define | HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk |
#define | HRTIM_BMTRGR_TDREP_Pos (20U) |
#define | HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) |
#define | HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk |
#define | HRTIM_BMTRGR_TDCMP1_Pos (21U) |
#define | HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) |
#define | HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk |
#define | HRTIM_BMTRGR_TDCMP2_Pos (22U) |
#define | HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) |
#define | HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk |
#define | HRTIM_BMTRGR_TERST_Pos (23U) |
#define | HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) |
#define | HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk |
#define | HRTIM_BMTRGR_TEREP_Pos (24U) |
#define | HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) |
#define | HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk |
#define | HRTIM_BMTRGR_TECMP1_Pos (25U) |
#define | HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) |
#define | HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk |
#define | HRTIM_BMTRGR_TECMP2_Pos (26U) |
#define | HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) |
#define | HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk |
#define | HRTIM_BMTRGR_TAEEV7_Pos (27U) |
#define | HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) |
#define | HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk |
#define | HRTIM_BMTRGR_TDEEV8_Pos (28U) |
#define | HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) |
#define | HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk |
#define | HRTIM_BMTRGR_EEV7_Pos (29U) |
#define | HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) |
#define | HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk |
#define | HRTIM_BMTRGR_EEV8_Pos (30U) |
#define | HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) |
#define | HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk |
#define | HRTIM_BMTRGR_OCHPEV_Pos (31U) |
#define | HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) |
#define | HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk |
#define | HRTIM_BMCMPR_BMCMPR_Pos (0U) |
#define | HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) |
#define | HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk |
#define | HRTIM_BMPER_BMPER_Pos (0U) |
#define | HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) |
#define | HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk |
#define | HRTIM_EECR1_EE1SRC_Pos (0U) |
#define | HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) |
#define | HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk |
#define | HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) |
#define | HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) |
#define | HRTIM_EECR1_EE1POL_Pos (2U) |
#define | HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) |
#define | HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk |
#define | HRTIM_EECR1_EE1SNS_Pos (3U) |
#define | HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) |
#define | HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk |
#define | HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) |
#define | HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) |
#define | HRTIM_EECR1_EE1FAST_Pos (5U) |
#define | HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) |
#define | HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk |
#define | HRTIM_EECR1_EE2SRC_Pos (6U) |
#define | HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) |
#define | HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk |
#define | HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) |
#define | HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) |
#define | HRTIM_EECR1_EE2POL_Pos (8U) |
#define | HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) |
#define | HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk |
#define | HRTIM_EECR1_EE2SNS_Pos (9U) |
#define | HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) |
#define | HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk |
#define | HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) |
#define | HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) |
#define | HRTIM_EECR1_EE2FAST_Pos (11U) |
#define | HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) |
#define | HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk |
#define | HRTIM_EECR1_EE3SRC_Pos (12U) |
#define | HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) |
#define | HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk |
#define | HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) |
#define | HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) |
#define | HRTIM_EECR1_EE3POL_Pos (14U) |
#define | HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) |
#define | HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk |
#define | HRTIM_EECR1_EE3SNS_Pos (15U) |
#define | HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) |
#define | HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk |
#define | HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) |
#define | HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) |
#define | HRTIM_EECR1_EE3FAST_Pos (17U) |
#define | HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) |
#define | HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk |
#define | HRTIM_EECR1_EE4SRC_Pos (18U) |
#define | HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) |
#define | HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk |
#define | HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) |
#define | HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) |
#define | HRTIM_EECR1_EE4POL_Pos (20U) |
#define | HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) |
#define | HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk |
#define | HRTIM_EECR1_EE4SNS_Pos (21U) |
#define | HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) |
#define | HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk |
#define | HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) |
#define | HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) |
#define | HRTIM_EECR1_EE4FAST_Pos (23U) |
#define | HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) |
#define | HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk |
#define | HRTIM_EECR1_EE5SRC_Pos (24U) |
#define | HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) |
#define | HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk |
#define | HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) |
#define | HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) |
#define | HRTIM_EECR1_EE5POL_Pos (26U) |
#define | HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) |
#define | HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk |
#define | HRTIM_EECR1_EE5SNS_Pos (27U) |
#define | HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) |
#define | HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk |
#define | HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) |
#define | HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) |
#define | HRTIM_EECR1_EE5FAST_Pos (29U) |
#define | HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) |
#define | HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk |
#define | HRTIM_EECR2_EE6SRC_Pos (0U) |
#define | HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) |
#define | HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk |
#define | HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) |
#define | HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) |
#define | HRTIM_EECR2_EE6POL_Pos (2U) |
#define | HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) |
#define | HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk |
#define | HRTIM_EECR2_EE6SNS_Pos (3U) |
#define | HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) |
#define | HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk |
#define | HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) |
#define | HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) |
#define | HRTIM_EECR2_EE7SRC_Pos (6U) |
#define | HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) |
#define | HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk |
#define | HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) |
#define | HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) |
#define | HRTIM_EECR2_EE7POL_Pos (8U) |
#define | HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) |
#define | HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk |
#define | HRTIM_EECR2_EE7SNS_Pos (9U) |
#define | HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) |
#define | HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk |
#define | HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) |
#define | HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) |
#define | HRTIM_EECR2_EE8SRC_Pos (12U) |
#define | HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) |
#define | HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk |
#define | HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) |
#define | HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) |
#define | HRTIM_EECR2_EE8POL_Pos (14U) |
#define | HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) |
#define | HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk |
#define | HRTIM_EECR2_EE8SNS_Pos (15U) |
#define | HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) |
#define | HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk |
#define | HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) |
#define | HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) |
#define | HRTIM_EECR2_EE9SRC_Pos (18U) |
#define | HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) |
#define | HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk |
#define | HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) |
#define | HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) |
#define | HRTIM_EECR2_EE9POL_Pos (20U) |
#define | HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) |
#define | HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk |
#define | HRTIM_EECR2_EE9SNS_Pos (21U) |
#define | HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) |
#define | HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk |
#define | HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) |
#define | HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) |
#define | HRTIM_EECR2_EE10SRC_Pos (24U) |
#define | HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) |
#define | HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk |
#define | HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) |
#define | HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) |
#define | HRTIM_EECR2_EE10POL_Pos (26U) |
#define | HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) |
#define | HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk |
#define | HRTIM_EECR2_EE10SNS_Pos (27U) |
#define | HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) |
#define | HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk |
#define | HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) |
#define | HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) |
#define | HRTIM_EECR3_EE6F_Pos (0U) |
#define | HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) |
#define | HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk |
#define | HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) |
#define | HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) |
#define | HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) |
#define | HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) |
#define | HRTIM_EECR3_EE7F_Pos (6U) |
#define | HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) |
#define | HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk |
#define | HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) |
#define | HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) |
#define | HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) |
#define | HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) |
#define | HRTIM_EECR3_EE8F_Pos (12U) |
#define | HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) |
#define | HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk |
#define | HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) |
#define | HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) |
#define | HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) |
#define | HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) |
#define | HRTIM_EECR3_EE9F_Pos (18U) |
#define | HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) |
#define | HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk |
#define | HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) |
#define | HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) |
#define | HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) |
#define | HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) |
#define | HRTIM_EECR3_EE10F_Pos (24U) |
#define | HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) |
#define | HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk |
#define | HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) |
#define | HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) |
#define | HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) |
#define | HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) |
#define | HRTIM_EECR3_EEVSD_Pos (30U) |
#define | HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) |
#define | HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk |
#define | HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) |
#define | HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) |
#define | HRTIM_ADC1R_AD1MC1_Pos (0U) |
#define | HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) |
#define | HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk |
#define | HRTIM_ADC1R_AD1MC2_Pos (1U) |
#define | HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) |
#define | HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk |
#define | HRTIM_ADC1R_AD1MC3_Pos (2U) |
#define | HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) |
#define | HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk |
#define | HRTIM_ADC1R_AD1MC4_Pos (3U) |
#define | HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) |
#define | HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk |
#define | HRTIM_ADC1R_AD1MPER_Pos (4U) |
#define | HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) |
#define | HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk |
#define | HRTIM_ADC1R_AD1EEV1_Pos (5U) |
#define | HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) |
#define | HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk |
#define | HRTIM_ADC1R_AD1EEV2_Pos (6U) |
#define | HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) |
#define | HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk |
#define | HRTIM_ADC1R_AD1EEV3_Pos (7U) |
#define | HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) |
#define | HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk |
#define | HRTIM_ADC1R_AD1EEV4_Pos (8U) |
#define | HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) |
#define | HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk |
#define | HRTIM_ADC1R_AD1EEV5_Pos (9U) |
#define | HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) |
#define | HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk |
#define | HRTIM_ADC1R_AD1TAC2_Pos (10U) |
#define | HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) |
#define | HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk |
#define | HRTIM_ADC1R_AD1TAC3_Pos (11U) |
#define | HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) |
#define | HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk |
#define | HRTIM_ADC1R_AD1TAC4_Pos (12U) |
#define | HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) |
#define | HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk |
#define | HRTIM_ADC1R_AD1TAPER_Pos (13U) |
#define | HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) |
#define | HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk |
#define | HRTIM_ADC1R_AD1TARST_Pos (14U) |
#define | HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) |
#define | HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk |
#define | HRTIM_ADC1R_AD1TBC2_Pos (15U) |
#define | HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) |
#define | HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk |
#define | HRTIM_ADC1R_AD1TBC3_Pos (16U) |
#define | HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) |
#define | HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk |
#define | HRTIM_ADC1R_AD1TBC4_Pos (17U) |
#define | HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) |
#define | HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk |
#define | HRTIM_ADC1R_AD1TBPER_Pos (18U) |
#define | HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) |
#define | HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk |
#define | HRTIM_ADC1R_AD1TBRST_Pos (19U) |
#define | HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) |
#define | HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk |
#define | HRTIM_ADC1R_AD1TCC2_Pos (20U) |
#define | HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) |
#define | HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk |
#define | HRTIM_ADC1R_AD1TCC3_Pos (21U) |
#define | HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) |
#define | HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk |
#define | HRTIM_ADC1R_AD1TCC4_Pos (22U) |
#define | HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) |
#define | HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk |
#define | HRTIM_ADC1R_AD1TCPER_Pos (23U) |
#define | HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) |
#define | HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk |
#define | HRTIM_ADC1R_AD1TDC2_Pos (24U) |
#define | HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) |
#define | HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk |
#define | HRTIM_ADC1R_AD1TDC3_Pos (25U) |
#define | HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) |
#define | HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk |
#define | HRTIM_ADC1R_AD1TDC4_Pos (26U) |
#define | HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) |
#define | HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk |
#define | HRTIM_ADC1R_AD1TDPER_Pos (27U) |
#define | HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) |
#define | HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk |
#define | HRTIM_ADC1R_AD1TEC2_Pos (28U) |
#define | HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) |
#define | HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk |
#define | HRTIM_ADC1R_AD1TEC3_Pos (29U) |
#define | HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) |
#define | HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk |
#define | HRTIM_ADC1R_AD1TEC4_Pos (30U) |
#define | HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) |
#define | HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk |
#define | HRTIM_ADC1R_AD1TEPER_Pos (31U) |
#define | HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) |
#define | HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk |
#define | HRTIM_ADC2R_AD2MC1_Pos (0U) |
#define | HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) |
#define | HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk |
#define | HRTIM_ADC2R_AD2MC2_Pos (1U) |
#define | HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) |
#define | HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk |
#define | HRTIM_ADC2R_AD2MC3_Pos (2U) |
#define | HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) |
#define | HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk |
#define | HRTIM_ADC2R_AD2MC4_Pos (3U) |
#define | HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) |
#define | HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk |
#define | HRTIM_ADC2R_AD2MPER_Pos (4U) |
#define | HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) |
#define | HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk |
#define | HRTIM_ADC2R_AD2EEV6_Pos (5U) |
#define | HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) |
#define | HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk |
#define | HRTIM_ADC2R_AD2EEV7_Pos (6U) |
#define | HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) |
#define | HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk |
#define | HRTIM_ADC2R_AD2EEV8_Pos (7U) |
#define | HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) |
#define | HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk |
#define | HRTIM_ADC2R_AD2EEV9_Pos (8U) |
#define | HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) |
#define | HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk |
#define | HRTIM_ADC2R_AD2EEV10_Pos (9U) |
#define | HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) |
#define | HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk |
#define | HRTIM_ADC2R_AD2TAC2_Pos (10U) |
#define | HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) |
#define | HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk |
#define | HRTIM_ADC2R_AD2TAC3_Pos (11U) |
#define | HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) |
#define | HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk |
#define | HRTIM_ADC2R_AD2TAC4_Pos (12U) |
#define | HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) |
#define | HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk |
#define | HRTIM_ADC2R_AD2TAPER_Pos (13U) |
#define | HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) |
#define | HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk |
#define | HRTIM_ADC2R_AD2TBC2_Pos (14U) |
#define | HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) |
#define | HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk |
#define | HRTIM_ADC2R_AD2TBC3_Pos (15U) |
#define | HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) |
#define | HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk |
#define | HRTIM_ADC2R_AD2TBC4_Pos (16U) |
#define | HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) |
#define | HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk |
#define | HRTIM_ADC2R_AD2TBPER_Pos (17U) |
#define | HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) |
#define | HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk |
#define | HRTIM_ADC2R_AD2TCC2_Pos (18U) |
#define | HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) |
#define | HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk |
#define | HRTIM_ADC2R_AD2TCC3_Pos (19U) |
#define | HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) |
#define | HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk |
#define | HRTIM_ADC2R_AD2TCC4_Pos (20U) |
#define | HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) |
#define | HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk |
#define | HRTIM_ADC2R_AD2TCPER_Pos (21U) |
#define | HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) |
#define | HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk |
#define | HRTIM_ADC2R_AD2TCRST_Pos (22U) |
#define | HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) |
#define | HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk |
#define | HRTIM_ADC2R_AD2TDC2_Pos (23U) |
#define | HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) |
#define | HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk |
#define | HRTIM_ADC2R_AD2TDC3_Pos (24U) |
#define | HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) |
#define | HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk |
#define | HRTIM_ADC2R_AD2TDC4_Pos (25U) |
#define | HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) |
#define | HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk |
#define | HRTIM_ADC2R_AD2TDPER_Pos (26U) |
#define | HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) |
#define | HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk |
#define | HRTIM_ADC2R_AD2TDRST_Pos (27U) |
#define | HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) |
#define | HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk |
#define | HRTIM_ADC2R_AD2TEC2_Pos (28U) |
#define | HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) |
#define | HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk |
#define | HRTIM_ADC2R_AD2TEC3_Pos (29U) |
#define | HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) |
#define | HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk |
#define | HRTIM_ADC2R_AD2TEC4_Pos (30U) |
#define | HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) |
#define | HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk |
#define | HRTIM_ADC2R_AD2TERST_Pos (31U) |
#define | HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) |
#define | HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk |
#define | HRTIM_ADC3R_AD3MC1_Pos (0U) |
#define | HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) |
#define | HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk |
#define | HRTIM_ADC3R_AD3MC2_Pos (1U) |
#define | HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) |
#define | HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk |
#define | HRTIM_ADC3R_AD3MC3_Pos (2U) |
#define | HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) |
#define | HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk |
#define | HRTIM_ADC3R_AD3MC4_Pos (3U) |
#define | HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) |
#define | HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk |
#define | HRTIM_ADC3R_AD3MPER_Pos (4U) |
#define | HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) |
#define | HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk |
#define | HRTIM_ADC3R_AD3EEV1_Pos (5U) |
#define | HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) |
#define | HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk |
#define | HRTIM_ADC3R_AD3EEV2_Pos (6U) |
#define | HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) |
#define | HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk |
#define | HRTIM_ADC3R_AD3EEV3_Pos (7U) |
#define | HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) |
#define | HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk |
#define | HRTIM_ADC3R_AD3EEV4_Pos (8U) |
#define | HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) |
#define | HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk |
#define | HRTIM_ADC3R_AD3EEV5_Pos (9U) |
#define | HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) |
#define | HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk |
#define | HRTIM_ADC3R_AD3TAC2_Pos (10U) |
#define | HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) |
#define | HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk |
#define | HRTIM_ADC3R_AD3TAC3_Pos (11U) |
#define | HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) |
#define | HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk |
#define | HRTIM_ADC3R_AD3TAC4_Pos (12U) |
#define | HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) |
#define | HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk |
#define | HRTIM_ADC3R_AD3TAPER_Pos (13U) |
#define | HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) |
#define | HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk |
#define | HRTIM_ADC3R_AD3TARST_Pos (14U) |
#define | HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) |
#define | HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk |
#define | HRTIM_ADC3R_AD3TBC2_Pos (15U) |
#define | HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) |
#define | HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk |
#define | HRTIM_ADC3R_AD3TBC3_Pos (16U) |
#define | HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) |
#define | HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk |
#define | HRTIM_ADC3R_AD3TBC4_Pos (17U) |
#define | HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) |
#define | HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk |
#define | HRTIM_ADC3R_AD3TBPER_Pos (18U) |
#define | HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) |
#define | HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk |
#define | HRTIM_ADC3R_AD3TBRST_Pos (19U) |
#define | HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) |
#define | HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk |
#define | HRTIM_ADC3R_AD3TCC2_Pos (20U) |
#define | HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) |
#define | HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk |
#define | HRTIM_ADC3R_AD3TCC3_Pos (21U) |
#define | HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) |
#define | HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk |
#define | HRTIM_ADC3R_AD3TCC4_Pos (22U) |
#define | HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) |
#define | HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk |
#define | HRTIM_ADC3R_AD3TCPER_Pos (23U) |
#define | HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) |
#define | HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk |
#define | HRTIM_ADC3R_AD3TDC2_Pos (24U) |
#define | HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) |
#define | HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk |
#define | HRTIM_ADC3R_AD3TDC3_Pos (25U) |
#define | HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) |
#define | HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk |
#define | HRTIM_ADC3R_AD3TDC4_Pos (26U) |
#define | HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) |
#define | HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk |
#define | HRTIM_ADC3R_AD3TDPER_Pos (27U) |
#define | HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) |
#define | HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk |
#define | HRTIM_ADC3R_AD3TEC2_Pos (28U) |
#define | HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) |
#define | HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk |
#define | HRTIM_ADC3R_AD3TEC3_Pos (29U) |
#define | HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) |
#define | HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk |
#define | HRTIM_ADC3R_AD3TEC4_Pos (30U) |
#define | HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) |
#define | HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk |
#define | HRTIM_ADC3R_AD3TEPER_Pos (31U) |
#define | HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) |
#define | HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk |
#define | HRTIM_ADC4R_AD4MC1_Pos (0U) |
#define | HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) |
#define | HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk |
#define | HRTIM_ADC4R_AD4MC2_Pos (1U) |
#define | HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) |
#define | HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk |
#define | HRTIM_ADC4R_AD4MC3_Pos (2U) |
#define | HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) |
#define | HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk |
#define | HRTIM_ADC4R_AD4MC4_Pos (3U) |
#define | HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) |
#define | HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk |
#define | HRTIM_ADC4R_AD4MPER_Pos (4U) |
#define | HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) |
#define | HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk |
#define | HRTIM_ADC4R_AD4EEV6_Pos (5U) |
#define | HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) |
#define | HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk |
#define | HRTIM_ADC4R_AD4EEV7_Pos (6U) |
#define | HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) |
#define | HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk |
#define | HRTIM_ADC4R_AD4EEV8_Pos (7U) |
#define | HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) |
#define | HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk |
#define | HRTIM_ADC4R_AD4EEV9_Pos (8U) |
#define | HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) |
#define | HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk |
#define | HRTIM_ADC4R_AD4EEV10_Pos (9U) |
#define | HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) |
#define | HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk |
#define | HRTIM_ADC4R_AD4TAC2_Pos (10U) |
#define | HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) |
#define | HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk |
#define | HRTIM_ADC4R_AD4TAC3_Pos (11U) |
#define | HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) |
#define | HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk |
#define | HRTIM_ADC4R_AD4TAC4_Pos (12U) |
#define | HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) |
#define | HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk |
#define | HRTIM_ADC4R_AD4TAPER_Pos (13U) |
#define | HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) |
#define | HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk |
#define | HRTIM_ADC4R_AD4TBC2_Pos (14U) |
#define | HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) |
#define | HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk |
#define | HRTIM_ADC4R_AD4TBC3_Pos (15U) |
#define | HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) |
#define | HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk |
#define | HRTIM_ADC4R_AD4TBC4_Pos (16U) |
#define | HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) |
#define | HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk |
#define | HRTIM_ADC4R_AD4TBPER_Pos (17U) |
#define | HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) |
#define | HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk |
#define | HRTIM_ADC4R_AD4TCC2_Pos (18U) |
#define | HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) |
#define | HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk |
#define | HRTIM_ADC4R_AD4TCC3_Pos (19U) |
#define | HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) |
#define | HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk |
#define | HRTIM_ADC4R_AD4TCC4_Pos (20U) |
#define | HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) |
#define | HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk |
#define | HRTIM_ADC4R_AD4TCPER_Pos (21U) |
#define | HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) |
#define | HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk |
#define | HRTIM_ADC4R_AD4TCRST_Pos (22U) |
#define | HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) |
#define | HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk |
#define | HRTIM_ADC4R_AD4TDC2_Pos (23U) |
#define | HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) |
#define | HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk |
#define | HRTIM_ADC4R_AD4TDC3_Pos (24U) |
#define | HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) |
#define | HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk |
#define | HRTIM_ADC4R_AD4TDC4_Pos (25U) |
#define | HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) |
#define | HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk |
#define | HRTIM_ADC4R_AD4TDPER_Pos (26U) |
#define | HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) |
#define | HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk |
#define | HRTIM_ADC4R_AD4TDRST_Pos (27U) |
#define | HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) |
#define | HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk |
#define | HRTIM_ADC4R_AD4TEC2_Pos (28U) |
#define | HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) |
#define | HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk |
#define | HRTIM_ADC4R_AD4TEC3_Pos (29U) |
#define | HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) |
#define | HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk |
#define | HRTIM_ADC4R_AD4TEC4_Pos (30U) |
#define | HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) |
#define | HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk |
#define | HRTIM_ADC4R_AD4TERST_Pos (31U) |
#define | HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) |
#define | HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk |
#define | HRTIM_FLTINR1_FLT1E_Pos (0U) |
#define | HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) |
#define | HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk |
#define | HRTIM_FLTINR1_FLT1P_Pos (1U) |
#define | HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) |
#define | HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk |
#define | HRTIM_FLTINR1_FLT1SRC_Pos (2U) |
#define | HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) |
#define | HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk |
#define | HRTIM_FLTINR1_FLT1F_Pos (3U) |
#define | HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) |
#define | HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk |
#define | HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) |
#define | HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) |
#define | HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) |
#define | HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) |
#define | HRTIM_FLTINR1_FLT1LCK_Pos (7U) |
#define | HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) |
#define | HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk |
#define | HRTIM_FLTINR1_FLT2E_Pos (8U) |
#define | HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) |
#define | HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk |
#define | HRTIM_FLTINR1_FLT2P_Pos (9U) |
#define | HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) |
#define | HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk |
#define | HRTIM_FLTINR1_FLT2SRC_Pos (10U) |
#define | HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) |
#define | HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk |
#define | HRTIM_FLTINR1_FLT2F_Pos (11U) |
#define | HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) |
#define | HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk |
#define | HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) |
#define | HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) |
#define | HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) |
#define | HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) |
#define | HRTIM_FLTINR1_FLT2LCK_Pos (15U) |
#define | HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) |
#define | HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk |
#define | HRTIM_FLTINR1_FLT3E_Pos (16U) |
#define | HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) |
#define | HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk |
#define | HRTIM_FLTINR1_FLT3P_Pos (17U) |
#define | HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) |
#define | HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk |
#define | HRTIM_FLTINR1_FLT3SRC_Pos (18U) |
#define | HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) |
#define | HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk |
#define | HRTIM_FLTINR1_FLT3F_Pos (19U) |
#define | HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) |
#define | HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk |
#define | HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) |
#define | HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) |
#define | HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) |
#define | HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) |
#define | HRTIM_FLTINR1_FLT3LCK_Pos (23U) |
#define | HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) |
#define | HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk |
#define | HRTIM_FLTINR1_FLT4E_Pos (24U) |
#define | HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) |
#define | HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk |
#define | HRTIM_FLTINR1_FLT4P_Pos (25U) |
#define | HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) |
#define | HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk |
#define | HRTIM_FLTINR1_FLT4SRC_Pos (26U) |
#define | HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) |
#define | HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk |
#define | HRTIM_FLTINR1_FLT4F_Pos (27U) |
#define | HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) |
#define | HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk |
#define | HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) |
#define | HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) |
#define | HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) |
#define | HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) |
#define | HRTIM_FLTINR1_FLT4LCK_Pos (31U) |
#define | HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) |
#define | HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk |
#define | HRTIM_FLTINR2_FLT5E_Pos (0U) |
#define | HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) |
#define | HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk |
#define | HRTIM_FLTINR2_FLT5P_Pos (1U) |
#define | HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) |
#define | HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk |
#define | HRTIM_FLTINR2_FLT5SRC_Pos (2U) |
#define | HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) |
#define | HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk |
#define | HRTIM_FLTINR2_FLT5F_Pos (3U) |
#define | HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) |
#define | HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk |
#define | HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) |
#define | HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) |
#define | HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) |
#define | HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) |
#define | HRTIM_FLTINR2_FLT5LCK_Pos (7U) |
#define | HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) |
#define | HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk |
#define | HRTIM_FLTINR2_FLTSD_Pos (24U) |
#define | HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) |
#define | HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk |
#define | HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) |
#define | HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) |
#define | HRTIM_BDMUPR_MCR_Pos (0U) |
#define | HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) |
#define | HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk |
#define | HRTIM_BDMUPR_MICR_Pos (1U) |
#define | HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) |
#define | HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk |
#define | HRTIM_BDMUPR_MDIER_Pos (2U) |
#define | HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) |
#define | HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk |
#define | HRTIM_BDMUPR_MCNT_Pos (3U) |
#define | HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) |
#define | HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk |
#define | HRTIM_BDMUPR_MPER_Pos (4U) |
#define | HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) |
#define | HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk |
#define | HRTIM_BDMUPR_MREP_Pos (5U) |
#define | HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) |
#define | HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk |
#define | HRTIM_BDMUPR_MCMP1_Pos (6U) |
#define | HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) |
#define | HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk |
#define | HRTIM_BDMUPR_MCMP2_Pos (7U) |
#define | HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) |
#define | HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk |
#define | HRTIM_BDMUPR_MCMP3_Pos (8U) |
#define | HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) |
#define | HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk |
#define | HRTIM_BDMUPR_MCMP4_Pos (9U) |
#define | HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) |
#define | HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk |
#define | HRTIM_BDTUPR_TIMCR_Pos (0U) |
#define | HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) |
#define | HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk |
#define | HRTIM_BDTUPR_TIMICR_Pos (1U) |
#define | HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) |
#define | HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk |
#define | HRTIM_BDTUPR_TIMDIER_Pos (2U) |
#define | HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) |
#define | HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk |
#define | HRTIM_BDTUPR_TIMCNT_Pos (3U) |
#define | HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) |
#define | HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk |
#define | HRTIM_BDTUPR_TIMPER_Pos (4U) |
#define | HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) |
#define | HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk |
#define | HRTIM_BDTUPR_TIMREP_Pos (5U) |
#define | HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) |
#define | HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk |
#define | HRTIM_BDTUPR_TIMCMP1_Pos (6U) |
#define | HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) |
#define | HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk |
#define | HRTIM_BDTUPR_TIMCMP2_Pos (7U) |
#define | HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) |
#define | HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk |
#define | HRTIM_BDTUPR_TIMCMP3_Pos (8U) |
#define | HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) |
#define | HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk |
#define | HRTIM_BDTUPR_TIMCMP4_Pos (9U) |
#define | HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) |
#define | HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk |
#define | HRTIM_BDTUPR_TIMDTR_Pos (10U) |
#define | HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) |
#define | HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk |
#define | HRTIM_BDTUPR_TIMSET1R_Pos (11U) |
#define | HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) |
#define | HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk |
#define | HRTIM_BDTUPR_TIMRST1R_Pos (12U) |
#define | HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) |
#define | HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk |
#define | HRTIM_BDTUPR_TIMSET2R_Pos (13U) |
#define | HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) |
#define | HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk |
#define | HRTIM_BDTUPR_TIMRST2R_Pos (14U) |
#define | HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) |
#define | HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk |
#define | HRTIM_BDTUPR_TIMEEFR1_Pos (15U) |
#define | HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) |
#define | HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk |
#define | HRTIM_BDTUPR_TIMEEFR2_Pos (16U) |
#define | HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) |
#define | HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk |
#define | HRTIM_BDTUPR_TIMRSTR_Pos (17U) |
#define | HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) |
#define | HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk |
#define | HRTIM_BDTUPR_TIMCHPR_Pos (18U) |
#define | HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) |
#define | HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk |
#define | HRTIM_BDTUPR_TIMOUTR_Pos (19U) |
#define | HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) |
#define | HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk |
#define | HRTIM_BDTUPR_TIMFLTR_Pos (20U) |
#define | HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) |
#define | HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk |
#define | HRTIM_BDMADR_BDMADR_Pos (0U) |
#define | HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) |
#define | HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk |
#define | RAMECC_IER_GECCDEBWIE_Pos (3U) |
#define | RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) |
#define | RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk |
#define | RAMECC_IER_GECCDEIE_Pos (2U) |
#define | RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) |
#define | RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk |
#define | RAMECC_IER_GECCSEIE_Pos (1U) |
#define | RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) |
#define | RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk |
#define | RAMECC_IER_GIE_Pos (0U) |
#define | RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) |
#define | RAMECC_IER_GIE RAMECC_IER_GIE_Msk |
#define | RAMECC_CR_ECCELEN_Pos (5U) |
#define | RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) |
#define | RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk |
#define | RAMECC_CR_ECCDEBWIE_Pos (4U) |
#define | RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) |
#define | RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk |
#define | RAMECC_CR_ECCDEIE_Pos (3U) |
#define | RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) |
#define | RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk |
#define | RAMECC_CR_ECCSEIE_Pos (2U) |
#define | RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) |
#define | RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk |
#define | RAMECC_SR_DEBWDF_Pos (2U) |
#define | RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) |
#define | RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk |
#define | RAMECC_SR_DEDF_Pos (1U) |
#define | RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) |
#define | RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk |
#define | RAMECC_SR_SEDCF_Pos (0U) |
#define | RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) |
#define | RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk |
#define | RAMECC_FAR_FADD_Pos (0U) |
#define | RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) |
#define | RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk |
#define | RAMECC_FAR_FDATAL_Pos (0U) |
#define | RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos) |
#define | RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk |
#define | RAMECC_FAR_FDATAH_Pos (0U) |
#define | RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos) |
#define | RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */ |
#define | RAMECC_FECR_FEC_Pos (0U) |
#define | RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) |
#define | RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk |
#define | MDIOS_CR_EN_Pos (0U) |
#define | MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) |
#define | MDIOS_CR_EN MDIOS_CR_EN_Msk |
#define | MDIOS_CR_WRIE_Pos (1U) |
#define | MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) |
#define | MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk |
#define | MDIOS_CR_RDIE_Pos (2U) |
#define | MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) |
#define | MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk |
#define | MDIOS_CR_EIE_Pos (3U) |
#define | MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) |
#define | MDIOS_CR_EIE MDIOS_CR_EIE_Msk |
#define | MDIOS_CR_DPC_Pos (7U) |
#define | MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) |
#define | MDIOS_CR_DPC MDIOS_CR_DPC_Msk |
#define | MDIOS_CR_PORT_ADDRESS_Pos (8U) |
#define | MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) |
#define | MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk |
#define | MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) |
#define | MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) |
#define | MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) |
#define | MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) |
#define | MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) |
#define | MDIOS_SR_PERF_Pos (0U) |
#define | MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) |
#define | MDIOS_SR_PERF MDIOS_SR_PERF_Msk |
#define | MDIOS_SR_SERF_Pos (1U) |
#define | MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) |
#define | MDIOS_SR_SERF MDIOS_SR_SERF_Msk |
#define | MDIOS_SR_TERF_Pos (2U) |
#define | MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) |
#define | MDIOS_SR_TERF MDIOS_SR_TERF_Msk |
#define | MDIOS_SR_CPERF_Pos (0U) |
#define | MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) |
#define | MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk |
#define | MDIOS_SR_CSERF_Pos (1U) |
#define | MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) |
#define | MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk |
#define | MDIOS_SR_CTERF_Pos (2U) |
#define | MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) |
#define | MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk |
#define | USB_OTG_GOTGCTL_SRQSCS_Pos (0U) |
#define | USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) |
#define | USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk |
#define | USB_OTG_GOTGCTL_SRQ_Pos (1U) |
#define | USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) |
#define | USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk |
#define | USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) |
#define | USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) |
#define | USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk |
#define | USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) |
#define | USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) |
#define | USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk |
#define | USB_OTG_GOTGCTL_AVALOEN_Pos (4U) |
#define | USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) |
#define | USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk |
#define | USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) |
#define | USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) |
#define | USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk |
#define | USB_OTG_GOTGCTL_BVALOEN_Pos (6U) |
#define | USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) |
#define | USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk |
#define | USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) |
#define | USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) |
#define | USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk |
#define | USB_OTG_GOTGCTL_HNGSCS_Pos (8U) |
#define | USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) |
#define | USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk |
#define | USB_OTG_GOTGCTL_HNPRQ_Pos (9U) |
#define | USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) |
#define | USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk |
#define | USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) |
#define | USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) |
#define | USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk |
#define | USB_OTG_GOTGCTL_DHNPEN_Pos (11U) |
#define | USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) |
#define | USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk |
#define | USB_OTG_GOTGCTL_EHEN_Pos (12U) |
#define | USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) |
#define | USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk |
#define | USB_OTG_GOTGCTL_CIDSTS_Pos (16U) |
#define | USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) |
#define | USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk |
#define | USB_OTG_GOTGCTL_DBCT_Pos (17U) |
#define | USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) |
#define | USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk |
#define | USB_OTG_GOTGCTL_ASVLD_Pos (18U) |
#define | USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) |
#define | USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk |
#define | USB_OTG_GOTGCTL_BSESVLD_Pos (19U) |
#define | USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) |
#define | USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk |
#define | USB_OTG_GOTGCTL_OTGVER_Pos (20U) |
#define | USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) |
#define | USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk |
#define | USB_OTG_GOTGCTL_CURMOD_Pos (21U) |
#define | USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) |
#define | USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk |
#define | USB_OTG_HCFG_FSLSPCS_Pos (0U) |
#define | USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) |
#define | USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk |
#define | USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) |
#define | USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) |
#define | USB_OTG_HCFG_FSLSS_Pos (2U) |
#define | USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) |
#define | USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk |
#define | USB_OTG_DCFG_DSPD_Pos (0U) |
#define | USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) |
#define | USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk |
#define | USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) |
#define | USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) |
#define | USB_OTG_DCFG_NZLSOHSK_Pos (2U) |
#define | USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) |
#define | USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk |
#define | USB_OTG_DCFG_DAD_Pos (4U) |
#define | USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk |
#define | USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) |
#define | USB_OTG_DCFG_PFIVL_Pos (11U) |
#define | USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) |
#define | USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk |
#define | USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) |
#define | USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) |
#define | USB_OTG_DCFG_XCVRDLY_Pos (14U) |
#define | USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) |
#define | USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk |
#define | USB_OTG_DCFG_ERRATIM_Pos (15U) |
#define | USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) |
#define | USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk |
#define | USB_OTG_DCFG_PERSCHIVL_Pos (24U) |
#define | USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) |
#define | USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk |
#define | USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) |
#define | USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) |
#define | USB_OTG_PCGCR_STPPCLK_Pos (0U) |
#define | USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) |
#define | USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk |
#define | USB_OTG_PCGCR_GATEHCLK_Pos (1U) |
#define | USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) |
#define | USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk |
#define | USB_OTG_PCGCR_PHYSUSP_Pos (4U) |
#define | USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) |
#define | USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk |
#define | USB_OTG_GOTGINT_SEDET_Pos (2U) |
#define | USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) |
#define | USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk |
#define | USB_OTG_GOTGINT_SRSSCHG_Pos (8U) |
#define | USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) |
#define | USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk |
#define | USB_OTG_GOTGINT_HNSSCHG_Pos (9U) |
#define | USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) |
#define | USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk |
#define | USB_OTG_GOTGINT_HNGDET_Pos (17U) |
#define | USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) |
#define | USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk |
#define | USB_OTG_GOTGINT_ADTOCHG_Pos (18U) |
#define | USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) |
#define | USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk |
#define | USB_OTG_GOTGINT_DBCDNE_Pos (19U) |
#define | USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) |
#define | USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk |
#define | USB_OTG_DCTL_RWUSIG_Pos (0U) |
#define | USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) |
#define | USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk |
#define | USB_OTG_DCTL_SDIS_Pos (1U) |
#define | USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) |
#define | USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk |
#define | USB_OTG_DCTL_GINSTS_Pos (2U) |
#define | USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) |
#define | USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk |
#define | USB_OTG_DCTL_GONSTS_Pos (3U) |
#define | USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) |
#define | USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk |
#define | USB_OTG_DCTL_TCTL_Pos (4U) |
#define | USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) |
#define | USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk |
#define | USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) |
#define | USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) |
#define | USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) |
#define | USB_OTG_DCTL_SGINAK_Pos (7U) |
#define | USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) |
#define | USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk |
#define | USB_OTG_DCTL_CGINAK_Pos (8U) |
#define | USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) |
#define | USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk |
#define | USB_OTG_DCTL_SGONAK_Pos (9U) |
#define | USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) |
#define | USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk |
#define | USB_OTG_DCTL_CGONAK_Pos (10U) |
#define | USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) |
#define | USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk |
#define | USB_OTG_DCTL_POPRGDNE_Pos (11U) |
#define | USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) |
#define | USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk |
#define | USB_OTG_DCTL_ENCONTONBNA_Pos (17U) |
#define | USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) |
#define | USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk |
#define | USB_OTG_DCTL_DSBESLRJCT_Pos (18U) |
#define | USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) |
#define | USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk |
#define | USB_OTG_HFIR_FRIVL_Pos (0U) |
#define | USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) |
#define | USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk |
#define | USB_OTG_HFNUM_FRNUM_Pos (0U) |
#define | USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) |
#define | USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk |
#define | USB_OTG_HFNUM_FTREM_Pos (16U) |
#define | USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) |
#define | USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk |
#define | USB_OTG_DSTS_SUSPSTS_Pos (0U) |
#define | USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) |
#define | USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk |
#define | USB_OTG_DSTS_ENUMSPD_Pos (1U) |
#define | USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) |
#define | USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk |
#define | USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) |
#define | USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) |
#define | USB_OTG_DSTS_EERR_Pos (3U) |
#define | USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) |
#define | USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk |
#define | USB_OTG_DSTS_FNSOF_Pos (8U) |
#define | USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) |
#define | USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk |
#define | USB_OTG_GAHBCFG_GINT_Pos (0U) |
#define | USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) |
#define | USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk |
#define | USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) |
#define | USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
#define | USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk |
#define | USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
#define | USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
#define | USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
#define | USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
#define | USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
#define | USB_OTG_GAHBCFG_DMAEN_Pos (5U) |
#define | USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) |
#define | USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk |
#define | USB_OTG_GAHBCFG_TXFELVL_Pos (7U) |
#define | USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) |
#define | USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk |
#define | USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) |
#define | USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) |
#define | USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk |
#define | USB_OTG_GUSBCFG_TOCAL_Pos (0U) |
#define | USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) |
#define | USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk |
#define | USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) |
#define | USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) |
#define | USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) |
#define | USB_OTG_GUSBCFG_PHYSEL_Pos (6U) |
#define | USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) |
#define | USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk |
#define | USB_OTG_GUSBCFG_SRPCAP_Pos (8U) |
#define | USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) |
#define | USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk |
#define | USB_OTG_GUSBCFG_HNPCAP_Pos (9U) |
#define | USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) |
#define | USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk |
#define | USB_OTG_GUSBCFG_TRDT_Pos (10U) |
#define | USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) |
#define | USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk |
#define | USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) |
#define | USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) |
#define | USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) |
#define | USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) |
#define | USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) |
#define | USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) |
#define | USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk |
#define | USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) |
#define | USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) |
#define | USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk |
#define | USB_OTG_GUSBCFG_ULPIAR_Pos (18U) |
#define | USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) |
#define | USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk |
#define | USB_OTG_GUSBCFG_ULPICSM_Pos (19U) |
#define | USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) |
#define | USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk |
#define | USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) |
#define | USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) |
#define | USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk |
#define | USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) |
#define | USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) |
#define | USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk |
#define | USB_OTG_GUSBCFG_TSDPS_Pos (22U) |
#define | USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) |
#define | USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk |
#define | USB_OTG_GUSBCFG_PCCI_Pos (23U) |
#define | USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) |
#define | USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk |
#define | USB_OTG_GUSBCFG_PTCI_Pos (24U) |
#define | USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) |
#define | USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk |
#define | USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) |
#define | USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) |
#define | USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk |
#define | USB_OTG_GUSBCFG_FHMOD_Pos (29U) |
#define | USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) |
#define | USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk |
#define | USB_OTG_GUSBCFG_FDMOD_Pos (30U) |
#define | USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) |
#define | USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk |
#define | USB_OTG_GUSBCFG_CTXPKT_Pos (31U) |
#define | USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) |
#define | USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk |
#define | USB_OTG_GRSTCTL_CSRST_Pos (0U) |
#define | USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) |
#define | USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk |
#define | USB_OTG_GRSTCTL_HSRST_Pos (1U) |
#define | USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) |
#define | USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk |
#define | USB_OTG_GRSTCTL_FCRST_Pos (2U) |
#define | USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) |
#define | USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk |
#define | USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) |
#define | USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) |
#define | USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk |
#define | USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) |
#define | USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) |
#define | USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk |
#define | USB_OTG_GRSTCTL_TXFNUM_Pos (6U) |
#define | USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) |
#define | USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk |
#define | USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) |
#define | USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) |
#define | USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) |
#define | USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) |
#define | USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) |
#define | USB_OTG_GRSTCTL_DMAREQ_Pos (30U) |
#define | USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) |
#define | USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk |
#define | USB_OTG_GRSTCTL_AHBIDL_Pos (31U) |
#define | USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) |
#define | USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk |
#define | USB_OTG_DIEPMSK_XFRCM_Pos (0U) |
#define | USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) |
#define | USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk |
#define | USB_OTG_DIEPMSK_EPDM_Pos (1U) |
#define | USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) |
#define | USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk |
#define | USB_OTG_DIEPMSK_TOM_Pos (3U) |
#define | USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) |
#define | USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk |
#define | USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) |
#define | USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) |
#define | USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk |
#define | USB_OTG_DIEPMSK_INEPNMM_Pos (5U) |
#define | USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) |
#define | USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk |
#define | USB_OTG_DIEPMSK_INEPNEM_Pos (6U) |
#define | USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) |
#define | USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk |
#define | USB_OTG_DIEPMSK_TXFURM_Pos (8U) |
#define | USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) |
#define | USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk |
#define | USB_OTG_DIEPMSK_BIM_Pos (9U) |
#define | USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) |
#define | USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk |
#define | USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) |
#define | USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) |
#define | USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk |
#define | USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) |
#define | USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk |
#define | USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) |
#define | USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk |
#define | USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
#define | USB_OTG_HAINT_HAINT_Pos (0U) |
#define | USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) |
#define | USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk |
#define | USB_OTG_DOEPMSK_XFRCM_Pos (0U) |
#define | USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) |
#define | USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk |
#define | USB_OTG_DOEPMSK_EPDM_Pos (1U) |
#define | USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) |
#define | USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk |
#define | USB_OTG_DOEPMSK_AHBERRM_Pos (2U) |
#define | USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) |
#define | USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk |
#define | USB_OTG_DOEPMSK_STUPM_Pos (3U) |
#define | USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) |
#define | USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk |
#define | USB_OTG_DOEPMSK_OTEPDM_Pos (4U) |
#define | USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) |
#define | USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk |
#define | USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) |
#define | USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) |
#define | USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk |
#define | USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) |
#define | USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) |
#define | USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk |
#define | USB_OTG_DOEPMSK_OPEM_Pos (8U) |
#define | USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) |
#define | USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk |
#define | USB_OTG_DOEPMSK_BOIM_Pos (9U) |
#define | USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) |
#define | USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk |
#define | USB_OTG_DOEPMSK_BERRM_Pos (12U) |
#define | USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) |
#define | USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk |
#define | USB_OTG_DOEPMSK_NAKM_Pos (13U) |
#define | USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) |
#define | USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk |
#define | USB_OTG_DOEPMSK_NYETM_Pos (14U) |
#define | USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) |
#define | USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk |
#define | USB_OTG_GINTSTS_CMOD_Pos (0U) |
#define | USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) |
#define | USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk |
#define | USB_OTG_GINTSTS_MMIS_Pos (1U) |
#define | USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) |
#define | USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk |
#define | USB_OTG_GINTSTS_OTGINT_Pos (2U) |
#define | USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) |
#define | USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk |
#define | USB_OTG_GINTSTS_SOF_Pos (3U) |
#define | USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) |
#define | USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk |
#define | USB_OTG_GINTSTS_RXFLVL_Pos (4U) |
#define | USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) |
#define | USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk |
#define | USB_OTG_GINTSTS_NPTXFE_Pos (5U) |
#define | USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) |
#define | USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk |
#define | USB_OTG_GINTSTS_GINAKEFF_Pos (6U) |
#define | USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) |
#define | USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk |
#define | USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) |
#define | USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) |
#define | USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk |
#define | USB_OTG_GINTSTS_ESUSP_Pos (10U) |
#define | USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) |
#define | USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk |
#define | USB_OTG_GINTSTS_USBSUSP_Pos (11U) |
#define | USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) |
#define | USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk |
#define | USB_OTG_GINTSTS_USBRST_Pos (12U) |
#define | USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) |
#define | USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk |
#define | USB_OTG_GINTSTS_ENUMDNE_Pos (13U) |
#define | USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) |
#define | USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk |
#define | USB_OTG_GINTSTS_ISOODRP_Pos (14U) |
#define | USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) |
#define | USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk |
#define | USB_OTG_GINTSTS_EOPF_Pos (15U) |
#define | USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) |
#define | USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk |
#define | USB_OTG_GINTSTS_IEPINT_Pos (18U) |
#define | USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) |
#define | USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk |
#define | USB_OTG_GINTSTS_OEPINT_Pos (19U) |
#define | USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) |
#define | USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk |
#define | USB_OTG_GINTSTS_IISOIXFR_Pos (20U) |
#define | USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) |
#define | USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk |
#define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) |
#define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) |
#define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk |
#define | USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) |
#define | USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) |
#define | USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk |
#define | USB_OTG_GINTSTS_RSTDET_Pos (23U) |
#define | USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) |
#define | USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk |
#define | USB_OTG_GINTSTS_HPRTINT_Pos (24U) |
#define | USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) |
#define | USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk |
#define | USB_OTG_GINTSTS_HCINT_Pos (25U) |
#define | USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) |
#define | USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk |
#define | USB_OTG_GINTSTS_PTXFE_Pos (26U) |
#define | USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) |
#define | USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk |
#define | USB_OTG_GINTSTS_LPMINT_Pos (27U) |
#define | USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) |
#define | USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk |
#define | USB_OTG_GINTSTS_CIDSCHG_Pos (28U) |
#define | USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) |
#define | USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk |
#define | USB_OTG_GINTSTS_DISCINT_Pos (29U) |
#define | USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) |
#define | USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk |
#define | USB_OTG_GINTSTS_SRQINT_Pos (30U) |
#define | USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) |
#define | USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk |
#define | USB_OTG_GINTSTS_WKUINT_Pos (31U) |
#define | USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) |
#define | USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk |
#define | USB_OTG_GINTMSK_MMISM_Pos (1U) |
#define | USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) |
#define | USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk |
#define | USB_OTG_GINTMSK_OTGINT_Pos (2U) |
#define | USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) |
#define | USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk |
#define | USB_OTG_GINTMSK_SOFM_Pos (3U) |
#define | USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) |
#define | USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk |
#define | USB_OTG_GINTMSK_RXFLVLM_Pos (4U) |
#define | USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) |
#define | USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk |
#define | USB_OTG_GINTMSK_NPTXFEM_Pos (5U) |
#define | USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) |
#define | USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk |
#define | USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) |
#define | USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) |
#define | USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk |
#define | USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) |
#define | USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) |
#define | USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk |
#define | USB_OTG_GINTMSK_ESUSPM_Pos (10U) |
#define | USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) |
#define | USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk |
#define | USB_OTG_GINTMSK_USBSUSPM_Pos (11U) |
#define | USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) |
#define | USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk |
#define | USB_OTG_GINTMSK_USBRST_Pos (12U) |
#define | USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) |
#define | USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk |
#define | USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) |
#define | USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) |
#define | USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk |
#define | USB_OTG_GINTMSK_ISOODRPM_Pos (14U) |
#define | USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) |
#define | USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk |
#define | USB_OTG_GINTMSK_EOPFM_Pos (15U) |
#define | USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) |
#define | USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk |
#define | USB_OTG_GINTMSK_EPMISM_Pos (17U) |
#define | USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) |
#define | USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk |
#define | USB_OTG_GINTMSK_IEPINT_Pos (18U) |
#define | USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) |
#define | USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk |
#define | USB_OTG_GINTMSK_OEPINT_Pos (19U) |
#define | USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) |
#define | USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk |
#define | USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) |
#define | USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) |
#define | USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk |
#define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) |
#define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) |
#define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk |
#define | USB_OTG_GINTMSK_FSUSPM_Pos (22U) |
#define | USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) |
#define | USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk |
#define | USB_OTG_GINTMSK_RSTDEM_Pos (23U) |
#define | USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) |
#define | USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk |
#define | USB_OTG_GINTMSK_PRTIM_Pos (24U) |
#define | USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) |
#define | USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk |
#define | USB_OTG_GINTMSK_HCIM_Pos (25U) |
#define | USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) |
#define | USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk |
#define | USB_OTG_GINTMSK_PTXFEM_Pos (26U) |
#define | USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) |
#define | USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk |
#define | USB_OTG_GINTMSK_LPMINTM_Pos (27U) |
#define | USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) |
#define | USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk |
#define | USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) |
#define | USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) |
#define | USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk |
#define | USB_OTG_GINTMSK_DISCINT_Pos (29U) |
#define | USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) |
#define | USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk |
#define | USB_OTG_GINTMSK_SRQIM_Pos (30U) |
#define | USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) |
#define | USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk |
#define | USB_OTG_GINTMSK_WUIM_Pos (31U) |
#define | USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) |
#define | USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk |
#define | USB_OTG_DAINT_IEPINT_Pos (0U) |
#define | USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) |
#define | USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk |
#define | USB_OTG_DAINT_OEPINT_Pos (16U) |
#define | USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) |
#define | USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk |
#define | USB_OTG_HAINTMSK_HAINTM_Pos (0U) |
#define | USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) |
#define | USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk |
#define | USB_OTG_GRXSTSP_EPNUM_Pos (0U) |
#define | USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) |
#define | USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk |
#define | USB_OTG_GRXSTSP_BCNT_Pos (4U) |
#define | USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) |
#define | USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk |
#define | USB_OTG_GRXSTSP_DPID_Pos (15U) |
#define | USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) |
#define | USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk |
#define | USB_OTG_GRXSTSP_PKTSTS_Pos (17U) |
#define | USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) |
#define | USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk |
#define | USB_OTG_DAINTMSK_IEPM_Pos (0U) |
#define | USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) |
#define | USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk |
#define | USB_OTG_DAINTMSK_OEPM_Pos (16U) |
#define | USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) |
#define | USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk |
#define | USB_OTG_CHNUM_Pos (0U) |
#define | USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) |
#define | USB_OTG_CHNUM USB_OTG_CHNUM_Msk |
#define | USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) |
#define | USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) |
#define | USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) |
#define | USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) |
#define | USB_OTG_BCNT_Pos (4U) |
#define | USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) |
#define | USB_OTG_BCNT USB_OTG_BCNT_Msk |
#define | USB_OTG_DPID_Pos (15U) |
#define | USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) |
#define | USB_OTG_DPID USB_OTG_DPID_Msk |
#define | USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) |
#define | USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) |
#define | USB_OTG_PKTSTS_Pos (17U) |
#define | USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) |
#define | USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk |
#define | USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) |
#define | USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) |
#define | USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) |
#define | USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) |
#define | USB_OTG_EPNUM_Pos (0U) |
#define | USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) |
#define | USB_OTG_EPNUM USB_OTG_EPNUM_Msk |
#define | USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) |
#define | USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) |
#define | USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) |
#define | USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) |
#define | USB_OTG_FRMNUM_Pos (21U) |
#define | USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) |
#define | USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk |
#define | USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) |
#define | USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) |
#define | USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) |
#define | USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) |
#define | USB_OTG_GRXFSIZ_RXFD_Pos (0U) |
#define | USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) |
#define | USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk |
#define | USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) |
#define | USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) |
#define | USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk |
#define | USB_OTG_NPTXFSA_Pos (0U) |
#define | USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) |
#define | USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk |
#define | USB_OTG_NPTXFD_Pos (16U) |
#define | USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) |
#define | USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk |
#define | USB_OTG_TX0FSA_Pos (0U) |
#define | USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) |
#define | USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk |
#define | USB_OTG_TX0FD_Pos (16U) |
#define | USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) |
#define | USB_OTG_TX0FD USB_OTG_TX0FD_Msk |
#define | USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) |
#define | USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) |
#define | USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk |
#define | USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) |
#define | USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
#define | USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) |
#define | USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) |
#define | USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk |
#define | USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) |
#define | USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) |
#define | USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk |
#define | USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk |
#define | USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHREN_Pos (16U) |
#define | USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk |
#define | USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk |
#define | USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
#define | USB_OTG_DTHRCTL_ARPEN_Pos (27U) |
#define | USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) |
#define | USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk |
#define | USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) |
#define | USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) |
#define | USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk |
#define | USB_OTG_DEACHINT_IEP1INT_Pos (1U) |
#define | USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) |
#define | USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk |
#define | USB_OTG_DEACHINT_OEP1INT_Pos (17U) |
#define | USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) |
#define | USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk |
#define | USB_OTG_GCCFG_DCDET_Pos (0U) |
#define | USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) |
#define | USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk |
#define | USB_OTG_GCCFG_PDET_Pos (1U) |
#define | USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) |
#define | USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk |
#define | USB_OTG_GCCFG_SDET_Pos (2U) |
#define | USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) |
#define | USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk |
#define | USB_OTG_GCCFG_PS2DET_Pos (3U) |
#define | USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) |
#define | USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk |
#define | USB_OTG_GCCFG_PWRDWN_Pos (16U) |
#define | USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) |
#define | USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk |
#define | USB_OTG_GCCFG_BCDEN_Pos (17U) |
#define | USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) |
#define | USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk |
#define | USB_OTG_GCCFG_DCDEN_Pos (18U) |
#define | USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) |
#define | USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk |
#define | USB_OTG_GCCFG_PDEN_Pos (19U) |
#define | USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) |
#define | USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk |
#define | USB_OTG_GCCFG_SDEN_Pos (20U) |
#define | USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) |
#define | USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk |
#define | USB_OTG_GCCFG_VBDEN_Pos (21U) |
#define | USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) |
#define | USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk |
#define | USB_OTG_GPWRDN_ADPMEN_Pos (0U) |
#define | USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) |
#define | USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk |
#define | USB_OTG_GPWRDN_ADPIF_Pos (23U) |
#define | USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) |
#define | USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk |
#define | USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) |
#define | USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) |
#define | USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk |
#define | USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) |
#define | USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) |
#define | USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk |
#define | USB_OTG_CID_PRODUCT_ID_Pos (0U) |
#define | USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) |
#define | USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk |
#define | USB_OTG_GLPMCFG_LPMEN_Pos (0U) |
#define | USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) |
#define | USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk |
#define | USB_OTG_GLPMCFG_LPMACK_Pos (1U) |
#define | USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) |
#define | USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk |
#define | USB_OTG_GLPMCFG_BESL_Pos (2U) |
#define | USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) |
#define | USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk |
#define | USB_OTG_GLPMCFG_REMWAKE_Pos (6U) |
#define | USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) |
#define | USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk |
#define | USB_OTG_GLPMCFG_L1SSEN_Pos (7U) |
#define | USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) |
#define | USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk |
#define | USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) |
#define | USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) |
#define | USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk |
#define | USB_OTG_GLPMCFG_L1DSEN_Pos (12U) |
#define | USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) |
#define | USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk |
#define | USB_OTG_GLPMCFG_LPMRSP_Pos (13U) |
#define | USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) |
#define | USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk |
#define | USB_OTG_GLPMCFG_SLPSTS_Pos (15U) |
#define | USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) |
#define | USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk |
#define | USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) |
#define | USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) |
#define | USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk |
#define | USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) |
#define | USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) |
#define | USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk |
#define | USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) |
#define | USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) |
#define | USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk |
#define | USB_OTG_GLPMCFG_SNDLPM_Pos (24U) |
#define | USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) |
#define | USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk |
#define | USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) |
#define | USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) |
#define | USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk |
#define | USB_OTG_GLPMCFG_ENBESL_Pos (28U) |
#define | USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) |
#define | USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk |
#define | USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) |
#define | USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk |
#define | USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) |
#define | USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk |
#define | USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) |
#define | USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk |
#define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) |
#define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) |
#define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk |
#define | USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) |
#define | USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk |
#define | USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) |
#define | USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk |
#define | USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) |
#define | USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk |
#define | USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) |
#define | USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk |
#define | USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) |
#define | USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) |
#define | USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk |
#define | USB_OTG_HPRT_PCSTS_Pos (0U) |
#define | USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) |
#define | USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk |
#define | USB_OTG_HPRT_PCDET_Pos (1U) |
#define | USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) |
#define | USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk |
#define | USB_OTG_HPRT_PENA_Pos (2U) |
#define | USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) |
#define | USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk |
#define | USB_OTG_HPRT_PENCHNG_Pos (3U) |
#define | USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) |
#define | USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk |
#define | USB_OTG_HPRT_POCA_Pos (4U) |
#define | USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) |
#define | USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk |
#define | USB_OTG_HPRT_POCCHNG_Pos (5U) |
#define | USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) |
#define | USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk |
#define | USB_OTG_HPRT_PRES_Pos (6U) |
#define | USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) |
#define | USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk |
#define | USB_OTG_HPRT_PSUSP_Pos (7U) |
#define | USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) |
#define | USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk |
#define | USB_OTG_HPRT_PRST_Pos (8U) |
#define | USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) |
#define | USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk |
#define | USB_OTG_HPRT_PLSTS_Pos (10U) |
#define | USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) |
#define | USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk |
#define | USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) |
#define | USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) |
#define | USB_OTG_HPRT_PPWR_Pos (12U) |
#define | USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) |
#define | USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk |
#define | USB_OTG_HPRT_PTCTL_Pos (13U) |
#define | USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) |
#define | USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk |
#define | USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) |
#define | USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) |
#define | USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) |
#define | USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) |
#define | USB_OTG_HPRT_PSPD_Pos (17U) |
#define | USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) |
#define | USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk |
#define | USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) |
#define | USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) |
#define | USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) |
#define | USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk |
#define | USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) |
#define | USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk |
#define | USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) |
#define | USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk |
#define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) |
#define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) |
#define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk |
#define | USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) |
#define | USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk |
#define | USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) |
#define | USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk |
#define | USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) |
#define | USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk |
#define | USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) |
#define | USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk |
#define | USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) |
#define | USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk |
#define | USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) |
#define | USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk |
#define | USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) |
#define | USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) |
#define | USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk |
#define | USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) |
#define | USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) |
#define | USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk |
#define | USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) |
#define | USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) |
#define | USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk |
#define | USB_OTG_DIEPCTL_MPSIZ_Pos (0U) |
#define | USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) |
#define | USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk |
#define | USB_OTG_DIEPCTL_USBAEP_Pos (15U) |
#define | USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) |
#define | USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk |
#define | USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) |
#define | USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) |
#define | USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk |
#define | USB_OTG_DIEPCTL_NAKSTS_Pos (17U) |
#define | USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) |
#define | USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk |
#define | USB_OTG_DIEPCTL_EPTYP_Pos (18U) |
#define | USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) |
#define | USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk |
#define | USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) |
#define | USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) |
#define | USB_OTG_DIEPCTL_STALL_Pos (21U) |
#define | USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) |
#define | USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk |
#define | USB_OTG_DIEPCTL_TXFNUM_Pos (22U) |
#define | USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) |
#define | USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk |
#define | USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) |
#define | USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) |
#define | USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) |
#define | USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) |
#define | USB_OTG_DIEPCTL_CNAK_Pos (26U) |
#define | USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) |
#define | USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk |
#define | USB_OTG_DIEPCTL_SNAK_Pos (27U) |
#define | USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) |
#define | USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk |
#define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) |
#define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) |
#define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk |
#define | USB_OTG_DIEPCTL_SODDFRM_Pos (29U) |
#define | USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) |
#define | USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk |
#define | USB_OTG_DIEPCTL_EPDIS_Pos (30U) |
#define | USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) |
#define | USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk |
#define | USB_OTG_DIEPCTL_EPENA_Pos (31U) |
#define | USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) |
#define | USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk |
#define | USB_OTG_HCCHAR_MPSIZ_Pos (0U) |
#define | USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) |
#define | USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk |
#define | USB_OTG_HCCHAR_EPNUM_Pos (11U) |
#define | USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) |
#define | USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk |
#define | USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) |
#define | USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) |
#define | USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) |
#define | USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) |
#define | USB_OTG_HCCHAR_EPDIR_Pos (15U) |
#define | USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) |
#define | USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk |
#define | USB_OTG_HCCHAR_LSDEV_Pos (17U) |
#define | USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) |
#define | USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk |
#define | USB_OTG_HCCHAR_EPTYP_Pos (18U) |
#define | USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) |
#define | USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk |
#define | USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) |
#define | USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) |
#define | USB_OTG_HCCHAR_MC_Pos (20U) |
#define | USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) |
#define | USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk |
#define | USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) |
#define | USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) |
#define | USB_OTG_HCCHAR_DAD_Pos (22U) |
#define | USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk |
#define | USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) |
#define | USB_OTG_HCCHAR_ODDFRM_Pos (29U) |
#define | USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) |
#define | USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk |
#define | USB_OTG_HCCHAR_CHDIS_Pos (30U) |
#define | USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) |
#define | USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk |
#define | USB_OTG_HCCHAR_CHENA_Pos (31U) |
#define | USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) |
#define | USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk |
#define | USB_OTG_HCSPLT_PRTADDR_Pos (0U) |
#define | USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk |
#define | USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_Pos (7U) |
#define | USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk |
#define | USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) |
#define | USB_OTG_HCSPLT_XACTPOS_Pos (14U) |
#define | USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) |
#define | USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk |
#define | USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) |
#define | USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) |
#define | USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) |
#define | USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) |
#define | USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk |
#define | USB_OTG_HCSPLT_SPLITEN_Pos (31U) |
#define | USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) |
#define | USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk |
#define | USB_OTG_HCINT_XFRC_Pos (0U) |
#define | USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) |
#define | USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk |
#define | USB_OTG_HCINT_CHH_Pos (1U) |
#define | USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) |
#define | USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk |
#define | USB_OTG_HCINT_AHBERR_Pos (2U) |
#define | USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) |
#define | USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk |
#define | USB_OTG_HCINT_STALL_Pos (3U) |
#define | USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) |
#define | USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk |
#define | USB_OTG_HCINT_NAK_Pos (4U) |
#define | USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) |
#define | USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk |
#define | USB_OTG_HCINT_ACK_Pos (5U) |
#define | USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) |
#define | USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk |
#define | USB_OTG_HCINT_NYET_Pos (6U) |
#define | USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) |
#define | USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk |
#define | USB_OTG_HCINT_TXERR_Pos (7U) |
#define | USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) |
#define | USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk |
#define | USB_OTG_HCINT_BBERR_Pos (8U) |
#define | USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) |
#define | USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk |
#define | USB_OTG_HCINT_FRMOR_Pos (9U) |
#define | USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) |
#define | USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk |
#define | USB_OTG_HCINT_DTERR_Pos (10U) |
#define | USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) |
#define | USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk |
#define | USB_OTG_DIEPINT_XFRC_Pos (0U) |
#define | USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) |
#define | USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk |
#define | USB_OTG_DIEPINT_EPDISD_Pos (1U) |
#define | USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) |
#define | USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk |
#define | USB_OTG_DIEPINT_AHBERR_Pos (2U) |
#define | USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) |
#define | USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk |
#define | USB_OTG_DIEPINT_TOC_Pos (3U) |
#define | USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) |
#define | USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk |
#define | USB_OTG_DIEPINT_ITTXFE_Pos (4U) |
#define | USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) |
#define | USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk |
#define | USB_OTG_DIEPINT_INEPNM_Pos (5U) |
#define | USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) |
#define | USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk |
#define | USB_OTG_DIEPINT_INEPNE_Pos (6U) |
#define | USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) |
#define | USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk |
#define | USB_OTG_DIEPINT_TXFE_Pos (7U) |
#define | USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) |
#define | USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk |
#define | USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) |
#define | USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) |
#define | USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk |
#define | USB_OTG_DIEPINT_BNA_Pos (9U) |
#define | USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) |
#define | USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk |
#define | USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) |
#define | USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) |
#define | USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk |
#define | USB_OTG_DIEPINT_BERR_Pos (12U) |
#define | USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) |
#define | USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk |
#define | USB_OTG_DIEPINT_NAK_Pos (13U) |
#define | USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) |
#define | USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk |
#define | USB_OTG_HCINTMSK_XFRCM_Pos (0U) |
#define | USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) |
#define | USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk |
#define | USB_OTG_HCINTMSK_CHHM_Pos (1U) |
#define | USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) |
#define | USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk |
#define | USB_OTG_HCINTMSK_AHBERR_Pos (2U) |
#define | USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) |
#define | USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk |
#define | USB_OTG_HCINTMSK_STALLM_Pos (3U) |
#define | USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) |
#define | USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk |
#define | USB_OTG_HCINTMSK_NAKM_Pos (4U) |
#define | USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) |
#define | USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk |
#define | USB_OTG_HCINTMSK_ACKM_Pos (5U) |
#define | USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) |
#define | USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk |
#define | USB_OTG_HCINTMSK_NYET_Pos (6U) |
#define | USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) |
#define | USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk |
#define | USB_OTG_HCINTMSK_TXERRM_Pos (7U) |
#define | USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) |
#define | USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk |
#define | USB_OTG_HCINTMSK_BBERRM_Pos (8U) |
#define | USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) |
#define | USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk |
#define | USB_OTG_HCINTMSK_FRMORM_Pos (9U) |
#define | USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) |
#define | USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk |
#define | USB_OTG_HCINTMSK_DTERRM_Pos (10U) |
#define | USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) |
#define | USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk |
#define | USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) |
#define | USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) |
#define | USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk |
#define | USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) |
#define | USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
#define | USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk |
#define | USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) |
#define | USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) |
#define | USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk |
#define | USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) |
#define | USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) |
#define | USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk |
#define | USB_OTG_HCTSIZ_PKTCNT_Pos (19U) |
#define | USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) |
#define | USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk |
#define | USB_OTG_HCTSIZ_DOPING_Pos (31U) |
#define | USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) |
#define | USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk |
#define | USB_OTG_HCTSIZ_DPID_Pos (29U) |
#define | USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) |
#define | USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk |
#define | USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) |
#define | USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) |
#define | USB_OTG_DIEPDMA_DMAADDR_Pos (0U) |
#define | USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) |
#define | USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk |
#define | USB_OTG_HCDMA_DMAADDR_Pos (0U) |
#define | USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) |
#define | USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk |
#define | USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) |
#define | USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) |
#define | USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk |
#define | USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) |
#define | USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) |
#define | USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk |
#define | USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) |
#define | USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) |
#define | USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk |
#define | USB_OTG_DOEPCTL_MPSIZ_Pos (0U) |
#define | USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) |
#define | USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ |
#define | USB_OTG_DOEPCTL_USBAEP_Pos (15U) |
#define | USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) |
#define | USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk |
#define | USB_OTG_DOEPCTL_NAKSTS_Pos (17U) |
#define | USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) |
#define | USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk |
#define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) |
#define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) |
#define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk |
#define | USB_OTG_DOEPCTL_SODDFRM_Pos (29U) |
#define | USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) |
#define | USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk |
#define | USB_OTG_DOEPCTL_EPTYP_Pos (18U) |
#define | USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) |
#define | USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk |
#define | USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) |
#define | USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) |
#define | USB_OTG_DOEPCTL_SNPM_Pos (20U) |
#define | USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) |
#define | USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk |
#define | USB_OTG_DOEPCTL_STALL_Pos (21U) |
#define | USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) |
#define | USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk |
#define | USB_OTG_DOEPCTL_CNAK_Pos (26U) |
#define | USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) |
#define | USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk |
#define | USB_OTG_DOEPCTL_SNAK_Pos (27U) |
#define | USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) |
#define | USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk |
#define | USB_OTG_DOEPCTL_EPDIS_Pos (30U) |
#define | USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) |
#define | USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk |
#define | USB_OTG_DOEPCTL_EPENA_Pos (31U) |
#define | USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) |
#define | USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk |
#define | USB_OTG_DOEPINT_XFRC_Pos (0U) |
#define | USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) |
#define | USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk |
#define | USB_OTG_DOEPINT_EPDISD_Pos (1U) |
#define | USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) |
#define | USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk |
#define | USB_OTG_DOEPINT_AHBERR_Pos (2U) |
#define | USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) |
#define | USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk |
#define | USB_OTG_DOEPINT_STUP_Pos (3U) |
#define | USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) |
#define | USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk |
#define | USB_OTG_DOEPINT_OTEPDIS_Pos (4U) |
#define | USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) |
#define | USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk |
#define | USB_OTG_DOEPINT_OTEPSPR_Pos (5U) |
#define | USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) |
#define | USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk |
#define | USB_OTG_DOEPINT_B2BSTUP_Pos (6U) |
#define | USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) |
#define | USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk |
#define | USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) |
#define | USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) |
#define | USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk |
#define | USB_OTG_DOEPINT_BERR_Pos (12U) |
#define | USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) |
#define | USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk |
#define | USB_OTG_DOEPINT_NAK_Pos (13U) |
#define | USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) |
#define | USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk |
#define | USB_OTG_DOEPINT_NYET_Pos (14U) |
#define | USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) |
#define | USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk |
#define | USB_OTG_DOEPINT_STPKTRX_Pos (15U) |
#define | USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) |
#define | USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk |
#define | USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) |
#define | USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) |
#define | USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk |
#define | USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) |
#define | USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
#define | USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk |
#define | USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) |
#define | USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) |
#define | USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk |
#define | USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) |
#define | USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) |
#define | USB_OTG_PCGCCTL_STOPCLK_Pos (0U) |
#define | USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) |
#define | USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk |
#define | USB_OTG_PCGCCTL_GATECLK_Pos (1U) |
#define | USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) |
#define | USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk |
#define | USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) |
#define | USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) |
#define | USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk |
#define | IS_ADC_ALL_INSTANCE(INSTANCE) |
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
#define | IS_COMP_ALL_INSTANCE(INSTANCE) |
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
#define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
#define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
#define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
#define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
#define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
#define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
#define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
#define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
#define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
#define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
#define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
#define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
#define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
#define | IS_I2C_ALL_INSTANCE(INSTANCE) |
#define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
#define | IS_I2S_ALL_INSTANCE(INSTANCE) |
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
#define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
#define | IS_SPI_ALL_INSTANCE(INSTANCE) |
#define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
#define | IS_LPTIM_INSTANCE(INSTANCE) |
#define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
#define | IS_TIM_INSTANCE(INSTANCE) |
#define | IS_TIM_CC1_INSTANCE(INSTANCE) |
#define | IS_TIM_CC2_INSTANCE(INSTANCE) |
#define | IS_TIM_CC3_INSTANCE(INSTANCE) |
#define | IS_TIM_CC4_INSTANCE(INSTANCE) |
#define | IS_TIM_CC5_INSTANCE(INSTANCE) |
#define | IS_TIM_CC6_INSTANCE(INSTANCE) |
#define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
#define | IS_TIM_XOR_INSTANCE(INSTANCE) |
#define | IS_TIM_DMA_INSTANCE(INSTANCE) |
#define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
#define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
#define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
#define | IS_TIM_ETR_INSTANCE(INSTANCE) |
#define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
#define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
#define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
#define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
#define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
#define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
#define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
#define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
#define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
#define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
#define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
#define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
#define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
#define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
#define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
#define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
#define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
#define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
#define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
#define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
#define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
#define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
#define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
#define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
#define | IS_USART_INSTANCE(INSTANCE) |
#define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
#define | IS_UART_INSTANCE(INSTANCE) |
#define | IS_UART_FIFO_INSTANCE(INSTANCE) |
#define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
#define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
#define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
#define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
#define | IS_UART_LIN_INSTANCE(INSTANCE) |
#define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
#define | IS_IRDA_INSTANCE(INSTANCE) |
#define | IS_SMARTCARD_INSTANCE(INSTANCE) |
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
#define | IS_SAI_ALL_INSTANCE(INSTANCE) |
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
#define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
#define | IS_PCD_ALL_INSTANCE(INSTANCE) |
#define | IS_HCD_ALL_INSTANCE(INSTANCE) |
#define | HASH_RNG_IRQn RNG_IRQn |
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
#define | PVD_IRQn PVD_AVD_IRQn |
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
#define | COMP_IRQHandler COMP1_IRQHandler |
CMSIS STM32H742xx Device Peripheral Access Layer Header File.
Copyright (c) 2019 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.