xttcps_hw.h

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
 
/*****************************************************************************/
#ifndef XTTCPS_HW_H     /* prevent circular inclusions */
#define XTTCPS_HW_H     /* by using protection macros */
 
#ifdef __cplusplus
extern "C" {
#endif
 
/***************************** Include Files *********************************/
 
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#ifdef __rtems__
#include <xil_system.h>
#endif
 
/************************** Constant Definitions *****************************/
/*
 * Flag for a9 processor
 */
 #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
 #define ARMA9
 #endif
 
#define XTTCPS_CLK_CNTRL_OFFSET     0x00000000U  
#define XTTCPS_CNT_CNTRL_OFFSET     0x0000000CU  
#define XTTCPS_COUNT_VALUE_OFFSET   0x00000018U  
#define XTTCPS_INTERVAL_VAL_OFFSET  0x00000024U  
#define XTTCPS_MATCH_0_OFFSET       0x00000030U  
#define XTTCPS_MATCH_1_OFFSET       0x0000003CU  
#define XTTCPS_MATCH_2_OFFSET       0x00000048U  
#define XTTCPS_ISR_OFFSET           0x00000054U  
#define XTTCPS_IER_OFFSET           0x00000060U  
/* @} */
 
#define XTTCPS_CLK_CNTRL_PS_EN_MASK     0x00000001U  
#define XTTCPS_CLK_CNTRL_PS_VAL_MASK    0x0000001EU  
#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT            1U  
#define XTTCPS_CLK_CNTRL_PS_DISABLE             16U  
#define XTTCPS_CLK_CNTRL_SRC_MASK       0x00000020U  
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK  0x00000040U  
/* @} */
 
#define XTTCPS_CNT_CNTRL_DIS_MASK       0x00000001U 
#define XTTCPS_CNT_CNTRL_INT_MASK       0x00000002U 
#define XTTCPS_CNT_CNTRL_DECR_MASK      0x00000004U 
#define XTTCPS_CNT_CNTRL_MATCH_MASK     0x00000008U 
#define XTTCPS_CNT_CNTRL_RST_MASK       0x00000010U 
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK   0x00000020U 
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK  0x00000040U 
#define XTTCPS_CNT_CNTRL_RESET_VALUE    0x00000021U 
/* @} */
 
#if defined(ARMA9)
#define XTTCPS_COUNT_VALUE_MASK     0x0000FFFFU 
#else
#define XTTCPS_COUNT_VALUE_MASK     0xFFFFFFFFU 
#endif
/* @} */
 
#if defined(ARMA9)
#define XTTCPS_INTERVAL_VAL_MASK    0x0000FFFFU 
#else
#define XTTCPS_INTERVAL_VAL_MASK    0xFFFFFFFFU 
#endif
/* @} */
 
#if defined(ARMA9)
#define XTTCPS_MATCH_MASK       0x0000FFFFU 
#else
#define XTTCPS_MATCH_MASK       0xFFFFFFFFU 
#endif
#define XTTCPS_NUM_MATCH_REG             3U 
/* @} */
 
#define XTTCPS_IXR_INTERVAL_MASK    0x00000001U  
#define XTTCPS_IXR_MATCH_0_MASK     0x00000002U  
#define XTTCPS_IXR_MATCH_1_MASK     0x00000004U  
#define XTTCPS_IXR_MATCH_2_MASK     0x00000008U  
#define XTTCPS_IXR_CNT_OVR_MASK     0x00000010U  
#define XTTCPS_IXR_ALL_MASK         0x0000001FU  
/* @} */
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/****************************************************************************/
#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
 
/****************************************************************************/
#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
 
/****************************************************************************/
#define XTtcPs_Match_N_Offset(MatchIndex) \
        ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
 
/************************** Function Prototypes ******************************/
 
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */