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#define | XTTCPS_HW_H /* by using protection macros */ |
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#define | ARMA9 |
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Interval Value Register is the maximum value the counter will count up or down to.
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#define | XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU |
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This file defines the hardware interface to one of the three timer counters in the Ps block.
MODIFICATION HISTORY:
Ver Who Date Changes
1.00a drg/jz 01/21/10 First release
3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
mask 16 bit values for zynq and 32 bit values for
zynq ultrascale+mpsoc "
◆ XTTCPS_CLK_CNTRL_EXT_EDGE_MASK
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U |
◆ XTTCPS_CLK_CNTRL_OFFSET
#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U |
◆ XTTCPS_CLK_CNTRL_PS_DISABLE
#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U |
◆ XTTCPS_CLK_CNTRL_PS_EN_MASK
#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U |
◆ XTTCPS_CLK_CNTRL_PS_VAL_MASK
#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU |
◆ XTTCPS_CLK_CNTRL_PS_VAL_SHIFT
#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U |
◆ XTTCPS_CLK_CNTRL_SRC_MASK
#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U |
◆ XTTCPS_CNT_CNTRL_DECR_MASK
#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U |
◆ XTTCPS_CNT_CNTRL_DIS_MASK
#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U |
◆ XTTCPS_CNT_CNTRL_EN_WAVE_MASK
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U |
◆ XTTCPS_CNT_CNTRL_INT_MASK
#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U |
◆ XTTCPS_CNT_CNTRL_MATCH_MASK
#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U |
◆ XTTCPS_CNT_CNTRL_OFFSET
#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU |
◆ XTTCPS_CNT_CNTRL_POL_WAVE_MASK
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U |
◆ XTTCPS_CNT_CNTRL_RESET_VALUE
#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U |
◆ XTTCPS_CNT_CNTRL_RST_MASK
#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U |
◆ XTTCPS_COUNT_VALUE_MASK
#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU |
◆ XTTCPS_COUNT_VALUE_OFFSET
#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U |
◆ XTTCPS_IER_OFFSET
#define XTTCPS_IER_OFFSET 0x00000060U |
Interrupt Enable Register
◆ XTTCPS_INTERVAL_VAL_MASK
#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU |
◆ XTTCPS_INTERVAL_VAL_OFFSET
#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U |
◆ XTTCPS_ISR_OFFSET
#define XTTCPS_ISR_OFFSET 0x00000054U |
Interrupt Status Register
◆ XTTCPS_IXR_ALL_MASK
#define XTTCPS_IXR_ALL_MASK 0x0000001FU |
◆ XTTCPS_IXR_CNT_OVR_MASK
#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U |
◆ XTTCPS_IXR_INTERVAL_MASK
#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U |
◆ XTTCPS_IXR_MATCH_0_MASK
#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U |
◆ XTTCPS_IXR_MATCH_1_MASK
#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U |
◆ XTTCPS_IXR_MATCH_2_MASK
#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U |
◆ XTTCPS_MATCH_0_OFFSET
#define XTTCPS_MATCH_0_OFFSET 0x00000030U |
◆ XTTCPS_MATCH_1_OFFSET
#define XTTCPS_MATCH_1_OFFSET 0x0000003CU |
◆ XTTCPS_MATCH_2_OFFSET
#define XTTCPS_MATCH_2_OFFSET 0x00000048U |
◆ XTTCPS_MATCH_MASK
#define XTTCPS_MATCH_MASK 0x0000FFFFU |
◆ XTtcPs_Match_N_Offset
#define XTtcPs_Match_N_Offset |
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MatchIndex | ) |
((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) |
Calculate a match register offset using the Match Register index.
- Parameters
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MatchIndex | is the 0-2 value of the match register |
- Returns
- MATCH_N_OFFSET.
- Note
- C-style signature: u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
◆ XTTCPS_NUM_MATCH_REG
#define XTTCPS_NUM_MATCH_REG 3U |
◆ XTtcPs_ReadReg
#define XTtcPs_ReadReg |
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BaseAddress, |
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RegOffset |
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| (Xil_In32((BaseAddress) + (u32)(RegOffset))) |
Read the given Timer Counter register.
- Parameters
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BaseAddress | is the base address of the timer counter device. |
RegOffset | is the register offset to be read |
- Returns
- The 32-bit value of the register
- Note
- C-style signature: u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
◆ XTtcPs_WriteReg
#define XTtcPs_WriteReg |
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BaseAddress, |
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RegOffset, |
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Data |
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| (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) |
Write the given Timer Counter register.
- Parameters
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BaseAddress | is the base address of the timer counter device. |
RegOffset | is the register offset to be written |
Data | is the 32-bit value to write to the register |
- Returns
- None.
- Note
- C-style signature: void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
u32 Data)