RTEMS 6.1-rc2
|
Go to the source code of this file.
Macros | |
#define | XTTCPS_HW_H /* by using protection macros */ |
#define | ARMA9 |
Register Map | |
Register offsets from the base address of the device. | |
#define | XTTCPS_CLK_CNTRL_OFFSET 0x00000000U |
#define | XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU |
#define | XTTCPS_COUNT_VALUE_OFFSET 0x00000018U |
#define | XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U |
#define | XTTCPS_MATCH_0_OFFSET 0x00000030U |
#define | XTTCPS_MATCH_1_OFFSET 0x0000003CU |
#define | XTTCPS_MATCH_2_OFFSET 0x00000048U |
#define | XTTCPS_ISR_OFFSET 0x00000054U |
#define | XTTCPS_IER_OFFSET 0x00000060U |
Clock Control Register | |
Clock Control Register definitions | |
#define | XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U |
#define | XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU |
#define | XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U |
#define | XTTCPS_CLK_CNTRL_PS_DISABLE 16U |
#define | XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U |
#define | XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U |
Counter Control Register | |
Counter Control Register definitions | |
#define | XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U |
#define | XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U |
#define | XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U |
#define | XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U |
#define | XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U |
#define | XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U |
#define | XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U |
#define | XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U |
Current Counter Value Register | |
Current Counter Value Register definitions | |
#define | XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU |
Interval Value Register | |
Interval Value Register is the maximum value the counter will count up or down to. | |
#define | XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU |
Match Registers | |
Definitions for Match registers, each timer counter has three match registers. | |
#define | XTTCPS_MATCH_MASK 0x0000FFFFU |
#define | XTTCPS_NUM_MATCH_REG 3U |
Interrupt Registers | |
Following register bit mask is for all interrupt registers. | |
#define | XTTCPS_IXR_INTERVAL_MASK 0x00000001U |
#define | XTTCPS_IXR_MATCH_0_MASK 0x00000002U |
#define | XTTCPS_IXR_MATCH_1_MASK 0x00000004U |
#define | XTTCPS_IXR_MATCH_2_MASK 0x00000008U |
#define | XTTCPS_IXR_CNT_OVR_MASK 0x00000010U |
#define | XTTCPS_IXR_ALL_MASK 0x0000001FU |
#define | XTtcPs_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (u32)(RegOffset))) |
#define | XTtcPs_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) |
#define | XTtcPs_Match_N_Offset(MatchIndex) ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) |