xil_cache.h

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
 
/*****************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
 
#if defined XENV_VXWORKS
/* VxWorks environment */
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#else
/* standalone environment */
 
#include "mb_interface.h"
#include "xil_types.h"
#include "xparameters.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
/****************************************************************************/
#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
 
/****************************************************************************/
#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
 
/****************************************************************************/
#define Xil_L1DCacheInvalidateRange(Addr, Len) \
            microblaze_invalidate_dcache_range((Addr), (Len))
 
/****************************************************************************/
#define Xil_L2CacheInvalidateRange(Addr, Len) \
        microblaze_invalidate_cache_ext_range((Addr), (Len))
 
/****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
#   define Xil_L1DCacheFlushRange(Addr, Len) \
        microblaze_flush_dcache_range((Addr), (Len))
#else
#   define Xil_L1DCacheFlushRange(Addr, Len) \
        microblaze_invalidate_dcache_range((Addr), (Len))
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
 
/****************************************************************************/
#define Xil_L2CacheFlushRange(Addr, Len) \
        microblaze_flush_cache_ext_range((Addr), (Len))
 
/****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
#   define Xil_L1DCacheFlush() microblaze_flush_dcache()
#else
#   define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
 
/****************************************************************************/
#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
 
/****************************************************************************/
#define Xil_L1ICacheInvalidateRange(Addr, Len) \
            microblaze_invalidate_icache_range((Addr), (Len))
 
/****************************************************************************/
#define Xil_L1ICacheInvalidate() \
            microblaze_invalidate_icache()
 
 
/****************************************************************************/
#define Xil_L1DCacheEnable() \
            microblaze_enable_dcache()
 
/****************************************************************************/
#define Xil_L1DCacheDisable() \
            microblaze_disable_dcache()
 
/****************************************************************************/
#define Xil_L1ICacheEnable() \
            microblaze_enable_icache()
 
/****************************************************************************/
#define Xil_L1ICacheDisable() \
            microblaze_disable_icache()
 
/****************************************************************************/
#define Xil_DCacheEnable() Xil_L1DCacheEnable()
 
/****************************************************************************/
#define Xil_ICacheEnable() Xil_L1ICacheEnable()
 
/****************************************************************************/
#define Xil_DCacheInvalidate() \
    Xil_L2CacheInvalidate(); \
    Xil_L1DCacheInvalidate();
 
 
/****************************************************************************/
#define Xil_DCacheInvalidateRange(Addr, Len) \
    Xil_L2CacheInvalidateRange((Addr), (Len)); \
    Xil_L1DCacheInvalidateRange((Addr), (Len));
 
 
/****************************************************************************/
#define Xil_DCacheFlush() \
    Xil_L2CacheFlush(); \
    Xil_L1DCacheFlush();
 
/****************************************************************************/
#define Xil_DCacheFlushRange(Addr, Len) \
    Xil_L2CacheFlushRange((Addr), (Len)); \
    Xil_L1DCacheFlushRange((Addr), (Len));
 
 
/****************************************************************************/
#define Xil_ICacheInvalidate() \
    Xil_L2CacheInvalidate(); \
    Xil_L1ICacheInvalidate();
 
 
/****************************************************************************/
#define Xil_ICacheInvalidateRange(Addr, Len) \
    Xil_L2CacheInvalidateRange((Addr), (Len)); \
    Xil_L1ICacheInvalidateRange((Addr), (Len));
 
void Xil_DCacheDisable(void);
void Xil_ICacheDisable(void);
 
#ifdef __cplusplus
}
#endif
 
#endif
 
#endif