xil_cache.h File Reference

#include "mb_interface.h"
#include "xil_types.h"
#include "xparameters.h"

Go to the source code of this file.

Macros
#define	Xil_L1DCacheInvalidate()   microblaze_invalidate_dcache()
	Invalidate the entire L1 data cache. If the cacheline is modified (dirty), the modified contents are lost.
#define	Xil_L2CacheInvalidate()   microblaze_invalidate_cache_ext()
	Invalidate the entire L2 data cache. If the cacheline is modified (dirty),the modified contents are lost.
#define	Xil_L1DCacheInvalidateRange(Addr, Len)    microblaze_invalidate_dcache_range((Addr), (Len))
	Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the L1 data cache, the cacheline containing that byte is invalidated.If the cacheline is modified (dirty), the modified contents are lost.
#define	Xil_L2CacheInvalidateRange(Addr, Len)    microblaze_invalidate_cache_ext_range((Addr), (Len))
	Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the L1 data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost.
#define	Xil_L1DCacheFlushRange(Addr, Len)    microblaze_invalidate_dcache_range((Addr), (Len))
	Flush the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the data cache, and is modified (dirty), the cacheline will be written to system memory.The cacheline will also be invalidated.
#define	Xil_L2CacheFlushRange(Addr, Len)    microblaze_flush_cache_ext_range((Addr), (Len))
	Flush the L2 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the data cache, and is modified (dirty), the cacheline will be written to system memory. The cacheline will also be invalidated.
#define	Xil_L1DCacheFlush()   microblaze_invalidate_dcache()
	Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be written to system memory. The entire data cache will be invalidated.
#define	Xil_L2CacheFlush()   microblaze_flush_cache_ext()
	Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be written to system memory. The entire data cache will be invalidated.
#define	Xil_L1ICacheInvalidateRange(Addr, Len)    microblaze_invalidate_icache_range((Addr), (Len))
	Invalidate the instruction cache for the given address range.
#define	Xil_L1ICacheInvalidate()    microblaze_invalidate_icache()
	Invalidate the entire instruction cache.
#define	Xil_L1DCacheEnable()    microblaze_enable_dcache()
	Enable the L1 data cache.
#define	Xil_L1DCacheDisable()    microblaze_disable_dcache()
	Disable the L1 data cache.
#define	Xil_L1ICacheEnable()    microblaze_enable_icache()
	Enable the instruction cache.
#define	Xil_L1ICacheDisable()    microblaze_disable_icache()
	Disable the L1 Instruction cache.
#define	Xil_DCacheEnable()   Xil_L1DCacheEnable()
	Enable the data cache.
#define	Xil_ICacheEnable()   Xil_L1ICacheEnable()
	Enable the instruction cache.
#define	Xil_DCacheInvalidate()
	Invalidate the entire Data cache.
#define	Xil_DCacheInvalidateRange(Addr, Len)
	Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.
#define	Xil_DCacheFlush()
	Flush the entire Data cache.
#define	Xil_DCacheFlushRange(Addr, Len)
	Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the written to system memory first before the before the line is invalidated.
#define	Xil_ICacheInvalidate()
	Invalidate the entire instruction cache.
#define	Xil_ICacheInvalidateRange(Addr, Len)
	Invalidate the instruction cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Functions
void	Xil_DCacheDisable (void)
	Disable the Data cache.
void	Xil_ICacheDisable (void)
	Disable the instruction cache.