Macros
#define	Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
	Invalidate the entire L1 data cache. If the cacheline is modified (dirty), the modified contents are lost.

#define	Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
	Invalidate the entire L2 data cache. If the cacheline is modified (dirty),the modified contents are lost.

#define	Xil_L1DCacheInvalidateRange(Addr, Len) microblaze_invalidate_dcache_range((Addr), (Len))
	Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the L1 data cache, the cacheline containing that byte is invalidated.If the cacheline is modified (dirty), the modified contents are lost.

#define	Xil_L2CacheInvalidateRange(Addr, Len) microblaze_invalidate_cache_ext_range((Addr), (Len))
	Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the L1 data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost.

#define	Xil_L1DCacheFlushRange(Addr, Len) microblaze_invalidate_dcache_range((Addr), (Len))
	Flush the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the data cache, and is modified (dirty), the cacheline will be written to system memory.The cacheline will also be invalidated.

#define	Xil_L2CacheFlushRange(Addr, Len) microblaze_flush_cache_ext_range((Addr), (Len))
	Flush the L2 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the data cache, and is modified (dirty), the cacheline will be written to system memory. The cacheline will also be invalidated.

#define	Xil_L1DCacheFlush() microblaze_invalidate_dcache()
	Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be written to system memory. The entire data cache will be invalidated.

#define	Xil_L2CacheFlush() microblaze_flush_cache_ext()
	Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be written to system memory. The entire data cache will be invalidated.

#define	Xil_L1ICacheInvalidateRange(Addr, Len) microblaze_invalidate_icache_range((Addr), (Len))
	Invalidate the instruction cache for the given address range.

#define	Xil_L1ICacheInvalidate() microblaze_invalidate_icache()
	Invalidate the entire instruction cache.

#define	Xil_L1DCacheEnable() microblaze_enable_dcache()
	Enable the L1 data cache.

#define	Xil_L1DCacheDisable() microblaze_disable_dcache()
	Disable the L1 data cache.

#define	Xil_L1ICacheEnable() microblaze_enable_icache()
	Enable the instruction cache.

#define	Xil_L1ICacheDisable() microblaze_disable_icache()
	Disable the L1 Instruction cache.

#define	Xil_DCacheEnable() Xil_L1DCacheEnable()
	Enable the data cache.

#define	Xil_ICacheEnable() Xil_L1ICacheEnable()
	Enable the instruction cache.

#define	Xil_DCacheInvalidate()
	Invalidate the entire Data cache.

#define	Xil_DCacheInvalidateRange(Addr, Len)
	Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

#define	Xil_DCacheFlush()
	Flush the entire Data cache.

#define	Xil_DCacheFlushRange(Addr, Len)
	Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the written to system memory first before the before the line is invalidated.

#define	Xil_ICacheInvalidate()
	Invalidate the entire instruction cache.

#define	Xil_ICacheInvalidateRange(Addr, Len)
	Invalidate the instruction cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Functions
void	Xil_DCacheDisable (void)
	Disable the Data cache.

void	Xil_ICacheDisable (void)
	Disable the instruction cache.

Detailed Description

The xil_cache.h file contains cache related driver functions (or macros) that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation. The functions in this header file can be used across all Xilinx supported processors.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -------------------------------------------------------
1.00  hbm  07/28/09 Initial release
3.02a sdm  10/24/11 Updated the file to include xparameters.h so that
                    the correct cache flush routines are used based on
                    whether the write-back or write-through caches are
                    used (cr #630532).
3.10a asa  05/04/13 This version of MicroBlaze BSP adds support for system
                  cache/L2 cache. The existing/old APIs/macros in this
                  file are renamed to imply that they deal with L1 cache.
                  New macros/APIs are added to address similar features for
                  L2 cache. Users can include this file in their application
                  to use the various cache related APIs. These changes are
                  done for implementing PR #697214.

Macro Definition Documentation

◆ Xil_DCacheEnable

void Xil_DCacheEnable ( ) Xil_L1DCacheEnable()

Enable the data cache.

Returns: None.

◆ Xil_DCacheFlush

void Xil_DCacheFlush ( )

Value:

Xil_L2CacheFlush(); \

Xil_L1DCacheFlush();

Xil_L2CacheFlush

#define Xil_L2CacheFlush()

Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be written to system me...

Definition: xil_cache.h:183

Flush the entire Data cache.

Returns: None.

◆ Xil_DCacheFlushRange

#define Xil_DCacheFlushRange	(	Addr,
		Len
	)

Value:

Xil_L2CacheFlushRange((Addr), (Len)); \

Xil_L1DCacheFlushRange((Addr), (Len));

Xil_L2CacheFlushRange

#define Xil_L2CacheFlushRange(Addr, Len)

Flush the L2 data cache for the given address range. If the bytes specified by the address (Addr) are...

Definition: xil_cache.h:156

Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the written to system memory first before the before the line is invalidated.

Parameters

Addr	Start address of range to be flushed.
Len	Length of range to be flushed in bytes.

Returns: None.

◆ Xil_DCacheInvalidate

void Xil_DCacheInvalidate ( )

Value:

Xil_L2CacheInvalidate(); \

Xil_L1DCacheInvalidate();

Xil_L2CacheInvalidate

#define Xil_L2CacheInvalidate()

Invalidate the entire L2 data cache. If the cacheline is modified (dirty),the modified contents are l...

Definition: xil_cache.h:84

Invalidate the entire Data cache.

Returns: None.

◆ Xil_DCacheInvalidateRange

#define Xil_DCacheInvalidateRange	(	Addr,
		Len
	)

Value:

Xil_L2CacheInvalidateRange((Addr), (Len)); \

Xil_L1DCacheInvalidateRange((Addr), (Len));

Xil_L2CacheInvalidateRange

#define Xil_L2CacheInvalidateRange(Addr, Len)

Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr...

Definition: xil_cache.h:119

Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Parameters

Addr	Start address of range to be invalidated.
Len	Length of range to be invalidated in bytes.

Returns: None.

◆ Xil_ICacheEnable

void Xil_ICacheEnable ( ) Xil_L1ICacheEnable()

Enable the instruction cache.

Returns: None.

◆ Xil_ICacheInvalidate

void Xil_ICacheInvalidate ( )

Value:

Xil_L2CacheInvalidate(); \

Xil_L1ICacheInvalidate();

Invalidate the entire instruction cache.

Returns: None.

◆ Xil_ICacheInvalidateRange

#define Xil_ICacheInvalidateRange	(	Addr,
		Len
	)

Value:

Xil_L2CacheInvalidateRange((Addr), (Len)); \

Xil_L1ICacheInvalidateRange((Addr), (Len));

Invalidate the instruction cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Parameters

Addr	Start address of ragne to be invalidated.
Len	Length of range to be invalidated in bytes.

Returns: None.

◆ Xil_L1DCacheDisable

#define Xil_L1DCacheDisable ( ) microblaze_disable_dcache()

Disable the L1 data cache.

Returns: None.

Note: This is processor specific.

◆ Xil_L1DCacheEnable

#define Xil_L1DCacheEnable ( ) microblaze_enable_dcache()

Enable the L1 data cache.

Returns: None.

Note: This is processor specific.

◆ Xil_L1DCacheFlush

#define Xil_L1DCacheFlush ( ) microblaze_invalidate_dcache()

Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be written to system memory. The entire data cache will be invalidated.

Returns: None.

◆ Xil_L1DCacheFlushRange

#define Xil_L1DCacheFlushRange	(	Addr,
		Len
	)	microblaze_invalidate_dcache_range((Addr), (Len))

Flush the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the data cache, and is modified (dirty), the cacheline will be written to system memory.The cacheline will also be invalidated.

Parameters

Addr	the starting address of the range to be flushed.
Len	length in byte to be flushed.

Returns: None.

◆ Xil_L1DCacheInvalidate

#define Xil_L1DCacheInvalidate ( ) microblaze_invalidate_dcache()

Invalidate the entire L1 data cache. If the cacheline is modified (dirty), the modified contents are lost.

Returns: None.

Note: Processor must be in real mode.

◆ Xil_L1DCacheInvalidateRange

#define Xil_L1DCacheInvalidateRange	(	Addr,
		Len
	)	microblaze_invalidate_dcache_range((Addr), (Len))

Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the L1 data cache, the cacheline containing that byte is invalidated.If the cacheline is modified (dirty), the modified contents are lost.

Parameters

Addr	is address of range to be invalidated.
Len	is the length in bytes to be invalidated.

Returns: None.

Note: Processor must be in real mode.

◆ Xil_L1ICacheDisable

#define Xil_L1ICacheDisable ( ) microblaze_disable_icache()

Disable the L1 Instruction cache.

Returns: None.

Note: This is processor specific.

◆ Xil_L1ICacheEnable

#define Xil_L1ICacheEnable ( ) microblaze_enable_icache()

Enable the instruction cache.

Returns: None.

Note: This is processor specific.

◆ Xil_L1ICacheInvalidate

#define Xil_L1ICacheInvalidate ( ) microblaze_invalidate_icache()

Invalidate the entire instruction cache.

Returns: None.

◆ Xil_L1ICacheInvalidateRange

#define Xil_L1ICacheInvalidateRange	(	Addr,
		Len
	)	microblaze_invalidate_icache_range((Addr), (Len))

Invalidate the instruction cache for the given address range.

Parameters

Addr	is address of ragne to be invalidated.
Len	is the length in bytes to be invalidated.

Returns: None.

◆ Xil_L2CacheFlush

#define Xil_L2CacheFlush ( ) microblaze_flush_cache_ext()

Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be written to system memory. The entire data cache will be invalidated.

Returns: None.

◆ Xil_L2CacheFlushRange

#define Xil_L2CacheFlushRange	(	Addr,
		Len
	)	microblaze_flush_cache_ext_range((Addr), (Len))

Flush the L2 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the data cache, and is modified (dirty), the cacheline will be written to system memory. The cacheline will also be invalidated.

Parameters

Addr	the starting address of the range to be flushed.
Len	length in byte to be flushed.

Returns: None.

◆ Xil_L2CacheInvalidate

#define Xil_L2CacheInvalidate ( ) microblaze_invalidate_cache_ext()

Invalidate the entire L2 data cache. If the cacheline is modified (dirty),the modified contents are lost.

Returns: None.

Note: Processor must be in real mode.

◆ Xil_L2CacheInvalidateRange

#define Xil_L2CacheInvalidateRange	(	Addr,
		Len
	)	microblaze_invalidate_cache_ext_range((Addr), (Len))

Invalidate the L1 data cache for the given address range. If the bytes specified by the address (Addr) are cached by the L1 data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost.

Parameters

Addr	address of range to be invalidated.
Len	length in bytes to be invalidated.

Returns: None.

Note: Processor must be in real mode.

Function Documentation

◆ Xil_DCacheDisable()

void Xil_DCacheDisable ( void )

Disable the Data cache.

Returns: None.

Returns: None.

◆ Xil_ICacheDisable()

void Xil_ICacheDisable ( void )

Disable the instruction cache.

Returns: None.

Returns: None.

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ Xil_DCacheEnable

◆ Xil_DCacheFlush

◆ Xil_DCacheFlushRange

◆ Xil_DCacheInvalidate

◆ Xil_DCacheInvalidateRange

◆ Xil_ICacheEnable

◆ Xil_ICacheInvalidate

◆ Xil_ICacheInvalidateRange

◆ Xil_L1DCacheDisable

◆ Xil_L1DCacheEnable

◆ Xil_L1DCacheFlush

◆ Xil_L1DCacheFlushRange

◆ Xil_L1DCacheInvalidate

◆ Xil_L1DCacheInvalidateRange

◆ Xil_L1ICacheDisable

◆ Xil_L1ICacheEnable

◆ Xil_L1ICacheInvalidate

◆ Xil_L1ICacheInvalidateRange

◆ Xil_L2CacheFlush

◆ Xil_L2CacheFlushRange

◆ Xil_L2CacheInvalidate

◆ Xil_L2CacheInvalidateRange

Function Documentation

◆ Xil_DCacheDisable()

◆ Xil_ICacheDisable()