Cortex A53 64bit Processor Cache Functions

Macros
#define	Xil_DCacheFlushRange   Xil_DCacheInvalidateRange
#define	Xil_DCacheFlushRange   Xil_DCacheInvalidateRange

Functions
void	Xil_DCacheEnable (void)
	Enable the Data cache.
void	Xil_DCacheDisable (void)
	Disable the Data cache.
void	Xil_DCacheInvalidate (void)
	Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.
void	Xil_DCacheInvalidateRange (INTPTR adr, INTPTR len)
	Invalidate the Data cache for the given address range. The cachelines present in the adderss range are cleaned and invalidated.
void	Xil_DCacheInvalidateLine (INTPTR adr)
	Invalidate a Data cache line. The cacheline is cleaned and invalidated.
void	Xil_DCacheFlush (void)
	Flush the Data cache.
void	Xil_DCacheFlushLine (INTPTR adr)
	Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.
void	Xil_ICacheEnable (void)
	Enable the instruction cache.
void	Xil_ICacheDisable (void)
	Disable the instruction cache.
void	Xil_ICacheInvalidate (void)
	Invalidate the entire instruction cache.
void	Xil_ICacheInvalidateRange (INTPTR adr, INTPTR len)
	Invalidate the instruction cache for the given address range. If the instructions specified by the address range are cached by the instrunction cache, the cachelines containing those instructions are invalidated.
void	Xil_ICacheInvalidateLine (INTPTR adr)
	Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.
void	Xil_ConfigureL1Prefetch (u8 num)
	Configure the maximum number of outstanding data prefetches allowed in L1 cache.

Detailed Description

Cache functions provide access to cache related operations such as flush and invalidate for instruction and data caches. It gives option to perform the cache operations on a single cacheline, a range of memory and an entire cache.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -----------------------------------------------
5.00    pkp  05/29/14 First release

Function Documentation

Xil_ConfigureL1Prefetch()

void Xil_ConfigureL1Prefetch

(

u8

num

)

Configure the maximum number of outstanding data prefetches allowed in L1 cache.

Parameters

num	maximum number of outstanding data prefetches allowed, valid values are 0-7.

Returns

None.

Note

This function is implemented only for EL3 privilege level.

Xil_DCacheDisable()

void Xil_DCacheDisable

(

void

)

Disable the Data cache.

Returns

None.

Returns

None.

Xil_DCacheEnable()

void Xil_DCacheEnable

(

void

)

Enable the Data cache.

Returns

None.

Returns

None.

Xil_DCacheFlush()

void Xil_DCacheFlush

(

void

)

Flush the Data cache.

Returns

None.

Flush the Data cache.

Returns

None.

Xil_DCacheFlushLine()

void Xil_DCacheFlushLine

(

INTPTR

adr

)

Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.

Parameters

adr	64bit address of the data to be flushed.

Returns

None.

Note

The bottom 6 bits are set to 0, forced by architecture.

Parameters

adr	32bit address of the data to be flushed.

Returns

None.

Note

The bottom 5 bits are set to 0, forced by architecture.

Xil_DCacheInvalidate()

void Xil_DCacheInvalidate

(

void

)

Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.

Returns

None.

Note

In Cortex-A53, functionality to simply invalid the cachelines is not present. Such operations are a problem for an environment that supports virtualisation. It would allow one OS to invalidate a line belonging to another OS. This could lead to the other OS crashing because of the loss of essential data. Hence, such operations are promoted to clean and invalidate which avoids such corruption.

Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.

Returns

None.

Xil_DCacheInvalidateLine()

void Xil_DCacheInvalidateLine

(

INTPTR

adr

)

Invalidate a Data cache line. The cacheline is cleaned and invalidated.

Parameters

adr	64bit address of the data to be flushed.

Returns

None.

Note

In Cortex-A53, functionality to simply invalid the cachelines is not present. Such operations are a problem for an environment that supports virtualisation. It would allow one OS to invalidate a line belonging to another OS. This could lead to the other OS crashing because of the loss of essential data. Hence, such operations are promoted to clean and invalidate which avoids such corruption.

Invalidate a Data cache line. The cacheline is cleaned and invalidated.

Parameters

adr	32bit address of the data to be flushed.

Returns

None.

Note

The bottom 5 bits are set to 0, forced by architecture.

Xil_DCacheInvalidateRange()

void Xil_DCacheInvalidateRange	(	INTPTR	adr,
		INTPTR	len
	)

Invalidate the Data cache for the given address range. The cachelines present in the adderss range are cleaned and invalidated.

Parameters

adr	64bit start address of the range to be invalidated.
len	Length of the range to be invalidated in bytes.

Returns

None.

Note

In Cortex-A53, functionality to simply invalid the cachelines is not present. Such operations are a problem for an environment that supports virtualisation. It would allow one OS to invalidate a line belonging to another OS. This could lead to the other OS crashing because of the loss of essential data. Hence, such operations are promoted to clean and invalidate which avoids such corruption.

Xil_ICacheDisable()

void Xil_ICacheDisable

(

void

)

Disable the instruction cache.

Returns

None.

Returns

None.

Xil_ICacheEnable()

void Xil_ICacheEnable

(

void

)

Enable the instruction cache.

Returns

None.

Returns

None.

Xil_ICacheInvalidate()

void Xil_ICacheInvalidate

(

void

)

Invalidate the entire instruction cache.

Returns

None.

Returns

None.

Xil_ICacheInvalidateLine()

void Xil_ICacheInvalidateLine

(

INTPTR

adr

)

Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Parameters

adr	64bit address of the instruction to be invalidated.

Returns

None.

Note

The bottom 6 bits are set to 0, forced by architecture.

Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Parameters

adr	32bit address of the instruction to be invalidated.

Returns

None.

Note

The bottom 5 bits are set to 0, forced by architecture.

Xil_ICacheInvalidateRange()

void Xil_ICacheInvalidateRange	(	INTPTR	adr,
		INTPTR	len
	)

Invalidate the instruction cache for the given address range. If the instructions specified by the address range are cached by the instrunction cache, the cachelines containing those instructions are invalidated.

Parameters

adr	64bit start address of the range to be invalidated.
len	Length of the range to be invalidated in bytes.

Returns

None.