Clock

Files
file	fsl_clock.h
file	fsl_clock.h

Data Structures
struct	_clock_arm_pll_config
	PLL configuration for ARM. More...
struct	_clock_usb_pll_config
	PLL configuration for USB. More...
struct	_clock_sys_pll_config
	PLL configuration for System. More...
struct	_clock_audio_pll_config
	PLL configuration for AUDIO and VIDEO. More...
struct	_clock_video_pll_config
	PLL configuration for AUDIO and VIDEO. More...
struct	_clock_enet_pll_config
	PLL configuration for ENET. More...
struct	_clock_group_config
	The structure used to configure clock group. More...
struct	_clock_pll_ss_config
	Spread specturm configure Pll. More...
struct	_clock_sys_pll2_config
	PLL configure for Sys Pll2. More...
struct	_clock_sys_pll1_config
	PLL configure for Sys Pll1. More...
struct	_clock_audio_pll_gpc_config
	PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL. More...
struct	_clock_root_config_t
	Clock root configuration. More...
struct	_clock_root_setpoint_config_t
	Clock root configuration in SetPoint Mode. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0
	Configure whether driver controls clock.
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0
	Configure whether driver controls clock.

Variables
bool	_clock_group_config::clockOff
uint16_t	_clock_group_config::resetDiv
uint8_t	_clock_group_config::div0
clock_pll_post_div_t	_clock_arm_pll_config::postDivider
uint32_t	_clock_arm_pll_config::loopDivider
uint8_t	_clock_usb_pll_config::loopDivider
uint8_t	_clock_usb_pll_config::src
uint16_t	_clock_pll_ss_config::stop
uint16_t	_clock_pll_ss_config::step
uint32_t	_clock_sys_pll2_config::mfd
clock_pll_ss_config_t *	_clock_sys_pll2_config::ss
bool	_clock_sys_pll2_config::ssEnable
bool	_clock_sys_pll1_config::pllDiv2En
bool	_clock_sys_pll1_config::pllDiv5En
clock_pll_ss_config_t *	_clock_sys_pll1_config::ss
bool	_clock_sys_pll1_config::ssEnable
uint8_t	_clock_audio_pll_config::loopDivider
uint8_t	_clock_audio_pll_config::postDivider
uint32_t	_clock_audio_pll_config::numerator
uint32_t	_clock_audio_pll_config::denominator
clock_pll_ss_config_t *	_clock_audio_pll_config::ss
bool	_clock_audio_pll_config::ssEnable
uint8_t	_clock_audio_pll_gpc_config::loopDivider
uint32_t	_clock_audio_pll_gpc_config::numerator
uint32_t	_clock_audio_pll_gpc_config::denominator
clock_pll_ss_config_t *	_clock_audio_pll_gpc_config::ss
bool	_clock_audio_pll_gpc_config::ssEnable
bool	_clock_enet_pll_config::enableClkOutput
bool	_clock_enet_pll_config::enableClkOutput25M
uint8_t	_clock_enet_pll_config::loopDivider
uint8_t	_clock_enet_pll_config::src
bool	_clock_enet_pll_config::enableClkOutput1
uint8_t	_clock_enet_pll_config::loopDivider1
bool	_clock_root_config_t::clockOff
uint8_t	_clock_root_config_t::mux
uint8_t	_clock_root_config_t::div
uint8_t	_clock_root_setpoint_config_t::grade
bool	_clock_root_setpoint_config_t::clockOff
uint8_t	_clock_root_setpoint_config_t::mux
uint8_t	_clock_root_setpoint_config_t::div

Driver version
enum	_clock_name {   kCLOCK_CpuClk = 0x0U , kCLOCK_AhbClk = 0x1U , kCLOCK_SemcClk = 0x2U , kCLOCK_IpgClk = 0x3U ,   kCLOCK_PerClk = 0x4U , kCLOCK_OscClk = 0x5U , kCLOCK_RtcClk = 0x6U , kCLOCK_ArmPllClk = 0x7U ,   kCLOCK_Usb1PllClk = 0x8U , kCLOCK_Usb1PllPfd0Clk = 0x9U , kCLOCK_Usb1PllPfd1Clk = 0xAU , kCLOCK_Usb1PllPfd2Clk = 0xBU ,   kCLOCK_Usb1PllPfd3Clk = 0xCU , kCLOCK_Usb1SwClk = 0x17U , kCLOCK_Usb1Sw120MClk = 0x18U , kCLOCK_Usb1Sw60MClk = 0x19U ,   kCLOCK_Usb1Sw80MClk = 0x1AU , kCLOCK_Usb2PllClk = 0xDU , kCLOCK_SysPllClk = 0xEU , kCLOCK_SysPllPfd0Clk = 0xFU ,   kCLOCK_SysPllPfd1Clk = 0x10U , kCLOCK_SysPllPfd2Clk = 0x11U , kCLOCK_SysPllPfd3Clk = 0x12U , kCLOCK_EnetPll0Clk = 0x13U ,   kCLOCK_EnetPll1Clk = 0x14U , kCLOCK_AudioPllClk = 0x15U , kCLOCK_VideoPllClk = 0x16U , kCLOCK_NoneName = CLOCK_SOURCE_NONE ,   kCLOCK_OscRc16M = 0 , kCLOCK_OscRc48M = 1 , kCLOCK_OscRc48MDiv2 = 2 , kCLOCK_OscRc400M = 3 ,   kCLOCK_Osc24M = 4 , kCLOCK_Osc24MOut = 5 , kCLOCK_ArmPll = 6 , kCLOCK_ArmPllOut = 7 ,   kCLOCK_SysPll2 = 8 , kCLOCK_SysPll2Out = 9 , kCLOCK_SysPll2Pfd0 = 10 , kCLOCK_SysPll2Pfd1 = 11 ,   kCLOCK_SysPll2Pfd2 = 12 , kCLOCK_SysPll2Pfd3 = 13 , kCLOCK_SysPll3 = 14 , kCLOCK_SysPll3Out = 15 ,   kCLOCK_SysPll3Div2 = 16 , kCLOCK_SysPll3Pfd0 = 17 , kCLOCK_SysPll3Pfd1 = 18 , kCLOCK_SysPll3Pfd2 = 19 ,   kCLOCK_SysPll3Pfd3 = 20 , kCLOCK_SysPll1 = 21 , kCLOCK_SysPll1Out = 22 , kCLOCK_SysPll1Div2 = 23 ,   kCLOCK_SysPll1Div5 = 24 , kCLOCK_AudioPll = 25 , kCLOCK_AudioPllOut = 26 , kCLOCK_VideoPll = 27 ,   kCLOCK_VideoPllOut = 28 , kCLOCK_CpuClk , kCLOCK_CoreSysClk , kCLOCK_Reserved = 0xFFU }
	Clock name used to get clock frequency. More...
enum	_clock_ip_name {   kCLOCK_IpInvalid = -1 , kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT , kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT , kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT ,   kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT , kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT , kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT , kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT ,   kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT , kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT , kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT , kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT ,   kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT , kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT , kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT , kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT ,   kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT , kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT , kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT , kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT ,   kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT , kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT , kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT , kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT ,   kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT , kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT , kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT , kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT ,   kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT , kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT , kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT , kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT ,   kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT , kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT , kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT , kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT ,   kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT , kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT , kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT , kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT ,   kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT , kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT , kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT , kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT ,   kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT , kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT , kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT , kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT ,   kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT , kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT , kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT , kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT ,   kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT , kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT , kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT , kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT ,   kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT , kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT , kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT , kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT ,   kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT , kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT , kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT , kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT ,   kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT , kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT , kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT , kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT ,   kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT , kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT , kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT , kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT ,   kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT , kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT , kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT , kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT ,   kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT , kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT , kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT , kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT ,   kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT , kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT , kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT , kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT ,   kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT , kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT , kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT , kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT ,   kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT , kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT , kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT , kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT ,   kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT , kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT , kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT , kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT ,   kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT , kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT , kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT , kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT ,   kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT , kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT , kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT , kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT ,   kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT , kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT , kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT , kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT ,   kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT , kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT , kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT , kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT ,   kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT }
	CCM CCGR gate control for each module independently. More...
enum	_clock_osc { kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U , kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...
enum	_clock_gate_value {   kCLOCK_ClockNotNeeded = 0U , kCLOCK_ClockNeededRun = 1U , kCLOCK_ClockNeededRunWait = 3U , kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK ,   kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK }
	Clock gate value. More...
enum	_clock_mode_t {   kCLOCK_ModeRun = 0U , kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U , kCLOCK_ModeRun = 0U ,   kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U }
	System clock mode. More...
enum	_clock_mux {   kCLOCK_Pll3SwMux , kCLOCK_PeriphMux , kCLOCK_SemcAltMux , kCLOCK_SemcMux ,   kCLOCK_PrePeriphMux , kCLOCK_TraceMux , kCLOCK_PeriphClk2Mux , kCLOCK_LpspiMux ,   kCLOCK_FlexspiMux , kCLOCK_Usdhc2Mux , kCLOCK_Usdhc1Mux , kCLOCK_Sai3Mux ,   kCLOCK_Sai2Mux , kCLOCK_Sai1Mux , kCLOCK_PerclkMux , kCLOCK_Flexio2Mux ,   kCLOCK_CanMux , kCLOCK_UartMux , kCLOCK_SpdifMux , kCLOCK_Flexio1Mux ,   kCLOCK_Lpi2cMux , kCLOCK_LcdifPreMux , kCLOCK_CsiMux }
	MUX control names for clock mux setting. More...
enum	_clock_div {   kCLOCK_ArmDiv , kCLOCK_PeriphClk2Div , kCLOCK_SemcDiv , kCLOCK_AhbDiv ,   kCLOCK_IpgDiv , kCLOCK_LpspiDiv , kCLOCK_LcdifDiv , kCLOCK_FlexspiDiv ,   kCLOCK_PerclkDiv , kCLOCK_CanDiv , kCLOCK_TraceDiv , kCLOCK_Usdhc2Div ,   kCLOCK_Usdhc1Div , kCLOCK_UartDiv , kCLOCK_Flexio2Div , kCLOCK_Sai3PreDiv ,   kCLOCK_Sai3Div , kCLOCK_Flexio2PreDiv , kCLOCK_Sai1PreDiv , kCLOCK_Sai1Div ,   kCLOCK_Sai2PreDiv , kCLOCK_Sai2Div , kCLOCK_Spdif0PreDiv , kCLOCK_Spdif0Div ,   kCLOCK_Flexio1PreDiv , kCLOCK_Flexio1Div , kCLOCK_Lpi2cDiv , kCLOCK_LcdifPreDiv ,   kCLOCK_CsiDiv , kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV }
	DIV control names for clock div setting. More...
enum	_clock_div_value {   kCLOCK_ArmDivBy1 = 0 , kCLOCK_ArmDivBy2 = 1 , kCLOCK_ArmDivBy3 = 2 , kCLOCK_ArmDivBy4 = 3 ,   kCLOCK_ArmDivBy5 = 4 , kCLOCK_ArmDivBy6 = 5 , kCLOCK_ArmDivBy7 = 6 , kCLOCK_ArmDivBy8 = 7 ,   kCLOCK_PeriphClk2DivBy1 = 0 , kCLOCK_PeriphClk2DivBy2 = 1 , kCLOCK_PeriphClk2DivBy3 = 2 , kCLOCK_PeriphClk2DivBy4 = 3 ,   kCLOCK_PeriphClk2DivBy5 = 4 , kCLOCK_PeriphClk2DivBy6 = 5 , kCLOCK_PeriphClk2DivBy7 = 6 , kCLOCK_PeriphClk2DivBy8 = 7 ,   kCLOCK_SemcDivBy1 = 0 , kCLOCK_SemcDivBy2 = 1 , kCLOCK_SemcDivBy3 = 2 , kCLOCK_SemcDivBy4 = 3 ,   kCLOCK_SemcDivBy5 = 4 , kCLOCK_SemcDivBy6 = 5 , kCLOCK_SemcDivBy7 = 6 , kCLOCK_SemcDivBy8 = 7 ,   kCLOCK_AhbDivBy1 = 0 , kCLOCK_AhbDivBy2 = 1 , kCLOCK_AhbDivBy3 = 2 , kCLOCK_AhbDivBy4 = 3 ,   kCLOCK_AhbDivBy5 = 4 , kCLOCK_AhbDivBy6 = 5 , kCLOCK_AhbDivBy7 = 6 , kCLOCK_AhbDivBy8 = 7 ,   kCLOCK_IpgDivBy1 = 0 , kCLOCK_IpgDivBy2 = 1 , kCLOCK_IpgDivBy3 = 2 , kCLOCK_IpgDivBy4 = 3 ,   kCLOCK_LpspiDivBy1 = 0 , kCLOCK_LpspiDivBy2 = 1 , kCLOCK_LpspiDivBy3 = 2 , kCLOCK_LpspiDivBy4 = 3 ,   kCLOCK_LpspiDivBy5 = 4 , kCLOCK_LpspiDivBy6 = 5 , kCLOCK_LpspiDivBy7 = 6 , kCLOCK_LpspiDivBy8 = 7 ,   kCLOCK_LcdifDivBy1 = 0 , kCLOCK_LcdifDivBy2 = 1 , kCLOCK_LcdifDivBy3 = 2 , kCLOCK_LcdifDivBy4 = 3 ,   kCLOCK_LcdifDivBy5 = 4 , kCLOCK_LcdifDivBy6 = 5 , kCLOCK_LcdifDivBy7 = 6 , kCLOCK_LcdifDivBy8 = 7 ,   kCLOCK_FlexspiDivBy1 = 0 , kCLOCK_FlexspiDivBy2 = 1 , kCLOCK_FlexspiDivBy3 = 2 , kCLOCK_FlexspiDivBy4 = 3 ,   kCLOCK_FlexspiDivBy5 = 4 , kCLOCK_FlexspiDivBy6 = 5 , kCLOCK_FlexspiDivBy7 = 6 , kCLOCK_FlexspiDivBy8 = 7 ,   kCLOCK_TraceDivBy1 = 0 , kCLOCK_TraceDivBy2 = 1 , kCLOCK_TraceDivBy3 = 2 , kCLOCK_TraceDivBy4 = 3 ,   kCLOCK_Usdhc2DivBy1 = 0 , kCLOCK_Usdhc2DivBy2 = 1 , kCLOCK_Usdhc2DivBy3 = 2 , kCLOCK_Usdhc2DivBy4 = 3 ,   kCLOCK_Usdhc2DivBy5 = 4 , kCLOCK_Usdhc2DivBy6 = 5 , kCLOCK_Usdhc2DivBy7 = 6 , kCLOCK_Usdhc2DivBy8 = 7 ,   kCLOCK_Usdhc1DivBy1 = 0 , kCLOCK_Usdhc1DivBy2 = 1 , kCLOCK_Usdhc1DivBy3 = 2 , kCLOCK_Usdhc1DivBy4 = 3 ,   kCLOCK_Usdhc1DivBy5 = 4 , kCLOCK_Usdhc1DivBy6 = 5 , kCLOCK_Usdhc1DivBy7 = 6 , kCLOCK_Usdhc1DivBy8 = 7 ,   kCLOCK_Flexio2DivBy1 = 0 , kCLOCK_Flexio2DivBy2 = 1 , kCLOCK_Flexio2DivBy3 = 2 , kCLOCK_Flexio2DivBy4 = 3 ,   kCLOCK_Flexio2DivBy5 = 4 , kCLOCK_Flexio2DivBy6 = 5 , kCLOCK_Flexio2DivBy7 = 6 , kCLOCK_Flexio2DivBy8 = 7 ,   kCLOCK_Sai3PreDivBy1 = 0 , kCLOCK_Sai3PreDivBy2 = 1 , kCLOCK_Sai3PreDivBy3 = 2 , kCLOCK_Sai3PreDivBy4 = 3 ,   kCLOCK_Sai3PreDivBy5 = 4 , kCLOCK_Sai3PreDivBy6 = 5 , kCLOCK_Sai3PreDivBy7 = 6 , kCLOCK_Sai3PreDivBy8 = 7 ,   kCLOCK_Flexio2PreDivBy1 = 0 , kCLOCK_Flexio2PreDivBy2 = 1 , kCLOCK_Flexio2PreDivBy3 = 2 , kCLOCK_Flexio2PreDivBy4 = 3 ,   kCLOCK_Flexio2PreDivBy5 = 4 , kCLOCK_Flexio2PreDivBy6 = 5 , kCLOCK_Flexio2PreDivBy7 = 6 , kCLOCK_Flexio2PreDivBy8 = 7 ,   kCLOCK_Sai1PreDivBy1 = 0 , kCLOCK_Sai1PreDivBy2 = 1 , kCLOCK_Sai1PreDivBy3 = 2 , kCLOCK_Sai1PreDivBy4 = 3 ,   kCLOCK_Sai1PreDivBy5 = 4 , kCLOCK_Sai1PreDivBy6 = 5 , kCLOCK_Sai1PreDivBy7 = 6 , kCLOCK_Sai1PreDivBy8 = 7 ,   kCLOCK_Sai2PreDivBy1 = 0 , kCLOCK_Sai2PreDivBy2 = 1 , kCLOCK_Sai2PreDivBy3 = 2 , kCLOCK_Sai2PreDivBy4 = 3 ,   kCLOCK_Sai2PreDivBy5 = 4 , kCLOCK_Sai2PreDivBy6 = 5 , kCLOCK_Sai2PreDivBy7 = 6 , kCLOCK_Sai2PreDivBy8 = 7 ,   kCLOCK_Spdif0PreDivBy1 = 0 , kCLOCK_Spdif0PreDivBy2 = 1 , kCLOCK_Spdif0PreDivBy3 = 2 , kCLOCK_Spdif0PreDivBy4 = 3 ,   kCLOCK_Spdif0PreDivBy5 = 4 , kCLOCK_Spdif0PreDivBy6 = 5 , kCLOCK_Spdif0PreDivBy7 = 6 , kCLOCK_Spdif0PreDivBy8 = 7 ,   kCLOCK_Spdif0DivBy1 = 0 , kCLOCK_Spdif0DivBy2 = 1 , kCLOCK_Spdif0DivBy3 = 2 , kCLOCK_Spdif0DivBy4 = 3 ,   kCLOCK_Spdif0DivBy5 = 4 , kCLOCK_Spdif0DivBy6 = 5 , kCLOCK_Spdif0DivBy7 = 6 , kCLOCK_Spdif0DivBy8 = 7 ,   kCLOCK_Flexio1PreDivBy1 = 0 , kCLOCK_Flexio1PreDivBy2 = 1 , kCLOCK_Flexio1PreDivBy3 = 2 , kCLOCK_Flexio1PreDivBy4 = 3 ,   kCLOCK_Flexio1PreDivBy5 = 4 , kCLOCK_Flexio1PreDivBy6 = 5 , kCLOCK_Flexio1PreDivBy7 = 6 , kCLOCK_Flexio1PreDivBy8 = 7 ,   kCLOCK_Flexio1DivBy1 = 0 , kCLOCK_Flexio1DivBy2 = 1 , kCLOCK_Flexio1DivBy3 = 2 , kCLOCK_Flexio1DivBy4 = 3 ,   kCLOCK_Flexio1DivBy5 = 4 , kCLOCK_Flexio1DivBy6 = 5 , kCLOCK_Flexio1DivBy7 = 6 , kCLOCK_Flexio1DivBy8 = 7 ,   kCLOCK_LcdifPreDivBy1 = 0 , kCLOCK_LcdifPreDivBy2 = 1 , kCLOCK_LcdifPreDivBy3 = 2 , kCLOCK_LcdifPreDivBy4 = 3 ,   kCLOCK_LcdifPreDivBy5 = 4 , kCLOCK_LcdifPreDivBy6 = 5 , kCLOCK_LcdifPreDivBy7 = 6 , kCLOCK_LcdifPreDivBy8 = 7 ,   kCLOCK_CsiDivBy1 = 0 , kCLOCK_CsiDivBy2 = 1 , kCLOCK_CsiDivBy3 = 2 , kCLOCK_CsiDivBy4 = 3 ,   kCLOCK_CsiDivBy5 = 4 , kCLOCK_CsiDivBy6 = 5 , kCLOCK_CsiDivBy7 = 6 , kCLOCK_CsiDivBy8 = 7 ,   kCLOCK_MiscDivBy1 = 0 , kCLOCK_MiscDivBy2 = 1 , kCLOCK_MiscDivBy3 = 2 , kCLOCK_MiscDivBy4 = 3 ,   kCLOCK_MiscDivBy5 = 4 , kCLOCK_MiscDivBy6 = 5 , kCLOCK_MiscDivBy7 = 6 , kCLOCK_MiscDivBy8 = 7 ,   kCLOCK_MiscDivBy9 = 8 , kCLOCK_MiscDivBy10 = 9 , kCLOCK_MiscDivBy11 = 10 , kCLOCK_MiscDivBy12 = 11 ,   kCLOCK_MiscDivBy13 = 12 , kCLOCK_MiscDivBy14 = 13 , kCLOCK_MiscDivBy15 = 14 , kCLOCK_MiscDivBy16 = 15 ,   kCLOCK_MiscDivBy17 = 16 , kCLOCK_MiscDivBy18 = 17 , kCLOCK_MiscDivBy19 = 18 , kCLOCK_MiscDivBy20 = 19 ,   kCLOCK_MiscDivBy21 = 20 , kCLOCK_MiscDivBy22 = 21 , kCLOCK_MiscDivBy23 = 22 , kCLOCK_MiscDivBy24 = 23 ,   kCLOCK_MiscDivBy25 = 24 , kCLOCK_MiscDivBy26 = 25 , kCLOCK_MiscDivBy27 = 26 , kCLOCK_MiscDivBy28 = 27 ,   kCLOCK_MiscDivBy29 = 28 , kCLOCK_MiscDivBy30 = 29 , kCLOCK_MiscDivBy31 = 30 , kCLOCK_MiscDivBy32 = 31 ,   kCLOCK_MiscDivBy33 = 32 , kCLOCK_MiscDivBy34 = 33 , kCLOCK_MiscDivBy35 = 34 , kCLOCK_MiscDivBy36 = 35 ,   kCLOCK_MiscDivBy37 = 36 , kCLOCK_MiscDivBy38 = 37 , kCLOCK_MiscDivBy39 = 38 , kCLOCK_MiscDivBy40 = 39 ,   kCLOCK_MiscDivBy41 = 40 , kCLOCK_MiscDivBy42 = 41 , kCLOCK_MiscDivBy43 = 42 , kCLOCK_MiscDivBy44 = 43 ,   kCLOCK_MiscDivBy45 = 44 , kCLOCK_MiscDivBy46 = 45 , kCLOCK_MiscDivBy47 = 46 , kCLOCK_MiscDivBy48 = 47 ,   kCLOCK_MiscDivBy49 = 48 , kCLOCK_MiscDivBy50 = 49 , kCLOCK_MiscDivBy51 = 50 , kCLOCK_MiscDivBy52 = 51 ,   kCLOCK_MiscDivBy53 = 52 , kCLOCK_MiscDivBy54 = 53 , kCLOCK_MiscDivBy55 = 54 , kCLOCK_MiscDivBy56 = 55 ,   kCLOCK_MiscDivBy57 = 56 , kCLOCK_MiscDivBy58 = 57 , kCLOCK_MiscDivBy59 = 58 , kCLOCK_MiscDivBy60 = 59 ,   kCLOCK_MiscDivBy61 = 60 , kCLOCK_MiscDivBy62 = 61 , kCLOCK_MiscDivBy63 = 62 , kCLOCK_MiscDivBy64 = 63 }
	Clock divider value. More...
enum	_clock_usb_src { kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU , kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...
enum	_clock_usb_phy_src { kCLOCK_Usbphy480M = 0 , kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...
enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U , kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...
enum	_clock_pll {   kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT) , kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT) , kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT) , kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT) ,   kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT) , kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT) , kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT) , kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT) ,   kCLOCK_PllArm , kCLOCK_PllSys1 , kCLOCK_PllSys2 , kCLOCK_PllSys3 ,   kCLOCK_PllAudio , kCLOCK_PllVideo , kCLOCK_PllInvalid = -1 }
	PLL name. More...
enum	_clock_pfd {   kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U ,   kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...
enum	_clock_output1_selection {   kCLOCK_OutputPllUsb1 = 0U , kCLOCK_OutputPllSys = 1U , kCLOCK_OutputPllVideo = 3U , kCLOCK_OutputSemcClk = 5U ,   kCLOCK_OutputLcdifPixClk = 0xAU , kCLOCK_OutputAhbClk = 0xBU , kCLOCK_OutputIpgClk = 0xCU , kCLOCK_OutputPerClk = 0xDU ,   kCLOCK_OutputCkilSyncClk = 0xEU , kCLOCK_OutputPll4MainClk = 0xFU , kCLOCK_DisableClockOutput1 = 0x10U }
	The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on. More...
enum	_clock_output2_selection {   kCLOCK_OutputUsdhc1Clk = 3U , kCLOCK_OutputLpi2cClk = 6U , kCLOCK_OutputCsiClk = 0xBU , kCLOCK_OutputOscClk = 0xEU ,   kCLOCK_OutputUsdhc2Clk = 0x11U , kCLOCK_OutputSai1Clk = 0x12U , kCLOCK_OutputSai2Clk = 0x13U , kCLOCK_OutputSai3Clk = 0x14U ,   kCLOCK_OutputCanClk = 0x17U , kCLOCK_OutputFlexspiClk = 0x1BU , kCLOCK_OutputUartClk = 0x1CU , kCLOCK_OutputSpdif0Clk = 0x1DU ,   kCLOCK_DisableClockOutput2 = 0x1FU }
	The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on. More...
enum	_clock_output_divider {   kCLOCK_DivideBy1 = 0U , kCLOCK_DivideBy2 , kCLOCK_DivideBy3 , kCLOCK_DivideBy4 ,   kCLOCK_DivideBy5 , kCLOCK_DivideBy6 , kCLOCK_DivideBy7 , kCLOCK_DivideBy8 }
	The enumerator of clock output's divider. More...
enum	_clock_root {   kCLOCK_Usdhc1ClkRoot = 0U , kCLOCK_Usdhc2ClkRoot , kCLOCK_FlexspiClkRoot , kCLOCK_CsiClkRoot ,   kCLOCK_LpspiClkRoot , kCLOCK_TraceClkRoot , kCLOCK_Sai1ClkRoot , kCLOCK_Sai2ClkRoot ,   kCLOCK_Sai3ClkRoot , kCLOCK_Lpi2cClkRoot , kCLOCK_CanClkRoot , kCLOCK_UartClkRoot ,   kCLOCK_LcdifClkRoot , kCLOCK_SpdifClkRoot , kCLOCK_Flexio1ClkRoot , kCLOCK_Flexio2ClkRoot ,   kCLOCK_Root_M7 = 0 , kCLOCK_Root_M4 = 1 , kCLOCK_Root_Bus = 2 , kCLOCK_Root_Bus_Lpsr = 3 ,   kCLOCK_Root_Semc = 4 , kCLOCK_Root_Cssys = 5 , kCLOCK_Root_Cstrace = 6 , kCLOCK_Root_M4_Systick = 7 ,   kCLOCK_Root_M7_Systick = 8 , kCLOCK_Root_Adc1 = 9 , kCLOCK_Root_Adc2 = 10 , kCLOCK_Root_Acmp = 11 ,   kCLOCK_Root_Flexio1 = 12 , kCLOCK_Root_Flexio2 = 13 , kCLOCK_Root_Gpt1 = 14 , kCLOCK_Root_Gpt2 = 15 ,   kCLOCK_Root_Gpt3 = 16 , kCLOCK_Root_Gpt4 = 17 , kCLOCK_Root_Gpt5 = 18 , kCLOCK_Root_Gpt6 = 19 ,   kCLOCK_Root_Flexspi1 = 20 , kCLOCK_Root_Flexspi2 = 21 , kCLOCK_Root_Can1 = 22 , kCLOCK_Root_Can2 = 23 ,   kCLOCK_Root_Can3 = 24 , kCLOCK_Root_Lpuart1 = 25 , kCLOCK_Root_Lpuart2 = 26 , kCLOCK_Root_Lpuart3 = 27 ,   kCLOCK_Root_Lpuart4 = 28 , kCLOCK_Root_Lpuart5 = 29 , kCLOCK_Root_Lpuart6 = 30 , kCLOCK_Root_Lpuart7 = 31 ,   kCLOCK_Root_Lpuart8 = 32 , kCLOCK_Root_Lpuart9 = 33 , kCLOCK_Root_Lpuart10 = 34 , kCLOCK_Root_Lpuart11 = 35 ,   kCLOCK_Root_Lpuart12 = 36 , kCLOCK_Root_Lpi2c1 = 37 , kCLOCK_Root_Lpi2c2 = 38 , kCLOCK_Root_Lpi2c3 = 39 ,   kCLOCK_Root_Lpi2c4 = 40 , kCLOCK_Root_Lpi2c5 = 41 , kCLOCK_Root_Lpi2c6 = 42 , kCLOCK_Root_Lpspi1 = 43 ,   kCLOCK_Root_Lpspi2 = 44 , kCLOCK_Root_Lpspi3 = 45 , kCLOCK_Root_Lpspi4 = 46 , kCLOCK_Root_Lpspi5 = 47 ,   kCLOCK_Root_Lpspi6 = 48 , kCLOCK_Root_Emv1 = 49 , kCLOCK_Root_Emv2 = 50 , kCLOCK_Root_Enet1 = 51 ,   kCLOCK_Root_Enet2 = 52 , kCLOCK_Root_Enet_25m = 54 , kCLOCK_Root_Enet_Timer1 = 55 , kCLOCK_Root_Enet_Timer2 = 56 ,   kCLOCK_Root_Usdhc1 = 58 , kCLOCK_Root_Usdhc2 = 59 , kCLOCK_Root_Asrc = 60 , kCLOCK_Root_Mqs = 61 ,   kCLOCK_Root_Mic = 62 , kCLOCK_Root_Spdif = 63 , kCLOCK_Root_Sai1 = 64 , kCLOCK_Root_Sai2 = 65 ,   kCLOCK_Root_Sai3 = 66 , kCLOCK_Root_Sai4 = 67 , kCLOCK_Root_Gc355 = 68 , kCLOCK_Root_Lcdif = 69 ,   kCLOCK_Root_Lcdifv2 = 70 , kCLOCK_Root_Mipi_Ref = 71 , kCLOCK_Root_Mipi_Esc = 72 , kCLOCK_Root_Csi2 = 73 ,   kCLOCK_Root_Csi2_Esc = 74 , kCLOCK_Root_Csi2_Ui = 75 , kCLOCK_Root_Csi = 76 , kCLOCK_Root_Cko1 = 77 ,   kCLOCK_Root_Cko2 = 78 }
	The enumerator of clock root. More...
typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency.
typedef enum _clock_ip_name	clock_ip_name_t
	CCM CCGR gate control for each module independently.
typedef enum _clock_osc	clock_osc_t
	OSC 24M sorce select.
typedef enum _clock_gate_value	clock_gate_value_t
	Clock gate value.
typedef enum _clock_mode_t	clock_mode_t
	System clock mode.
typedef enum _clock_mux	clock_mux_t
	MUX control names for clock mux setting.
typedef enum _clock_div	clock_div_t
	DIV control names for clock div setting.
typedef enum _clock_div_value	clock_div_value_t
	Clock divider value.
typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition.
typedef enum _clock_usb_phy_src	clock_usb_phy_src_t
	Source of the USB HS PHY.
typedef struct _clock_arm_pll_config	clock_arm_pll_config_t
	PLL configuration for ARM.
typedef struct _clock_usb_pll_config	clock_usb_pll_config_t
	PLL configuration for USB.
typedef struct _clock_sys_pll_config	clock_sys_pll_config_t
	PLL configuration for System.
typedef struct _clock_audio_pll_config	clock_audio_pll_config_t
	PLL configuration for AUDIO and VIDEO.
typedef struct _clock_video_pll_config	clock_video_pll_config_t
	PLL configuration for AUDIO and VIDEO.
typedef struct _clock_enet_pll_config	clock_enet_pll_config_t
	PLL configuration for ENET.
typedef enum _clock_pll	clock_pll_t
	PLL name.
typedef enum _clock_pfd	clock_pfd_t
	PLL PFD name.
typedef enum _clock_output1_selection	clock_output1_selection_t
	The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
typedef enum _clock_output2_selection	clock_output2_selection_t
	The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
typedef enum _clock_output_divider	clock_output_divider_t
	The enumerator of clock output's divider.
typedef enum _clock_root	clock_root_t
	The enumerator of clock root.
volatile uint32_t	g_xtalFreq
	External XTAL (24M OSC/SYSOSC) clock frequency.
volatile uint32_t	g_rtcXtalFreq
	External RTC XTAL (32K OSC) clock frequency.
uint32_t	CLOCK_GetAhbFreq (void)
	Gets the AHB clock frequency.
uint32_t	CLOCK_GetSemcFreq (void)
	Gets the SEMC clock frequency.
uint32_t	CLOCK_GetIpgFreq (void)
	Gets the IPG clock frequency.
uint32_t	CLOCK_GetPerClkFreq (void)
	Gets the PER clock frequency.
uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name.
uint32_t	CLOCK_GetClockRootFreq (clock_root_t clockRoot)
	Gets the frequency of selected clock root.
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 5, 1))
	CLOCK driver version 2.5.1.
#define	SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY   (600000000UL)
#define	CCM_ANALOG_PLL_BYPASS_SHIFT   (16U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK   (0xC000U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT   (14U)
#define	CCSR_OFFSET   0x0C
	CCM registers offset.
#define	CBCDR_OFFSET   0x14
#define	CBCMR_OFFSET   0x18
#define	CSCMR1_OFFSET   0x1C
#define	CSCMR2_OFFSET   0x20
#define	CSCDR1_OFFSET   0x24
#define	CDCDR_OFFSET   0x30
#define	CSCDR2_OFFSET   0x38
#define	CSCDR3_OFFSET   0x3C
#define	CACRR_OFFSET   0x10
#define	CS1CDR_OFFSET   0x28
#define	CS2CDR_OFFSET   0x2C
#define	PLL_ARM_OFFSET   0x00
	CCM Analog registers offset.
#define	PLL_SYS_OFFSET   0x30
#define	PLL_USB1_OFFSET   0x10
#define	PLL_AUDIO_OFFSET   0x70
#define	PLL_VIDEO_OFFSET   0xA0
#define	PLL_ENET_OFFSET   0xE0
#define	PLL_USB2_OFFSET   0x20
#define	CCM_TUPLE(reg, shift, mask, busyShift)    (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define	CCM_TUPLE_REG(base, tuple)   (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
#define	CCM_TUPLE_SHIFT(tuple)   ((((uint32_t)tuple) >> 8U) & 0x1FU)
#define	CCM_TUPLE_MASK(tuple)    ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
#define	CCM_TUPLE_BUSY_SHIFT(tuple)   ((((uint32_t)tuple) >> 26U) & 0x3FU)
#define	CCM_NO_BUSY_WAIT   (0x20U)
#define	CCM_ANALOG_TUPLE(reg, shift)   ((((reg)&0xFFFU) << 16U) | (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.
#define	CCM_ANALOG_TUPLE_SHIFT(tuple)   (((uint32_t)tuple) & 0x1FU)
#define	CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)    (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
#define	CCM_ANALOG_TUPLE_REG(base, tuple)   CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
#define	CLKPN_FREQ   0U
	clock1PN frequency.
#define	CLOCK_SetXtal0Freq   CLOCK_SetXtalFreq
#define	CLOCK_SetXtal32Freq   CLOCK_SetRtcXtalFreq
#define	ADC_CLOCKS
	Clock ip name array for ADC.
#define	AOI_CLOCKS
	Clock ip name array for AOI.
#define	BEE_CLOCKS
	Clock ip name array for BEE.
#define	CMP_CLOCKS
	Clock ip name array for CMP.
#define	CSI_CLOCKS
	Clock ip name array for CSI.
#define	DCDC_CLOCKS
	Clock ip name array for DCDC.
#define	DCP_CLOCKS
	Clock ip name array for DCP.
#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS.
#define	EDMA_CLOCKS
	Clock ip name array for DMA.
#define	ENC_CLOCKS
	Clock ip name array for ENC.
#define	ENET_CLOCKS
	Clock ip name array for ENET.
#define	EWM_CLOCKS
	Clock ip name array for EWM.
#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN.
#define	FLEXCAN_PERIPH_CLOCKS
	Clock ip name array for FLEXCAN Peripheral clock.
#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO.
#define	FLEXRAM_CLOCKS
	Clock ip name array for FLEXRAM.
#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI.
#define	FLEXSPI_EXSC_CLOCKS
	Clock ip name array for FLEXSPI EXSC.
#define	GPIO_CLOCKS
	Clock ip name array for GPIO.
#define	GPT_CLOCKS
	Clock ip name array for GPT.
#define	KPP_CLOCKS
	Clock ip name array for KPP.
#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF.
#define	LCDIF_PERIPH_CLOCKS
	Clock ip name array for LCDIF PIXEL.
#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C.
#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI.
#define	LPUART_CLOCKS
	Clock ip name array for LPUART.
#define	MQS_CLOCKS
	Clock ip name array for MQS.
#define	OCRAM_EXSC_CLOCKS
	Clock ip name array for OCRAM EXSC.
#define	PIT_CLOCKS
	Clock ip name array for PIT.
#define	PWM_CLOCKS
	Clock ip name array for PWM.
#define	PXP_CLOCKS
	Clock ip name array for PXP.
#define	RTWDOG_CLOCKS
	Clock ip name array for RTWDOG.
#define	SAI_CLOCKS
	Clock ip name array for SAI.
#define	SEMC_CLOCKS
	Clock ip name array for SEMC.
#define	SEMC_EXSC_CLOCKS
	Clock ip name array for SEMC EXSC.
#define	TMR_CLOCKS
	Clock ip name array for QTIMER.
#define	TRNG_CLOCKS
	Clock ip name array for TRNG.
#define	TSC_CLOCKS
	Clock ip name array for TSC.
#define	WDOG_CLOCKS
	Clock ip name array for WDOG.
#define	USDHC_CLOCKS
	Clock ip name array for USDHC.
#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF.
#define	XBARA_CLOCKS
	Clock ip name array for XBARA.
#define	XBARB_CLOCKS
	Clock ip name array for XBARB.
#define	CLOCK_SOURCE_NONE   (0xFFU)
#define	CLOCK_ROOT_SOUCE
#define	CLOCK_ROOT_MUX_TUPLE
#define	CLOCK_ROOT_NONE_PRE_DIV   0UL
#define	CLOCK_ROOT_DIV_TUPLE
#define	kCLOCK_CoreSysClk   kCLOCK_CpuClk
#define	CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq

Driver version
enum	_clock_lpcg {   kCLOCK_M7 = 0 , kCLOCK_M4 = 1 , kCLOCK_Sim_M7 = 2 , kCLOCK_Sim_M = 3 ,   kCLOCK_Sim_Disp = 4 , kCLOCK_Sim_Per = 5 , kCLOCK_Sim_Lpsr = 6 , kCLOCK_Anadig = 7 ,   kCLOCK_Dcdc = 8 , kCLOCK_Src = 9 , kCLOCK_Ccm = 10 , kCLOCK_Gpc = 11 ,   kCLOCK_Ssarc = 12 , kCLOCK_Sim_R = 13 , kCLOCK_Wdog1 = 14 , kCLOCK_Wdog2 = 15 ,   kCLOCK_Wdog3 = 16 , kCLOCK_Wdog4 = 17 , kCLOCK_Ewm0 = 18 , kCLOCK_Sema = 19 ,   kCLOCK_Mu_A = 20 , kCLOCK_Mu_B = 21 , kCLOCK_Edma = 22 , kCLOCK_Edma_Lpsr = 23 ,   kCLOCK_Romcp = 24 , kCLOCK_Ocram = 25 , kCLOCK_Flexram = 26 , kCLOCK_Lmem = 27 ,   kCLOCK_Flexspi1 = 28 , kCLOCK_Flexspi2 = 29 , kCLOCK_Rdc = 30 , kCLOCK_M7_Xrdc = 31 ,   kCLOCK_M4_Xrdc = 32 , kCLOCK_Semc = 33 , kCLOCK_Xecc = 34 , kCLOCK_Iee = 35 ,   kCLOCK_Key_Manager = 36 , kCLOCK_Puf = 36 , kCLOCK_Ocotp = 37 , kCLOCK_Snvs_Hp = 38 ,   kCLOCK_Snvs = 39 , kCLOCK_Caam = 40 , kCLOCK_Jtag_Mux = 41 , kCLOCK_Cstrace = 42 ,   kCLOCK_Xbar1 = 43 , kCLOCK_Xbar2 = 44 , kCLOCK_Xbar3 = 45 , kCLOCK_Aoi1 = 46 ,   kCLOCK_Aoi2 = 47 , kCLOCK_Adc_Etc = 48 , kCLOCK_Iomuxc = 49 , kCLOCK_Iomuxc_Lpsr = 50 ,   kCLOCK_Gpio = 51 , kCLOCK_Kpp = 52 , kCLOCK_Flexio1 = 53 , kCLOCK_Flexio2 = 54 ,   kCLOCK_Lpadc1 = 55 , kCLOCK_Lpadc2 = 56 , kCLOCK_Dac = 57 , kCLOCK_Acmp1 = 58 ,   kCLOCK_Acmp2 = 59 , kCLOCK_Acmp3 = 60 , kCLOCK_Acmp4 = 61 , kCLOCK_Pit1 = 62 ,   kCLOCK_Pit2 = 63 , kCLOCK_Gpt1 = 64 , kCLOCK_Gpt2 = 65 , kCLOCK_Gpt3 = 66 ,   kCLOCK_Gpt4 = 67 , kCLOCK_Gpt5 = 68 , kCLOCK_Gpt6 = 69 , kCLOCK_Qtimer1 = 70 ,   kCLOCK_Qtimer2 = 71 , kCLOCK_Qtimer3 = 72 , kCLOCK_Qtimer4 = 73 , kCLOCK_Enc1 = 74 ,   kCLOCK_Enc2 = 75 , kCLOCK_Enc3 = 76 , kCLOCK_Enc4 = 77 , kCLOCK_Hrtimer = 78 ,   kCLOCK_Pwm1 = 79 , kCLOCK_Pwm2 = 80 , kCLOCK_Pwm3 = 81 , kCLOCK_Pwm4 = 82 ,   kCLOCK_Can1 = 83 , kCLOCK_Can2 = 84 , kCLOCK_Can3 = 85 , kCLOCK_Lpuart1 = 86 ,   kCLOCK_Lpuart2 = 87 , kCLOCK_Lpuart3 = 88 , kCLOCK_Lpuart4 = 89 , kCLOCK_Lpuart5 = 90 ,   kCLOCK_Lpuart6 = 91 , kCLOCK_Lpuart7 = 92 , kCLOCK_Lpuart8 = 93 , kCLOCK_Lpuart9 = 94 ,   kCLOCK_Lpuart10 = 95 , kCLOCK_Lpuart11 = 96 , kCLOCK_Lpuart12 = 97 , kCLOCK_Lpi2c1 = 98 ,   kCLOCK_Lpi2c2 = 99 , kCLOCK_Lpi2c3 = 100 , kCLOCK_Lpi2c4 = 101 , kCLOCK_Lpi2c5 = 102 ,   kCLOCK_Lpi2c6 = 103 , kCLOCK_Lpspi1 = 104 , kCLOCK_Lpspi2 = 105 , kCLOCK_Lpspi3 = 106 ,   kCLOCK_Lpspi4 = 107 , kCLOCK_Lpspi5 = 108 , kCLOCK_Lpspi6 = 109 , kCLOCK_Sim1 = 110 ,   kCLOCK_Sim2 = 111 , kCLOCK_Enet = 112 , kCLOCK_Enet_1g = 113 , kCLOCK_Usb = 115 ,   kCLOCK_Cdog = 116 , kCLOCK_Usdhc1 = 117 , kCLOCK_Usdhc2 = 118 , kCLOCK_Asrc = 119 ,   kCLOCK_Mqs = 120 , kCLOCK_Pdm = 121 , kCLOCK_Spdif = 122 , kCLOCK_Sai1 = 123 ,   kCLOCK_Sai2 = 124 , kCLOCK_Sai3 = 125 , kCLOCK_Sai4 = 126 , kCLOCK_Pxp = 127 ,   kCLOCK_Gpu2d = 128 , kCLOCK_Lcdif = 129 , kCLOCK_Lcdifv2 = 130 , kCLOCK_Mipi_Dsi = 131 ,   kCLOCK_Mipi_Csi = 132 , kCLOCK_Csi = 133 , kCLOCK_Dcic_Mipi = 134 , kCLOCK_Dcic_Lcd = 135 ,   kCLOCK_Video_Mux = 136 , kCLOCK_Uniq_Edt_I = 137 , kCLOCK_IpInvalid }
	Clock LPCG index. More...
enum	_clock_name {   kCLOCK_CpuClk = 0x0U , kCLOCK_AhbClk = 0x1U , kCLOCK_SemcClk = 0x2U , kCLOCK_IpgClk = 0x3U ,   kCLOCK_PerClk = 0x4U , kCLOCK_OscClk = 0x5U , kCLOCK_RtcClk = 0x6U , kCLOCK_ArmPllClk = 0x7U ,   kCLOCK_Usb1PllClk = 0x8U , kCLOCK_Usb1PllPfd0Clk = 0x9U , kCLOCK_Usb1PllPfd1Clk = 0xAU , kCLOCK_Usb1PllPfd2Clk = 0xBU ,   kCLOCK_Usb1PllPfd3Clk = 0xCU , kCLOCK_Usb1SwClk = 0x17U , kCLOCK_Usb1Sw120MClk = 0x18U , kCLOCK_Usb1Sw60MClk = 0x19U ,   kCLOCK_Usb1Sw80MClk = 0x1AU , kCLOCK_Usb2PllClk = 0xDU , kCLOCK_SysPllClk = 0xEU , kCLOCK_SysPllPfd0Clk = 0xFU ,   kCLOCK_SysPllPfd1Clk = 0x10U , kCLOCK_SysPllPfd2Clk = 0x11U , kCLOCK_SysPllPfd3Clk = 0x12U , kCLOCK_EnetPll0Clk = 0x13U ,   kCLOCK_EnetPll1Clk = 0x14U , kCLOCK_AudioPllClk = 0x15U , kCLOCK_VideoPllClk = 0x16U , kCLOCK_NoneName = CLOCK_SOURCE_NONE ,   kCLOCK_OscRc16M = 0 , kCLOCK_OscRc48M = 1 , kCLOCK_OscRc48MDiv2 = 2 , kCLOCK_OscRc400M = 3 ,   kCLOCK_Osc24M = 4 , kCLOCK_Osc24MOut = 5 , kCLOCK_ArmPll = 6 , kCLOCK_ArmPllOut = 7 ,   kCLOCK_SysPll2 = 8 , kCLOCK_SysPll2Out = 9 , kCLOCK_SysPll2Pfd0 = 10 , kCLOCK_SysPll2Pfd1 = 11 ,   kCLOCK_SysPll2Pfd2 = 12 , kCLOCK_SysPll2Pfd3 = 13 , kCLOCK_SysPll3 = 14 , kCLOCK_SysPll3Out = 15 ,   kCLOCK_SysPll3Div2 = 16 , kCLOCK_SysPll3Pfd0 = 17 , kCLOCK_SysPll3Pfd1 = 18 , kCLOCK_SysPll3Pfd2 = 19 ,   kCLOCK_SysPll3Pfd3 = 20 , kCLOCK_SysPll1 = 21 , kCLOCK_SysPll1Out = 22 , kCLOCK_SysPll1Div2 = 23 ,   kCLOCK_SysPll1Div5 = 24 , kCLOCK_AudioPll = 25 , kCLOCK_AudioPllOut = 26 , kCLOCK_VideoPll = 27 ,   kCLOCK_VideoPllOut = 28 , kCLOCK_CpuClk , kCLOCK_CoreSysClk , kCLOCK_Reserved = 0xFFU }
	Clock name. More...
enum	_clock_root {   kCLOCK_Usdhc1ClkRoot = 0U , kCLOCK_Usdhc2ClkRoot , kCLOCK_FlexspiClkRoot , kCLOCK_CsiClkRoot ,   kCLOCK_LpspiClkRoot , kCLOCK_TraceClkRoot , kCLOCK_Sai1ClkRoot , kCLOCK_Sai2ClkRoot ,   kCLOCK_Sai3ClkRoot , kCLOCK_Lpi2cClkRoot , kCLOCK_CanClkRoot , kCLOCK_UartClkRoot ,   kCLOCK_LcdifClkRoot , kCLOCK_SpdifClkRoot , kCLOCK_Flexio1ClkRoot , kCLOCK_Flexio2ClkRoot ,   kCLOCK_Root_M7 = 0 , kCLOCK_Root_M4 = 1 , kCLOCK_Root_Bus = 2 , kCLOCK_Root_Bus_Lpsr = 3 ,   kCLOCK_Root_Semc = 4 , kCLOCK_Root_Cssys = 5 , kCLOCK_Root_Cstrace = 6 , kCLOCK_Root_M4_Systick = 7 ,   kCLOCK_Root_M7_Systick = 8 , kCLOCK_Root_Adc1 = 9 , kCLOCK_Root_Adc2 = 10 , kCLOCK_Root_Acmp = 11 ,   kCLOCK_Root_Flexio1 = 12 , kCLOCK_Root_Flexio2 = 13 , kCLOCK_Root_Gpt1 = 14 , kCLOCK_Root_Gpt2 = 15 ,   kCLOCK_Root_Gpt3 = 16 , kCLOCK_Root_Gpt4 = 17 , kCLOCK_Root_Gpt5 = 18 , kCLOCK_Root_Gpt6 = 19 ,   kCLOCK_Root_Flexspi1 = 20 , kCLOCK_Root_Flexspi2 = 21 , kCLOCK_Root_Can1 = 22 , kCLOCK_Root_Can2 = 23 ,   kCLOCK_Root_Can3 = 24 , kCLOCK_Root_Lpuart1 = 25 , kCLOCK_Root_Lpuart2 = 26 , kCLOCK_Root_Lpuart3 = 27 ,   kCLOCK_Root_Lpuart4 = 28 , kCLOCK_Root_Lpuart5 = 29 , kCLOCK_Root_Lpuart6 = 30 , kCLOCK_Root_Lpuart7 = 31 ,   kCLOCK_Root_Lpuart8 = 32 , kCLOCK_Root_Lpuart9 = 33 , kCLOCK_Root_Lpuart10 = 34 , kCLOCK_Root_Lpuart11 = 35 ,   kCLOCK_Root_Lpuart12 = 36 , kCLOCK_Root_Lpi2c1 = 37 , kCLOCK_Root_Lpi2c2 = 38 , kCLOCK_Root_Lpi2c3 = 39 ,   kCLOCK_Root_Lpi2c4 = 40 , kCLOCK_Root_Lpi2c5 = 41 , kCLOCK_Root_Lpi2c6 = 42 , kCLOCK_Root_Lpspi1 = 43 ,   kCLOCK_Root_Lpspi2 = 44 , kCLOCK_Root_Lpspi3 = 45 , kCLOCK_Root_Lpspi4 = 46 , kCLOCK_Root_Lpspi5 = 47 ,   kCLOCK_Root_Lpspi6 = 48 , kCLOCK_Root_Emv1 = 49 , kCLOCK_Root_Emv2 = 50 , kCLOCK_Root_Enet1 = 51 ,   kCLOCK_Root_Enet2 = 52 , kCLOCK_Root_Enet_25m = 54 , kCLOCK_Root_Enet_Timer1 = 55 , kCLOCK_Root_Enet_Timer2 = 56 ,   kCLOCK_Root_Usdhc1 = 58 , kCLOCK_Root_Usdhc2 = 59 , kCLOCK_Root_Asrc = 60 , kCLOCK_Root_Mqs = 61 ,   kCLOCK_Root_Mic = 62 , kCLOCK_Root_Spdif = 63 , kCLOCK_Root_Sai1 = 64 , kCLOCK_Root_Sai2 = 65 ,   kCLOCK_Root_Sai3 = 66 , kCLOCK_Root_Sai4 = 67 , kCLOCK_Root_Gc355 = 68 , kCLOCK_Root_Lcdif = 69 ,   kCLOCK_Root_Lcdifv2 = 70 , kCLOCK_Root_Mipi_Ref = 71 , kCLOCK_Root_Mipi_Esc = 72 , kCLOCK_Root_Csi2 = 73 ,   kCLOCK_Root_Csi2_Esc = 74 , kCLOCK_Root_Csi2_Ui = 75 , kCLOCK_Root_Csi = 76 , kCLOCK_Root_Cko1 = 77 ,   kCLOCK_Root_Cko2 = 78 }
	Root clock index. More...
enum	_clock_root_mux_source {   kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M7_ClockRoot_MuxOsc24MOut = 1U , kCLOCK_M7_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M7_ClockRoot_MuxOscRc16M = 3U ,   kCLOCK_M7_ClockRoot_MuxArmPllOut = 4U , kCLOCK_M7_ClockRoot_MuxSysPll3Out = 6U , kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M4_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_M4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_M4_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_M4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_M4_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_BUS_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_BUS_ClockRoot_MuxOscRc400M = 2U , kCLOCK_BUS_ClockRoot_MuxOscRc16M = 3U , kCLOCK_BUS_ClockRoot_MuxSysPll3Out = 4U , kCLOCK_BUS_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_BUS_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M = 2U , kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M = 3U , kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SEMC_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SEMC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5 = 4U , kCLOCK_SEMC_ClockRoot_MuxSysPll2Out = 5U ,   kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1 = 6U , kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0 = 7U , kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CSSYS_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSSYS_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1 = 6U , kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out = 7U , kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M = 3U , kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M = 3U , kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 5U ,   kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 7U , kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ADC1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ADC1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_ADC1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ADC2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ADC2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_ADC2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ACMP_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ACMP_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 4U , kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_ACMP_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_GPT2_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_GPT2_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT3_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GPT3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_GPT3_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_GPT3_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT4_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GPT4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT5_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GPT5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT6_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GPT6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 4U , kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out = 5U ,   kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2 = 6U , kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out = 7U , kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0 = 4U , kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out = 5U ,   kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2 = 6U , kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out = 7U , kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CAN1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_CAN1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CAN2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_CAN2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CAN3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART7_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART7_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART8_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART8_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART9_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART9_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART10_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART10_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART11_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART11_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPUART12_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART12_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_EMV1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_EMV1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_EMV1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_EMV1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_EMV2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_EMV2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_EMV2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5 = 5U ,   kCLOCK_EMV2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ENET1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET1_ClockRoot_MuxAudioPllOut = 5U ,   kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ENET2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET2_ClockRoot_MuxAudioPllOut = 5U ,   kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut = 5U ,   kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut = 5U ,   kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut = 5U ,   kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_USDHC1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0 = 5U ,   kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_USDHC1_ClockRoot_MuxArmPllOut = 7U , kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_USDHC2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0 = 5U ,   kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_USDHC2_ClockRoot_MuxArmPllOut = 7U , kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ASRC_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ASRC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5 = 4U , kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2 = 5U ,   kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MQS_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_MQS_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MQS_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MQS_ClockRoot_MuxSysPll1Div5 = 4U , kCLOCK_MQS_ClockRoot_MuxSysPll3Div2 = 5U ,   kCLOCK_MQS_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MIC_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_MIC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MIC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_MIC_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_MIC_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SPDIF_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 5U ,   kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 5U ,   kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI3_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 5U ,   kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI4_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_SAI4_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GC355_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_GC355_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GC355_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GC355_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1 = 5U ,   kCLOCK_GC355_ClockRoot_MuxSysPll3Out = 6U , kCLOCK_GC355_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LCDIF_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LCDIF_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2 = 5U ,   kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2 = 5U ,   kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0 = 5U ,   kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0 = 5U ,   kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CSI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI2_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_CSI2_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CSI_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI_ClockRoot_MuxSysPll3Out = 5U ,   kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1 = 6U , kCLOCK_CSI_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CKO1_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CKO1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CKO1_ClockRoot_MuxSysPll2Out = 5U ,   kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1 = 6U , kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CKO2_ClockRoot_MuxOsc24MOut = 1U ,   kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CKO2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3 = 4U , kCLOCK_CKO2_ClockRoot_MuxOscRc48M = 5U ,   kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1 = 6U , kCLOCK_CKO2_ClockRoot_MuxAudioPllOut = 7U }
	The enumerator of clock roots' clock source mux value. More...
enum	_clock_group { kCLOCK_Group_FlexRAM = 0 , kCLOCK_Group_MipiDsi = 1 , kCLOCK_Group_Last }
	Clock group enumeration. More...
enum	_clock_osc { kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U , kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...
enum	_clock_gate_value {   kCLOCK_ClockNotNeeded = 0U , kCLOCK_ClockNeededRun = 1U , kCLOCK_ClockNeededRunWait = 3U , kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK ,   kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK }
	Clock gate value. More...
enum	_clock_mode_t {   kCLOCK_ModeRun = 0U , kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U , kCLOCK_ModeRun = 0U ,   kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U }
	System clock mode. More...
enum	_clock_usb_src { kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU , kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...
enum	_clock_usb_phy_src { kCLOCK_Usbphy480M = 0 , kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...
enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U , kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...
enum	_clock_pll_post_div { kCLOCK_PllPostDiv8 = 0U , kCLOCK_PllPostDiv4 = 1U }
	PLL post divider enumeration. More...
enum	_clock_pll {   kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT) , kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT) , kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT) , kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT) ,   kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT) , kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT) , kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT) , kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT) ,   kCLOCK_PllArm , kCLOCK_PllSys1 , kCLOCK_PllSys2 , kCLOCK_PllSys3 ,   kCLOCK_PllAudio , kCLOCK_PllVideo , kCLOCK_PllInvalid = -1 }
	PLL name. More...
enum	_clock_pfd {   kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U ,   kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...
enum	_clock_control_mode { kCLOCK_SoftwareMode = 0U , kCLOCK_GpcMode }
	The enumeration of control mode. More...
enum	_clock_24MOsc_mode { kCLOCK_24MOscHighGainMode = 0U , kCLOCK_24MOscBypassMode = 1U , kCLOCK_24MOscLowPowerMode = 2U }
	The enumeration of 24MHz crystal oscillator mode. More...
enum	_clock_16MOsc_source { kCLOCK_16MOscSourceFrom16MOsc = 0U , kCLOCK_16MOscSourceFrom24MOsc = 1U }
	The enumeration of 16MHz RC oscillator clock source. More...
enum	_clock_1MHzOut_behavior { kCLOCK_1MHzOutDisable = 0U , kCLOCK_1MHzOutEnableLocked1Mhz = 1U , kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U }
	The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. More...
enum	_clock_level {   kCLOCK_Level0 = 0x0UL , kCLOCK_Level1 = 0x1UL , kCLOCK_Level2 = 0x2UL , kCLOCK_Level3 = 0x3UL ,   kCLOCK_Level4 = 0x4UL }
	The clock dependence level. More...
typedef enum _clock_lpcg	clock_lpcg_t
	Clock LPCG index.
typedef enum _clock_name	clock_name_t
	Clock name.
typedef enum _clock_root	clock_root_t
	Root clock index.
typedef enum _clock_root_mux_source	clock_root_mux_source_t
	The enumerator of clock roots' clock source mux value.
typedef enum _clock_group	clock_group_t
	Clock group enumeration.
typedef struct _clock_group_config	clock_group_config_t
	The structure used to configure clock group.
typedef enum _clock_osc	clock_osc_t
	OSC 24M sorce select.
typedef enum _clock_gate_value	clock_gate_value_t
	Clock gate value.
typedef enum _clock_mode_t	clock_mode_t
	System clock mode.
typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition.
typedef enum _clock_usb_phy_src	clock_usb_phy_src_t
	Source of the USB HS PHY.
typedef enum _clock_pll_post_div	clock_pll_post_div_t
	PLL post divider enumeration.
typedef struct _clock_arm_pll_config	clock_arm_pll_config_t
	PLL configuration for ARM.
typedef struct _clock_usb_pll_config	clock_usb_pll_config_t
	PLL configuration for USB.
typedef struct _clock_pll_ss_config	clock_pll_ss_config_t
	Spread specturm configure Pll.
typedef struct _clock_sys_pll2_config	clock_sys_pll2_config_t
	PLL configure for Sys Pll2.
typedef struct _clock_sys_pll1_config	clock_sys_pll1_config_t
	PLL configure for Sys Pll1.
typedef struct _clock_audio_pll_config	clock_av_pll_config_t
	PLL configuration for AUDIO and VIDEO.
typedef struct _clock_audio_pll_config	clock_audio_pll_config_t
typedef struct _clock_audio_pll_config	clock_video_pll_config_t
typedef struct _clock_audio_pll_gpc_config	clock_audio_pll_gpc_config_t
	PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.
typedef struct _clock_audio_pll_gpc_config	clock_video_pll_gpc_config_t
typedef struct _clock_audio_pll_gpc_config	clock_sys_pll1_gpc_config_t
typedef struct _clock_enet_pll_config	clock_enet_pll_config_t
	PLL configuration for ENET.
typedef struct _clock_root_config_t	clock_root_config_t
	Clock root configuration.
typedef struct _clock_root_setpoint_config_t	clock_root_setpoint_config_t
	Clock root configuration in SetPoint Mode.
typedef enum _clock_pll	clock_pll_t
	PLL name.
typedef enum _clock_pfd	clock_pfd_t
	PLL PFD name.
typedef enum _clock_control_mode	clock_control_mode_t
	The enumeration of control mode.
typedef enum _clock_24MOsc_mode	clock_24MOsc_mode_t
	The enumeration of 24MHz crystal oscillator mode.
typedef enum _clock_16MOsc_source	clock_16MOsc_source_t
	The enumeration of 16MHz RC oscillator clock source.
typedef enum _clock_1MHzOut_behavior	clock_1MHzOut_behavior_t
	The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.
typedef enum _clock_level	clock_level_t
	The clock dependence level.
void	CLOCK_SetGroupConfig (clock_group_t group, const clock_group_config_t *config)
	Set the clock group configuration.
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 1, 2))
	CLOCK driver version.
#define	SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY   (240000000UL)
#define	CCSR_OFFSET   0x0C
	CCM registers offset.
#define	CBCDR_OFFSET   0x14
#define	CBCMR_OFFSET   0x18
#define	CSCMR1_OFFSET   0x1C
#define	CSCMR2_OFFSET   0x20
#define	CSCDR1_OFFSET   0x24
#define	CDCDR_OFFSET   0x30
#define	CSCDR2_OFFSET   0x38
#define	CSCDR3_OFFSET   0x3C
#define	CACRR_OFFSET   0x10
#define	CS1CDR_OFFSET   0x28
#define	CS2CDR_OFFSET   0x2C
#define	ARM_PLL_OFFSET   0x00
	CCM Analog registers offset.
#define	PLL_SYS_OFFSET   0x30
#define	PLL_USB1_OFFSET   0x10
#define	PLL_AUDIO_OFFSET   0x70
#define	PLL_VIDEO_OFFSET   0xA0
#define	PLL_ENET_OFFSET   0xE0
#define	PLL_USB2_OFFSET   0x20
#define	CCM_TUPLE(reg, shift, mask, busyShift)    (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define	CCM_TUPLE_REG(base, tuple)   (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
#define	CCM_TUPLE_SHIFT(tuple)   (((tuple) >> 8U) & 0x1FU)
#define	CCM_TUPLE_MASK(tuple)   ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
#define	CCM_TUPLE_BUSY_SHIFT(tuple)   (((tuple) >> 26U) & 0x3FU)
#define	CCM_BUSY_WAIT   (0x20U)
#define	CCM_ANALOG_TUPLE(reg, shift)   (((reg & 0xFFFU) << 16U) | (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.
#define	CCM_ANALOG_TUPLE_SHIFT(tuple)   (((uint32_t)tuple) & 0x1FU)
#define	CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)    (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
#define	CCM_ANALOG_TUPLE_REG(base, tuple)   CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
#define	SYS_PLL1_FREQ   (1000000000UL)
	SYS_PLL_FREQ frequency in Hz.
#define	SYS_PLL2_MFI   (22UL)
#define	SYS_PLL2_FREQ   (XTAL_FREQ * SYS_PLL2_MFI)
#define	SYS_PLL3_MFI   (20UL)
#define	SYS_PLL3_FREQ   (XTAL_FREQ * SYS_PLL3_MFI)
#define	XTAL_FREQ   (24000000UL)
#define	LPADC_CLOCKS
	Clock gate name array for ADC.
#define	ADC_ETC_CLOCKS
	Clock gate name array for ADC.
#define	AOI_CLOCKS
	Clock gate name array for AOI.
#define	DCDC_CLOCKS
	Clock gate name array for DCDC.
#define	DCDC_CLOCKS
	Clock gate name array for DCDC.
#define	SRC_CLOCKS
	Clock gate name array for SRC.
#define	GPC_CLOCKS
	Clock gate name array for GPC.
#define	SSARC_CLOCKS
	Clock gate name array for SSARC.
#define	WDOG_CLOCKS
	Clock gate name array for WDOG.
#define	EWM_CLOCKS
	Clock gate name array for EWM.
#define	SEMA_CLOCKS
	Clock gate name array for Sema.
#define	MU_CLOCKS
	Clock gate name array for MU.
#define	EDMA_CLOCKS
	Clock gate name array for EDMA.
#define	FLEXRAM_CLOCKS
	Clock gate name array for FLEXRAM.
#define	LMEM_CLOCKS
	Clock gate name array for LMEM.
#define	FLEXSPI_CLOCKS
	Clock gate name array for FLEXSPI.
#define	RDC_CLOCKS
	Clock gate name array for RDC.
#define	SEMC_CLOCKS
	Clock ip name array for SEMC.
#define	XECC_CLOCKS
	Clock ip name array for XECC.
#define	IEE_CLOCKS
	Clock ip name array for IEE.
#define	KEYMANAGER_CLOCKS
	Clock ip name array for KEY_MANAGER.
#define	PUF_CLOCKS
	Clock ip name array for PUF.
#define	OCOTP_CLOCKS
	Clock ip name array for OCOTP.
#define	CAAM_CLOCKS
	Clock ip name array for CAAM.
#define	XBAR_CLOCKS
	Clock ip name array for XBAR.
#define	IOMUXC_CLOCKS
	Clock ip name array for IOMUXC.
#define	GPIO_CLOCKS
	Clock ip name array for GPIO.
#define	KPP_CLOCKS
	Clock ip name array for KPP.
#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO.
#define	DAC_CLOCKS
	Clock ip name array for DAC.
#define	CMP_CLOCKS
	Clock ip name array for CMP.
#define	PIT_CLOCKS
	Clock ip name array for PIT.
#define	GPT_CLOCKS
	Clock ip name array for GPT.
#define	TMR_CLOCKS
	Clock ip name array for QTIMER.
#define	ENC_CLOCKS
	Clock ip name array for ENC.
#define	PWM_CLOCKS
	Clock ip name array for PWM.
#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN.
#define	LPUART_CLOCKS
	Clock ip name array for LPUART.
#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C.
#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI.
#define	EMVSIM_CLOCKS
	Clock ip name array for EMVSIM.
#define	ENET_CLOCKS
	Clock ip name array for ENET.
#define	USB_CLOCKS
	Clock ip name array for USB.
#define	CDOG_CLOCKS
	Clock ip name array for CDOG.
#define	USDHC_CLOCKS
	Clock ip name array for USDHC.
#define	ASRC_CLOCKS
	Clock ip name array for ASRC.
#define	MQS_CLOCKS
	Clock ip name array for MQS.
#define	PDM_CLOCKS
	Clock ip name array for PDM.
#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF.
#define	SAI_CLOCKS
	Clock ip name array for SAI.
#define	PXP_CLOCKS
	Clock ip name array for PXP.
#define	GPU2D_CLOCKS
	Clock ip name array for GPU2d.
#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF.
#define	LCDIFV2_CLOCKS
	Clock ip name array for LCDIFV2.
#define	MIPI_DSI_HOST_CLOCKS
	Clock ip name array for MIPI_DSI.
#define	MIPI_CSI2RX_CLOCKS
	Clock ip name array for MIPI_CSI.
#define	CSI_CLOCKS
	Clock ip name array for CSI.
#define	DCIC_CLOCKS
	Clock ip name array for DCIC.
#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS.
#define	XBARA_CLOCKS
	Clock ip name array for XBARA.
#define	XBARB_CLOCKS
	Clock ip name array for XBARB.
#define	CCM_OBS_M7_CLK_ROOT   128, 4
#define	CCM_OBS_M4_CLK_ROOT   129, 0
#define	CCM_OBS_BUS_CLK_ROOT   130, 2
#define	CCM_OBS_BUS_LPSR_CLK_ROOT   131, 0
#define	CCM_OBS_SEMC_CLK_ROOT   132, 2
#define	CCM_OBS_CSSYS_CLK_ROOT   133, 2
#define	CCM_OBS_CSTRACE_CLK_ROOT   134, 2
#define	CCM_OBS_M4_SYSTICK_CLK_ROOT   135, 0
#define	CCM_OBS_M7_SYSTICK_CLK_ROOT   136, 2
#define	CCM_OBS_ADC1_CLK_ROOT   137, 2
#define	CCM_OBS_ADC2_CLK_ROOT   138, 2
#define	CCM_OBS_ACMP_CLK_ROOT   139, 2
#define	CCM_OBS_FLEXIO1_CLK_ROOT   140, 2
#define	CCM_OBS_FLEXIO2_CLK_ROOT   141, 2
#define	CCM_OBS_GPT1_CLK_ROOT   142, 2
#define	CCM_OBS_GPT2_CLK_ROOT   143, 2
#define	CCM_OBS_GPT3_CLK_ROOT   144, 2
#define	CCM_OBS_GPT4_CLK_ROOT   145, 2
#define	CCM_OBS_GPT5_CLK_ROOT   146, 2
#define	CCM_OBS_GPT6_CLK_ROOT   147, 2
#define	CCM_OBS_FLEXSPI1_CLK_ROOT   148, 2
#define	CCM_OBS_FLEXSPI2_CLK_ROOT   149, 2
#define	CCM_OBS_CAN1_CLK_ROOT   150, 2
#define	CCM_OBS_CAN2_CLK_ROOT   151, 2
#define	CCM_OBS_CAN3_CLK_ROOT   152, 0
#define	CCM_OBS_LPUART1_CLK_ROOT   153, 2
#define	CCM_OBS_LPUART2_CLK_ROOT   154, 2
#define	CCM_OBS_LPUART3_CLK_ROOT   155, 2
#define	CCM_OBS_LPUART4_CLK_ROOT   156, 2
#define	CCM_OBS_LPUART5_CLK_ROOT   157, 2
#define	CCM_OBS_LPUART6_CLK_ROOT   158, 2
#define	CCM_OBS_LPUART7_CLK_ROOT   159, 2
#define	CCM_OBS_LPUART8_CLK_ROOT   160, 2
#define	CCM_OBS_LPUART9_CLK_ROOT   161, 2
#define	CCM_OBS_LPUART10_CLK_ROOT   162, 2
#define	CCM_OBS_LPUART11_CLK_ROOT   163, 0
#define	CCM_OBS_LPUART12_CLK_ROOT   164, 0
#define	CCM_OBS_LPI2C1_CLK_ROOT   165, 2
#define	CCM_OBS_LPI2C2_CLK_ROOT   166, 2
#define	CCM_OBS_LPI2C3_CLK_ROOT   167, 2
#define	CCM_OBS_LPI2C4_CLK_ROOT   168, 2
#define	CCM_OBS_LPI2C5_CLK_ROOT   169, 0
#define	CCM_OBS_LPI2C6_CLK_ROOT   170, 0
#define	CCM_OBS_LPSPI1_CLK_ROOT   171, 2
#define	CCM_OBS_LPSPI2_CLK_ROOT   172, 2
#define	CCM_OBS_LPSPI3_CLK_ROOT   173, 2
#define	CCM_OBS_LPSPI4_CLK_ROOT   174, 2
#define	CCM_OBS_LPSPI5_CLK_ROOT   175, 0
#define	CCM_OBS_LPSPI6_CLK_ROOT   176, 0
#define	CCM_OBS_EMV1_CLK_ROOT   177, 2
#define	CCM_OBS_EMV2_CLK_ROOT   178, 2
#define	CCM_OBS_ENET1_CLK_ROOT   179, 2
#define	CCM_OBS_ENET2_CLK_ROOT   180, 2
#define	CCM_OBS_ENET_25M_CLK_ROOT   182, 2
#define	CCM_OBS_ENET_TIMER1_CLK_ROOT   183, 2
#define	CCM_OBS_ENET_TIMER2_CLK_ROOT   184, 2
#define	CCM_OBS_USDHC1_CLK_ROOT   186, 2
#define	CCM_OBS_USDHC2_CLK_ROOT   187, 2
#define	CCM_OBS_ASRC_CLK_ROOT   188, 2
#define	CCM_OBS_MQS_CLK_ROOT   189, 2
#define	CCM_OBS_MIC_CLK_ROOT   190, 0
#define	CCM_OBS_SPDIF_CLK_ROOT   191, 2
#define	CCM_OBS_SAI1_CLK_ROOT   192, 2
#define	CCM_OBS_SAI2_CLK_ROOT   193, 2
#define	CCM_OBS_SAI3_CLK_ROOT   194, 2
#define	CCM_OBS_SAI4_CLK_ROOT   195, 0
#define	CCM_OBS_GC355_CLK_ROOT   196, 2
#define	CCM_OBS_LCDIF_CLK_ROOT   197, 2
#define	CCM_OBS_LCDIFV2_CLK_ROOT   198, 2
#define	CCM_OBS_MIPI_REF_CLK_ROOT   199, 2
#define	CCM_OBS_MIPI_ESC_CLK_ROOT   200, 2
#define	CCM_OBS_CSI2_CLK_ROOT   201, 2
#define	CCM_OBS_CSI2_ESC_CLK_ROOT   202, 2
#define	CCM_OBS_CSI2_UI_CLK_ROOT   203, 2
#define	CCM_OBS_CSI_CLK_ROOT   204, 2
#define	CCM_OBS_CCM_CKO1_CLK_ROOT   205, 0
#define	CCM_OBS_CCM_CKO2_CLK_ROOT   206, 2
#define	CCM_OBS_CM7_CORE_STCLKEN   207, 4
#define	CCM_OBS_CCM_FLEXRAM_CLK_ROOT   208, 4
#define	CCM_OBS_MIPI_DSI_TXESC   209, 2
#define	CCM_OBS_MIPI_DSI_RXESC   210, 2
#define	CCM_OBS_OSC_RC_16M   224, 0
#define	CCM_OBS_OSC_RC_48M   225, 0
#define	CCM_OBS_OSC_RC_48M_DIV2   226, 0
#define	CCM_OBS_OSC_RC_400M   227, 0
#define	CCM_OBS_OSC_24M_OUT   229, 0
#define	CCM_OBS_ARM_PLL_OUT   231, 2
#define	CCM_OBS_SYS_PLL2_OUT   233, 2
#define	CCM_OBS_SYS_PLL2_PFD0   234, 2
#define	CCM_OBS_SYS_PLL2_PFD1   235, 2
#define	CCM_OBS_SYS_PLL2_PFD2   236, 2
#define	CCM_OBS_SYS_PLL2_PFD3   237, 2
#define	CCM_OBS_SYS_PLL3_OUT   239, 2
#define	CCM_OBS_SYS_PLL3_DIV2   240, 2
#define	CCM_OBS_SYS_PLL3_PFD0   241, 2
#define	CCM_OBS_SYS_PLL3_PFD1   242, 2
#define	CCM_OBS_SYS_PLL3_PFD2   243, 2
#define	CCM_OBS_SYS_PLL3_PFD3   244, 2
#define	CCM_OBS_SYS_PLL1_OUT   246, 2
#define	CCM_OBS_SYS_PLL1_DIV2   247, 2
#define	CCM_OBS_SYS_PLL1_DIV5   248, 2
#define	CCM_OBS_PLL_AUDIO_OUT   250, 2
#define	CCM_OBS_PLL_VIDEO_OUT   252, 2
#define	CCM_OBS_DIV   3
#define	clock_ip_name_t   clock_lpcg_t
#define	CLOCK_GetCpuClkFreq   CLOCK_GetM4Freq
#define	CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq
#define	PLL_PFD_COUNT   4

OSC operations
void	CLOCK_InitExternalClk (bool bypassXtalOsc)
	Initialize the external 24MHz clock.
void	CLOCK_DeinitExternalClk (void)
	Deinitialize the external 24MHz clock.
void	CLOCK_SwitchOsc (clock_osc_t osc)
	Switch the OSC.
void	CLOCK_InitRcOsc24M (void)
	Initialize the RC oscillator 24MHz clock.
void	CLOCK_DeinitRcOsc24M (void)
	Power down the RCOSC 24M clock.
bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock.
bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock.

PLL/PFD operations
void	CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
	Initialize the ARM PLL.
void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL.
void	CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
	Initialize the System PLL.
void	CLOCK_DeinitSysPll (void)
	De-initialize the System PLL.
void	CLOCK_InitUsb1Pll (const clock_usb_pll_config_t *config)
	Initialize the USB1 PLL.
void	CLOCK_DeinitUsb1Pll (void)
	Deinitialize the USB1 PLL.
void	CLOCK_InitUsb2Pll (const clock_usb_pll_config_t *config)
	Initialize the USB2 PLL.
void	CLOCK_DeinitUsb2Pll (void)
	Deinitialize the USB2 PLL.
void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL.
void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL.
void	CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
	Initialize the video PLL.
void	CLOCK_DeinitVideoPll (void)
	De-initialize the Video PLL.
void	CLOCK_InitEnetPll (const clock_enet_pll_config_t *config)
	Initialize the ENET PLL.
void	CLOCK_DeinitEnetPll (void)
	Deinitialize the ENET PLL.
uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency.
void	CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the System PLL PFD.
void	CLOCK_DeinitSysPfd (clock_pfd_t pfd)
	De-initialize the System PLL PFD.
bool	CLOCK_IsSysPfdEnabled (clock_pfd_t pfd)
	Check if Sys PFD is enabled.
void	CLOCK_InitUsb1Pfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the USB1 PLL PFD.
void	CLOCK_DeinitUsb1Pfd (clock_pfd_t pfd)
	De-initialize the USB1 PLL PFD.
bool	CLOCK_IsUsb1PfdEnabled (clock_pfd_t pfd)
	Check if Usb1 PFD is enabled.
uint32_t	CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
	Get current System PLL PFD output frequency.
uint32_t	CLOCK_GetUsb1PfdFreq (clock_pfd_t pfd)
	Get current USB1 PLL PFD output frequency.
bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock.
void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock.
bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock.
void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock.

Clock Output Inferfaces
void	CLOCK_SetClockOutput1 (clock_output1_selection_t selection, clock_output_divider_t divider)
	Set the clock source and the divider of the clock output1.
void	CLOCK_SetClockOutput2 (clock_output2_selection_t selection, clock_output_divider_t divider)
	Set the clock source and the divider of the clock output2.
uint32_t	CLOCK_GetClockOutCLKO1Freq (void)
	Get the frequency of clock output1 clock signal.
uint32_t	CLOCK_GetClockOutClkO2Freq (void)
	Get the frequency of clock output2 clock signal.

OSC operations
void	CLOCK_OSC_EnableOsc24M (void)
	Enable OSC 24Mhz.
void	CLOCK_OSC_SetOsc24MWorkMode (clock_24MOsc_mode_t workMode)
	Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.
void	CLOCK_OSC_EnableOscRc400M (void)
	Enable OSC RC 400Mhz.
void	CLOCK_OSC_TrimOscRc400M (bool enable, bool bypass, uint16_t trim)
	Trims OSC RC 400MHz.
void	CLOCK_OSC_SetOscRc400MRefClkDiv (uint8_t divValue)
	Set the divide value for ref_clk to generate slow clock.
void	CLOCK_OSC_SetOscRc400MFastClkCount (uint16_t targetCount)
	Set the target count for the fast clock.
void	CLOCK_OSC_SetOscRc400MHysteresisValue (uint8_t negHysteresis, uint8_t posHysteresis)
	Set the negative and positive hysteresis value for the tuned clock.
void	CLOCK_OSC_BypassOscRc400MTuneLogic (bool enableBypass)
	Bypass/un-bypass the tune logic.
void	CLOCK_OSC_EnableOscRc400MTuneLogic (bool enable)
	Start/Stop the tune logic.
void	CLOCK_OSC_FreezeOscRc400MTuneValue (bool enableFreeze)
	Freeze/Unfreeze the tuning value.
void	CLOCK_OSC_SetOscRc400MTuneValue (uint8_t tuneValue)
	Set the 400MHz RC oscillator tune value when the tune logic is disabled.
void	CLOCK_OSC_Set1MHzOutputBehavior (clock_1MHzOut_behavior_t behavior)
	Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.
void	CLOCK_OSC_SetLocked1MHzCount (uint16_t count)
	Set the count for the locked 1MHz clock out.
bool	CLOCK_OSC_CheckLocked1MHzErrorFlag (void)
	Check the error flag for locked 1MHz clock out.
void	CLOCK_OSC_ClearLocked1MHzErrorFlag (void)
	Clear the error flag for locked 1MHz clock out.
uint16_t	CLOCK_OSC_GetCurrentOscRc400MFastClockCount (void)
	Get current count for the fast clock during the tune process.
uint8_t	CLOCK_OSC_GetCurrentOscRc400MTuneValue (void)
	Get current tune value used by oscillator during tune process.
void	CLOCK_OSC_SetOsc16MConfig (clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut)
	Configure the 16MHz oscillator.
status_t	CLOCK_CalcArmPllFreq (clock_arm_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency.
status_t	CLOCK_InitArmPllWithFreq (uint32_t freqInMhz)
	Initializes the Arm PLL with Specific Frequency (in Mhz).
void	CLOCK_CalcPllSpreadSpectrum (uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
	Calculate spread spectrum step and stop.
void	CLOCK_InitSysPll1 (const clock_sys_pll1_config_t *config)
	Initialize the System PLL1.
void	CLOCK_DeinitSysPll1 (void)
	De-initialize the System PLL1.
void	CLOCK_GPC_SetSysPll1OutputFreq (const clock_sys_pll1_gpc_config_t *config)
	Set System PLL1 output frequency in GPC mode.
void	CLOCK_InitSysPll2 (const clock_sys_pll2_config_t *config)
	Initialize the System PLL2.
void	CLOCK_DeinitSysPll2 (void)
	De-initialize the System PLL2.
bool	CLOCK_IsSysPll2PfdEnabled (clock_pfd_t pfd)
	Check if Sys PLL2 PFD is enabled.
void	CLOCK_InitSysPll3 (void)
	Initialize the System PLL3.
void	CLOCK_DeinitSysPll3 (void)
	De-initialize the System PLL3.
bool	CLOCK_IsSysPll3PfdEnabled (clock_pfd_t pfd)
	Check if Sys PLL3 PFD is enabled.

PLL/PFD operations
void	CLOCK_SetPllBypass (clock_pll_t pll, bool bypass)
	PLL bypass setting.
status_t	CLOCK_CalcAvPllFreq (clock_av_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency.
status_t	CLOCK_InitAudioPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Audio PLL with Specific Frequency (in Mhz).
void	CLOCK_GPC_SetAudioPllOutputFreq (const clock_audio_pll_gpc_config_t *config)
	Set Audio PLL output frequency in GPC mode.
status_t	CLOCK_InitVideoPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Video PLL with Specific Frequency (in Mhz).
void	CLOCK_GPC_SetVideoPllOutputFreq (const clock_video_pll_gpc_config_t *config)
	Set Video PLL output frequency in GPC mode.
void	CLOCK_InitPfd (clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
	Initialize PLL PFD.
void	CLOCK_DeinitPfd (clock_pll_t pll, clock_pfd_t pfd)
	De-initialize selected PLL PFD.
uint32_t	CLOCK_GetPfdFreq (clock_pll_t pll, clock_pfd_t pfd)
	Get current PFD output frequency.
uint32_t	CLOCK_GetFreqFromObs (uint32_t obsSigIndex, uint32_t obsIndex)
void	CLOCK_OSCPLL_ControlBySetPointMode (clock_name_t name, uint16_t spValue, uint16_t stbyValue)
	Set this clock works in SetPoint control Mode.
void	CLOCK_OSCPLL_ControlByCpuLowPowerMode (clock_name_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
	Set this clock works in CPU Low Power Mode.
void	CLOCK_ROOT_ControlBySetPointMode (clock_root_t name, const clock_root_setpoint_config_t *spTable)
	Set this clock works in SetPoint controlled Mode.
void	CLOCK_LPCG_ControlBySetPointMode (clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue)
	Set this clock works in SetPoint control Mode.
void	CLOCK_LPCG_ControlByCpuLowPowerMode (clock_lpcg_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
	Set this clock works in CPU Low Power Mode.

Detailed Description

Macro Definition Documentation

ADC_CLOCKS

#define ADC_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
    }

Clock ip name array for ADC.

ADC_ETC_CLOCKS

#define ADC_ETC_CLOCKS

Value:

    {                  \
        kCLOCK_Adc_Etc \
    }

Clock gate name array for ADC.

AOI_CLOCKS [1/2]

#define AOI_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
    }

Clock ip name array for AOI.

AOI_CLOCKS [2/2]

#define AOI_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
    }

Clock gate name array for AOI.

ASRC_CLOCKS

#define ASRC_CLOCKS

Value:

    {               \
        kCLOCK_Asrc \
    }

Clock ip name array for ASRC.

BEE_CLOCKS

#define BEE_CLOCKS

Value:

    {              \
        kCLOCK_Bee \
    }

Clock ip name array for BEE.

CAAM_CLOCKS

#define CAAM_CLOCKS

Value:

    {               \
        kCLOCK_Caam \
    }

Clock ip name array for CAAM.

CDOG_CLOCKS

#define CDOG_CLOCKS

Value:

    {               \
        kCLOCK_Cdog \
    }

Clock ip name array for CDOG.

CLOCK_GetCoreSysClkFreq [1/2]

#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq

For compatible with other platforms without CCM.

CLOCK_GetCoreSysClkFreq [2/2]

#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq

For compatible with other platforms without CCM.

CLOCK_ROOT_DIV_TUPLE

#define CLOCK_ROOT_DIV_TUPLE

Value:

    {                                                                                             \
        {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div},             \
            {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_CsiDiv},           \
            {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv},           \
            {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div},             \
            {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv},            \
            {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv},              \
            {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div},       \
            {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
    }

CLOCK_ROOT_MUX_TUPLE

#define CLOCK_ROOT_MUX_TUPLE

Value:

    {                                                                                                           \
        kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_CsiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \
            kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux,     \
            kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux,                          \
    }

CMP_CLOCKS [1/2]

#define CMP_CLOCKS

Value:

    {                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }

Clock ip name array for CMP.

CMP_CLOCKS [2/2]

#define CMP_CLOCKS

Value:

    {                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }

Clock ip name array for CMP.

CSI_CLOCKS [1/2]

#define CSI_CLOCKS

Value:

    {              \
        kCLOCK_Csi \
    }

Clock ip name array for CSI.

CSI_CLOCKS [2/2]

#define CSI_CLOCKS

Value:

    {              \
        kCLOCK_Csi \
    }

Clock ip name array for CSI.

DAC_CLOCKS

#define DAC_CLOCKS

Value:

    {              \
        kCLOCK_Dac \
    }

Clock ip name array for DAC.

DCDC_CLOCKS [1/3]

#define DCDC_CLOCKS

Value:

    {               \
        kCLOCK_Dcdc \
    }

Clock ip name array for DCDC.

DCDC_CLOCKS [2/3]

#define DCDC_CLOCKS

Value:

    {               \
        kCLOCK_Dcdc \
    }

Clock gate name array for DCDC.

Clock ip name array for DCDC.

DCDC_CLOCKS [3/3]

#define DCDC_CLOCKS

Value:

    {               \
        kCLOCK_Dcdc \
    }

Clock gate name array for DCDC.

Clock ip name array for DCDC.

DCIC_CLOCKS

#define DCIC_CLOCKS

Value:

    {                                                       \
        kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \
    }

Clock ip name array for DCIC.

DCP_CLOCKS

#define DCP_CLOCKS

Value:

    {              \
        kCLOCK_Dcp \
    }

Clock ip name array for DCP.

DMAMUX_CLOCKS [1/2]

#define DMAMUX_CLOCKS

Value:

    {                 \
        kCLOCK_Dma    \
    }

Clock ip name array for DMAMUX_CLOCKS.

DMAMUX_CLOCKS [2/2]

#define DMAMUX_CLOCKS

Value:

    {                                 \
        kCLOCK_Edma, kCLOCK_Edma_Lpsr \
    }

Clock ip name array for DMAMUX_CLOCKS.

EDMA_CLOCKS [1/2]

#define EDMA_CLOCKS

Value:

    {               \
        kCLOCK_Dma  \
    }

Clock ip name array for DMA.

EDMA_CLOCKS [2/2]

#define EDMA_CLOCKS

Value:

    {                                 \
        kCLOCK_Edma, kCLOCK_Edma_Lpsr \
    }

Clock gate name array for EDMA.

EMVSIM_CLOCKS

#define EMVSIM_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \
    }

Clock ip name array for EMVSIM.

ENC_CLOCKS [1/2]

#define ENC_CLOCKS

Value:

    {                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }

Clock ip name array for ENC.

ENC_CLOCKS [2/2]

#define ENC_CLOCKS

Value:

    {                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }

Clock ip name array for ENC.

ENET_CLOCKS [1/2]

#define ENET_CLOCKS

Value:

    {               \
        kCLOCK_Enet \
    }

Clock ip name array for ENET.

ENET_CLOCKS [2/2]

#define ENET_CLOCKS

Value:

    {                               \
        kCLOCK_Enet, kCLOCK_Enet_1g \
    }

Clock ip name array for ENET.

EWM_CLOCKS [1/2]

#define EWM_CLOCKS

Value:

    {               \
        kCLOCK_Ewm0 \
    }

Clock ip name array for EWM.

EWM_CLOCKS [2/2]

#define EWM_CLOCKS

Value:

    {               \
        kCLOCK_Ewm0 \
    }

Clock gate name array for EWM.

FLEXCAN_CLOCKS [1/2]

#define FLEXCAN_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
    }

Clock ip name array for FLEXCAN.

FLEXCAN_CLOCKS [2/2]

#define FLEXCAN_CLOCKS

Value:

    {                                                           \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
    }

Clock ip name array for FLEXCAN.

FLEXCAN_PERIPH_CLOCKS

#define FLEXCAN_PERIPH_CLOCKS

Value:

    {                                                \
        kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
    }

Clock ip name array for FLEXCAN Peripheral clock.

FLEXIO_CLOCKS [1/2]

#define FLEXIO_CLOCKS

Value:

    {                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }

Clock ip name array for FLEXIO.

FLEXIO_CLOCKS [2/2]

#define FLEXIO_CLOCKS

Value:

    {                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }

Clock ip name array for FLEXIO.

FLEXRAM_CLOCKS [1/2]

#define FLEXRAM_CLOCKS

Value:

    {                  \
        kCLOCK_FlexRam \
    }

Clock ip name array for FLEXRAM.

FLEXRAM_CLOCKS [2/2]

#define FLEXRAM_CLOCKS

Value:

    {                  \
        kCLOCK_Flexram \
    }

Clock gate name array for FLEXRAM.

FLEXSPI_CLOCKS [1/2]

#define FLEXSPI_CLOCKS

Value:

    {                  \
        kCLOCK_FlexSpi \
    }

Clock ip name array for FLEXSPI.

FLEXSPI_CLOCKS [2/2]

#define FLEXSPI_CLOCKS

Value:

    {                                                      \
        kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
    }

Clock gate name array for FLEXSPI.

FLEXSPI_EXSC_CLOCKS

#define FLEXSPI_EXSC_CLOCKS

Value:

    {                       \
        kCLOCK_FlexSpiExsc  \
    }

Clock ip name array for FLEXSPI EXSC.

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL [1/2]

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL [2/2]

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

GPC_CLOCKS

#define GPC_CLOCKS

Value:

    {              \
        kCLOCK_Gpc \
    }

Clock gate name array for GPC.

GPIO_CLOCKS [1/2]

#define GPIO_CLOCKS

Value:

    {                                                                                          \
        kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
    }

Clock ip name array for GPIO.

GPIO_CLOCKS [2/2]

#define GPIO_CLOCKS

Value:

    {                                                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
            kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio,                            \
    }

Clock ip name array for GPIO.

GPT_CLOCKS [1/2]

#define GPT_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
    }

Clock ip name array for GPT.

GPT_CLOCKS [2/2]

#define GPT_CLOCKS

Value:

    {                                                                                                  \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \
    }

Clock ip name array for GPT.

GPU2D_CLOCKS

#define GPU2D_CLOCKS

Value:

    {                \
        kCLOCK_Gpu2d \
    }

Clock ip name array for GPU2d.

IEE_CLOCKS

#define IEE_CLOCKS

Value:

    {              \
        kCLOCK_Iee \
    }

Clock ip name array for IEE.

IOMUXC_CLOCKS

#define IOMUXC_CLOCKS

Value:

    {                                     \
        kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \
    }

Clock ip name array for IOMUXC.

kCLOCK_CoreSysClk

#define kCLOCK_CoreSysClk   kCLOCK_CpuClk

For compatible with other platforms without CCM.

KEYMANAGER_CLOCKS

#define KEYMANAGER_CLOCKS

Value:

    {                      \
        kCLOCK_Key_Manager \
    }

Clock ip name array for KEY_MANAGER.

KPP_CLOCKS [1/2]

#define KPP_CLOCKS

Value:

    {              \
        kCLOCK_Kpp \
    }

Clock ip name array for KPP.

KPP_CLOCKS [2/2]

#define KPP_CLOCKS

Value:

    {              \
        kCLOCK_Kpp \
    }

Clock ip name array for KPP.

LCDIF_CLOCKS [1/2]

#define LCDIF_CLOCKS

Value:

    {                \
        kCLOCK_Lcd   \
    }

Clock ip name array for LCDIF.

LCDIF_CLOCKS [2/2]

#define LCDIF_CLOCKS

Value:

    {                \
        kCLOCK_Lcdif \
    }

Clock ip name array for LCDIF.

LCDIF_PERIPH_CLOCKS

#define LCDIF_PERIPH_CLOCKS

Value:

    {                       \
        kCLOCK_LcdPixel     \
    }

Clock ip name array for LCDIF PIXEL.

LCDIFV2_CLOCKS

#define LCDIFV2_CLOCKS

Value:

    {                  \
        kCLOCK_Lcdifv2 \
    }

Clock ip name array for LCDIFV2.

LMEM_CLOCKS

#define LMEM_CLOCKS

Value:

    {               \
        kCLOCK_Lmem \
    }

Clock gate name array for LMEM.

LPADC_CLOCKS

#define LPADC_CLOCKS

Value:

    {                                                  \
        kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \
    }

Clock gate name array for ADC.

LPI2C_CLOCKS [1/2]

#define LPI2C_CLOCKS

Value:

    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
    }

Clock ip name array for LPI2C.

LPI2C_CLOCKS [2/2]

#define LPI2C_CLOCKS

Value:

    {                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
    }

Clock ip name array for LPI2C.

LPSPI_CLOCKS [1/2]

#define LPSPI_CLOCKS

Value:

    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
    }

Clock ip name array for LPSPI.

LPSPI_CLOCKS [2/2]

#define LPSPI_CLOCKS

Value:

    {                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
    }

Clock ip name array for LPSPI.

LPUART_CLOCKS [1/2]

#define LPUART_CLOCKS

Value:

    {                                                                                                     \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8                                                \
    }

Clock ip name array for LPUART.

LPUART_CLOCKS [2/2]

#define LPUART_CLOCKS

Value:

    {                                                                                                         \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5,     \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
            kCLOCK_Lpuart12                                                                                   \
    }

Clock ip name array for LPUART.

MIPI_CSI2RX_CLOCKS

#define MIPI_CSI2RX_CLOCKS

Value:

    {                      \
        kCLOCK_Mipi_Csi    \
    }

Clock ip name array for MIPI_CSI.

MIPI_DSI_HOST_CLOCKS

#define MIPI_DSI_HOST_CLOCKS

Value:

    {                        \
        kCLOCK_Mipi_Dsi      \
    }

Clock ip name array for MIPI_DSI.

MQS_CLOCKS [1/2]

#define MQS_CLOCKS

Value:

    {              \
        kCLOCK_Mqs \
    }

Clock ip name array for MQS.

MQS_CLOCKS [2/2]

#define MQS_CLOCKS

Value:

    {              \
        kCLOCK_Mqs \
    }

Clock ip name array for MQS.

MU_CLOCKS

#define MU_CLOCKS

Value:

    {               \
        kCLOCK_Mu_B \
    }

Clock gate name array for MU.

OCOTP_CLOCKS

#define OCOTP_CLOCKS

Value:

    {                \
        kCLOCK_Ocotp \
    }

Clock ip name array for OCOTP.

OCRAM_EXSC_CLOCKS

#define OCRAM_EXSC_CLOCKS

Value:

    {                     \
        kCLOCK_OcramExsc  \
    }

Clock ip name array for OCRAM EXSC.

PDM_CLOCKS

#define PDM_CLOCKS

Value:

    {              \
        kCLOCK_Pdm \
    }

Clock ip name array for PDM.

PIT_CLOCKS [1/2]

#define PIT_CLOCKS

Value:

    {              \
        kCLOCK_Pit \
    }

Clock ip name array for PIT.

PIT_CLOCKS [2/2]

#define PIT_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \
    }

Clock ip name array for PIT.

PUF_CLOCKS

#define PUF_CLOCKS

Value:

    {              \
        kCLOCK_Puf \
    }

Clock ip name array for PUF.

PWM_CLOCKS [1/2]

#define PWM_CLOCKS

Value:

    {                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }

Clock ip name array for PWM.

PWM_CLOCKS [2/2]

#define PWM_CLOCKS

Value:

    {                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }

Clock ip name array for PWM.

PXP_CLOCKS [1/2]

#define PXP_CLOCKS

Value:

    {              \
        kCLOCK_Pxp \
    }

Clock ip name array for PXP.

PXP_CLOCKS [2/2]

#define PXP_CLOCKS

Value:

    {              \
        kCLOCK_Pxp \
    }

Clock ip name array for PXP.

RDC_CLOCKS

#define RDC_CLOCKS

Value:

    {                                              \
        kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \
    }

Clock gate name array for RDC.

RTWDOG_CLOCKS

#define RTWDOG_CLOCKS

Value:

    {                 \
        kCLOCK_Wdog3  \
    }

Clock ip name array for RTWDOG.

SAI_CLOCKS [1/2]

#define SAI_CLOCKS

Value:

    {                                                           \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
    }

Clock ip name array for SAI.

SAI_CLOCKS [2/2]

#define SAI_CLOCKS

Value:

    {                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
    }

Clock ip name array for SAI.

SEMA_CLOCKS

#define SEMA_CLOCKS

Value:

    {               \
        kCLOCK_Sema \
    }

Clock gate name array for Sema.

SEMC_CLOCKS [1/2]

#define SEMC_CLOCKS

Value:

    {               \
        kCLOCK_Semc \
    }

Clock ip name array for SEMC.

SEMC_CLOCKS [2/2]

#define SEMC_CLOCKS

Value:

    {               \
        kCLOCK_Semc \
    }

Clock ip name array for SEMC.

SEMC_EXSC_CLOCKS

#define SEMC_EXSC_CLOCKS

Value:

    {                    \
        kCLOCK_SemcExsc  \
    }

Clock ip name array for SEMC EXSC.

SPDIF_CLOCKS [1/2]

#define SPDIF_CLOCKS

Value:

    {                \
        kCLOCK_Spdif \
    }

Clock ip name array for SPDIF.

SPDIF_CLOCKS [2/2]

#define SPDIF_CLOCKS

Value:

    {                \
        kCLOCK_Spdif \
    }

Clock ip name array for SPDIF.

SRC_CLOCKS

#define SRC_CLOCKS

Value:

    {              \
        kCLOCK_Src \
    }

Clock gate name array for SRC.

SSARC_CLOCKS

#define SSARC_CLOCKS

Value:

    {                \
        kCLOCK_Ssarc \
    }

Clock gate name array for SSARC.

TMR_CLOCKS [1/2]

#define TMR_CLOCKS

Value:

    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
    }

Clock ip name array for QTIMER.

TMR_CLOCKS [2/2]

#define TMR_CLOCKS

Value:

    {                                                                                    \
        kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \
    }

Clock ip name array for QTIMER.

TRNG_CLOCKS

#define TRNG_CLOCKS

Value:

    {               \
        kCLOCK_Trng \
    }

Clock ip name array for TRNG.

TSC_CLOCKS

#define TSC_CLOCKS

Value:

    {              \
        kCLOCK_Tsc \
    }

Clock ip name array for TSC.

USB_CLOCKS

#define USB_CLOCKS

Value:

    {              \
        kCLOCK_Usb \
    }

Clock ip name array for USB.

USDHC_CLOCKS [1/2]

#define USDHC_CLOCKS

Value:

    {                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }

Clock ip name array for USDHC.

USDHC_CLOCKS [2/2]

#define USDHC_CLOCKS

Value:

    {                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }

Clock ip name array for USDHC.

WDOG_CLOCKS [1/2]

#define WDOG_CLOCKS

Value:

    {                                                \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
    }

Clock ip name array for WDOG.

WDOG_CLOCKS [2/2]

#define WDOG_CLOCKS

Value:

    {                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \
    }

Clock gate name array for WDOG.

XBAR_CLOCKS

#define XBAR_CLOCKS

Value:

    {                                                              \
        kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

Clock ip name array for XBAR.

XBARA_CLOCKS [1/2]

#define XBARA_CLOCKS

Value:

    {                                  \
        kCLOCK_IpInvalid, kCLOCK_Xbar1 \
    }

Clock ip name array for XBARA.

XBARA_CLOCKS [2/2]

#define XBARA_CLOCKS

Value:

    {                                  \
        kCLOCK_IpInvalid, kCLOCK_Xbar1 \
    }

Clock ip name array for XBARA.

XBARB_CLOCKS [1/2]

#define XBARB_CLOCKS

Value:

    {                                                                  \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

Clock ip name array for XBARB.

XBARB_CLOCKS [2/2]

#define XBARB_CLOCKS

Value:

    {                                                                  \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

Clock ip name array for XBARB.

XECC_CLOCKS

#define XECC_CLOCKS

Value:

    {               \
        kCLOCK_Xecc \
    }

Clock ip name array for XECC.

Typedef Documentation

clock_arm_pll_config_t

typedef struct _clock_arm_pll_config clock_arm_pll_config_t

PLL configuration for ARM.

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

clock_control_mode_t

typedef enum _clock_control_mode clock_control_mode_t

The enumeration of control mode.

clock_div_t

typedef enum _clock_div clock_div_t

DIV control names for clock div setting.

These constants define div control names for clock div setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

clock_mux_t

typedef enum _clock_mux clock_mux_t

MUX control names for clock mux setting.

These constants define the mux control names for clock mux setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

clock_output2_selection_t

typedef enum _clock_output2_selection clock_output2_selection_t

The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.

clock_root_t

typedef enum _clock_root clock_root_t

Root clock index.

Enumeration Type Documentation

_clock_16MOsc_source

enum _clock_16MOsc_source

The enumeration of 16MHz RC oscillator clock source.

Enumerator
kCLOCK_16MOscSourceFrom16MOsc	Source from 16MHz RC oscialltor.
kCLOCK_16MOscSourceFrom24MOsc	Source from 24MHz crystal oscillator.

_clock_1MHzOut_behavior

enum _clock_1MHzOut_behavior

The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.

Enumerator
kCLOCK_1MHzOutDisable	Disable 1MHz output clock.
kCLOCK_1MHzOutEnableLocked1Mhz	Enable 1MHz output clock, and select locked 1MHz to output.
kCLOCK_1MHzOutEnableFreeRunning1Mhz	Enable 1MHZ output clock, and select free-running 1MHz to output.

_clock_24MOsc_mode

enum _clock_24MOsc_mode

The enumeration of 24MHz crystal oscillator mode.

Enumerator
kCLOCK_24MOscHighGainMode	24MHz crystal oscillator work as high gain mode.
kCLOCK_24MOscBypassMode	24MHz crystal oscillator work as bypass mode.
kCLOCK_24MOscLowPowerMode	24MHz crystal oscillator work as low power mode.

_clock_control_mode

enum _clock_control_mode

The enumeration of control mode.

Enumerator
kCLOCK_SoftwareMode	Software control mode.
kCLOCK_GpcMode	GPC control mode.

_clock_div

enum _clock_div

DIV control names for clock div setting.

These constants define div control names for clock div setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

Enumerator
kCLOCK_ArmDiv	core div name
kCLOCK_PeriphClk2Div	periph clock2 div name
kCLOCK_SemcDiv	semc div name
kCLOCK_AhbDiv	ahb div name
kCLOCK_IpgDiv	ipg div name
kCLOCK_LpspiDiv	lpspi div name
kCLOCK_LcdifDiv	lcdif div name
kCLOCK_FlexspiDiv	flexspi div name
kCLOCK_PerclkDiv	perclk div name
kCLOCK_CanDiv	can div name
kCLOCK_TraceDiv	trace div name
kCLOCK_Usdhc2Div	usdhc2 div name
kCLOCK_Usdhc1Div	usdhc1 div name
kCLOCK_UartDiv	uart div name
kCLOCK_Flexio2Div	flexio2 pre div name
kCLOCK_Sai3PreDiv	sai3 pre div name
kCLOCK_Sai3Div	sai3 div name
kCLOCK_Flexio2PreDiv	sai3 pre div name
kCLOCK_Sai1PreDiv	sai1 pre div name
kCLOCK_Sai1Div	sai1 div name
kCLOCK_Sai2PreDiv	sai2 pre div name
kCLOCK_Sai2Div	sai2 div name
kCLOCK_Spdif0PreDiv	spdif pre div name
kCLOCK_Spdif0Div	spdif div name
kCLOCK_Flexio1PreDiv	flexio1 pre div name
kCLOCK_Flexio1Div	flexio1 div name
kCLOCK_Lpi2cDiv	lpi2c div name
kCLOCK_LcdifPreDiv	lcdif pre div name
kCLOCK_CsiDiv	csi div name
kCLOCK_NonePreDiv	None Pre div.

_clock_div_value

enum _clock_div_value

Clock divider value.

Enumerator
kCLOCK_ArmDivBy1	ARM clock divider set to divided by 1.
kCLOCK_ArmDivBy2	ARM clock divider set to divided by 2.
kCLOCK_ArmDivBy3	ARM clock divider set to divided by 3.
kCLOCK_ArmDivBy4	ARM clock divider set to divided by 4.
kCLOCK_ArmDivBy5	ARM clock divider set to divided by 5.
kCLOCK_ArmDivBy6	ARM clock divider set to divided by 6.
kCLOCK_ArmDivBy7	ARM clock divider set to divided by 7.
kCLOCK_ArmDivBy8	ARM clock divider set to divided by 8.
kCLOCK_PeriphClk2DivBy1	PeriphClk2 divider set to divided by 1.
kCLOCK_PeriphClk2DivBy2	PeriphClk2 divider set to divided by 2.
kCLOCK_PeriphClk2DivBy3	PeriphClk2 divider set to divided by 3.
kCLOCK_PeriphClk2DivBy4	PeriphClk2 divider set to divided by 4.
kCLOCK_PeriphClk2DivBy5	PeriphClk2 divider set to divided by 5.
kCLOCK_PeriphClk2DivBy6	PeriphClk2 divider set to divided by 6.
kCLOCK_PeriphClk2DivBy7	PeriphClk2 divider set to divided by 7.
kCLOCK_PeriphClk2DivBy8	PeriphClk2 divider set to divided by 8.
kCLOCK_SemcDivBy1	SEMC divider set to divided by 1.
kCLOCK_SemcDivBy2	SEMC divider set to divided by 2.
kCLOCK_SemcDivBy3	SEMC divider set to divided by 3.
kCLOCK_SemcDivBy4	SEMC divider set to divided by 4.
kCLOCK_SemcDivBy5	SEMC divider set to divided by 5.
kCLOCK_SemcDivBy6	SEMC divider set to divided by 6.
kCLOCK_SemcDivBy7	SEMC divider set to divided by 7.
kCLOCK_SemcDivBy8	SEMC divider set to divided by 8.
kCLOCK_AhbDivBy1	AHB divider set to divided by 1.
kCLOCK_AhbDivBy2	AHB divider set to divided by 2.
kCLOCK_AhbDivBy3	AHB divider set to divided by 3.
kCLOCK_AhbDivBy4	AHB divider set to divided by 4.
kCLOCK_AhbDivBy5	AHB divider set to divided by 5.
kCLOCK_AhbDivBy6	AHB divider set to divided by 6.
kCLOCK_AhbDivBy7	AHB divider set to divided by 7.
kCLOCK_AhbDivBy8	AHB divider set to divided by 8.
kCLOCK_IpgDivBy1	Ipg divider set to divided by 1.
kCLOCK_IpgDivBy2	Ipg divider set to divided by 2.
kCLOCK_IpgDivBy3	Ipg divider set to divided by 3.
kCLOCK_IpgDivBy4	Ipg divider set to divided by 4.
kCLOCK_LpspiDivBy1	LPSPI divider set to divided by 1.
kCLOCK_LpspiDivBy2	LPSPI divider set to divided by 2.
kCLOCK_LpspiDivBy3	LPSPI divider set to divided by 3.
kCLOCK_LpspiDivBy4	LPSPI divider set to divided by 4.
kCLOCK_LpspiDivBy5	LPSPI divider set to divided by 5.
kCLOCK_LpspiDivBy6	LPSPI divider set to divided by 6.
kCLOCK_LpspiDivBy7	LPSPI divider set to divided by 7.
kCLOCK_LpspiDivBy8	LPSPI divider set to divided by 8.
kCLOCK_LcdifDivBy1	LPDIF divider set to divided by 1.
kCLOCK_LcdifDivBy2	LPDIF divider set to divided by 2.
kCLOCK_LcdifDivBy3	LPDIF divider set to divided by 3.
kCLOCK_LcdifDivBy4	LPDIF divider set to divided by 4.
kCLOCK_LcdifDivBy5	LPDIF divider set to divided by 5.
kCLOCK_LcdifDivBy6	LPDIF divider set to divided by 6.
kCLOCK_LcdifDivBy7	LPDIF divider set to divided by 7.
kCLOCK_LcdifDivBy8	LPDIF divider set to divided by 8.
kCLOCK_FlexspiDivBy1	FLEXSPI divider set to divided by 1.
kCLOCK_FlexspiDivBy2	FLEXSPI divider set to divided by 2.
kCLOCK_FlexspiDivBy3	FLEXSPI divider set to divided by 3.
kCLOCK_FlexspiDivBy4	FLEXSPI divider set to divided by 4.
kCLOCK_FlexspiDivBy5	FLEXSPI divider set to divided by 5.
kCLOCK_FlexspiDivBy6	FLEXSPI divider set to divided by 6.
kCLOCK_FlexspiDivBy7	FLEXSPI divider set to divided by 7.
kCLOCK_FlexspiDivBy8	FLEXSPI divider set to divided by 8.
kCLOCK_TraceDivBy1	TRACE divider set to divided by 1.
kCLOCK_TraceDivBy2	TRACE divider set to divided by 2.
kCLOCK_TraceDivBy3	TRACE divider set to divided by 3.
kCLOCK_TraceDivBy4	TRACE divider set to divided by 4.
kCLOCK_Usdhc2DivBy1	USDHC2 divider set to divided by 1.
kCLOCK_Usdhc2DivBy2	USDHC2 divider set to divided by 2.
kCLOCK_Usdhc2DivBy3	USDHC2 divider set to divided by 3.
kCLOCK_Usdhc2DivBy4	USDHC2 divider set to divided by 4.
kCLOCK_Usdhc2DivBy5	USDHC2 divider set to divided by 5.
kCLOCK_Usdhc2DivBy6	USDHC2 divider set to divided by 6.
kCLOCK_Usdhc2DivBy7	USDHC2 divider set to divided by 7.
kCLOCK_Usdhc2DivBy8	USDHC2 divider set to divided by 8.
kCLOCK_Usdhc1DivBy1	USDHC1 divider set to divided by 1.
kCLOCK_Usdhc1DivBy2	USDHC1 divider set to divided by 2.
kCLOCK_Usdhc1DivBy3	USDHC1 divider set to divided by 3.
kCLOCK_Usdhc1DivBy4	USDHC1 divider set to divided by 4.
kCLOCK_Usdhc1DivBy5	USDHC1 divider set to divided by 5.
kCLOCK_Usdhc1DivBy6	USDHC1 divider set to divided by 6.
kCLOCK_Usdhc1DivBy7	USDHC1 divider set to divided by 7.
kCLOCK_Usdhc1DivBy8	USDHC1 divider set to divided by 8.
kCLOCK_Flexio2DivBy1	Flexio2 divider set to divided by 1.
kCLOCK_Flexio2DivBy2	Flexio2 divider set to divided by 2.
kCLOCK_Flexio2DivBy3	Flexio2 divider set to divided by 3.
kCLOCK_Flexio2DivBy4	Flexio2 divider set to divided by 4.
kCLOCK_Flexio2DivBy5	Flexio2 divider set to divided by 5.
kCLOCK_Flexio2DivBy6	Flexio2 divider set to divided by 6.
kCLOCK_Flexio2DivBy7	Flexio2 divider set to divided by 7.
kCLOCK_Flexio2DivBy8	Flexio2 divider set to divided by 8.
kCLOCK_Sai3PreDivBy1	SAI3ClkPred divider set to divided by 1.
kCLOCK_Sai3PreDivBy2	SAI3ClkPred divider set to divided by 2.
kCLOCK_Sai3PreDivBy3	SAI3ClkPred divider set to divided by 3.
kCLOCK_Sai3PreDivBy4	SAI3ClkPred divider set to divided by 4.
kCLOCK_Sai3PreDivBy5	SAI3ClkPred divider set to divided by 5.
kCLOCK_Sai3PreDivBy6	SAI3ClkPred divider set to divided by 6.
kCLOCK_Sai3PreDivBy7	SAI3ClkPred divider set to divided by 7.
kCLOCK_Sai3PreDivBy8	SAI3ClkPred divider set to divided by 8.
kCLOCK_Flexio2PreDivBy1	Flexio2 pre divider set to divided by 1.
kCLOCK_Flexio2PreDivBy2	Flexio2 pre divider set to divided by 2.
kCLOCK_Flexio2PreDivBy3	Flexio2 pre divider set to divided by 3.
kCLOCK_Flexio2PreDivBy4	Flexio2 pre divider set to divided by 4.
kCLOCK_Flexio2PreDivBy5	Flexio2 pre divider set to divided by 5.
kCLOCK_Flexio2PreDivBy6	Flexio2 pre divider set to divided by 6.
kCLOCK_Flexio2PreDivBy7	Flexio2 pre divider set to divided by 7.
kCLOCK_Flexio2PreDivBy8	Flexio2 pre divider set to divided by 8.
kCLOCK_Sai1PreDivBy1	SAI1 pred divider set to divided by 1.
kCLOCK_Sai1PreDivBy2	SAI1 pred divider set to divided by 2.
kCLOCK_Sai1PreDivBy3	SAI1 pred divider set to divided by 3.
kCLOCK_Sai1PreDivBy4	SAI1 pred divider set to divided by 4.
kCLOCK_Sai1PreDivBy5	SAI1 pred divider set to divided by 5.
kCLOCK_Sai1PreDivBy6	SAI1 pred divider set to divided by 6.
kCLOCK_Sai1PreDivBy7	SAI1 pred divider set to divided by 7.
kCLOCK_Sai1PreDivBy8	SAI1 pred divider set to divided by 8.
kCLOCK_Sai2PreDivBy1	SAI2ClkPred divider set to divided by 1.
kCLOCK_Sai2PreDivBy2	SAI2ClkPred divider set to divided by 2.
kCLOCK_Sai2PreDivBy3	SAI2ClkPred divider set to divided by 3.
kCLOCK_Sai2PreDivBy4	SAI2ClkPred divider set to divided by 4.
kCLOCK_Sai2PreDivBy5	SAI2ClkPred divider set to divided by 5.
kCLOCK_Sai2PreDivBy6	SAI2ClkPred divider set to divided by 6.
kCLOCK_Sai2PreDivBy7	SAI2ClkPred divider set to divided by 7.
kCLOCK_Sai2PreDivBy8	SAI2ClkPred divider set to divided by 8.
kCLOCK_Spdif0PreDivBy1	SPDIF0 pred divider set to divided by 1.
kCLOCK_Spdif0PreDivBy2	SPDIF0 pred divider set to divided by 2.
kCLOCK_Spdif0PreDivBy3	SPDIF0 pred divider set to divided by 3.
kCLOCK_Spdif0PreDivBy4	SPDIF0 pred divider set to divided by 4.
kCLOCK_Spdif0PreDivBy5	SPDIF0 pred divider set to divided by 5.
kCLOCK_Spdif0PreDivBy6	SPDIF0 pred divider set to divided by 6.
kCLOCK_Spdif0PreDivBy7	SPDIF0 pred divider set to divided by 7.
kCLOCK_Spdif0PreDivBy8	SPDIF0 pred divider set to divided by 8.
kCLOCK_Spdif0DivBy1	SPDIF divider set to divided by 1.
kCLOCK_Spdif0DivBy2	SPDIF divider set to divided by 2.
kCLOCK_Spdif0DivBy3	SPDIF divider set to divided by 3.
kCLOCK_Spdif0DivBy4	SPDIF divider set to divided by 4.
kCLOCK_Spdif0DivBy5	SPDIF divider set to divided by 5.
kCLOCK_Spdif0DivBy6	SPDIF divider set to divided by 6.
kCLOCK_Spdif0DivBy7	SPDIF divider set to divided by 7.
kCLOCK_Spdif0DivBy8	SPDIF divider set to divided by 8.
kCLOCK_Flexio1PreDivBy1	Flexio1 pre divider set to divided by 1.
kCLOCK_Flexio1PreDivBy2	Flexio1 pre divider set to divided by 2.
kCLOCK_Flexio1PreDivBy3	Flexio1 pre divider set to divided by 3.
kCLOCK_Flexio1PreDivBy4	Flexio1 pre divider set to divided by 4.
kCLOCK_Flexio1PreDivBy5	Flexio1 pre divider set to divided by 5.
kCLOCK_Flexio1PreDivBy6	Flexio1 pre divider set to divided by 6.
kCLOCK_Flexio1PreDivBy7	Flexio1 pre divider set to divided by 7.
kCLOCK_Flexio1PreDivBy8	Flexio1 pre divider set to divided by 8.
kCLOCK_Flexio1DivBy1	Flexio1 divider set to divided by 1.
kCLOCK_Flexio1DivBy2	Flexio1 divider set to divided by 2.
kCLOCK_Flexio1DivBy3	Flexio1 divider set to divided by 3.
kCLOCK_Flexio1DivBy4	Flexio1 divider set to divided by 4.
kCLOCK_Flexio1DivBy5	Flexio1 divider set to divided by 5.
kCLOCK_Flexio1DivBy6	Flexio1 divider set to divided by 6.
kCLOCK_Flexio1DivBy7	Flexio1 divider set to divided by 7.
kCLOCK_Flexio1DivBy8	Flexio1 divider set to divided by 8.
kCLOCK_LcdifPreDivBy1	Lcdif pre divider set to divided by 1.
kCLOCK_LcdifPreDivBy2	Lcdif pre divider set to divided by 2.
kCLOCK_LcdifPreDivBy3	Lcdif pre divider set to divided by 3.
kCLOCK_LcdifPreDivBy4	Lcdif pre divider set to divided by 4.
kCLOCK_LcdifPreDivBy5	Lcdif pre divider set to divided by 5.
kCLOCK_LcdifPreDivBy6	Lcdif pre divider set to divided by 6.
kCLOCK_LcdifPreDivBy7	Lcdif pre divider set to divided by 7.
kCLOCK_LcdifPreDivBy8	Lcdif pre divider set to divided by 8.
kCLOCK_CsiDivBy1	Csi pre divider set to divided by 1.
kCLOCK_CsiDivBy2	Csi pre divider set to divided by 2.
kCLOCK_CsiDivBy3	Csi pre divider set to divided by 3.
kCLOCK_CsiDivBy4	Csi pre divider set to divided by 4.
kCLOCK_CsiDivBy5	Csi pre divider set to divided by 5.
kCLOCK_CsiDivBy6	Csi pre divider set to divided by 6.
kCLOCK_CsiDivBy7	Csi pre divider set to divided by 7.
kCLOCK_CsiDivBy8	Csi pre divider set to divided by 8.
kCLOCK_MiscDivBy1	Misc divider like LPI2C set to divided by1.
kCLOCK_MiscDivBy2	Misc divider like LPI2C set to divided by2.
kCLOCK_MiscDivBy3	Misc divider like LPI2C set to divided by3.
kCLOCK_MiscDivBy4	Misc divider like LPI2C set to divided by4.
kCLOCK_MiscDivBy5	Misc divider like LPI2C set to divided by5.
kCLOCK_MiscDivBy6	Misc divider like LPI2C set to divided by6.
kCLOCK_MiscDivBy7	Misc divider like LPI2C set to divided by7.
kCLOCK_MiscDivBy8	Misc divider like LPI2C set to divided by8.
kCLOCK_MiscDivBy9	Misc divider like LPI2C set to divided by9.
kCLOCK_MiscDivBy10	Misc divider like LPI2C set to divided by10.
kCLOCK_MiscDivBy11	Misc divider like LPI2C set to divided by11.
kCLOCK_MiscDivBy12	Misc divider like LPI2C set to divided by12.
kCLOCK_MiscDivBy13	Misc divider like LPI2C set to divided by13.
kCLOCK_MiscDivBy14	Misc divider like LPI2C set to divided by14.
kCLOCK_MiscDivBy15	Misc divider like LPI2C set to divided by15.
kCLOCK_MiscDivBy16	Misc divider like LPI2C set to divided by16.
kCLOCK_MiscDivBy17	Misc divider like LPI2C set to divided by17.
kCLOCK_MiscDivBy18	Misc divider like LPI2C set to divided by18.
kCLOCK_MiscDivBy19	Misc divider like LPI2C set to divided by19.
kCLOCK_MiscDivBy20	Misc divider like LPI2C set to divided by20.
kCLOCK_MiscDivBy21	Misc divider like LPI2C set to divided by21.
kCLOCK_MiscDivBy22	Misc divider like LPI2C set to divided by22.
kCLOCK_MiscDivBy23	Misc divider like LPI2C set to divided by23.
kCLOCK_MiscDivBy24	Misc divider like LPI2C set to divided by24.
kCLOCK_MiscDivBy25	Misc divider like LPI2C set to divided by25.
kCLOCK_MiscDivBy26	Misc divider like LPI2C set to divided by26.
kCLOCK_MiscDivBy27	Misc divider like LPI2C set to divided by27.
kCLOCK_MiscDivBy28	Misc divider like LPI2C set to divided by28.
kCLOCK_MiscDivBy29	Misc divider like LPI2C set to divided by29.
kCLOCK_MiscDivBy30	Misc divider like LPI2C set to divided by30.
kCLOCK_MiscDivBy31	Misc divider like LPI2C set to divided by31.
kCLOCK_MiscDivBy32	Misc divider like LPI2C set to divided by32.
kCLOCK_MiscDivBy33	Misc divider like LPI2C set to divided by33.
kCLOCK_MiscDivBy34	Misc divider like LPI2C set to divided by34.
kCLOCK_MiscDivBy35	Misc divider like LPI2C set to divided by35.
kCLOCK_MiscDivBy36	Misc divider like LPI2C set to divided by36.
kCLOCK_MiscDivBy37	Misc divider like LPI2C set to divided by37.
kCLOCK_MiscDivBy38	Misc divider like LPI2C set to divided by38.
kCLOCK_MiscDivBy39	Misc divider like LPI2C set to divided by39.
kCLOCK_MiscDivBy40	Misc divider like LPI2C set to divided by40.
kCLOCK_MiscDivBy41	Misc divider like LPI2C set to divided by41.
kCLOCK_MiscDivBy42	Misc divider like LPI2C set to divided by42.
kCLOCK_MiscDivBy43	Misc divider like LPI2C set to divided by43.
kCLOCK_MiscDivBy44	Misc divider like LPI2C set to divided by44.
kCLOCK_MiscDivBy45	Misc divider like LPI2C set to divided by45.
kCLOCK_MiscDivBy46	Misc divider like LPI2C set to divided by46.
kCLOCK_MiscDivBy47	Misc divider like LPI2C set to divided by47.
kCLOCK_MiscDivBy48	Misc divider like LPI2C set to divided by48.
kCLOCK_MiscDivBy49	Misc divider like LPI2C set to divided by49.
kCLOCK_MiscDivBy50	Misc divider like LPI2C set to divided by50.
kCLOCK_MiscDivBy51	Misc divider like LPI2C set to divided by51.
kCLOCK_MiscDivBy52	Misc divider like LPI2C set to divided by52.
kCLOCK_MiscDivBy53	Misc divider like LPI2C set to divided by53.
kCLOCK_MiscDivBy54	Misc divider like LPI2C set to divided by54.
kCLOCK_MiscDivBy55	Misc divider like LPI2C set to divided by55.
kCLOCK_MiscDivBy56	Misc divider like LPI2C set to divided by56.
kCLOCK_MiscDivBy57	Misc divider like LPI2C set to divided by57.
kCLOCK_MiscDivBy58	Misc divider like LPI2C set to divided by58.
kCLOCK_MiscDivBy59	Misc divider like LPI2C set to divided by59.
kCLOCK_MiscDivBy60	Misc divider like LPI2C set to divided by60.
kCLOCK_MiscDivBy61	Misc divider like LPI2C set to divided by61.
kCLOCK_MiscDivBy62	Misc divider like LPI2C set to divided by62.
kCLOCK_MiscDivBy63	Misc divider like LPI2C set to divided by63.
kCLOCK_MiscDivBy64	Misc divider like LPI2C set to divided by64.

_clock_gate_value [1/2]

enum _clock_gate_value

Clock gate value.

Enumerator
kCLOCK_ClockNotNeeded	Clock is off during all modes.
kCLOCK_ClockNeededRun	Clock is on in run mode, but off in WAIT and STOP modes
kCLOCK_ClockNeededRunWait	Clock is on during all modes, except STOP mode
kCLOCK_Off	Clock is off.
kCLOCK_On	Clock is on

_clock_gate_value [2/2]

enum _clock_gate_value

Clock gate value.

Enumerator
kCLOCK_ClockNotNeeded	Clock is off during all modes.
kCLOCK_ClockNeededRun	Clock is on in run mode, but off in WAIT and STOP modes
kCLOCK_ClockNeededRunWait	Clock is on during all modes, except STOP mode
kCLOCK_Off	Clock is off.
kCLOCK_On	Clock is on

_clock_group

enum _clock_group

Clock group enumeration.

Enumerator
kCLOCK_Group_FlexRAM	FlexRAM clock group.
kCLOCK_Group_MipiDsi	Mipi Dsi clock group.
kCLOCK_Group_Last	Last clock group.

_clock_ip_name

enum _clock_ip_name

CCM CCGR gate control for each module independently.

Enumerator
kCLOCK_Aips_tz1	CCGR0, CG0
kCLOCK_Aips_tz2	CCGR0, CG1
kCLOCK_Mqs	CCGR0, CG2
kCLOCK_FlexSpiExsc	CCGR0, CG3
kCLOCK_Sim_M_Main	CCGR0, CG4
kCLOCK_Dcp	CCGR0, CG5
kCLOCK_Lpuart3	CCGR0, CG6
kCLOCK_Can1	CCGR0, CG7
kCLOCK_Can1S	CCGR0, CG8
kCLOCK_Can2	CCGR0, CG9
kCLOCK_Can2S	CCGR0, CG10
kCLOCK_Trace	CCGR0, CG11
kCLOCK_Gpt2	CCGR0, CG12
kCLOCK_Gpt2S	CCGR0, CG13
kCLOCK_Lpuart2	CCGR0, CG14
kCLOCK_Gpio2	CCGR0, CG15
kCLOCK_Lpspi1	CCGR1, CG0
kCLOCK_Lpspi2	CCGR1, CG1
kCLOCK_Lpspi3	CCGR1, CG2
kCLOCK_Lpspi4	CCGR1, CG3
kCLOCK_Adc2	CCGR1, CG4
kCLOCK_Enet	CCGR1, CG5
kCLOCK_Pit	CCGR1, CG6
kCLOCK_Aoi2	CCGR1, CG7
kCLOCK_Adc1	CCGR1, CG8
kCLOCK_SemcExsc	CCGR1, CG9
kCLOCK_Gpt1	CCGR1, CG10
kCLOCK_Gpt1S	CCGR1, CG11
kCLOCK_Lpuart4	CCGR1, CG12
kCLOCK_Gpio1	CCGR1, CG13
kCLOCK_Csu	CCGR1, CG14
kCLOCK_Gpio5	CCGR1, CG15
kCLOCK_OcramExsc	CCGR2, CG0
kCLOCK_Csi	CCGR2, CG1
kCLOCK_IomuxcSnvs	CCGR2, CG2
kCLOCK_Lpi2c1	CCGR2, CG3
kCLOCK_Lpi2c2	CCGR2, CG4
kCLOCK_Lpi2c3	CCGR2, CG5
kCLOCK_Ocotp	CCGR2, CG6
kCLOCK_Xbar3	CCGR2, CG7
kCLOCK_Ipmux1	CCGR2, CG8
kCLOCK_Ipmux2	CCGR2, CG9
kCLOCK_Ipmux3	CCGR2, CG10
kCLOCK_Xbar1	CCGR2, CG11
kCLOCK_Xbar2	CCGR2, CG12
kCLOCK_Gpio3	CCGR2, CG13
kCLOCK_Lcd	CCGR2, CG14
kCLOCK_Pxp	CCGR2, CG15
kCLOCK_Flexio2	CCGR3, CG0
kCLOCK_Lpuart5	CCGR3, CG1
kCLOCK_Semc	CCGR3, CG2
kCLOCK_Lpuart6	CCGR3, CG3
kCLOCK_Aoi1	CCGR3, CG4
kCLOCK_LcdPixel	CCGR3, CG5
kCLOCK_Gpio4	CCGR3, CG6
kCLOCK_Ewm0	CCGR3, CG7
kCLOCK_Wdog1	CCGR3, CG8
kCLOCK_FlexRam	CCGR3, CG9
kCLOCK_Acmp1	CCGR3, CG10
kCLOCK_Acmp2	CCGR3, CG11
kCLOCK_Acmp3	CCGR3, CG12
kCLOCK_Acmp4	CCGR3, CG13
kCLOCK_Ocram	CCGR3, CG14
kCLOCK_IomuxcSnvsGpr	CCGR3, CG15
kCLOCK_Sim_m7_clk_r	CCGR4, CG0
kCLOCK_Iomuxc	CCGR4, CG1
kCLOCK_IomuxcGpr	CCGR4, CG2
kCLOCK_Bee	CCGR4, CG3
kCLOCK_SimM7	CCGR4, CG4
kCLOCK_Tsc	CCGR4, CG5
kCLOCK_SimM	CCGR4, CG6
kCLOCK_SimEms	CCGR4, CG7
kCLOCK_Pwm1	CCGR4, CG8
kCLOCK_Pwm2	CCGR4, CG9
kCLOCK_Pwm3	CCGR4, CG10
kCLOCK_Pwm4	CCGR4, CG11
kCLOCK_Enc1	CCGR4, CG12
kCLOCK_Enc2	CCGR4, CG13
kCLOCK_Enc3	CCGR4, CG14
kCLOCK_Enc4	CCGR4, CG15
kCLOCK_Rom	CCGR5, CG0
kCLOCK_Flexio1	CCGR5, CG1
kCLOCK_Wdog3	CCGR5, CG2
kCLOCK_Dma	CCGR5, CG3
kCLOCK_Kpp	CCGR5, CG4
kCLOCK_Wdog2	CCGR5, CG5
kCLOCK_Aips_tz4	CCGR5, CG6
kCLOCK_Spdif	CCGR5, CG7
kCLOCK_SimMain	CCGR5, CG8
kCLOCK_Sai1	CCGR5, CG9
kCLOCK_Sai2	CCGR5, CG10
kCLOCK_Sai3	CCGR5, CG11
kCLOCK_Lpuart1	CCGR5, CG12
kCLOCK_Lpuart7	CCGR5, CG13
kCLOCK_SnvsHp	CCGR5, CG14
kCLOCK_SnvsLp	CCGR5, CG15
kCLOCK_UsbOh3	CCGR6, CG0
kCLOCK_Usdhc1	CCGR6, CG1
kCLOCK_Usdhc2	CCGR6, CG2
kCLOCK_Dcdc	CCGR6, CG3
kCLOCK_Ipmux4	CCGR6, CG4
kCLOCK_FlexSpi	CCGR6, CG5
kCLOCK_Trng	CCGR6, CG6
kCLOCK_Lpuart8	CCGR6, CG7
kCLOCK_Timer4	CCGR6, CG8
kCLOCK_Aips_tz3	CCGR6, CG9
kCLOCK_SimPer	CCGR6, CG10
kCLOCK_Anadig	CCGR6, CG11
kCLOCK_Lpi2c4	CCGR6, CG12
kCLOCK_Timer1	CCGR6, CG13
kCLOCK_Timer2	CCGR6, CG14
kCLOCK_Timer3	CCGR6, CG15

_clock_level

enum _clock_level

The clock dependence level.

Enumerator
kCLOCK_Level0	Not needed in any mode.
kCLOCK_Level1	Needed in RUN mode.
kCLOCK_Level2	Needed in RUN and WAIT mode.
kCLOCK_Level3	Needed in RUN, WAIT and STOP mode.
kCLOCK_Level4	Always on in any mode.

_clock_lpcg

enum _clock_lpcg

Clock LPCG index.

Enumerator
kCLOCK_M7	Clock LPCG M7.
kCLOCK_M4	Clock LPCG M4.
kCLOCK_Sim_M7	Clock LPCG SIM M7.
kCLOCK_Sim_M	Clock LPCG SIM M4.
kCLOCK_Sim_Disp	Clock LPCG SIM DISP.
kCLOCK_Sim_Per	Clock LPCG SIM PER.
kCLOCK_Sim_Lpsr	Clock LPCG SIM LPSR.
kCLOCK_Anadig	Clock LPCG Anadig.
kCLOCK_Dcdc	Clock LPCG DCDC.
kCLOCK_Src	Clock LPCG SRC.
kCLOCK_Ccm	Clock LPCG CCM.
kCLOCK_Gpc	Clock LPCG GPC.
kCLOCK_Ssarc	Clock LPCG SSARC.
kCLOCK_Sim_R	Clock LPCG SIM_R.
kCLOCK_Wdog1	Clock LPCG WDOG1.
kCLOCK_Wdog2	Clock LPCG WDOG2.
kCLOCK_Wdog3	Clock LPCG WDOG3.
kCLOCK_Wdog4	Clock LPCG WDOG4.
kCLOCK_Ewm0	Clock LPCG EWM0.
kCLOCK_Sema	Clock LPCG SEMA.
kCLOCK_Mu_A	Clock LPCG MU_A.
kCLOCK_Mu_B	Clock LPCG MU_B.
kCLOCK_Edma	Clock LPCG EDMA.
kCLOCK_Edma_Lpsr	Clock LPCG EDMA_LPSR.
kCLOCK_Romcp	Clock LPCG ROMCP.
kCLOCK_Ocram	Clock LPCG OCRAM.
kCLOCK_Flexram	Clock LPCG FLEXRAM.
kCLOCK_Lmem	Clock LPCG Lmem.
kCLOCK_Flexspi1	Clock LPCG Flexspi1.
kCLOCK_Flexspi2	Clock LPCG Flexspi2.
kCLOCK_Rdc	Clock LPCG RDC.
kCLOCK_M7_Xrdc	Clock LPCG M7 XRDC.
kCLOCK_M4_Xrdc	Clock LPCG M4 XRDC.
kCLOCK_Semc	Clock LPCG SEMC.
kCLOCK_Xecc	Clock LPCG XECC.
kCLOCK_Iee	Clock LPCG IEE.
kCLOCK_Key_Manager	Clock LPCG KEY_MANAGER.
kCLOCK_Puf	Clock LPCG PUF.
kCLOCK_Ocotp	Clock LPCG OSOTP.
kCLOCK_Snvs_Hp	Clock LPCG SNVS_HP.
kCLOCK_Snvs	Clock LPCG SNVS.
kCLOCK_Caam	Clock LPCG Caam.
kCLOCK_Jtag_Mux	Clock LPCG JTAG_MUX.
kCLOCK_Cstrace	Clock LPCG CSTRACE.
kCLOCK_Xbar1	Clock LPCG XBAR1.
kCLOCK_Xbar2	Clock LPCG XBAR2.
kCLOCK_Xbar3	Clock LPCG XBAR3.
kCLOCK_Aoi1	Clock LPCG AOI1.
kCLOCK_Aoi2	Clock LPCG AOI2.
kCLOCK_Adc_Etc	Clock LPCG ADC_ETC.
kCLOCK_Iomuxc	Clock LPCG IOMUXC.
kCLOCK_Iomuxc_Lpsr	Clock LPCG IOMUXC_LPSR.
kCLOCK_Gpio	Clock LPCG GPIO.
kCLOCK_Kpp	Clock LPCG KPP.
kCLOCK_Flexio1	Clock LPCG FLEXIO1.
kCLOCK_Flexio2	Clock LPCG FLEXIO2.
kCLOCK_Lpadc1	Clock LPCG LPADC1.
kCLOCK_Lpadc2	Clock LPCG LPADC2.
kCLOCK_Dac	Clock LPCG DAC.
kCLOCK_Acmp1	Clock LPCG ACMP1.
kCLOCK_Acmp2	Clock LPCG ACMP2.
kCLOCK_Acmp3	Clock LPCG ACMP3.
kCLOCK_Acmp4	Clock LPCG ACMP4.
kCLOCK_Pit1	Clock LPCG PIT1.
kCLOCK_Pit2	Clock LPCG PIT2.
kCLOCK_Gpt1	Clock LPCG GPT1.
kCLOCK_Gpt2	Clock LPCG GPT2.
kCLOCK_Gpt3	Clock LPCG GPT3.
kCLOCK_Gpt4	Clock LPCG GPT4.
kCLOCK_Gpt5	Clock LPCG GPT5.
kCLOCK_Gpt6	Clock LPCG GPT6.
kCLOCK_Qtimer1	Clock LPCG QTIMER1.
kCLOCK_Qtimer2	Clock LPCG QTIMER2.
kCLOCK_Qtimer3	Clock LPCG QTIMER3.
kCLOCK_Qtimer4	Clock LPCG QTIMER4.
kCLOCK_Enc1	Clock LPCG Enc1.
kCLOCK_Enc2	Clock LPCG Enc2.
kCLOCK_Enc3	Clock LPCG Enc3.
kCLOCK_Enc4	Clock LPCG Enc4.
kCLOCK_Hrtimer	Clock LPCG Hrtimer.
kCLOCK_Pwm1	Clock LPCG PWM1.
kCLOCK_Pwm2	Clock LPCG PWM2.
kCLOCK_Pwm3	Clock LPCG PWM3.
kCLOCK_Pwm4	Clock LPCG PWM4.
kCLOCK_Can1	Clock LPCG CAN1.
kCLOCK_Can2	Clock LPCG CAN2.
kCLOCK_Can3	Clock LPCG CAN3.
kCLOCK_Lpuart1	Clock LPCG LPUART1.
kCLOCK_Lpuart2	Clock LPCG LPUART2.
kCLOCK_Lpuart3	Clock LPCG LPUART3.
kCLOCK_Lpuart4	Clock LPCG LPUART4.
kCLOCK_Lpuart5	Clock LPCG LPUART5.
kCLOCK_Lpuart6	Clock LPCG LPUART6.
kCLOCK_Lpuart7	Clock LPCG LPUART7.
kCLOCK_Lpuart8	Clock LPCG LPUART8.
kCLOCK_Lpuart9	Clock LPCG LPUART9.
kCLOCK_Lpuart10	Clock LPCG LPUART10.
kCLOCK_Lpuart11	Clock LPCG LPUART11.
kCLOCK_Lpuart12	Clock LPCG LPUART12.
kCLOCK_Lpi2c1	Clock LPCG LPI2C1.
kCLOCK_Lpi2c2	Clock LPCG LPI2C2.
kCLOCK_Lpi2c3	Clock LPCG LPI2C3.
kCLOCK_Lpi2c4	Clock LPCG LPI2C4.
kCLOCK_Lpi2c5	Clock LPCG LPI2C5.
kCLOCK_Lpi2c6	Clock LPCG LPI2C6.
kCLOCK_Lpspi1	Clock LPCG LPSPI1.
kCLOCK_Lpspi2	Clock LPCG LPSPI2.
kCLOCK_Lpspi3	Clock LPCG LPSPI3.
kCLOCK_Lpspi4	Clock LPCG LPSPI4.
kCLOCK_Lpspi5	Clock LPCG LPSPI5.
kCLOCK_Lpspi6	Clock LPCG LPSPI6.
kCLOCK_Sim1	Clock LPCG SIM1.
kCLOCK_Sim2	Clock LPCG SIM2.
kCLOCK_Enet	Clock LPCG ENET.
kCLOCK_Enet_1g	Clock LPCG ENET 1G.
kCLOCK_Usb	Clock LPCG USB.
kCLOCK_Cdog	Clock LPCG CDOG.
kCLOCK_Usdhc1	Clock LPCG USDHC1.
kCLOCK_Usdhc2	Clock LPCG USDHC2.
kCLOCK_Asrc	Clock LPCG ASRC.
kCLOCK_Mqs	Clock LPCG MQS.
kCLOCK_Pdm	Clock LPCG PDM.
kCLOCK_Spdif	Clock LPCG SPDIF.
kCLOCK_Sai1	Clock LPCG SAI1.
kCLOCK_Sai2	Clock LPCG SAI2.
kCLOCK_Sai3	Clock LPCG SAI3.
kCLOCK_Sai4	Clock LPCG SAI4.
kCLOCK_Pxp	Clock LPCG PXP.
kCLOCK_Gpu2d	Clock LPCG GPU2D.
kCLOCK_Lcdif	Clock LPCG LCDIF.
kCLOCK_Lcdifv2	Clock LPCG LCDIFV2.
kCLOCK_Mipi_Dsi	Clock LPCG MIPI DSI.
kCLOCK_Mipi_Csi	Clock LPCG MIPI CSI.
kCLOCK_Csi	Clock LPCG CSI.
kCLOCK_Dcic_Mipi	Clock LPCG DCIC MIPI.
kCLOCK_Dcic_Lcd	Clock LPCG DCIC LCD.
kCLOCK_Video_Mux	Clock LPCG VIDEO MUX.
kCLOCK_Uniq_Edt_I	Clock LPCG Uniq_Edt_I.
kCLOCK_IpInvalid	Invalid value.

_clock_mode_t [1/2]

enum _clock_mode_t

System clock mode.

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

_clock_mode_t [2/2]

enum _clock_mode_t

System clock mode.

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

_clock_mux

enum _clock_mux

MUX control names for clock mux setting.

These constants define the mux control names for clock mux setting.

• 0:7: REG offset to CCM_BASE in bytes.
• 8:15: Root clock setting bit field shift.
• 16:31: Root clock setting bit field width.

Enumerator
kCLOCK_Pll3SwMux	pll3_sw_clk mux name
kCLOCK_PeriphMux	periph mux name
kCLOCK_SemcAltMux	semc mux name
kCLOCK_SemcMux	semc mux name
kCLOCK_PrePeriphMux	pre-periph mux name
kCLOCK_TraceMux	trace mux name
kCLOCK_PeriphClk2Mux	periph clock2 mux name
kCLOCK_LpspiMux	lpspi mux name
kCLOCK_FlexspiMux	flexspi mux name
kCLOCK_Usdhc2Mux	usdhc2 mux name
kCLOCK_Usdhc1Mux	usdhc1 mux name
kCLOCK_Sai3Mux	sai3 mux name
kCLOCK_Sai2Mux	sai2 mux name
kCLOCK_Sai1Mux	sai1 mux name
kCLOCK_PerclkMux	perclk mux name
kCLOCK_Flexio2Mux	flexio2 mux name
kCLOCK_CanMux	can mux name
kCLOCK_UartMux	uart mux name
kCLOCK_SpdifMux	spdif mux name
kCLOCK_Flexio1Mux	flexio1 mux name
kCLOCK_Lpi2cMux	lpi2c mux name
kCLOCK_LcdifPreMux	lcdif pre mux name
kCLOCK_CsiMux	csi mux name

_clock_name [1/2]

enum _clock_name

Clock name used to get clock frequency.

Enumerator
kCLOCK_CpuClk	CPU clock
kCLOCK_AhbClk	AHB clock
kCLOCK_SemcClk	SEMC clock
kCLOCK_IpgClk	IPG clock
kCLOCK_PerClk	PER clock
kCLOCK_OscClk	OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL].
kCLOCK_RtcClk	RTC clock. (RTCCLK)
kCLOCK_ArmPllClk	ARMPLLCLK.
kCLOCK_Usb1PllClk	USB1PLLCLK.
kCLOCK_Usb1PllPfd0Clk	USB1PLLPDF0CLK.
kCLOCK_Usb1PllPfd1Clk	USB1PLLPFD1CLK.
kCLOCK_Usb1PllPfd2Clk	USB1PLLPFD2CLK.
kCLOCK_Usb1PllPfd3Clk	USB1PLLPFD3CLK.
kCLOCK_Usb1SwClk	USB1PLLSWCLK
kCLOCK_Usb1Sw120MClk	USB1PLLSw120MCLK
kCLOCK_Usb1Sw60MClk	USB1PLLSw60MCLK
kCLOCK_Usb1Sw80MClk	USB1PLLSw80MCLK
kCLOCK_Usb2PllClk	USB2PLLCLK.
kCLOCK_SysPllClk	SYSPLLCLK.
kCLOCK_SysPllPfd0Clk	SYSPLLPDF0CLK.
kCLOCK_SysPllPfd1Clk	SYSPLLPFD1CLK.
kCLOCK_SysPllPfd2Clk	SYSPLLPFD2CLK.
kCLOCK_SysPllPfd3Clk	SYSPLLPFD3CLK.
kCLOCK_EnetPll0Clk	Enet PLLCLK ref_enetpll0.
kCLOCK_EnetPll1Clk	Enet PLLCLK ref_enetpll1.
kCLOCK_AudioPllClk	Audio PLLCLK.
kCLOCK_VideoPllClk	Video PLLCLK.
kCLOCK_NoneName	None Clock Name.
kCLOCK_OscRc16M	16MHz RC Oscillator.
kCLOCK_OscRc48M	48MHz RC Oscillator.
kCLOCK_OscRc48MDiv2	48MHz RC Oscillator Div2.
kCLOCK_OscRc400M	400MHz RC Oscillator.
kCLOCK_Osc24M	24MHz Oscillator.
kCLOCK_Osc24MOut	48MHz Oscillator Out.
kCLOCK_ArmPll	ARM PLL.
kCLOCK_ArmPllOut	ARM PLL Out.
kCLOCK_SysPll2	SYS PLL2.
kCLOCK_SysPll2Out	SYS PLL2 OUT.
kCLOCK_SysPll2Pfd0	SYS PLL2 PFD0.
kCLOCK_SysPll2Pfd1	SYS PLL2 PFD1.
kCLOCK_SysPll2Pfd2	SYS PLL2 PFD2.
kCLOCK_SysPll2Pfd3	SYS PLL2 PFD3.
kCLOCK_SysPll3	SYS PLL3.
kCLOCK_SysPll3Out	SYS PLL3 OUT.
kCLOCK_SysPll3Div2	SYS PLL3 DIV2
kCLOCK_SysPll3Pfd0	SYS PLL3 PFD0.
kCLOCK_SysPll3Pfd1	SYS PLL3 PFD1
kCLOCK_SysPll3Pfd2	SYS PLL3 PFD2
kCLOCK_SysPll3Pfd3	SYS PLL3 PFD3
kCLOCK_SysPll1	SYS PLL1.
kCLOCK_SysPll1Out	SYS PLL1 OUT.
kCLOCK_SysPll1Div2	SYS PLL1 DIV2.
kCLOCK_SysPll1Div5	SYS PLL1 DIV5.
kCLOCK_AudioPll	SYS AUDIO PLL.
kCLOCK_AudioPllOut	SYS AUDIO PLL OUT.
kCLOCK_VideoPll	SYS VIDEO PLL.
kCLOCK_VideoPllOut	SYS VIDEO PLL OUT.
kCLOCK_CpuClk	SYS CPU CLK.
kCLOCK_CoreSysClk	SYS CORE SYS CLK.
kCLOCK_Reserved	Reserved.

_clock_name [2/2]

enum _clock_name

Clock name.

Enumerator
kCLOCK_CpuClk	CPU clock
kCLOCK_AhbClk	AHB clock
kCLOCK_SemcClk	SEMC clock
kCLOCK_IpgClk	IPG clock
kCLOCK_PerClk	PER clock
kCLOCK_OscClk	OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL].
kCLOCK_RtcClk	RTC clock. (RTCCLK)
kCLOCK_ArmPllClk	ARMPLLCLK.
kCLOCK_Usb1PllClk	USB1PLLCLK.
kCLOCK_Usb1PllPfd0Clk	USB1PLLPDF0CLK.
kCLOCK_Usb1PllPfd1Clk	USB1PLLPFD1CLK.
kCLOCK_Usb1PllPfd2Clk	USB1PLLPFD2CLK.
kCLOCK_Usb1PllPfd3Clk	USB1PLLPFD3CLK.
kCLOCK_Usb1SwClk	USB1PLLSWCLK
kCLOCK_Usb1Sw120MClk	USB1PLLSw120MCLK
kCLOCK_Usb1Sw60MClk	USB1PLLSw60MCLK
kCLOCK_Usb1Sw80MClk	USB1PLLSw80MCLK
kCLOCK_Usb2PllClk	USB2PLLCLK.
kCLOCK_SysPllClk	SYSPLLCLK.
kCLOCK_SysPllPfd0Clk	SYSPLLPDF0CLK.
kCLOCK_SysPllPfd1Clk	SYSPLLPFD1CLK.
kCLOCK_SysPllPfd2Clk	SYSPLLPFD2CLK.
kCLOCK_SysPllPfd3Clk	SYSPLLPFD3CLK.
kCLOCK_EnetPll0Clk	Enet PLLCLK ref_enetpll0.
kCLOCK_EnetPll1Clk	Enet PLLCLK ref_enetpll1.
kCLOCK_AudioPllClk	Audio PLLCLK.
kCLOCK_VideoPllClk	Video PLLCLK.
kCLOCK_NoneName	None Clock Name.
kCLOCK_OscRc16M	16MHz RC Oscillator.
kCLOCK_OscRc48M	48MHz RC Oscillator.
kCLOCK_OscRc48MDiv2	48MHz RC Oscillator Div2.
kCLOCK_OscRc400M	400MHz RC Oscillator.
kCLOCK_Osc24M	24MHz Oscillator.
kCLOCK_Osc24MOut	48MHz Oscillator Out.
kCLOCK_ArmPll	ARM PLL.
kCLOCK_ArmPllOut	ARM PLL Out.
kCLOCK_SysPll2	SYS PLL2.
kCLOCK_SysPll2Out	SYS PLL2 OUT.
kCLOCK_SysPll2Pfd0	SYS PLL2 PFD0.
kCLOCK_SysPll2Pfd1	SYS PLL2 PFD1.
kCLOCK_SysPll2Pfd2	SYS PLL2 PFD2.
kCLOCK_SysPll2Pfd3	SYS PLL2 PFD3.
kCLOCK_SysPll3	SYS PLL3.
kCLOCK_SysPll3Out	SYS PLL3 OUT.
kCLOCK_SysPll3Div2	SYS PLL3 DIV2
kCLOCK_SysPll3Pfd0	SYS PLL3 PFD0.
kCLOCK_SysPll3Pfd1	SYS PLL3 PFD1
kCLOCK_SysPll3Pfd2	SYS PLL3 PFD2
kCLOCK_SysPll3Pfd3	SYS PLL3 PFD3
kCLOCK_SysPll1	SYS PLL1.
kCLOCK_SysPll1Out	SYS PLL1 OUT.
kCLOCK_SysPll1Div2	SYS PLL1 DIV2.
kCLOCK_SysPll1Div5	SYS PLL1 DIV5.
kCLOCK_AudioPll	SYS AUDIO PLL.
kCLOCK_AudioPllOut	SYS AUDIO PLL OUT.
kCLOCK_VideoPll	SYS VIDEO PLL.
kCLOCK_VideoPllOut	SYS VIDEO PLL OUT.
kCLOCK_CpuClk	SYS CPU CLK.
kCLOCK_CoreSysClk	SYS CORE SYS CLK.
kCLOCK_Reserved	Reserved.

_clock_osc [1/2]

enum _clock_osc

OSC 24M sorce select.

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

_clock_osc [2/2]

enum _clock_osc

OSC 24M sorce select.

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

_clock_output1_selection

enum _clock_output1_selection

The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.

Enumerator
kCLOCK_OutputPllUsb1	Selects USB1 PLL clock(Divided by 2) output.
kCLOCK_OutputPllSys	Selects SYS PLL clock(Divided by 2) output.
kCLOCK_OutputPllVideo	Selects Video PLL clock(Divided by 2) output.
kCLOCK_OutputSemcClk	Selects semc clock root output.
kCLOCK_OutputLcdifPixClk	Selects Lcdif pix clock root output.
kCLOCK_OutputAhbClk	Selects AHB clock root output.
kCLOCK_OutputIpgClk	Selects IPG clock root output.
kCLOCK_OutputPerClk	Selects PERCLK clock root output.
kCLOCK_OutputCkilSyncClk	Selects Ckil clock root output.
kCLOCK_OutputPll4MainClk	Selects PLL4 main clock output.
kCLOCK_DisableClockOutput1	Disables CLKO1.

_clock_output2_selection

enum _clock_output2_selection

The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.

Enumerator
kCLOCK_OutputUsdhc1Clk	Selects USDHC1 clock root output.
kCLOCK_OutputLpi2cClk	Selects LPI2C clock root output.
kCLOCK_OutputCsiClk	Selects CSI clock root output.
kCLOCK_OutputOscClk	Selects OSC output.
kCLOCK_OutputUsdhc2Clk	Selects USDHC2 clock root output.
kCLOCK_OutputSai1Clk	Selects SAI1 clock root output.
kCLOCK_OutputSai2Clk	Selects SAI2 clock root output.
kCLOCK_OutputSai3Clk	Selects SAI3 clock root output.
kCLOCK_OutputCanClk	Selects CAN clock root output.
kCLOCK_OutputFlexspiClk	Selects FLEXSPI clock root output.
kCLOCK_OutputUartClk	Selects UART clock root output.
kCLOCK_OutputSpdif0Clk	Selects SPDIF0 clock root output.
kCLOCK_DisableClockOutput2	Disables CLKO2.

_clock_output_divider

enum _clock_output_divider

The enumerator of clock output's divider.

Enumerator
kCLOCK_DivideBy1	Output clock divided by 1.
kCLOCK_DivideBy2	Output clock divided by 2.
kCLOCK_DivideBy3	Output clock divided by 3.
kCLOCK_DivideBy4	Output clock divided by 4.
kCLOCK_DivideBy5	Output clock divided by 5.
kCLOCK_DivideBy6	Output clock divided by 6.
kCLOCK_DivideBy7	Output clock divided by 7.
kCLOCK_DivideBy8	Output clock divided by 8.

_clock_pfd [1/2]

enum _clock_pfd

PLL PFD name.

Enumerator
kCLOCK_Pfd0	PLL PFD0
kCLOCK_Pfd1	PLL PFD1
kCLOCK_Pfd2	PLL PFD2
kCLOCK_Pfd3	PLL PFD3
kCLOCK_Pfd0	PLL PFD0
kCLOCK_Pfd1	PLL PFD1
kCLOCK_Pfd2	PLL PFD2
kCLOCK_Pfd3	PLL PFD3

_clock_pfd [2/2]

enum _clock_pfd

PLL PFD name.

Enumerator
kCLOCK_Pfd0	PLL PFD0
kCLOCK_Pfd1	PLL PFD1
kCLOCK_Pfd2	PLL PFD2
kCLOCK_Pfd3	PLL PFD3
kCLOCK_Pfd0	PLL PFD0
kCLOCK_Pfd1	PLL PFD1
kCLOCK_Pfd2	PLL PFD2
kCLOCK_Pfd3	PLL PFD3

_clock_pll [1/2]

enum _clock_pll

PLL name.

Enumerator
kCLOCK_PllArm	PLL ARM
kCLOCK_PllSys	PLL SYS
kCLOCK_PllUsb1	PLL USB1
kCLOCK_PllAudio	PLL Audio
kCLOCK_PllVideo	PLL Video
kCLOCK_PllEnet	PLL Enet0
kCLOCK_PllEnet25M	PLL Enet1
kCLOCK_PllUsb2	PLL USB2
kCLOCK_PllArm	ARM PLL.
kCLOCK_PllSys1	SYS1 PLL, it has a dedicated frequency of 1GHz.
kCLOCK_PllSys2	SYS2 PLL, it has a dedicated frequency of 528MHz.
kCLOCK_PllSys3	SYS3 PLL, it has a dedicated frequency of 480MHz.
kCLOCK_PllAudio	Audio PLL.
kCLOCK_PllVideo	Video PLL.
kCLOCK_PllInvalid	Invalid value.

_clock_pll [2/2]

enum _clock_pll

PLL name.

Enumerator
kCLOCK_PllArm	PLL ARM
kCLOCK_PllSys	PLL SYS
kCLOCK_PllUsb1	PLL USB1
kCLOCK_PllAudio	PLL Audio
kCLOCK_PllVideo	PLL Video
kCLOCK_PllEnet	PLL Enet0
kCLOCK_PllEnet25M	PLL Enet1
kCLOCK_PllUsb2	PLL USB2
kCLOCK_PllArm	ARM PLL.
kCLOCK_PllSys1	SYS1 PLL, it has a dedicated frequency of 1GHz.
kCLOCK_PllSys2	SYS2 PLL, it has a dedicated frequency of 528MHz.
kCLOCK_PllSys3	SYS3 PLL, it has a dedicated frequency of 480MHz.
kCLOCK_PllAudio	Audio PLL.
kCLOCK_PllVideo	Video PLL.
kCLOCK_PllInvalid	Invalid value.

_clock_pll_clk_src [1/2]

enum _clock_pll_clk_src

PLL clock source, bypass cloco source also.

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N
kCLOCK_PllClkSrc24M	Pll clock source 24M
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N

_clock_pll_clk_src [2/2]

enum _clock_pll_clk_src

PLL clock source, bypass cloco source also.

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N
kCLOCK_PllClkSrc24M	Pll clock source 24M
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N

_clock_pll_post_div

enum _clock_pll_post_div

PLL post divider enumeration.

Enumerator
kCLOCK_PllPostDiv8	Divide by 8.
kCLOCK_PllPostDiv4	Divide by 4.

_clock_root [1/2]

enum _clock_root

The enumerator of clock root.

Enumerator
kCLOCK_Usdhc1ClkRoot	USDHC1 clock root.
kCLOCK_Usdhc2ClkRoot	USDHC2 clock root.
kCLOCK_FlexspiClkRoot	FLEXSPI clock root.
kCLOCK_CsiClkRoot	CSI clock root.
kCLOCK_LpspiClkRoot	LPSPI clock root.
kCLOCK_TraceClkRoot	Trace clock root.
kCLOCK_Sai1ClkRoot	SAI1 clock root.
kCLOCK_Sai2ClkRoot	SAI2 clock root.
kCLOCK_Sai3ClkRoot	SAI3 clock root.
kCLOCK_Lpi2cClkRoot	LPI2C clock root.
kCLOCK_CanClkRoot	CAN clock root.
kCLOCK_UartClkRoot	UART clock root.
kCLOCK_LcdifClkRoot	LCD clock root.
kCLOCK_SpdifClkRoot	SPDIF clock root.
kCLOCK_Flexio1ClkRoot	FLEXIO1 clock root.
kCLOCK_Flexio2ClkRoot	FLEXIO2 clock root.
kCLOCK_Root_M7	CLOCK Root M7.
kCLOCK_Root_M4	CLOCK Root M4.
kCLOCK_Root_Bus	CLOCK Root Bus.
kCLOCK_Root_Bus_Lpsr	CLOCK Root Bus Lpsr.
kCLOCK_Root_Semc	CLOCK Root Semc.
kCLOCK_Root_Cssys	CLOCK Root Cssys.
kCLOCK_Root_Cstrace	CLOCK Root Cstrace.
kCLOCK_Root_M4_Systick	CLOCK Root M4 Systick.
kCLOCK_Root_M7_Systick	CLOCK Root M7 Systick.
kCLOCK_Root_Adc1	CLOCK Root Adc1.
kCLOCK_Root_Adc2	CLOCK Root Adc2.
kCLOCK_Root_Acmp	CLOCK Root Acmp.
kCLOCK_Root_Flexio1	CLOCK Root Flexio1.
kCLOCK_Root_Flexio2	CLOCK Root Flexio2.
kCLOCK_Root_Gpt1	CLOCK Root Gpt1.
kCLOCK_Root_Gpt2	CLOCK Root Gpt2.
kCLOCK_Root_Gpt3	CLOCK Root Gpt3.
kCLOCK_Root_Gpt4	CLOCK Root Gpt4.
kCLOCK_Root_Gpt5	CLOCK Root Gpt5.
kCLOCK_Root_Gpt6	CLOCK Root Gpt6.
kCLOCK_Root_Flexspi1	CLOCK Root Flexspi1.
kCLOCK_Root_Flexspi2	CLOCK Root Flexspi2.
kCLOCK_Root_Can1	CLOCK Root Can1.
kCLOCK_Root_Can2	CLOCK Root Can2.
kCLOCK_Root_Can3	CLOCK Root Can3.
kCLOCK_Root_Lpuart1	CLOCK Root Lpuart1.
kCLOCK_Root_Lpuart2	CLOCK Root Lpuart2.
kCLOCK_Root_Lpuart3	CLOCK Root Lpuart3.
kCLOCK_Root_Lpuart4	CLOCK Root Lpuart4.
kCLOCK_Root_Lpuart5	CLOCK Root Lpuart5.
kCLOCK_Root_Lpuart6	CLOCK Root Lpuart6.
kCLOCK_Root_Lpuart7	CLOCK Root Lpuart7.
kCLOCK_Root_Lpuart8	CLOCK Root Lpuart8.
kCLOCK_Root_Lpuart9	CLOCK Root Lpuart9.
kCLOCK_Root_Lpuart10	CLOCK Root Lpuart10.
kCLOCK_Root_Lpuart11	CLOCK Root Lpuart11.
kCLOCK_Root_Lpuart12	CLOCK Root Lpuart12.
kCLOCK_Root_Lpi2c1	CLOCK Root Lpi2c1.
kCLOCK_Root_Lpi2c2	CLOCK Root Lpi2c2.
kCLOCK_Root_Lpi2c3	CLOCK Root Lpi2c3.
kCLOCK_Root_Lpi2c4	CLOCK Root Lpi2c4.
kCLOCK_Root_Lpi2c5	CLOCK Root Lpi2c5.
kCLOCK_Root_Lpi2c6	CLOCK Root Lpi2c6.
kCLOCK_Root_Lpspi1	CLOCK Root Lpspi1.
kCLOCK_Root_Lpspi2	CLOCK Root Lpspi2.
kCLOCK_Root_Lpspi3	CLOCK Root Lpspi3.
kCLOCK_Root_Lpspi4	CLOCK Root Lpspi4.
kCLOCK_Root_Lpspi5	CLOCK Root Lpspi5.
kCLOCK_Root_Lpspi6	CLOCK Root Lpspi6.
kCLOCK_Root_Emv1	CLOCK Root Emv1.
kCLOCK_Root_Emv2	CLOCK Root Emv2.
kCLOCK_Root_Enet1	CLOCK Root Enet1.
kCLOCK_Root_Enet2	CLOCK Root Enet2.
kCLOCK_Root_Enet_25m	CLOCK Root Enet 25M.
kCLOCK_Root_Enet_Timer1	CLOCK Root Enet Timer1.
kCLOCK_Root_Enet_Timer2	CLOCK Root Enet Timer2.
kCLOCK_Root_Usdhc1	CLOCK Root Usdhc1.
kCLOCK_Root_Usdhc2	CLOCK Root Usdhc2.
kCLOCK_Root_Asrc	CLOCK Root Asrc.
kCLOCK_Root_Mqs	CLOCK Root Mqs.
kCLOCK_Root_Mic	CLOCK Root MIC.
kCLOCK_Root_Spdif	CLOCK Root Spdif
kCLOCK_Root_Sai1	CLOCK Root Sai1.
kCLOCK_Root_Sai2	CLOCK Root Sai2.
kCLOCK_Root_Sai3	CLOCK Root Sai3.
kCLOCK_Root_Sai4	CLOCK Root Sai4.
kCLOCK_Root_Gc355	CLOCK Root Gc355.
kCLOCK_Root_Lcdif	CLOCK Root Lcdif.
kCLOCK_Root_Lcdifv2	CLOCK Root Lcdifv2.
kCLOCK_Root_Mipi_Ref	CLOCK Root Mipi Ref.
kCLOCK_Root_Mipi_Esc	CLOCK Root Mipi Esc.
kCLOCK_Root_Csi2	CLOCK Root Csi2.
kCLOCK_Root_Csi2_Esc	CLOCK Root Csi2 Esc.
kCLOCK_Root_Csi2_Ui	CLOCK Root Csi2 Ui.
kCLOCK_Root_Csi	CLOCK Root Csi.
kCLOCK_Root_Cko1	CLOCK Root CKo1.
kCLOCK_Root_Cko2	CLOCK Root CKo2.

_clock_root [2/2]

enum _clock_root

Root clock index.

Enumerator
kCLOCK_Usdhc1ClkRoot	USDHC1 clock root.
kCLOCK_Usdhc2ClkRoot	USDHC2 clock root.
kCLOCK_FlexspiClkRoot	FLEXSPI clock root.
kCLOCK_CsiClkRoot	CSI clock root.
kCLOCK_LpspiClkRoot	LPSPI clock root.
kCLOCK_TraceClkRoot	Trace clock root.
kCLOCK_Sai1ClkRoot	SAI1 clock root.
kCLOCK_Sai2ClkRoot	SAI2 clock root.
kCLOCK_Sai3ClkRoot	SAI3 clock root.
kCLOCK_Lpi2cClkRoot	LPI2C clock root.
kCLOCK_CanClkRoot	CAN clock root.
kCLOCK_UartClkRoot	UART clock root.
kCLOCK_LcdifClkRoot	LCD clock root.
kCLOCK_SpdifClkRoot	SPDIF clock root.
kCLOCK_Flexio1ClkRoot	FLEXIO1 clock root.
kCLOCK_Flexio2ClkRoot	FLEXIO2 clock root.
kCLOCK_Root_M7	CLOCK Root M7.
kCLOCK_Root_M4	CLOCK Root M4.
kCLOCK_Root_Bus	CLOCK Root Bus.
kCLOCK_Root_Bus_Lpsr	CLOCK Root Bus Lpsr.
kCLOCK_Root_Semc	CLOCK Root Semc.
kCLOCK_Root_Cssys	CLOCK Root Cssys.
kCLOCK_Root_Cstrace	CLOCK Root Cstrace.
kCLOCK_Root_M4_Systick	CLOCK Root M4 Systick.
kCLOCK_Root_M7_Systick	CLOCK Root M7 Systick.
kCLOCK_Root_Adc1	CLOCK Root Adc1.
kCLOCK_Root_Adc2	CLOCK Root Adc2.
kCLOCK_Root_Acmp	CLOCK Root Acmp.
kCLOCK_Root_Flexio1	CLOCK Root Flexio1.
kCLOCK_Root_Flexio2	CLOCK Root Flexio2.
kCLOCK_Root_Gpt1	CLOCK Root Gpt1.
kCLOCK_Root_Gpt2	CLOCK Root Gpt2.
kCLOCK_Root_Gpt3	CLOCK Root Gpt3.
kCLOCK_Root_Gpt4	CLOCK Root Gpt4.
kCLOCK_Root_Gpt5	CLOCK Root Gpt5.
kCLOCK_Root_Gpt6	CLOCK Root Gpt6.
kCLOCK_Root_Flexspi1	CLOCK Root Flexspi1.
kCLOCK_Root_Flexspi2	CLOCK Root Flexspi2.
kCLOCK_Root_Can1	CLOCK Root Can1.
kCLOCK_Root_Can2	CLOCK Root Can2.
kCLOCK_Root_Can3	CLOCK Root Can3.
kCLOCK_Root_Lpuart1	CLOCK Root Lpuart1.
kCLOCK_Root_Lpuart2	CLOCK Root Lpuart2.
kCLOCK_Root_Lpuart3	CLOCK Root Lpuart3.
kCLOCK_Root_Lpuart4	CLOCK Root Lpuart4.
kCLOCK_Root_Lpuart5	CLOCK Root Lpuart5.
kCLOCK_Root_Lpuart6	CLOCK Root Lpuart6.
kCLOCK_Root_Lpuart7	CLOCK Root Lpuart7.
kCLOCK_Root_Lpuart8	CLOCK Root Lpuart8.
kCLOCK_Root_Lpuart9	CLOCK Root Lpuart9.
kCLOCK_Root_Lpuart10	CLOCK Root Lpuart10.
kCLOCK_Root_Lpuart11	CLOCK Root Lpuart11.
kCLOCK_Root_Lpuart12	CLOCK Root Lpuart12.
kCLOCK_Root_Lpi2c1	CLOCK Root Lpi2c1.
kCLOCK_Root_Lpi2c2	CLOCK Root Lpi2c2.
kCLOCK_Root_Lpi2c3	CLOCK Root Lpi2c3.
kCLOCK_Root_Lpi2c4	CLOCK Root Lpi2c4.
kCLOCK_Root_Lpi2c5	CLOCK Root Lpi2c5.
kCLOCK_Root_Lpi2c6	CLOCK Root Lpi2c6.
kCLOCK_Root_Lpspi1	CLOCK Root Lpspi1.
kCLOCK_Root_Lpspi2	CLOCK Root Lpspi2.
kCLOCK_Root_Lpspi3	CLOCK Root Lpspi3.
kCLOCK_Root_Lpspi4	CLOCK Root Lpspi4.
kCLOCK_Root_Lpspi5	CLOCK Root Lpspi5.
kCLOCK_Root_Lpspi6	CLOCK Root Lpspi6.
kCLOCK_Root_Emv1	CLOCK Root Emv1.
kCLOCK_Root_Emv2	CLOCK Root Emv2.
kCLOCK_Root_Enet1	CLOCK Root Enet1.
kCLOCK_Root_Enet2	CLOCK Root Enet2.
kCLOCK_Root_Enet_25m	CLOCK Root Enet 25M.
kCLOCK_Root_Enet_Timer1	CLOCK Root Enet Timer1.
kCLOCK_Root_Enet_Timer2	CLOCK Root Enet Timer2.
kCLOCK_Root_Usdhc1	CLOCK Root Usdhc1.
kCLOCK_Root_Usdhc2	CLOCK Root Usdhc2.
kCLOCK_Root_Asrc	CLOCK Root Asrc.
kCLOCK_Root_Mqs	CLOCK Root Mqs.
kCLOCK_Root_Mic	CLOCK Root MIC.
kCLOCK_Root_Spdif	CLOCK Root Spdif
kCLOCK_Root_Sai1	CLOCK Root Sai1.
kCLOCK_Root_Sai2	CLOCK Root Sai2.
kCLOCK_Root_Sai3	CLOCK Root Sai3.
kCLOCK_Root_Sai4	CLOCK Root Sai4.
kCLOCK_Root_Gc355	CLOCK Root Gc355.
kCLOCK_Root_Lcdif	CLOCK Root Lcdif.
kCLOCK_Root_Lcdifv2	CLOCK Root Lcdifv2.
kCLOCK_Root_Mipi_Ref	CLOCK Root Mipi Ref.
kCLOCK_Root_Mipi_Esc	CLOCK Root Mipi Esc.
kCLOCK_Root_Csi2	CLOCK Root Csi2.
kCLOCK_Root_Csi2_Esc	CLOCK Root Csi2 Esc.
kCLOCK_Root_Csi2_Ui	CLOCK Root Csi2 Ui.
kCLOCK_Root_Csi	CLOCK Root Csi.
kCLOCK_Root_Cko1	CLOCK Root CKo1.
kCLOCK_Root_Cko2	CLOCK Root CKo2.

_clock_root_mux_source

enum _clock_root_mux_source

The enumerator of clock roots' clock source mux value.

Enumerator
kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2	M7 mux from MuxOscRc48MDiv2.
kCLOCK_M7_ClockRoot_MuxOsc24MOut	M7 mux from MuxOsc24MOut.
kCLOCK_M7_ClockRoot_MuxOscRc400M	M7 mux from MuxOscRc400M.
kCLOCK_M7_ClockRoot_MuxOscRc16M	M7 mux from MuxOscRc16M.
kCLOCK_M7_ClockRoot_MuxArmPllOut	M7 mux from MuxArmPllOut.
kCLOCK_M7_ClockRoot_MuxSysPll3Out	M7 mux from MuxSysPll3Out.
kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2	M4 mux from MuxOscRc48MDiv2.
kCLOCK_M4_ClockRoot_MuxOsc24MOut	M4 mux from MuxOsc24MOut.
kCLOCK_M4_ClockRoot_MuxOscRc400M	M4 mux from MuxOscRc400M.
kCLOCK_M4_ClockRoot_MuxOscRc16M	M4 mux from MuxOscRc16M.
kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3	M4 mux from MuxSysPll3Pfd3.
kCLOCK_M4_ClockRoot_MuxSysPll3Out	M4 mux from MuxSysPll3Out.
kCLOCK_M4_ClockRoot_MuxSysPll2Out	M4 mux from MuxSysPll2Out.
kCLOCK_M4_ClockRoot_MuxSysPll1Div5	M4 mux from MuxSysPll1Div5.
kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2	BUS mux from MuxOscRc48MDiv2.
kCLOCK_BUS_ClockRoot_MuxOsc24MOut	BUS mux from MuxOsc24MOut.
kCLOCK_BUS_ClockRoot_MuxOscRc400M	BUS mux from MuxOscRc400M.
kCLOCK_BUS_ClockRoot_MuxOscRc16M	BUS mux from MuxOscRc16M.
kCLOCK_BUS_ClockRoot_MuxSysPll3Out	BUS mux from MuxSysPll3Out.
kCLOCK_BUS_ClockRoot_MuxSysPll1Div5	BUS mux from MuxSysPll1Div5.
kCLOCK_BUS_ClockRoot_MuxSysPll2Out	BUS mux from MuxSysPll2Out.
kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3	BUS mux from MuxSysPll2Pfd3.
kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2	BUS_LPSR mux from MuxOscRc48MDiv2.
kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut	BUS_LPSR mux from MuxOsc24MOut.
kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M	BUS_LPSR mux from MuxOscRc400M.
kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M	BUS_LPSR mux from MuxOscRc16M.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3	BUS_LPSR mux from MuxSysPll3Pfd3.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out	BUS_LPSR mux from MuxSysPll3Out.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out	BUS_LPSR mux from MuxSysPll2Out.
kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5	BUS_LPSR mux from MuxSysPll1Div5.
kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2	SEMC mux from MuxOscRc48MDiv2.
kCLOCK_SEMC_ClockRoot_MuxOsc24MOut	SEMC mux from MuxOsc24MOut.
kCLOCK_SEMC_ClockRoot_MuxOscRc400M	SEMC mux from MuxOscRc400M.
kCLOCK_SEMC_ClockRoot_MuxOscRc16M	SEMC mux from MuxOscRc16M.
kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5	SEMC mux from MuxSysPll1Div5.
kCLOCK_SEMC_ClockRoot_MuxSysPll2Out	SEMC mux from MuxSysPll2Out.
kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1	SEMC mux from MuxSysPll2Pfd1.
kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0	SEMC mux from MuxSysPll3Pfd0.
kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2	CSSYS mux from MuxOscRc48MDiv2.
kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut	CSSYS mux from MuxOsc24MOut.
kCLOCK_CSSYS_ClockRoot_MuxOscRc400M	CSSYS mux from MuxOscRc400M.
kCLOCK_CSSYS_ClockRoot_MuxOscRc16M	CSSYS mux from MuxOscRc16M.
kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2	CSSYS mux from MuxSysPll3Div2.
kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5	CSSYS mux from MuxSysPll1Div5.
kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out	CSSYS mux from MuxSysPll2Out.
kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3	CSSYS mux from MuxSysPll2Pfd3.
kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2	CSTRACE mux from MuxOscRc48MDiv2.
kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut	CSTRACE mux from MuxOsc24MOut.
kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M	CSTRACE mux from MuxOscRc400M.
kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M	CSTRACE mux from MuxOscRc16M.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2	CSTRACE mux from MuxSysPll3Div2.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5	CSTRACE mux from MuxSysPll1Div5.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1	CSTRACE mux from MuxSysPll2Pfd1.
kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out	CSTRACE mux from MuxSysPll2Out.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2	M4_SYSTICK mux from MuxOscRc48MDiv2.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut	M4_SYSTICK mux from MuxOsc24MOut.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M	M4_SYSTICK mux from MuxOscRc400M.
kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M	M4_SYSTICK mux from MuxOscRc16M.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3	M4_SYSTICK mux from MuxSysPll3Pfd3.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out	M4_SYSTICK mux from MuxSysPll3Out.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0	M4_SYSTICK mux from MuxSysPll2Pfd0.
kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5	M4_SYSTICK mux from MuxSysPll1Div5.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2	M7_SYSTICK mux from MuxOscRc48MDiv2.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut	M7_SYSTICK mux from MuxOsc24MOut.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M	M7_SYSTICK mux from MuxOscRc400M.
kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M	M7_SYSTICK mux from MuxOscRc16M.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out	M7_SYSTICK mux from MuxSysPll2Out.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2	M7_SYSTICK mux from MuxSysPll3Div2.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5	M7_SYSTICK mux from MuxSysPll1Div5.
kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0	M7_SYSTICK mux from MuxSysPll2Pfd0.
kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2	ADC1 mux from MuxOscRc48MDiv2.
kCLOCK_ADC1_ClockRoot_MuxOsc24MOut	ADC1 mux from MuxOsc24MOut.
kCLOCK_ADC1_ClockRoot_MuxOscRc400M	ADC1 mux from MuxOscRc400M.
kCLOCK_ADC1_ClockRoot_MuxOscRc16M	ADC1 mux from MuxOscRc16M.
kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2	ADC1 mux from MuxSysPll3Div2.
kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5	ADC1 mux from MuxSysPll1Div5.
kCLOCK_ADC1_ClockRoot_MuxSysPll2Out	ADC1 mux from MuxSysPll2Out.
kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3	ADC1 mux from MuxSysPll2Pfd3.
kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2	ADC2 mux from MuxOscRc48MDiv2.
kCLOCK_ADC2_ClockRoot_MuxOsc24MOut	ADC2 mux from MuxOsc24MOut.
kCLOCK_ADC2_ClockRoot_MuxOscRc400M	ADC2 mux from MuxOscRc400M.
kCLOCK_ADC2_ClockRoot_MuxOscRc16M	ADC2 mux from MuxOscRc16M.
kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2	ADC2 mux from MuxSysPll3Div2.
kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5	ADC2 mux from MuxSysPll1Div5.
kCLOCK_ADC2_ClockRoot_MuxSysPll2Out	ADC2 mux from MuxSysPll2Out.
kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3	ADC2 mux from MuxSysPll2Pfd3.
kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2	ACMP mux from MuxOscRc48MDiv2.
kCLOCK_ACMP_ClockRoot_MuxOsc24MOut	ACMP mux from MuxOsc24MOut.
kCLOCK_ACMP_ClockRoot_MuxOscRc400M	ACMP mux from MuxOscRc400M.
kCLOCK_ACMP_ClockRoot_MuxOscRc16M	ACMP mux from MuxOscRc16M.
kCLOCK_ACMP_ClockRoot_MuxSysPll3Out	ACMP mux from MuxSysPll3Out.
kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5	ACMP mux from MuxSysPll1Div5.
kCLOCK_ACMP_ClockRoot_MuxAudioPllOut	ACMP mux from MuxAudioPllOut.
kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3	ACMP mux from MuxSysPll2Pfd3.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2	FLEXIO1 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut	FLEXIO1 mux from MuxOsc24MOut.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M	FLEXIO1 mux from MuxOscRc400M.
kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M	FLEXIO1 mux from MuxOscRc16M.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2	FLEXIO1 mux from MuxSysPll3Div2.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5	FLEXIO1 mux from MuxSysPll1Div5.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out	FLEXIO1 mux from MuxSysPll2Out.
kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3	FLEXIO1 mux from MuxSysPll2Pfd3.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2	FLEXIO2 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut	FLEXIO2 mux from MuxOsc24MOut.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M	FLEXIO2 mux from MuxOscRc400M.
kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M	FLEXIO2 mux from MuxOscRc16M.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2	FLEXIO2 mux from MuxSysPll3Div2.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5	FLEXIO2 mux from MuxSysPll1Div5.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out	FLEXIO2 mux from MuxSysPll2Out.
kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3	FLEXIO2 mux from MuxSysPll2Pfd3.
kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2	GPT1 mux from MuxOscRc48MDiv2.
kCLOCK_GPT1_ClockRoot_MuxOsc24MOut	GPT1 mux from MuxOsc24MOut.
kCLOCK_GPT1_ClockRoot_MuxOscRc400M	GPT1 mux from MuxOscRc400M.
kCLOCK_GPT1_ClockRoot_MuxOscRc16M	GPT1 mux from MuxOscRc16M.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2	GPT1 mux from MuxSysPll3Div2.
kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5	GPT1 mux from MuxSysPll1Div5.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2	GPT1 mux from MuxSysPll3Pfd2.
kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3	GPT1 mux from MuxSysPll3Pfd3.
kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2	GPT2 mux from MuxOscRc48MDiv2.
kCLOCK_GPT2_ClockRoot_MuxOsc24MOut	GPT2 mux from MuxOsc24MOut.
kCLOCK_GPT2_ClockRoot_MuxOscRc400M	GPT2 mux from MuxOscRc400M.
kCLOCK_GPT2_ClockRoot_MuxOscRc16M	GPT2 mux from MuxOscRc16M.
kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2	GPT2 mux from MuxSysPll3Div2.
kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5	GPT2 mux from MuxSysPll1Div5.
kCLOCK_GPT2_ClockRoot_MuxAudioPllOut	GPT2 mux from MuxAudioPllOut.
kCLOCK_GPT2_ClockRoot_MuxVideoPllOut	GPT2 mux from MuxVideoPllOut.
kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2	GPT3 mux from MuxOscRc48MDiv2.
kCLOCK_GPT3_ClockRoot_MuxOsc24MOut	GPT3 mux from MuxOsc24MOut.
kCLOCK_GPT3_ClockRoot_MuxOscRc400M	GPT3 mux from MuxOscRc400M.
kCLOCK_GPT3_ClockRoot_MuxOscRc16M	GPT3 mux from MuxOscRc16M.
kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2	GPT3 mux from MuxSysPll3Div2.
kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5	GPT3 mux from MuxSysPll1Div5.
kCLOCK_GPT3_ClockRoot_MuxAudioPllOut	GPT3 mux from MuxAudioPllOut.
kCLOCK_GPT3_ClockRoot_MuxVideoPllOut	GPT3 mux from MuxVideoPllOut.
kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2	GPT4 mux from MuxOscRc48MDiv2.
kCLOCK_GPT4_ClockRoot_MuxOsc24MOut	GPT4 mux from MuxOsc24MOut.
kCLOCK_GPT4_ClockRoot_MuxOscRc400M	GPT4 mux from MuxOscRc400M.
kCLOCK_GPT4_ClockRoot_MuxOscRc16M	GPT4 mux from MuxOscRc16M.
kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2	GPT4 mux from MuxSysPll3Div2.
kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5	GPT4 mux from MuxSysPll1Div5.
kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2	GPT4 mux from MuxSysPll3Pfd2.
kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3	GPT4 mux from MuxSysPll3Pfd3.
kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2	GPT5 mux from MuxOscRc48MDiv2.
kCLOCK_GPT5_ClockRoot_MuxOsc24MOut	GPT5 mux from MuxOsc24MOut.
kCLOCK_GPT5_ClockRoot_MuxOscRc400M	GPT5 mux from MuxOscRc400M.
kCLOCK_GPT5_ClockRoot_MuxOscRc16M	GPT5 mux from MuxOscRc16M.
kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2	GPT5 mux from MuxSysPll3Div2.
kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5	GPT5 mux from MuxSysPll1Div5.
kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2	GPT5 mux from MuxSysPll3Pfd2.
kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3	GPT5 mux from MuxSysPll3Pfd3.
kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2	GPT6 mux from MuxOscRc48MDiv2.
kCLOCK_GPT6_ClockRoot_MuxOsc24MOut	GPT6 mux from MuxOsc24MOut.
kCLOCK_GPT6_ClockRoot_MuxOscRc400M	GPT6 mux from MuxOscRc400M.
kCLOCK_GPT6_ClockRoot_MuxOscRc16M	GPT6 mux from MuxOscRc16M.
kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2	GPT6 mux from MuxSysPll3Div2.
kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5	GPT6 mux from MuxSysPll1Div5.
kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2	GPT6 mux from MuxSysPll3Pfd2.
kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3	GPT6 mux from MuxSysPll3Pfd3.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2	FLEXSPI1 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut	FLEXSPI1 mux from MuxOsc24MOut.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M	FLEXSPI1 mux from MuxOscRc400M.
kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M	FLEXSPI1 mux from MuxOscRc16M.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0	FLEXSPI1 mux from MuxSysPll3Pfd0.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out	FLEXSPI1 mux from MuxSysPll2Out.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2	FLEXSPI1 mux from MuxSysPll2Pfd2.
kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out	FLEXSPI1 mux from MuxSysPll3Out.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2	FLEXSPI2 mux from MuxOscRc48MDiv2.
kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut	FLEXSPI2 mux from MuxOsc24MOut.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M	FLEXSPI2 mux from MuxOscRc400M.
kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M	FLEXSPI2 mux from MuxOscRc16M.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0	FLEXSPI2 mux from MuxSysPll3Pfd0.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out	FLEXSPI2 mux from MuxSysPll2Out.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2	FLEXSPI2 mux from MuxSysPll2Pfd2.
kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out	FLEXSPI2 mux from MuxSysPll3Out.
kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2	CAN1 mux from MuxOscRc48MDiv2.
kCLOCK_CAN1_ClockRoot_MuxOsc24MOut	CAN1 mux from MuxOsc24MOut.
kCLOCK_CAN1_ClockRoot_MuxOscRc400M	CAN1 mux from MuxOscRc400M.
kCLOCK_CAN1_ClockRoot_MuxOscRc16M	CAN1 mux from MuxOscRc16M.
kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2	CAN1 mux from MuxSysPll3Div2.
kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5	CAN1 mux from MuxSysPll1Div5.
kCLOCK_CAN1_ClockRoot_MuxSysPll2Out	CAN1 mux from MuxSysPll2Out.
kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3	CAN1 mux from MuxSysPll2Pfd3.
kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2	CAN2 mux from MuxOscRc48MDiv2.
kCLOCK_CAN2_ClockRoot_MuxOsc24MOut	CAN2 mux from MuxOsc24MOut.
kCLOCK_CAN2_ClockRoot_MuxOscRc400M	CAN2 mux from MuxOscRc400M.
kCLOCK_CAN2_ClockRoot_MuxOscRc16M	CAN2 mux from MuxOscRc16M.
kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2	CAN2 mux from MuxSysPll3Div2.
kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5	CAN2 mux from MuxSysPll1Div5.
kCLOCK_CAN2_ClockRoot_MuxSysPll2Out	CAN2 mux from MuxSysPll2Out.
kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3	CAN2 mux from MuxSysPll2Pfd3.
kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2	CAN3 mux from MuxOscRc48MDiv2.
kCLOCK_CAN3_ClockRoot_MuxOsc24MOut	CAN3 mux from MuxOsc24MOut.
kCLOCK_CAN3_ClockRoot_MuxOscRc400M	CAN3 mux from MuxOscRc400M.
kCLOCK_CAN3_ClockRoot_MuxOscRc16M	CAN3 mux from MuxOscRc16M.
kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3	CAN3 mux from MuxSysPll3Pfd3.
kCLOCK_CAN3_ClockRoot_MuxSysPll3Out	CAN3 mux from MuxSysPll3Out.
kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3	CAN3 mux from MuxSysPll2Pfd3.
kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5	CAN3 mux from MuxSysPll1Div5.
kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2	LPUART1 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut	LPUART1 mux from MuxOsc24MOut.
kCLOCK_LPUART1_ClockRoot_MuxOscRc400M	LPUART1 mux from MuxOscRc400M.
kCLOCK_LPUART1_ClockRoot_MuxOscRc16M	LPUART1 mux from MuxOscRc16M.
kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2	LPUART1 mux from MuxSysPll3Div2.
kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5	LPUART1 mux from MuxSysPll1Div5.
kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out	LPUART1 mux from MuxSysPll2Out.
kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3	LPUART1 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2	LPUART2 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut	LPUART2 mux from MuxOsc24MOut.
kCLOCK_LPUART2_ClockRoot_MuxOscRc400M	LPUART2 mux from MuxOscRc400M.
kCLOCK_LPUART2_ClockRoot_MuxOscRc16M	LPUART2 mux from MuxOscRc16M.
kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2	LPUART2 mux from MuxSysPll3Div2.
kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5	LPUART2 mux from MuxSysPll1Div5.
kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out	LPUART2 mux from MuxSysPll2Out.
kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3	LPUART2 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2	LPUART3 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut	LPUART3 mux from MuxOsc24MOut.
kCLOCK_LPUART3_ClockRoot_MuxOscRc400M	LPUART3 mux from MuxOscRc400M.
kCLOCK_LPUART3_ClockRoot_MuxOscRc16M	LPUART3 mux from MuxOscRc16M.
kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2	LPUART3 mux from MuxSysPll3Div2.
kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5	LPUART3 mux from MuxSysPll1Div5.
kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out	LPUART3 mux from MuxSysPll2Out.
kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3	LPUART3 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2	LPUART4 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut	LPUART4 mux from MuxOsc24MOut.
kCLOCK_LPUART4_ClockRoot_MuxOscRc400M	LPUART4 mux from MuxOscRc400M.
kCLOCK_LPUART4_ClockRoot_MuxOscRc16M	LPUART4 mux from MuxOscRc16M.
kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2	LPUART4 mux from MuxSysPll3Div2.
kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5	LPUART4 mux from MuxSysPll1Div5.
kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out	LPUART4 mux from MuxSysPll2Out.
kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3	LPUART4 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2	LPUART5 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut	LPUART5 mux from MuxOsc24MOut.
kCLOCK_LPUART5_ClockRoot_MuxOscRc400M	LPUART5 mux from MuxOscRc400M.
kCLOCK_LPUART5_ClockRoot_MuxOscRc16M	LPUART5 mux from MuxOscRc16M.
kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2	LPUART5 mux from MuxSysPll3Div2.
kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5	LPUART5 mux from MuxSysPll1Div5.
kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out	LPUART5 mux from MuxSysPll2Out.
kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3	LPUART5 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2	LPUART6 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut	LPUART6 mux from MuxOsc24MOut.
kCLOCK_LPUART6_ClockRoot_MuxOscRc400M	LPUART6 mux from MuxOscRc400M.
kCLOCK_LPUART6_ClockRoot_MuxOscRc16M	LPUART6 mux from MuxOscRc16M.
kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2	LPUART6 mux from MuxSysPll3Div2.
kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5	LPUART6 mux from MuxSysPll1Div5.
kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out	LPUART6 mux from MuxSysPll2Out.
kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3	LPUART6 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2	LPUART7 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut	LPUART7 mux from MuxOsc24MOut.
kCLOCK_LPUART7_ClockRoot_MuxOscRc400M	LPUART7 mux from MuxOscRc400M.
kCLOCK_LPUART7_ClockRoot_MuxOscRc16M	LPUART7 mux from MuxOscRc16M.
kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2	LPUART7 mux from MuxSysPll3Div2.
kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5	LPUART7 mux from MuxSysPll1Div5.
kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out	LPUART7 mux from MuxSysPll2Out.
kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3	LPUART7 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2	LPUART8 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut	LPUART8 mux from MuxOsc24MOut.
kCLOCK_LPUART8_ClockRoot_MuxOscRc400M	LPUART8 mux from MuxOscRc400M.
kCLOCK_LPUART8_ClockRoot_MuxOscRc16M	LPUART8 mux from MuxOscRc16M.
kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2	LPUART8 mux from MuxSysPll3Div2.
kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5	LPUART8 mux from MuxSysPll1Div5.
kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out	LPUART8 mux from MuxSysPll2Out.
kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3	LPUART8 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2	LPUART9 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut	LPUART9 mux from MuxOsc24MOut.
kCLOCK_LPUART9_ClockRoot_MuxOscRc400M	LPUART9 mux from MuxOscRc400M.
kCLOCK_LPUART9_ClockRoot_MuxOscRc16M	LPUART9 mux from MuxOscRc16M.
kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2	LPUART9 mux from MuxSysPll3Div2.
kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5	LPUART9 mux from MuxSysPll1Div5.
kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out	LPUART9 mux from MuxSysPll2Out.
kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3	LPUART9 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2	LPUART10 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut	LPUART10 mux from MuxOsc24MOut.
kCLOCK_LPUART10_ClockRoot_MuxOscRc400M	LPUART10 mux from MuxOscRc400M.
kCLOCK_LPUART10_ClockRoot_MuxOscRc16M	LPUART10 mux from MuxOscRc16M.
kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2	LPUART10 mux from MuxSysPll3Div2.
kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5	LPUART10 mux from MuxSysPll1Div5.
kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out	LPUART10 mux from MuxSysPll2Out.
kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3	LPUART10 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2	LPUART11 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut	LPUART11 mux from MuxOsc24MOut.
kCLOCK_LPUART11_ClockRoot_MuxOscRc400M	LPUART11 mux from MuxOscRc400M.
kCLOCK_LPUART11_ClockRoot_MuxOscRc16M	LPUART11 mux from MuxOscRc16M.
kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3	LPUART11 mux from MuxSysPll3Pfd3.
kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out	LPUART11 mux from MuxSysPll3Out.
kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3	LPUART11 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5	LPUART11 mux from MuxSysPll1Div5.
kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2	LPUART12 mux from MuxOscRc48MDiv2.
kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut	LPUART12 mux from MuxOsc24MOut.
kCLOCK_LPUART12_ClockRoot_MuxOscRc400M	LPUART12 mux from MuxOscRc400M.
kCLOCK_LPUART12_ClockRoot_MuxOscRc16M	LPUART12 mux from MuxOscRc16M.
kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3	LPUART12 mux from MuxSysPll3Pfd3.
kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out	LPUART12 mux from MuxSysPll3Out.
kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3	LPUART12 mux from MuxSysPll2Pfd3.
kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5	LPUART12 mux from MuxSysPll1Div5.
kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2	LPI2C1 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut	LPI2C1 mux from MuxOsc24MOut.
kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M	LPI2C1 mux from MuxOscRc400M.
kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M	LPI2C1 mux from MuxOscRc16M.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2	LPI2C1 mux from MuxSysPll3Div2.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5	LPI2C1 mux from MuxSysPll1Div5.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out	LPI2C1 mux from MuxSysPll2Out.
kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3	LPI2C1 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2	LPI2C2 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut	LPI2C2 mux from MuxOsc24MOut.
kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M	LPI2C2 mux from MuxOscRc400M.
kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M	LPI2C2 mux from MuxOscRc16M.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2	LPI2C2 mux from MuxSysPll3Div2.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5	LPI2C2 mux from MuxSysPll1Div5.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out	LPI2C2 mux from MuxSysPll2Out.
kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3	LPI2C2 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2	LPI2C3 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut	LPI2C3 mux from MuxOsc24MOut.
kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M	LPI2C3 mux from MuxOscRc400M.
kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M	LPI2C3 mux from MuxOscRc16M.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2	LPI2C3 mux from MuxSysPll3Div2.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5	LPI2C3 mux from MuxSysPll1Div5.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out	LPI2C3 mux from MuxSysPll2Out.
kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3	LPI2C3 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2	LPI2C4 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut	LPI2C4 mux from MuxOsc24MOut.
kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M	LPI2C4 mux from MuxOscRc400M.
kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M	LPI2C4 mux from MuxOscRc16M.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2	LPI2C4 mux from MuxSysPll3Div2.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5	LPI2C4 mux from MuxSysPll1Div5.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out	LPI2C4 mux from MuxSysPll2Out.
kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3	LPI2C4 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2	LPI2C5 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut	LPI2C5 mux from MuxOsc24MOut.
kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M	LPI2C5 mux from MuxOscRc400M.
kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M	LPI2C5 mux from MuxOscRc16M.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3	LPI2C5 mux from MuxSysPll3Pfd3.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out	LPI2C5 mux from MuxSysPll3Out.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3	LPI2C5 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5	LPI2C5 mux from MuxSysPll1Div5.
kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2	LPI2C6 mux from MuxOscRc48MDiv2.
kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut	LPI2C6 mux from MuxOsc24MOut.
kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M	LPI2C6 mux from MuxOscRc400M.
kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M	LPI2C6 mux from MuxOscRc16M.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3	LPI2C6 mux from MuxSysPll3Pfd3.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out	LPI2C6 mux from MuxSysPll3Out.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3	LPI2C6 mux from MuxSysPll2Pfd3.
kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5	LPI2C6 mux from MuxSysPll1Div5.
kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2	LPSPI1 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut	LPSPI1 mux from MuxOsc24MOut.
kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M	LPSPI1 mux from MuxOscRc400M.
kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M	LPSPI1 mux from MuxOscRc16M.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2	LPSPI1 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5	LPSPI1 mux from MuxSysPll1Div5.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out	LPSPI1 mux from MuxSysPll2Out.
kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3	LPSPI1 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2	LPSPI2 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut	LPSPI2 mux from MuxOsc24MOut.
kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M	LPSPI2 mux from MuxOscRc400M.
kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M	LPSPI2 mux from MuxOscRc16M.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2	LPSPI2 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5	LPSPI2 mux from MuxSysPll1Div5.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out	LPSPI2 mux from MuxSysPll2Out.
kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3	LPSPI2 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2	LPSPI3 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut	LPSPI3 mux from MuxOsc24MOut.
kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M	LPSPI3 mux from MuxOscRc400M.
kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M	LPSPI3 mux from MuxOscRc16M.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2	LPSPI3 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5	LPSPI3 mux from MuxSysPll1Div5.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out	LPSPI3 mux from MuxSysPll2Out.
kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3	LPSPI3 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2	LPSPI4 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut	LPSPI4 mux from MuxOsc24MOut.
kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M	LPSPI4 mux from MuxOscRc400M.
kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M	LPSPI4 mux from MuxOscRc16M.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2	LPSPI4 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5	LPSPI4 mux from MuxSysPll1Div5.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out	LPSPI4 mux from MuxSysPll2Out.
kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3	LPSPI4 mux from MuxSysPll2Pfd3.
kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2	LPSPI5 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut	LPSPI5 mux from MuxOsc24MOut.
kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M	LPSPI5 mux from MuxOscRc400M.
kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M	LPSPI5 mux from MuxOscRc16M.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3	LPSPI5 mux from MuxSysPll3Pfd3.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out	LPSPI5 mux from MuxSysPll3Out.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2	LPSPI5 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5	LPSPI5 mux from MuxSysPll1Div5.
kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2	LPSPI6 mux from MuxOscRc48MDiv2.
kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut	LPSPI6 mux from MuxOsc24MOut.
kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M	LPSPI6 mux from MuxOscRc400M.
kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M	LPSPI6 mux from MuxOscRc16M.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3	LPSPI6 mux from MuxSysPll3Pfd3.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out	LPSPI6 mux from MuxSysPll3Out.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2	LPSPI6 mux from MuxSysPll3Pfd2.
kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5	LPSPI6 mux from MuxSysPll1Div5.
kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2	EMV1 mux from MuxOscRc48MDiv2.
kCLOCK_EMV1_ClockRoot_MuxOsc24MOut	EMV1 mux from MuxOsc24MOut.
kCLOCK_EMV1_ClockRoot_MuxOscRc400M	EMV1 mux from MuxOscRc400M.
kCLOCK_EMV1_ClockRoot_MuxOscRc16M	EMV1 mux from MuxOscRc16M.
kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2	EMV1 mux from MuxSysPll3Div2.
kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5	EMV1 mux from MuxSysPll1Div5.
kCLOCK_EMV1_ClockRoot_MuxSysPll2Out	EMV1 mux from MuxSysPll2Out.
kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3	EMV1 mux from MuxSysPll2Pfd3.
kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2	EMV2 mux from MuxOscRc48MDiv2.
kCLOCK_EMV2_ClockRoot_MuxOsc24MOut	EMV2 mux from MuxOsc24MOut.
kCLOCK_EMV2_ClockRoot_MuxOscRc400M	EMV2 mux from MuxOscRc400M.
kCLOCK_EMV2_ClockRoot_MuxOscRc16M	EMV2 mux from MuxOscRc16M.
kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2	EMV2 mux from MuxSysPll3Div2.
kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5	EMV2 mux from MuxSysPll1Div5.
kCLOCK_EMV2_ClockRoot_MuxSysPll2Out	EMV2 mux from MuxSysPll2Out.
kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3	EMV2 mux from MuxSysPll2Pfd3.
kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2	ENET1 mux from MuxOscRc48MDiv2.
kCLOCK_ENET1_ClockRoot_MuxOsc24MOut	ENET1 mux from MuxOsc24MOut.
kCLOCK_ENET1_ClockRoot_MuxOscRc400M	ENET1 mux from MuxOscRc400M.
kCLOCK_ENET1_ClockRoot_MuxOscRc16M	ENET1 mux from MuxOscRc16M.
kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2	ENET1 mux from MuxSysPll1Div2.
kCLOCK_ENET1_ClockRoot_MuxAudioPllOut	ENET1 mux from MuxAudioPllOut.
kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5	ENET1 mux from MuxSysPll1Div5.
kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1	ENET1 mux from MuxSysPll2Pfd1.
kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2	ENET2 mux from MuxOscRc48MDiv2.
kCLOCK_ENET2_ClockRoot_MuxOsc24MOut	ENET2 mux from MuxOsc24MOut.
kCLOCK_ENET2_ClockRoot_MuxOscRc400M	ENET2 mux from MuxOscRc400M.
kCLOCK_ENET2_ClockRoot_MuxOscRc16M	ENET2 mux from MuxOscRc16M.
kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2	ENET2 mux from MuxSysPll1Div2.
kCLOCK_ENET2_ClockRoot_MuxAudioPllOut	ENET2 mux from MuxAudioPllOut.
kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5	ENET2 mux from MuxSysPll1Div5.
kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1	ENET2 mux from MuxSysPll2Pfd1.
kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2	ENET_25M mux from MuxOscRc48MDiv2.
kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut	ENET_25M mux from MuxOsc24MOut.
kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M	ENET_25M mux from MuxOscRc400M.
kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M	ENET_25M mux from MuxOscRc16M.
kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2	ENET_25M mux from MuxSysPll1Div2.
kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut	ENET_25M mux from MuxAudioPllOut.
kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5	ENET_25M mux from MuxSysPll1Div5.
kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1	ENET_25M mux from MuxSysPll2Pfd1.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2	ENET_TIMER1 mux from MuxOscRc48MDiv2.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut	ENET_TIMER1 mux from MuxOsc24MOut.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M	ENET_TIMER1 mux from MuxOscRc400M.
kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M	ENET_TIMER1 mux from MuxOscRc16M.
kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2	ENET_TIMER1 mux from MuxSysPll1Div2.
kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut	ENET_TIMER1 mux from MuxAudioPllOut.
kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5	ENET_TIMER1 mux from MuxSysPll1Div5.
kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1	ENET_TIMER1 mux from MuxSysPll2Pfd1.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2	ENET_TIMER2 mux from MuxOscRc48MDiv2.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut	ENET_TIMER2 mux from MuxOsc24MOut.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M	ENET_TIMER2 mux from MuxOscRc400M.
kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M	ENET_TIMER2 mux from MuxOscRc16M.
kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2	ENET_TIMER2 mux from MuxSysPll1Div2.
kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut	ENET_TIMER2 mux from MuxAudioPllOut.
kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5	ENET_TIMER2 mux from MuxSysPll1Div5.
kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1	ENET_TIMER2 mux from MuxSysPll2Pfd1.
kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2	USDHC1 mux from MuxOscRc48MDiv2.
kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut	USDHC1 mux from MuxOsc24MOut.
kCLOCK_USDHC1_ClockRoot_MuxOscRc400M	USDHC1 mux from MuxOscRc400M.
kCLOCK_USDHC1_ClockRoot_MuxOscRc16M	USDHC1 mux from MuxOscRc16M.
kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2	USDHC1 mux from MuxSysPll2Pfd2.
kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0	USDHC1 mux from MuxSysPll2Pfd0.
kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5	USDHC1 mux from MuxSysPll1Div5.
kCLOCK_USDHC1_ClockRoot_MuxArmPllOut	USDHC1 mux from MuxArmPllOut.
kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2	USDHC2 mux from MuxOscRc48MDiv2.
kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut	USDHC2 mux from MuxOsc24MOut.
kCLOCK_USDHC2_ClockRoot_MuxOscRc400M	USDHC2 mux from MuxOscRc400M.
kCLOCK_USDHC2_ClockRoot_MuxOscRc16M	USDHC2 mux from MuxOscRc16M.
kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2	USDHC2 mux from MuxSysPll2Pfd2.
kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0	USDHC2 mux from MuxSysPll2Pfd0.
kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5	USDHC2 mux from MuxSysPll1Div5.
kCLOCK_USDHC2_ClockRoot_MuxArmPllOut	USDHC2 mux from MuxArmPllOut.
kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2	ASRC mux from MuxOscRc48MDiv2.
kCLOCK_ASRC_ClockRoot_MuxOsc24MOut	ASRC mux from MuxOsc24MOut.
kCLOCK_ASRC_ClockRoot_MuxOscRc400M	ASRC mux from MuxOscRc400M.
kCLOCK_ASRC_ClockRoot_MuxOscRc16M	ASRC mux from MuxOscRc16M.
kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5	ASRC mux from MuxSysPll1Div5.
kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2	ASRC mux from MuxSysPll3Div2.
kCLOCK_ASRC_ClockRoot_MuxAudioPllOut	ASRC mux from MuxAudioPllOut.
kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3	ASRC mux from MuxSysPll2Pfd3.
kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2	MQS mux from MuxOscRc48MDiv2.
kCLOCK_MQS_ClockRoot_MuxOsc24MOut	MQS mux from MuxOsc24MOut.
kCLOCK_MQS_ClockRoot_MuxOscRc400M	MQS mux from MuxOscRc400M.
kCLOCK_MQS_ClockRoot_MuxOscRc16M	MQS mux from MuxOscRc16M.
kCLOCK_MQS_ClockRoot_MuxSysPll1Div5	MQS mux from MuxSysPll1Div5.
kCLOCK_MQS_ClockRoot_MuxSysPll3Div2	MQS mux from MuxSysPll3Div2.
kCLOCK_MQS_ClockRoot_MuxAudioPllOut	MQS mux from MuxAudioPllOut.
kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3	MQS mux from MuxSysPll2Pfd3.
kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2	MIC mux from MuxOscRc48MDiv2.
kCLOCK_MIC_ClockRoot_MuxOsc24MOut	MIC mux from MuxOsc24MOut.
kCLOCK_MIC_ClockRoot_MuxOscRc400M	MIC mux from MuxOscRc400M.
kCLOCK_MIC_ClockRoot_MuxOscRc16M	MIC mux from MuxOscRc16M.
kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3	MIC mux from MuxSysPll3Pfd3.
kCLOCK_MIC_ClockRoot_MuxSysPll3Out	MIC mux from MuxSysPll3Out.
kCLOCK_MIC_ClockRoot_MuxAudioPllOut	MIC mux from MuxAudioPllOut.
kCLOCK_MIC_ClockRoot_MuxSysPll1Div5	MIC mux from MuxSysPll1Div5.
kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2	SPDIF mux from MuxOscRc48MDiv2.
kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut	SPDIF mux from MuxOsc24MOut.
kCLOCK_SPDIF_ClockRoot_MuxOscRc400M	SPDIF mux from MuxOscRc400M.
kCLOCK_SPDIF_ClockRoot_MuxOscRc16M	SPDIF mux from MuxOscRc16M.
kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut	SPDIF mux from MuxAudioPllOut.
kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out	SPDIF mux from MuxSysPll3Out.
kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2	SPDIF mux from MuxSysPll3Pfd2.
kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3	SPDIF mux from MuxSysPll2Pfd3.
kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2	SAI1 mux from MuxOscRc48MDiv2.
kCLOCK_SAI1_ClockRoot_MuxOsc24MOut	SAI1 mux from MuxOsc24MOut.
kCLOCK_SAI1_ClockRoot_MuxOscRc400M	SAI1 mux from MuxOscRc400M.
kCLOCK_SAI1_ClockRoot_MuxOscRc16M	SAI1 mux from MuxOscRc16M.
kCLOCK_SAI1_ClockRoot_MuxAudioPllOut	SAI1 mux from MuxAudioPllOut.
kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2	SAI1 mux from MuxSysPll3Pfd2.
kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5	SAI1 mux from MuxSysPll1Div5.
kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3	SAI1 mux from MuxSysPll2Pfd3.
kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2	SAI2 mux from MuxOscRc48MDiv2.
kCLOCK_SAI2_ClockRoot_MuxOsc24MOut	SAI2 mux from MuxOsc24MOut.
kCLOCK_SAI2_ClockRoot_MuxOscRc400M	SAI2 mux from MuxOscRc400M.
kCLOCK_SAI2_ClockRoot_MuxOscRc16M	SAI2 mux from MuxOscRc16M.
kCLOCK_SAI2_ClockRoot_MuxAudioPllOut	SAI2 mux from MuxAudioPllOut.
kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2	SAI2 mux from MuxSysPll3Pfd2.
kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5	SAI2 mux from MuxSysPll1Div5.
kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3	SAI2 mux from MuxSysPll2Pfd3.
kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2	SAI3 mux from MuxOscRc48MDiv2.
kCLOCK_SAI3_ClockRoot_MuxOsc24MOut	SAI3 mux from MuxOsc24MOut.
kCLOCK_SAI3_ClockRoot_MuxOscRc400M	SAI3 mux from MuxOscRc400M.
kCLOCK_SAI3_ClockRoot_MuxOscRc16M	SAI3 mux from MuxOscRc16M.
kCLOCK_SAI3_ClockRoot_MuxAudioPllOut	SAI3 mux from MuxAudioPllOut.
kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2	SAI3 mux from MuxSysPll3Pfd2.
kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5	SAI3 mux from MuxSysPll1Div5.
kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3	SAI3 mux from MuxSysPll2Pfd3.
kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2	SAI4 mux from MuxOscRc48MDiv2.
kCLOCK_SAI4_ClockRoot_MuxOsc24MOut	SAI4 mux from MuxOsc24MOut.
kCLOCK_SAI4_ClockRoot_MuxOscRc400M	SAI4 mux from MuxOscRc400M.
kCLOCK_SAI4_ClockRoot_MuxOscRc16M	SAI4 mux from MuxOscRc16M.
kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3	SAI4 mux from MuxSysPll3Pfd3.
kCLOCK_SAI4_ClockRoot_MuxSysPll3Out	SAI4 mux from MuxSysPll3Out.
kCLOCK_SAI4_ClockRoot_MuxAudioPllOut	SAI4 mux from MuxAudioPllOut.
kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5	SAI4 mux from MuxSysPll1Div5.
kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2	GC355 mux from MuxOscRc48MDiv2.
kCLOCK_GC355_ClockRoot_MuxOsc24MOut	GC355 mux from MuxOsc24MOut.
kCLOCK_GC355_ClockRoot_MuxOscRc400M	GC355 mux from MuxOscRc400M.
kCLOCK_GC355_ClockRoot_MuxOscRc16M	GC355 mux from MuxOscRc16M.
kCLOCK_GC355_ClockRoot_MuxSysPll2Out	GC355 mux from MuxSysPll2Out.
kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1	GC355 mux from MuxSysPll2Pfd1.
kCLOCK_GC355_ClockRoot_MuxSysPll3Out	GC355 mux from MuxSysPll3Out.
kCLOCK_GC355_ClockRoot_MuxVideoPllOut	GC355 mux from MuxVideoPllOut.
kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2	LCDIF mux from MuxOscRc48MDiv2.
kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut	LCDIF mux from MuxOsc24MOut.
kCLOCK_LCDIF_ClockRoot_MuxOscRc400M	LCDIF mux from MuxOscRc400M.
kCLOCK_LCDIF_ClockRoot_MuxOscRc16M	LCDIF mux from MuxOscRc16M.
kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out	LCDIF mux from MuxSysPll2Out.
kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2	LCDIF mux from MuxSysPll2Pfd2.
kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0	LCDIF mux from MuxSysPll3Pfd0.
kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut	LCDIF mux from MuxVideoPllOut.
kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2	LCDIFV2 mux from MuxOscRc48MDiv2.
kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut	LCDIFV2 mux from MuxOsc24MOut.
kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M	LCDIFV2 mux from MuxOscRc400M.
kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M	LCDIFV2 mux from MuxOscRc16M.
kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out	LCDIFV2 mux from MuxSysPll2Out.
kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2	LCDIFV2 mux from MuxSysPll2Pfd2.
kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0	LCDIFV2 mux from MuxSysPll3Pfd0.
kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut	LCDIFV2 mux from MuxVideoPllOut.
kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2	MIPI_REF mux from MuxOscRc48MDiv2.
kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut	MIPI_REF mux from MuxOsc24MOut.
kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M	MIPI_REF mux from MuxOscRc400M.
kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M	MIPI_REF mux from MuxOscRc16M.
kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out	MIPI_REF mux from MuxSysPll2Out.
kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0	MIPI_REF mux from MuxSysPll2Pfd0.
kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0	MIPI_REF mux from MuxSysPll3Pfd0.
kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut	MIPI_REF mux from MuxVideoPllOut.
kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2	MIPI_ESC mux from MuxOscRc48MDiv2.
kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut	MIPI_ESC mux from MuxOsc24MOut.
kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M	MIPI_ESC mux from MuxOscRc400M.
kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M	MIPI_ESC mux from MuxOscRc16M.
kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out	MIPI_ESC mux from MuxSysPll2Out.
kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0	MIPI_ESC mux from MuxSysPll2Pfd0.
kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0	MIPI_ESC mux from MuxSysPll3Pfd0.
kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut	MIPI_ESC mux from MuxVideoPllOut.
kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2	CSI2 mux from MuxOscRc48MDiv2.
kCLOCK_CSI2_ClockRoot_MuxOsc24MOut	CSI2 mux from MuxOsc24MOut.
kCLOCK_CSI2_ClockRoot_MuxOscRc400M	CSI2 mux from MuxOscRc400M.
kCLOCK_CSI2_ClockRoot_MuxOscRc16M	CSI2 mux from MuxOscRc16M.
kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2	CSI2 mux from MuxSysPll2Pfd2.
kCLOCK_CSI2_ClockRoot_MuxSysPll3Out	CSI2 mux from MuxSysPll3Out.
kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0	CSI2 mux from MuxSysPll2Pfd0.
kCLOCK_CSI2_ClockRoot_MuxVideoPllOut	CSI2 mux from MuxVideoPllOut.
kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2	CSI2_ESC mux from MuxOscRc48MDiv2.
kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut	CSI2_ESC mux from MuxOsc24MOut.
kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M	CSI2_ESC mux from MuxOscRc400M.
kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M	CSI2_ESC mux from MuxOscRc16M.
kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2	CSI2_ESC mux from MuxSysPll2Pfd2.
kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out	CSI2_ESC mux from MuxSysPll3Out.
kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0	CSI2_ESC mux from MuxSysPll2Pfd0.
kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut	CSI2_ESC mux from MuxVideoPllOut.
kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2	CSI2_UI mux from MuxOscRc48MDiv2.
kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut	CSI2_UI mux from MuxOsc24MOut.
kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M	CSI2_UI mux from MuxOscRc400M.
kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M	CSI2_UI mux from MuxOscRc16M.
kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2	CSI2_UI mux from MuxSysPll2Pfd2.
kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out	CSI2_UI mux from MuxSysPll3Out.
kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0	CSI2_UI mux from MuxSysPll2Pfd0.
kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut	CSI2_UI mux from MuxVideoPllOut.
kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2	CSI mux from MuxOscRc48MDiv2.
kCLOCK_CSI_ClockRoot_MuxOsc24MOut	CSI mux from MuxOsc24MOut.
kCLOCK_CSI_ClockRoot_MuxOscRc400M	CSI mux from MuxOscRc400M.
kCLOCK_CSI_ClockRoot_MuxOscRc16M	CSI mux from MuxOscRc16M.
kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2	CSI mux from MuxSysPll2Pfd2.
kCLOCK_CSI_ClockRoot_MuxSysPll3Out	CSI mux from MuxSysPll3Out.
kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1	CSI mux from MuxSysPll3Pfd1.
kCLOCK_CSI_ClockRoot_MuxVideoPllOut	CSI mux from MuxVideoPllOut.
kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2	CKO1 mux from MuxOscRc48MDiv2.
kCLOCK_CKO1_ClockRoot_MuxOsc24MOut	CKO1 mux from MuxOsc24MOut.
kCLOCK_CKO1_ClockRoot_MuxOscRc400M	CKO1 mux from MuxOscRc400M.
kCLOCK_CKO1_ClockRoot_MuxOscRc16M	CKO1 mux from MuxOscRc16M.
kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2	CKO1 mux from MuxSysPll2Pfd2.
kCLOCK_CKO1_ClockRoot_MuxSysPll2Out	CKO1 mux from MuxSysPll2Out.
kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1	CKO1 mux from MuxSysPll3Pfd1.
kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5	CKO1 mux from MuxSysPll1Div5.
kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2	CKO2 mux from MuxOscRc48MDiv2.
kCLOCK_CKO2_ClockRoot_MuxOsc24MOut	CKO2 mux from MuxOsc24MOut.
kCLOCK_CKO2_ClockRoot_MuxOscRc400M	CKO2 mux from MuxOscRc400M.
kCLOCK_CKO2_ClockRoot_MuxOscRc16M	CKO2 mux from MuxOscRc16M.
kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3	CKO2 mux from MuxSysPll2Pfd3.
kCLOCK_CKO2_ClockRoot_MuxOscRc48M	CKO2 mux from MuxOscRc48M.
kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1	CKO2 mux from MuxSysPll3Pfd1.
kCLOCK_CKO2_ClockRoot_MuxAudioPllOut	CKO2 mux from MuxAudioPllOut.

_clock_usb_phy_src [1/2]

enum _clock_usb_phy_src

Source of the USB HS PHY.

Enumerator
kCLOCK_Usbphy480M	Use 480M.
kCLOCK_Usbphy480M	Use 480M.

_clock_usb_phy_src [2/2]

enum _clock_usb_phy_src

Source of the USB HS PHY.

Enumerator
kCLOCK_Usbphy480M	Use 480M.
kCLOCK_Usbphy480M	Use 480M.

_clock_usb_src [1/2]

enum _clock_usb_src

USB clock source definition.

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

_clock_usb_src [2/2]

enum _clock_usb_src

USB clock source definition.

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

Function Documentation

CLOCK_CalcArmPllFreq()

status_t CLOCK_CalcArmPllFreq	(	clock_arm_pll_config_t *	config,
		uint32_t	freqInMhz
	)

Calculate corresponding config values per given frequency.

This function calculates config valudes per given frequency for Arm PLL

Parameters

config	pll config structure
freqInMhz	target frequency

CLOCK_CalcAvPllFreq()

status_t CLOCK_CalcAvPllFreq	(	clock_av_pll_config_t *	config,
		uint32_t	freqInMhz
	)

Calculate corresponding config values per given frequency.

This function calculates config valudes per given frequency for Audio/Video PLL.

Parameters

config	pll config structure
freqInMhz	target frequency

CLOCK_CalcPllSpreadSpectrum()

void CLOCK_CalcPllSpreadSpectrum	(	uint32_t	factor,
		uint32_t	range,
		uint32_t	mod,
		clock_pll_ss_config_t *	ss
	)

Calculate spread spectrum step and stop.

This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/video/syspll1), the factor is denominator.

Parameters

factor	factor to calculate step/stop
range	spread spectrum range
mod	spread spectrum modulation frequency
ss	calculated spread spectrum values

CLOCK_DeinitArmPll()

void CLOCK_DeinitArmPll

(

void

)

De-initialize the ARM PLL.

brief De-initialize the ARM PLL.

CLOCK_DeinitAudioPll()

void CLOCK_DeinitAudioPll

(

void

)

De-initialize the Audio PLL.

brief De-initialize the Audio PLL.

CLOCK_DeinitEnetPll()

void CLOCK_DeinitEnetPll

(

void

)

Deinitialize the ENET PLL.

This function disables the ENET PLL.

brief Deinitialize the ENET PLL.

This function disables the ENET PLL.

CLOCK_DeinitExternalClk()

void CLOCK_DeinitExternalClk

(

void

)

Deinitialize the external 24MHz clock.

This function disables the external 24MHz clock.

After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.

brief Deinitialize the external 24MHz clock.

This function disables the external 24MHz clock.

After this function, please call ref CLOCK_SetXtal0Freq to set external clock frequency to 0.

CLOCK_DeinitPfd()

void CLOCK_DeinitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

De-initialize selected PLL PFD.

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.

brief De-initialize selected PLL PFD.

param pll Which PLL of targeting PFD to be operated. param pfd Which PFD clock to enable.

CLOCK_DeinitRcOsc24M()

void CLOCK_DeinitRcOsc24M

(

void

)

Power down the RCOSC 24M clock.

brief Power down the RCOSC 24M clock.

CLOCK_DeinitSysPfd()

void CLOCK_DeinitSysPfd

(

clock_pfd_t

pfd

)

De-initialize the System PLL PFD.

This function disables the System PLL PFD.

Parameters

pfd	Which PFD clock to disable.

brief De-initialize the System PLL PFD.

This function disables the System PLL PFD.

param pfd Which PFD clock to disable.

CLOCK_DeinitSysPll()

void CLOCK_DeinitSysPll

(

void

)

De-initialize the System PLL.

brief De-initialize the System PLL.

CLOCK_DeinitUsb1Pfd()

void CLOCK_DeinitUsb1Pfd

(

clock_pfd_t

pfd

)

De-initialize the USB1 PLL PFD.

This function disables the USB1 PLL PFD.

Parameters

pfd	Which PFD clock to disable.

brief De-initialize the USB1 PLL PFD.

This function disables the USB1 PLL PFD.

param pfd Which PFD clock to disable.

CLOCK_DeinitUsb1Pll()

void CLOCK_DeinitUsb1Pll

(

void

)

Deinitialize the USB1 PLL.

brief Deinitialize the USB1 PLL.

CLOCK_DeinitUsb2Pll()

void CLOCK_DeinitUsb2Pll

(

void

)

Deinitialize the USB2 PLL.

brief Deinitialize the USB2 PLL.

CLOCK_DeinitVideoPll()

void CLOCK_DeinitVideoPll

(

void

)

De-initialize the Video PLL.

brief De-initialize the Video PLL.

CLOCK_DisableUsbhs0PhyPllClock()

void CLOCK_DisableUsbhs0PhyPllClock

(

void

)

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

brief Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

brief Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. param freq USB HS does not care about the clock source, so this parameter is ignored. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

brief Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

CLOCK_DisableUsbhs1PhyPllClock()

void CLOCK_DisableUsbhs1PhyPllClock

(

void

)

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

brief Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

brief Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

CLOCK_EnableUsbhs0Clock()

bool CLOCK_EnableUsbhs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. param freq USB HS does not care about the clock source, so this parameter is ignored. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. param freq USB HS does not care about the clock source, so this parameter is ignored. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

CLOCK_EnableUsbhs0PhyPllClock()

bool CLOCK_EnableUsbhs0PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

param src USB HS PHY PLL clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

param src USB HS PHY PLL clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

CLOCK_EnableUsbhs1Clock()

bool CLOCK_EnableUsbhs1Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. param freq USB HS does not care about the clock source, so this parameter is ignored. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

CLOCK_EnableUsbhs1PhyPllClock()

bool CLOCK_EnableUsbhs1PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

param src USB HS PHY PLL clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

CLOCK_GetAhbFreq()

uint32_t CLOCK_GetAhbFreq

(

void

)

Gets the AHB clock frequency.

Returns

The AHB clock frequency value in hertz.

brief Gets the AHB clock frequency.

return The AHB clock frequency value in hertz.

CLOCK_GetClockOutCLKO1Freq()

uint32_t CLOCK_GetClockOutCLKO1Freq

(

void

)

Get the frequency of clock output1 clock signal.

Returns

The frequency of clock output1 clock signal.

brief Get the frequency of clock output1 clock signal.

return The frequency of clock output1 clock signal.

CLOCK_GetClockOutClkO2Freq()

uint32_t CLOCK_GetClockOutClkO2Freq

(

void

)

Get the frequency of clock output2 clock signal.

Returns

The frequency of clock output2 clock signal.

brief Get the frequency of clock output2 clock signal.

return The frequency of clock output2 clock signal.

CLOCK_GetClockRootFreq()

uint32_t CLOCK_GetClockRootFreq

(

clock_root_t

clockRoot

)

Gets the frequency of selected clock root.

Parameters

clockRoot

The clock root used to get the frequency, please refer to clock_root_t.

Returns

The frequency of selected clock root.

brief Gets the frequency of selected clock root.

param clockRoot The clock root used to get the frequency, please refer to clock_root_t. return The frequency of selected clock root.

CLOCK_GetFreq()

uint32_t CLOCK_GetFreq

(

clock_name_t

name

)

Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns

Clock frequency value in hertz

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns

Clock frequency value in hertz

brief Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

param clockName Clock names defined in clock_name_t return Clock frequency value in hertz

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns

Clock frequency value in hertz

CLOCK_GetIpgFreq()

uint32_t CLOCK_GetIpgFreq

(

void

)

Gets the IPG clock frequency.

Returns

The IPG clock frequency value in hertz.

brief Gets the IPG clock frequency.

return The IPG clock frequency value in hertz.

CLOCK_GetPerClkFreq()

uint32_t CLOCK_GetPerClkFreq

(

void

)

Gets the PER clock frequency.

Returns

The PER clock frequency value in hertz.

brief Gets the PER clock frequency.

return The PER clock frequency value in hertz.

CLOCK_GetPfdFreq()

uint32_t CLOCK_GetPfdFreq	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

Get current PFD output frequency.

This function get current output frequency of specific System PLL PFD

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	pfd name to get frequency.

Returns

The PFD output frequency in hertz.

CLOCK_GetPllFreq()

uint32_t CLOCK_GetPllFreq

(

clock_pll_t

pll

)

Get current PLL output frequency.

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns

The PLL output frequency in hertz.

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns

The PLL output frequency in hertz.

brief Get current PLL output frequency.

This function get current output frequency of specific PLL

param pll pll name to get frequency. return The PLL output frequency in hertz.

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns

The PLL output frequency in hertz.

CLOCK_GetSemcFreq()

uint32_t CLOCK_GetSemcFreq

(

void

)

Gets the SEMC clock frequency.

Returns

The SEMC clock frequency value in hertz.

brief Gets the SEMC clock frequency.

return The SEMC clock frequency value in hertz.

CLOCK_GetSysPfdFreq()

uint32_t CLOCK_GetSysPfdFreq

(

clock_pfd_t

pfd

)

Get current System PLL PFD output frequency.

This function get current output frequency of specific System PLL PFD

Parameters

pfd	pfd name to get frequency.

Returns

The PFD output frequency in hertz.

brief Get current System PLL PFD output frequency.

This function get current output frequency of specific System PLL PFD

param pfd pfd name to get frequency. return The PFD output frequency in hertz.

CLOCK_GetUsb1PfdFreq()

uint32_t CLOCK_GetUsb1PfdFreq

(

clock_pfd_t

pfd

)

Get current USB1 PLL PFD output frequency.

This function get current output frequency of specific USB1 PLL PFD

Parameters

pfd	pfd name to get frequency.

Returns

The PFD output frequency in hertz.

brief Get current USB1 PLL PFD output frequency.

This function get current output frequency of specific USB1 PLL PFD

param pfd pfd name to get frequency. return The PFD output frequency in hertz.

CLOCK_GPC_SetAudioPllOutputFreq()

void CLOCK_GPC_SetAudioPllOutputFreq

(

const clock_audio_pll_gpc_config_t *

config

)

Set Audio PLL output frequency in GPC mode.

Parameters

config

Pointer to clock_audio_pll_gpc_config_t structure.

CLOCK_GPC_SetSysPll1OutputFreq()

void CLOCK_GPC_SetSysPll1OutputFreq

(

const clock_sys_pll1_gpc_config_t *

config

)

Set System PLL1 output frequency in GPC mode.

Parameters

config

Pointer to clock_sys_pll1_gpc_config_t.

CLOCK_GPC_SetVideoPllOutputFreq()

void CLOCK_GPC_SetVideoPllOutputFreq

(

const clock_video_pll_gpc_config_t *

config

)

Set Video PLL output frequency in GPC mode.

Parameters

config

Pointer to clock_audio_pll_gpc_config_t structure.

CLOCK_InitArmPll()

void CLOCK_InitArmPll

(

const clock_arm_pll_config_t *

config

)

Initialize the ARM PLL.

This function initialize the ARM PLL with specific settings

Parameters

config

configuration to set to PLL.

This function initialize the ARM PLL with specific settings

Parameters

config

configuration to set to PLL.

brief Initialize the ARM PLL.

This function initialize the ARM PLL with specific settings

param config configuration to set to PLL.

This function initialize the ARM PLL with specific settings

Parameters

config

configuration to set to PLL.

CLOCK_InitArmPllWithFreq()

status_t CLOCK_InitArmPllWithFreq

(

uint32_t

freqInMhz

)

Initializes the Arm PLL with Specific Frequency (in Mhz).

This function initializes the Arm PLL with specific frequency

Parameters

freqInMhz

target frequency

CLOCK_InitAudioPll()

void CLOCK_InitAudioPll

(

const clock_audio_pll_config_t *

config

)

Initializes the Audio PLL.

This function initializes the Audio PLL with specific settings

Parameters

config

Configuration to set to PLL.

This function initializes the Audio PLL with specific settings

Parameters

config

Configuration to set to PLL.

brief Initializes the Audio PLL.

This function initializes the Audio PLL with specific settings

param config Configuration to set to PLL.

This function initializes the Audio PLL with specific settings

Parameters

config

Configuration to set to PLL.

CLOCK_InitAudioPllWithFreq()

status_t CLOCK_InitAudioPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

Initializes the Audio PLL with Specific Frequency (in Mhz).

This function initializes the Audio PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

CLOCK_InitEnetPll()

void CLOCK_InitEnetPll

(

const clock_enet_pll_config_t *

config

)

Initialize the ENET PLL.

This function initializes the ENET PLL with specific settings.

Parameters

config

Configuration to set to PLL.

brief Initialize the ENET PLL.

This function initializes the ENET PLL with specific settings.

param config Configuration to set to PLL.

CLOCK_InitExternalClk()

void CLOCK_InitExternalClk

(

bool

bypassXtalOsc

)

Initialize the external 24MHz clock.

This function supports two modes:

1. Use external crystal oscillator.
2. Bypass the external crystal oscillator, using input source clock directly.

After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

Parameters

bypassXtalOsc

Pass in true to bypass the external crystal oscillator.

Note

This device does not support bypass external crystal oscillator, so the input parameter should always be false.

brief Initialize the external 24MHz clock.

This function supports two modes:

1. Use external crystal oscillator.
2. Bypass the external crystal oscillator, using input source clock directly.

After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

param bypassXtalOsc Pass in true to bypass the external crystal oscillator. note This device does not support bypass external crystal oscillator, so the input parameter should always be false.

CLOCK_InitPfd()

void CLOCK_InitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd,
		uint8_t	frac
	)

Initialize PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.
frac	The PFD FRAC value.

Note

It is recommended that PFD settings are kept between 12-35.

CLOCK_InitRcOsc24M()

void CLOCK_InitRcOsc24M

(

void

)

Initialize the RC oscillator 24MHz clock.

brief Initialize the RC oscillator 24MHz clock.

CLOCK_InitSysPfd()

void CLOCK_InitSysPfd	(	clock_pfd_t	pfd,
		uint8_t	pfdFrac
	)

Initialize the System PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pfd	Which PFD clock to enable.
pfdFrac	The PFD FRAC value.

Note

It is recommended that PFD settings are kept between 12-35.

brief Initialize the System PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

param pfd Which PFD clock to enable. param pfdFrac The PFD FRAC value. note It is recommended that PFD settings are kept between 12-35.

CLOCK_InitSysPll()

void CLOCK_InitSysPll

(

const clock_sys_pll_config_t *

config

)

Initialize the System PLL.

This function initializes the System PLL with specific settings

Parameters

config

Configuration to set to PLL.

brief Initialize the System PLL.

This function initializes the System PLL with specific settings

param config Configuration to set to PLL.

CLOCK_InitSysPll1()

void CLOCK_InitSysPll1

(

const clock_sys_pll1_config_t *

config

)

Initialize the System PLL1.

This function initializes the System PLL1 with specific settings

Parameters

config

Configuration to set to PLL1.

CLOCK_InitSysPll2()

void CLOCK_InitSysPll2

(

const clock_sys_pll2_config_t *

config

)

Initialize the System PLL2.

This function initializes the System PLL2 with specific settings

Parameters

config

Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum

CLOCK_InitSysPll3()

void CLOCK_InitSysPll3

(

void

)

Initialize the System PLL3.

This function initializes the System PLL3 with specific settings

CLOCK_InitUsb1Pfd()

void CLOCK_InitUsb1Pfd	(	clock_pfd_t	pfd,
		uint8_t	pfdFrac
	)

Initialize the USB1 PLL PFD.

This function initializes the USB1 PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pfd	Which PFD clock to enable.
pfdFrac	The PFD FRAC value.

Note

It is recommended that PFD settings are kept between 12-35.

brief Initialize the USB1 PLL PFD.

This function initializes the USB1 PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

param pfd Which PFD clock to enable. param pfdFrac The PFD FRAC value. note It is recommended that PFD settings are kept between 12-35.

CLOCK_InitUsb1Pll()

void CLOCK_InitUsb1Pll

(

const clock_usb_pll_config_t *

config

)

Initialize the USB1 PLL.

This function initializes the USB1 PLL with specific settings

Parameters

config

Configuration to set to PLL.

brief Initialize the USB1 PLL.

This function initializes the USB1 PLL with specific settings

param config Configuration to set to PLL.

CLOCK_InitUsb2Pll()

void CLOCK_InitUsb2Pll

(

const clock_usb_pll_config_t *

config

)

Initialize the USB2 PLL.

This function initializes the USB2 PLL with specific settings

Parameters

config

Configuration to set to PLL.

brief Initialize the USB2 PLL.

This function initializes the USB2 PLL with specific settings

param config Configuration to set to PLL.

CLOCK_InitVideoPll()

void CLOCK_InitVideoPll

(

const clock_video_pll_config_t *

config

)

Initialize the video PLL.

This function configures the Video PLL with specific settings

Parameters

config

configuration to set to PLL.

This function configures the Video PLL with specific settings

Parameters

config

configuration to set to PLL.

brief Initialize the video PLL.

This function configures the Video PLL with specific settings

param config configuration to set to PLL.

This function configures the Video PLL with specific settings

Parameters

config

configuration to set to PLL.

CLOCK_InitVideoPllWithFreq()

status_t CLOCK_InitVideoPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

Initializes the Video PLL with Specific Frequency (in Mhz).

This function initializes the Video PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

CLOCK_IsSysPfdEnabled()

bool CLOCK_IsSysPfdEnabled

(

clock_pfd_t

pfd

)

Check if Sys PFD is enabled.

Parameters

pfd	PFD control name

Returns

PFD bypass status.

• true: power on.
• false: power off.

brief Check if Sys PFD is enabled

param pfd PFD control name return PFD bypass status.

• true: power on.
• false: power off.

CLOCK_IsSysPll2PfdEnabled()

bool CLOCK_IsSysPll2PfdEnabled

(

clock_pfd_t

pfd

)

Check if Sys PLL2 PFD is enabled.

Parameters

pfd	PFD control name

Returns

PFD bypass status.

• true: power on.
• false: power off.

Note

Only useful in software control mode.

brief Check if Sys PLL2 PFD is enabled

param pfd PFD control name return PFD bypass status.

• true: power on.
• false: power off. note Only useful in software control mode.

CLOCK_IsSysPll3PfdEnabled()

bool CLOCK_IsSysPll3PfdEnabled

(

clock_pfd_t

pfd

)

Check if Sys PLL3 PFD is enabled.

Parameters

pfd	PFD control name

Returns

PFD bypass status.

• true: power on.
• false: power off.

Note

Only useful in software control mode.

brief Check if Sys PLL3 PFD is enabled

param pfd PFD control name return PFD bypass status.

• true: power on.
• false: power off. note Only useful in software control mode.

CLOCK_IsUsb1PfdEnabled()

bool CLOCK_IsUsb1PfdEnabled

(

clock_pfd_t

pfd

)

Check if Usb1 PFD is enabled.

Parameters

pfd	PFD control name.

Returns

PFD bypass status.

• true: power on.
• false: power off.

brief Check if Usb1 PFD is enabled

param pfd PFD control name. return PFD bypass status.

• true: power on.
• false: power off.

CLOCK_LPCG_ControlByCpuLowPowerMode()

void CLOCK_LPCG_ControlByCpuLowPowerMode	(	clock_lpcg_t	name,
		uint8_t	domainId,
		clock_level_t	level0,
		clock_level_t	level1
	)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.
level0,level1	Depend level of this clock.

CLOCK_LPCG_ControlBySetPointMode()

void CLOCK_LPCG_ControlBySetPointMode	(	clock_lpcg_t	name,
		uint16_t	spValue,
		uint16_t	stbyValue
	)

Set this clock works in SetPoint control Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
spValue	Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.
stbyValue	Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

CLOCK_OSC_BypassOscRc400MTuneLogic()

void CLOCK_OSC_BypassOscRc400MTuneLogic

(

bool

enableBypass

)

Bypass/un-bypass the tune logic.

Parameters

enableBypass

Used to control whether to bypass the turn logic. true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency. false Use the output of tune logic to run the oscillator.

brief Bypass/un-bypass the tune logic

param enableBypass Used to control whether to bypass the turn logic.

• true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
• false Use the output of tune logic to run the oscillator.

CLOCK_OSC_CheckLocked1MHzErrorFlag()

bool CLOCK_OSC_CheckLocked1MHzErrorFlag

(

void

)

Check the error flag for locked 1MHz clock out.

Returns

The error flag for locked 1MHz clock out.

• true The count value has been reached within one diviced ref clock period
• false No effect.

brief Check the error flag for locked 1MHz clock out.

return The error flag for locked 1MHz clock out.

• true The count value has been reached within one diviced ref clock period
• false No effect.

CLOCK_OSC_ClearLocked1MHzErrorFlag()

void CLOCK_OSC_ClearLocked1MHzErrorFlag

(

void

)

Clear the error flag for locked 1MHz clock out.

brief Clear the error flag for locked 1MHz clock out.

CLOCK_OSC_EnableOsc24M()

void CLOCK_OSC_EnableOsc24M

(

void

)

Enable OSC 24Mhz.

This function enables OSC 24Mhz.

CLOCK_OSC_EnableOscRc400M()

void CLOCK_OSC_EnableOscRc400M

(

void

)

Enable OSC RC 400Mhz.

This function enables OSC RC 400Mhz.

CLOCK_OSC_EnableOscRc400MTuneLogic()

void CLOCK_OSC_EnableOscRc400MTuneLogic

(

bool

enable

)

Start/Stop the tune logic.

Parameters

enable

Used to start or stop the tune logic. true Start tuning false Stop tuning and reset the tuning logic.

brief Start/Stop the tune logic.

param enable Used to start or stop the tune logic.

• true Start tuning
• false Stop tuning and reset the tuning logic.

CLOCK_OSC_FreezeOscRc400MTuneValue()

void CLOCK_OSC_FreezeOscRc400MTuneValue

(

bool

enableFreeze

)

Freeze/Unfreeze the tuning value.

Parameters

enableFreeze

Used to control whether to freeze the tune value. true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value. false Unfreezes and continues the tune operation.

brief Freeze/Unfreeze the tuning value.

param enableFreeze Used to control whether to freeze the tune value.

• true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
• false Unfreezes and continues the tune operation.

CLOCK_OSC_GetCurrentOscRc400MFastClockCount()

uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount

(

void

)

Get current count for the fast clock during the tune process.

Returns

The current count for the fast clock.

brief Get current count for the fast clock during the tune process.

return The current count for the fast clock.

CLOCK_OSC_GetCurrentOscRc400MTuneValue()

uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue

(

void

)

Get current tune value used by oscillator during tune process.

Returns

The current tune value.

brief Get current tune value used by oscillator during tune process.

return The current tune value.

CLOCK_OSC_Set1MHzOutputBehavior()

void CLOCK_OSC_Set1MHzOutputBehavior

(

clock_1MHzOut_behavior_t

behavior

)

Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.

Note

The 1MHz clock is divided from 400M RC Oscillator.

Parameters

behavior

The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.

note The 1MHz clock is divided from 400M RC Oscillator.

param behavior The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

CLOCK_OSC_SetLocked1MHzCount()

void CLOCK_OSC_SetLocked1MHzCount

(

uint16_t

count

)

Set the count for the locked 1MHz clock out.

Parameters

count

Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.

brief Set the count for the locked 1MHz clock out.

param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the osc_out_400M per divided ref_clk.

CLOCK_OSC_SetOsc16MConfig()

void CLOCK_OSC_SetOsc16MConfig	(	clock_16MOsc_source_t	source,
		bool	enablePowerSave,
		bool	enableClockOut
	)

Configure the 16MHz oscillator.

Parameters

source	Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t.
enablePowerSave	Enable/disable power save mode function at 16MHz OSC. true Enable power save mode function at 16MHz osc. false Disable power save mode function at 16MHz osc.
enableClockOut	Enable/Disable clock output for 16MHz RCOSC. true Enable clock output for 16MHz RCOSC. false Disable clock output for 16MHz RCOSC.

brief Configure the 16MHz oscillator.

param source Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t. param enablePowerSave Enable/disable power save mode function at 16MHz OSC.

• true Enable power save mode function at 16MHz osc.
• false Disable power save mode function at 16MHz osc. param enableClockOut Enable/Disable clock output for 16MHz RCOSC.
• true Enable clock output for 16MHz RCOSC.
• false Disable clock output for 16MHz RCOSC.

CLOCK_OSC_SetOsc24MWorkMode()

void CLOCK_OSC_SetOsc24MWorkMode

(

clock_24MOsc_mode_t

workMode

)

Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.

Parameters

workMode

The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.

param workMode The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

CLOCK_OSC_SetOscRc400MFastClkCount()

void CLOCK_OSC_SetOscRc400MFastClkCount

(

uint16_t

targetCount

)

Set the target count for the fast clock.

Parameters

targetCount

The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

brief Set the target count for the fast clock.

param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

CLOCK_OSC_SetOscRc400MHysteresisValue()

void CLOCK_OSC_SetOscRc400MHysteresisValue	(	uint8_t	negHysteresis,
		uint8_t	posHysteresis
	)

Set the negative and positive hysteresis value for the tuned clock.

Note

The hysteresis value should be set after the clock is tuned.

Parameters

negHysteresis	The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock
posHysteresis	The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

brief Set the negative and positive hysteresis value for the tuned clock.

note The hysteresis value should be set after the clock is tuned.

param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

CLOCK_OSC_SetOscRc400MRefClkDiv()

void CLOCK_OSC_SetOscRc400MRefClkDiv

(

uint8_t

divValue

)

Set the divide value for ref_clk to generate slow clock.

Note

slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

Parameters

divValue

The divide value to be set, the available range is 0~63.

brief Set the divide value for ref_clk to generate slow clock.

note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

param divValue The divide value to be set, the available range is 0~63.

CLOCK_OSC_SetOscRc400MTuneValue()

void CLOCK_OSC_SetOscRc400MTuneValue

(

uint8_t

tuneValue

)

Set the 400MHz RC oscillator tune value when the tune logic is disabled.

Parameters

tuneValue

The tune value to determine the frequency of Oscillator.

Parameters

tuneValue

The tune value to determine the frequency of Oscillator.

CLOCK_OSC_TrimOscRc400M()

void CLOCK_OSC_TrimOscRc400M	(	bool	enable,
		bool	bypass,
		uint16_t	trim
	)

Trims OSC RC 400MHz.

Parameters

enable	Used to enable trim function.
bypass	Bypass the trim function.
trim	Trim value.

CLOCK_OSCPLL_ControlByCpuLowPowerMode()

void CLOCK_OSCPLL_ControlByCpuLowPowerMode	(	clock_name_t	name,
		uint8_t	domainId,
		clock_level_t	level0,
		clock_level_t	level1
	)

Set this clock works in CPU Low Power Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.
level0,level1	Depend level of this clock.

CLOCK_OSCPLL_ControlBySetPointMode()

void CLOCK_OSCPLL_ControlBySetPointMode	(	clock_name_t	name,
		uint16_t	spValue,
		uint16_t	stbyValue
	)

Set this clock works in SetPoint control Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
spValue	Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.
stbyValue	Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

CLOCK_ROOT_ControlBySetPointMode()

void CLOCK_ROOT_ControlBySetPointMode	(	clock_root_t	name,
		const clock_root_setpoint_config_t *	spTable
	)

Set this clock works in SetPoint controlled Mode.

Note

When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
spTable	Point to the array that stores clock root settings for each setpoint. Note that the pointed array must have 16 elements.

CLOCK_SetClockOutput1()

void CLOCK_SetClockOutput1	(	clock_output1_selection_t	selection,
		clock_output_divider_t	divider
	)

Set the clock source and the divider of the clock output1.

Parameters

selection	The clock source to be output, please refer to clock_output1_selection_t.
divider	The divider of the output clock signal, please refer to clock_output_divider_t.

brief Set the clock source and the divider of the clock output1.

param selection The clock source to be output, please refer to clock_output1_selection_t. param divider The divider of the output clock signal, please refer to clock_output_divider_t.

CLOCK_SetClockOutput2()

void CLOCK_SetClockOutput2	(	clock_output2_selection_t	selection,
		clock_output_divider_t	divider
	)

Set the clock source and the divider of the clock output2.

Parameters

selection	The clock source to be output, please refer to clock_output2_selection_t.
divider	The divider of the output clock signal, please refer to clock_output_divider_t.

brief Set the clock source and the divider of the clock output2.

param selection The clock source to be output, please refer to clock_output2_selection_t. param divider The divider of the output clock signal, please refer to clock_output_divider_t.

CLOCK_SetGroupConfig()

void CLOCK_SetGroupConfig	(	clock_group_t	group,
		const clock_group_config_t *	config
	)

Set the clock group configuration.

Parameters

group	Which group to configure, see clock_group_t.
config	Configuration to set.

CLOCK_SetPllBypass()

void CLOCK_SetPllBypass	(	clock_pll_t	pll,
		bool	bypass
	)

PLL bypass setting.

Parameters

pll	PLL control name (see clock_pll_t enumeration)
bypass	Bypass the PLL. true: Bypass the PLL. false:Not bypass the PLL.

CLOCK_SwitchOsc()

void CLOCK_SwitchOsc

(

clock_osc_t

osc

)

Switch the OSC.

This function switches the OSC source for SoC.

Parameters

osc	OSC source to switch to.

brief Switch the OSC.

This function switches the OSC source for SoC.

param osc OSC source to switch to.

Variable Documentation

clockOff

bool _clock_group_config::clockOff

Turn off the clock.

denominator [1/2]

uint32_t _clock_audio_pll_config::denominator

30 bit denominator of fractional loop divider

denominator [2/2]

uint32_t _clock_audio_pll_gpc_config::denominator

30 bit denominator of fractional loop divider

div [1/2]

uint8_t _clock_root_config_t::div

it's the actual divider

div [2/2]

uint8_t _clock_root_setpoint_config_t::div

it's the actual divider

div0

uint8_t _clock_group_config::div0

Divide root clock by div0 + 1, valid range: 0 ~ 15.

enableClkOutput

bool _clock_enet_pll_config::enableClkOutput

Power on and enable PLL clock output for ENET0 (ref_enetpll0).

enableClkOutput1

bool _clock_enet_pll_config::enableClkOutput1

Power on and enable PLL clock output for ENET1 (ref_enetpll1).

enableClkOutput25M

bool _clock_enet_pll_config::enableClkOutput25M

Power on and enable PLL clock output for ENET1 (ref_enetpll1).

Power on and enable PLL clock output for ENET2 (ref_enetpll2).

g_rtcXtalFreq

volatile uint32_t g_rtcXtalFreq

extern

External RTC XTAL (32K OSC) clock frequency.

The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetRtcXtalFreq to set the value in to clock driver.

g_xtalFreq

volatile uint32_t g_xtalFreq

extern

External XTAL (24M OSC/SYSOSC) clock frequency.

The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 24MHz,

CLOCK_InitExternalClk(false);
CLOCK_SetXtalFreq(240000000);

grade

uint8_t _clock_root_setpoint_config_t::grade

Indicate speed grade for each SetPoint

loopDivider [1/5]

uint32_t _clock_arm_pll_config::loopDivider

PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2.

PLL loop divider. Valid range: 104-208.

loopDivider [2/5]

uint8_t _clock_usb_pll_config::loopDivider

PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22

loopDivider [3/5]

uint8_t _clock_audio_pll_config::loopDivider

PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

loopDivider [4/5]

uint8_t _clock_enet_pll_config::loopDivider

Controls the frequency of the ENET0 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

loopDivider [5/5]

uint8_t _clock_audio_pll_gpc_config::loopDivider

PLL loop divider.

loopDivider1

uint8_t _clock_enet_pll_config::loopDivider1

Controls the frequency of the ENET1 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

mfd

uint32_t _clock_sys_pll2_config::mfd

Denominator of spread spectrum

mux [1/2]

uint8_t _clock_root_config_t::mux

See clock_root_mux_source_t for details.

mux [2/2]

uint8_t _clock_root_setpoint_config_t::mux

See clock_root_mux_source_t for details.

numerator [1/2]

uint32_t _clock_audio_pll_config::numerator

30 bit numerator of fractional loop divider.

numerator [2/2]

uint32_t _clock_audio_pll_gpc_config::numerator

30 bit numerator of fractional loop divider.

pllDiv2En

bool _clock_sys_pll1_config::pllDiv2En

Enable Sys Pll1 divide-by-2 clock or not.

pllDiv5En

bool _clock_sys_pll1_config::pllDiv5En

Enable Sys Pll1 divide-by-5 clock or not.

postDivider [1/2]

uint8_t _clock_audio_pll_config::postDivider

Divider after the PLL, should only be 1, 2, 4, 8, 16.

Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.

postDivider [2/2]

clock_pll_post_div_t _clock_arm_pll_config::postDivider

Post divider.

resetDiv

uint16_t _clock_group_config::resetDiv

resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255.

src [1/2]

uint8_t _clock_usb_pll_config::src

Pll clock source, reference _clock_pll_clk_src

src [2/2]

uint8_t _clock_enet_pll_config::src

Pll clock source, reference _clock_pll_clk_src

ss [1/4]

clock_pll_ss_config_t* _clock_sys_pll2_config::ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

ss [2/4]

clock_pll_ss_config_t* _clock_sys_pll1_config::ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

ss [3/4]

clock_pll_ss_config_t* _clock_audio_pll_config::ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

ss [4/4]

clock_pll_ss_config_t* _clock_audio_pll_gpc_config::ss

Spread spectrum parameter, it can be NULL, if ssEnable is set to false

ssEnable [1/4]

bool _clock_sys_pll2_config::ssEnable

Enable spread spectrum flag

ssEnable [2/4]

bool _clock_sys_pll1_config::ssEnable

Enable spread spectrum flag

ssEnable [3/4]

bool _clock_audio_pll_config::ssEnable

Enable spread spectrum flag

ssEnable [4/4]

bool _clock_audio_pll_gpc_config::ssEnable

Enable spread spectrum flag

step

uint16_t _clock_pll_ss_config::step

Spread spectrum step value to get frequency change step.

stop

uint16_t _clock_pll_ss_config::stop

Spread spectrum stop value to get frequency change.