RTEMS 6.1-rc2
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Data Structures | Macros
fsl_clock.h File Reference
Clock
#include "fsl_common.h"

Go to the source code of this file.

Data Structures

struct  _clock_arm_pll_config
 PLL configuration for ARM. More...
 
struct  _clock_usb_pll_config
 PLL configuration for USB. More...
 
struct  _clock_sys_pll_config
 PLL configuration for System. More...
 
struct  _clock_audio_pll_config
 PLL configuration for AUDIO and VIDEO. More...
 
struct  _clock_video_pll_config
 PLL configuration for AUDIO and VIDEO. More...
 
struct  _clock_enet_pll_config
 PLL configuration for ENET. More...
 

Macros

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0
 Configure whether driver controls clock.
 

Functions

OSC operations
void CLOCK_InitExternalClk (bool bypassXtalOsc)
 Initialize the external 24MHz clock.
 
void CLOCK_DeinitExternalClk (void)
 Deinitialize the external 24MHz clock.
 
void CLOCK_SwitchOsc (clock_osc_t osc)
 Switch the OSC.
 
void CLOCK_InitRcOsc24M (void)
 Initialize the RC oscillator 24MHz clock.
 
void CLOCK_DeinitRcOsc24M (void)
 Power down the RCOSC 24M clock.
 
bool CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
 Enable USB HS clock.
 
bool CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
 Enable USB HS clock.
 
PLL/PFD operations
void CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
 Initialize the ARM PLL.
 
void CLOCK_DeinitArmPll (void)
 De-initialize the ARM PLL.
 
void CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
 Initialize the System PLL.
 
void CLOCK_DeinitSysPll (void)
 De-initialize the System PLL.
 
void CLOCK_InitUsb1Pll (const clock_usb_pll_config_t *config)
 Initialize the USB1 PLL.
 
void CLOCK_DeinitUsb1Pll (void)
 Deinitialize the USB1 PLL.
 
void CLOCK_InitUsb2Pll (const clock_usb_pll_config_t *config)
 Initialize the USB2 PLL.
 
void CLOCK_DeinitUsb2Pll (void)
 Deinitialize the USB2 PLL.
 
void CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
 Initializes the Audio PLL.
 
void CLOCK_DeinitAudioPll (void)
 De-initialize the Audio PLL.
 
void CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
 Initialize the video PLL.
 
void CLOCK_DeinitVideoPll (void)
 De-initialize the Video PLL.
 
void CLOCK_InitEnetPll (const clock_enet_pll_config_t *config)
 Initialize the ENET PLL.
 
void CLOCK_DeinitEnetPll (void)
 Deinitialize the ENET PLL.
 
uint32_t CLOCK_GetPllFreq (clock_pll_t pll)
 Get current PLL output frequency.
 
void CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t pfdFrac)
 Initialize the System PLL PFD.
 
void CLOCK_DeinitSysPfd (clock_pfd_t pfd)
 De-initialize the System PLL PFD.
 
bool CLOCK_IsSysPfdEnabled (clock_pfd_t pfd)
 Check if Sys PFD is enabled.
 
void CLOCK_InitUsb1Pfd (clock_pfd_t pfd, uint8_t pfdFrac)
 Initialize the USB1 PLL PFD.
 
void CLOCK_DeinitUsb1Pfd (clock_pfd_t pfd)
 De-initialize the USB1 PLL PFD.
 
bool CLOCK_IsUsb1PfdEnabled (clock_pfd_t pfd)
 Check if Usb1 PFD is enabled.
 
uint32_t CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
 Get current System PLL PFD output frequency.
 
uint32_t CLOCK_GetUsb1PfdFreq (clock_pfd_t pfd)
 Get current USB1 PLL PFD output frequency.
 
bool CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
 Enable USB HS PHY PLL clock.
 
void CLOCK_DisableUsbhs0PhyPllClock (void)
 Disable USB HS PHY PLL clock.
 
bool CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
 Enable USB HS PHY PLL clock.
 
void CLOCK_DisableUsbhs1PhyPllClock (void)
 Disable USB HS PHY PLL clock.
 
Clock Output Inferfaces
void CLOCK_SetClockOutput1 (clock_output1_selection_t selection, clock_output_divider_t divider)
 Set the clock source and the divider of the clock output1.
 
void CLOCK_SetClockOutput2 (clock_output2_selection_t selection, clock_output_divider_t divider)
 Set the clock source and the divider of the clock output2.
 
uint32_t CLOCK_GetClockOutCLKO1Freq (void)
 Get the frequency of clock output1 clock signal.
 
uint32_t CLOCK_GetClockOutClkO2Freq (void)
 Get the frequency of clock output2 clock signal.
 

Driver version

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 5, 1))
 CLOCK driver version 2.5.1.
 
#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY   (600000000UL)
 
#define CCM_ANALOG_PLL_BYPASS_SHIFT   (16U)
 
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK   (0xC000U)
 
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT   (14U)
 
#define CCSR_OFFSET   0x0C
 CCM registers offset.
 
#define CBCDR_OFFSET   0x14
 
#define CBCMR_OFFSET   0x18
 
#define CSCMR1_OFFSET   0x1C
 
#define CSCMR2_OFFSET   0x20
 
#define CSCDR1_OFFSET   0x24
 
#define CDCDR_OFFSET   0x30
 
#define CSCDR2_OFFSET   0x38
 
#define CSCDR3_OFFSET   0x3C
 
#define CACRR_OFFSET   0x10
 
#define CS1CDR_OFFSET   0x28
 
#define CS2CDR_OFFSET   0x2C
 
#define PLL_ARM_OFFSET   0x00
 CCM Analog registers offset.
 
#define PLL_SYS_OFFSET   0x30
 
#define PLL_USB1_OFFSET   0x10
 
#define PLL_AUDIO_OFFSET   0x70
 
#define PLL_VIDEO_OFFSET   0xA0
 
#define PLL_ENET_OFFSET   0xE0
 
#define PLL_USB2_OFFSET   0x20
 
#define CCM_TUPLE(reg, shift, mask, busyShift)    (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
 
#define CCM_TUPLE_REG(base, tuple)   (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
 
#define CCM_TUPLE_SHIFT(tuple)   ((((uint32_t)tuple) >> 8U) & 0x1FU)
 
#define CCM_TUPLE_MASK(tuple)    ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
 
#define CCM_TUPLE_BUSY_SHIFT(tuple)   ((((uint32_t)tuple) >> 26U) & 0x3FU)
 
#define CCM_NO_BUSY_WAIT   (0x20U)
 
#define CCM_ANALOG_TUPLE(reg, shift)   ((((reg)&0xFFFU) << 16U) | (shift))
 CCM ANALOG tuple macros to map corresponding registers and bit fields.
 
#define CCM_ANALOG_TUPLE_SHIFT(tuple)   (((uint32_t)tuple) & 0x1FU)
 
#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)    (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
 
#define CCM_ANALOG_TUPLE_REG(base, tuple)   CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
 
#define CLKPN_FREQ   0U
 clock1PN frequency.
 
#define CLOCK_SetXtal0Freq   CLOCK_SetXtalFreq
 
#define CLOCK_SetXtal32Freq   CLOCK_SetRtcXtalFreq
 
#define ADC_CLOCKS
 Clock ip name array for ADC.
 
#define AOI_CLOCKS
 Clock ip name array for AOI.
 
#define BEE_CLOCKS
 Clock ip name array for BEE.
 
#define CMP_CLOCKS
 Clock ip name array for CMP.
 
#define CSI_CLOCKS
 Clock ip name array for CSI.
 
#define DCDC_CLOCKS
 Clock ip name array for DCDC.
 
#define DCP_CLOCKS
 Clock ip name array for DCP.
 
#define DMAMUX_CLOCKS
 Clock ip name array for DMAMUX_CLOCKS.
 
#define EDMA_CLOCKS
 Clock ip name array for DMA.
 
#define ENC_CLOCKS
 Clock ip name array for ENC.
 
#define ENET_CLOCKS
 Clock ip name array for ENET.
 
#define EWM_CLOCKS
 Clock ip name array for EWM.
 
#define FLEXCAN_CLOCKS
 Clock ip name array for FLEXCAN.
 
#define FLEXCAN_PERIPH_CLOCKS
 Clock ip name array for FLEXCAN Peripheral clock.
 
#define FLEXIO_CLOCKS
 Clock ip name array for FLEXIO.
 
#define FLEXRAM_CLOCKS
 Clock ip name array for FLEXRAM.
 
#define FLEXSPI_CLOCKS
 Clock ip name array for FLEXSPI.
 
#define FLEXSPI_EXSC_CLOCKS
 Clock ip name array for FLEXSPI EXSC.
 
#define GPIO_CLOCKS
 Clock ip name array for GPIO.
 
#define GPT_CLOCKS
 Clock ip name array for GPT.
 
#define KPP_CLOCKS
 Clock ip name array for KPP.
 
#define LCDIF_CLOCKS
 Clock ip name array for LCDIF.
 
#define LCDIF_PERIPH_CLOCKS
 Clock ip name array for LCDIF PIXEL.
 
#define LPI2C_CLOCKS
 Clock ip name array for LPI2C.
 
#define LPSPI_CLOCKS
 Clock ip name array for LPSPI.
 
#define LPUART_CLOCKS
 Clock ip name array for LPUART.
 
#define MQS_CLOCKS
 Clock ip name array for MQS.
 
#define OCRAM_EXSC_CLOCKS
 Clock ip name array for OCRAM EXSC.
 
#define PIT_CLOCKS
 Clock ip name array for PIT.
 
#define PWM_CLOCKS
 Clock ip name array for PWM.
 
#define PXP_CLOCKS
 Clock ip name array for PXP.
 
#define RTWDOG_CLOCKS
 Clock ip name array for RTWDOG.
 
#define SAI_CLOCKS
 Clock ip name array for SAI.
 
#define SEMC_CLOCKS
 Clock ip name array for SEMC.
 
#define SEMC_EXSC_CLOCKS
 Clock ip name array for SEMC EXSC.
 
#define TMR_CLOCKS
 Clock ip name array for QTIMER.
 
#define TRNG_CLOCKS
 Clock ip name array for TRNG.
 
#define TSC_CLOCKS
 Clock ip name array for TSC.
 
#define WDOG_CLOCKS
 Clock ip name array for WDOG.
 
#define USDHC_CLOCKS
 Clock ip name array for USDHC.
 
#define SPDIF_CLOCKS
 Clock ip name array for SPDIF.
 
#define XBARA_CLOCKS
 Clock ip name array for XBARA.
 
#define XBARB_CLOCKS
 Clock ip name array for XBARB.
 
#define CLOCK_SOURCE_NONE   (0xFFU)
 
#define CLOCK_ROOT_SOUCE
 
#define CLOCK_ROOT_MUX_TUPLE
 
#define CLOCK_ROOT_NONE_PRE_DIV   0UL
 
#define CLOCK_ROOT_DIV_TUPLE
 
#define kCLOCK_CoreSysClk   kCLOCK_CpuClk
 
#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq
 
enum  _clock_name {
  kCLOCK_CpuClk = 0x0U , kCLOCK_AhbClk = 0x1U , kCLOCK_SemcClk = 0x2U , kCLOCK_IpgClk = 0x3U ,
  kCLOCK_PerClk = 0x4U , kCLOCK_OscClk = 0x5U , kCLOCK_RtcClk = 0x6U , kCLOCK_ArmPllClk = 0x7U ,
  kCLOCK_Usb1PllClk = 0x8U , kCLOCK_Usb1PllPfd0Clk = 0x9U , kCLOCK_Usb1PllPfd1Clk = 0xAU , kCLOCK_Usb1PllPfd2Clk = 0xBU ,
  kCLOCK_Usb1PllPfd3Clk = 0xCU , kCLOCK_Usb1SwClk = 0x17U , kCLOCK_Usb1Sw120MClk = 0x18U , kCLOCK_Usb1Sw60MClk = 0x19U ,
  kCLOCK_Usb1Sw80MClk = 0x1AU , kCLOCK_Usb2PllClk = 0xDU , kCLOCK_SysPllClk = 0xEU , kCLOCK_SysPllPfd0Clk = 0xFU ,
  kCLOCK_SysPllPfd1Clk = 0x10U , kCLOCK_SysPllPfd2Clk = 0x11U , kCLOCK_SysPllPfd3Clk = 0x12U , kCLOCK_EnetPll0Clk = 0x13U ,
  kCLOCK_EnetPll1Clk = 0x14U , kCLOCK_AudioPllClk = 0x15U , kCLOCK_VideoPllClk = 0x16U , kCLOCK_NoneName = CLOCK_SOURCE_NONE ,
  kCLOCK_OscRc16M = 0 , kCLOCK_OscRc48M = 1 , kCLOCK_OscRc48MDiv2 = 2 , kCLOCK_OscRc400M = 3 ,
  kCLOCK_Osc24M = 4 , kCLOCK_Osc24MOut = 5 , kCLOCK_ArmPll = 6 , kCLOCK_ArmPllOut = 7 ,
  kCLOCK_SysPll2 = 8 , kCLOCK_SysPll2Out = 9 , kCLOCK_SysPll2Pfd0 = 10 , kCLOCK_SysPll2Pfd1 = 11 ,
  kCLOCK_SysPll2Pfd2 = 12 , kCLOCK_SysPll2Pfd3 = 13 , kCLOCK_SysPll3 = 14 , kCLOCK_SysPll3Out = 15 ,
  kCLOCK_SysPll3Div2 = 16 , kCLOCK_SysPll3Pfd0 = 17 , kCLOCK_SysPll3Pfd1 = 18 , kCLOCK_SysPll3Pfd2 = 19 ,
  kCLOCK_SysPll3Pfd3 = 20 , kCLOCK_SysPll1 = 21 , kCLOCK_SysPll1Out = 22 , kCLOCK_SysPll1Div2 = 23 ,
  kCLOCK_SysPll1Div5 = 24 , kCLOCK_AudioPll = 25 , kCLOCK_AudioPllOut = 26 , kCLOCK_VideoPll = 27 ,
  kCLOCK_VideoPllOut = 28 , kCLOCK_CpuClk , kCLOCK_CoreSysClk , kCLOCK_Reserved = 0xFFU
}
 Clock name used to get clock frequency. More...
 
enum  _clock_ip_name {
  kCLOCK_IpInvalid = -1 , kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT , kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT , kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT ,
  kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT , kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT , kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT , kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT ,
  kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT , kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT , kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT , kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT ,
  kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT , kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT , kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT , kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT ,
  kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT , kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT , kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT , kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT ,
  kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT , kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT , kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT , kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT ,
  kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT , kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT , kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT , kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT ,
  kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT , kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT , kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT , kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT ,
  kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT , kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT , kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT , kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT ,
  kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT , kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT , kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT , kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT ,
  kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT , kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT , kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT , kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT ,
  kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT , kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT , kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT , kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT ,
  kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT , kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT , kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT , kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT ,
  kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT , kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT , kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT , kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT ,
  kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT , kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT , kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT , kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT ,
  kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT , kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT , kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT , kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT ,
  kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT , kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT , kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT , kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT ,
  kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT , kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT , kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT , kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT ,
  kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT , kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT , kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT , kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT ,
  kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT , kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT , kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT , kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT ,
  kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT , kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT , kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT , kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT ,
  kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT , kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT , kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT , kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT ,
  kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT , kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT , kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT , kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT ,
  kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT , kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT , kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT , kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT ,
  kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT , kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT , kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT , kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT ,
  kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT , kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT , kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT , kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT ,
  kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT , kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT , kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT , kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT ,
  kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT , kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT , kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT , kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT ,
  kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT
}
 CCM CCGR gate control for each module independently. More...
 
enum  _clock_osc { kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U , kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U }
 OSC 24M sorce select. More...
 
enum  _clock_gate_value {
  kCLOCK_ClockNotNeeded = 0U , kCLOCK_ClockNeededRun = 1U , kCLOCK_ClockNeededRunWait = 3U , kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK ,
  kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK
}
 Clock gate value. More...
 
enum  _clock_mode_t {
  kCLOCK_ModeRun = 0U , kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U , kCLOCK_ModeRun = 0U ,
  kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U
}
 System clock mode. More...
 
enum  _clock_mux {
  kCLOCK_Pll3SwMux , kCLOCK_PeriphMux , kCLOCK_SemcAltMux , kCLOCK_SemcMux ,
  kCLOCK_PrePeriphMux , kCLOCK_TraceMux , kCLOCK_PeriphClk2Mux , kCLOCK_LpspiMux ,
  kCLOCK_FlexspiMux , kCLOCK_Usdhc2Mux , kCLOCK_Usdhc1Mux , kCLOCK_Sai3Mux ,
  kCLOCK_Sai2Mux , kCLOCK_Sai1Mux , kCLOCK_PerclkMux , kCLOCK_Flexio2Mux ,
  kCLOCK_CanMux , kCLOCK_UartMux , kCLOCK_SpdifMux , kCLOCK_Flexio1Mux ,
  kCLOCK_Lpi2cMux , kCLOCK_LcdifPreMux , kCLOCK_CsiMux
}
 MUX control names for clock mux setting. More...
 
enum  _clock_div {
  kCLOCK_ArmDiv , kCLOCK_PeriphClk2Div , kCLOCK_SemcDiv , kCLOCK_AhbDiv ,
  kCLOCK_IpgDiv , kCLOCK_LpspiDiv , kCLOCK_LcdifDiv , kCLOCK_FlexspiDiv ,
  kCLOCK_PerclkDiv , kCLOCK_CanDiv , kCLOCK_TraceDiv , kCLOCK_Usdhc2Div ,
  kCLOCK_Usdhc1Div , kCLOCK_UartDiv , kCLOCK_Flexio2Div , kCLOCK_Sai3PreDiv ,
  kCLOCK_Sai3Div , kCLOCK_Flexio2PreDiv , kCLOCK_Sai1PreDiv , kCLOCK_Sai1Div ,
  kCLOCK_Sai2PreDiv , kCLOCK_Sai2Div , kCLOCK_Spdif0PreDiv , kCLOCK_Spdif0Div ,
  kCLOCK_Flexio1PreDiv , kCLOCK_Flexio1Div , kCLOCK_Lpi2cDiv , kCLOCK_LcdifPreDiv ,
  kCLOCK_CsiDiv , kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV
}
 DIV control names for clock div setting. More...
 
enum  _clock_div_value {
  kCLOCK_ArmDivBy1 = 0 , kCLOCK_ArmDivBy2 = 1 , kCLOCK_ArmDivBy3 = 2 , kCLOCK_ArmDivBy4 = 3 ,
  kCLOCK_ArmDivBy5 = 4 , kCLOCK_ArmDivBy6 = 5 , kCLOCK_ArmDivBy7 = 6 , kCLOCK_ArmDivBy8 = 7 ,
  kCLOCK_PeriphClk2DivBy1 = 0 , kCLOCK_PeriphClk2DivBy2 = 1 , kCLOCK_PeriphClk2DivBy3 = 2 , kCLOCK_PeriphClk2DivBy4 = 3 ,
  kCLOCK_PeriphClk2DivBy5 = 4 , kCLOCK_PeriphClk2DivBy6 = 5 , kCLOCK_PeriphClk2DivBy7 = 6 , kCLOCK_PeriphClk2DivBy8 = 7 ,
  kCLOCK_SemcDivBy1 = 0 , kCLOCK_SemcDivBy2 = 1 , kCLOCK_SemcDivBy3 = 2 , kCLOCK_SemcDivBy4 = 3 ,
  kCLOCK_SemcDivBy5 = 4 , kCLOCK_SemcDivBy6 = 5 , kCLOCK_SemcDivBy7 = 6 , kCLOCK_SemcDivBy8 = 7 ,
  kCLOCK_AhbDivBy1 = 0 , kCLOCK_AhbDivBy2 = 1 , kCLOCK_AhbDivBy3 = 2 , kCLOCK_AhbDivBy4 = 3 ,
  kCLOCK_AhbDivBy5 = 4 , kCLOCK_AhbDivBy6 = 5 , kCLOCK_AhbDivBy7 = 6 , kCLOCK_AhbDivBy8 = 7 ,
  kCLOCK_IpgDivBy1 = 0 , kCLOCK_IpgDivBy2 = 1 , kCLOCK_IpgDivBy3 = 2 , kCLOCK_IpgDivBy4 = 3 ,
  kCLOCK_LpspiDivBy1 = 0 , kCLOCK_LpspiDivBy2 = 1 , kCLOCK_LpspiDivBy3 = 2 , kCLOCK_LpspiDivBy4 = 3 ,
  kCLOCK_LpspiDivBy5 = 4 , kCLOCK_LpspiDivBy6 = 5 , kCLOCK_LpspiDivBy7 = 6 , kCLOCK_LpspiDivBy8 = 7 ,
  kCLOCK_LcdifDivBy1 = 0 , kCLOCK_LcdifDivBy2 = 1 , kCLOCK_LcdifDivBy3 = 2 , kCLOCK_LcdifDivBy4 = 3 ,
  kCLOCK_LcdifDivBy5 = 4 , kCLOCK_LcdifDivBy6 = 5 , kCLOCK_LcdifDivBy7 = 6 , kCLOCK_LcdifDivBy8 = 7 ,
  kCLOCK_FlexspiDivBy1 = 0 , kCLOCK_FlexspiDivBy2 = 1 , kCLOCK_FlexspiDivBy3 = 2 , kCLOCK_FlexspiDivBy4 = 3 ,
  kCLOCK_FlexspiDivBy5 = 4 , kCLOCK_FlexspiDivBy6 = 5 , kCLOCK_FlexspiDivBy7 = 6 , kCLOCK_FlexspiDivBy8 = 7 ,
  kCLOCK_TraceDivBy1 = 0 , kCLOCK_TraceDivBy2 = 1 , kCLOCK_TraceDivBy3 = 2 , kCLOCK_TraceDivBy4 = 3 ,
  kCLOCK_Usdhc2DivBy1 = 0 , kCLOCK_Usdhc2DivBy2 = 1 , kCLOCK_Usdhc2DivBy3 = 2 , kCLOCK_Usdhc2DivBy4 = 3 ,
  kCLOCK_Usdhc2DivBy5 = 4 , kCLOCK_Usdhc2DivBy6 = 5 , kCLOCK_Usdhc2DivBy7 = 6 , kCLOCK_Usdhc2DivBy8 = 7 ,
  kCLOCK_Usdhc1DivBy1 = 0 , kCLOCK_Usdhc1DivBy2 = 1 , kCLOCK_Usdhc1DivBy3 = 2 , kCLOCK_Usdhc1DivBy4 = 3 ,
  kCLOCK_Usdhc1DivBy5 = 4 , kCLOCK_Usdhc1DivBy6 = 5 , kCLOCK_Usdhc1DivBy7 = 6 , kCLOCK_Usdhc1DivBy8 = 7 ,
  kCLOCK_Flexio2DivBy1 = 0 , kCLOCK_Flexio2DivBy2 = 1 , kCLOCK_Flexio2DivBy3 = 2 , kCLOCK_Flexio2DivBy4 = 3 ,
  kCLOCK_Flexio2DivBy5 = 4 , kCLOCK_Flexio2DivBy6 = 5 , kCLOCK_Flexio2DivBy7 = 6 , kCLOCK_Flexio2DivBy8 = 7 ,
  kCLOCK_Sai3PreDivBy1 = 0 , kCLOCK_Sai3PreDivBy2 = 1 , kCLOCK_Sai3PreDivBy3 = 2 , kCLOCK_Sai3PreDivBy4 = 3 ,
  kCLOCK_Sai3PreDivBy5 = 4 , kCLOCK_Sai3PreDivBy6 = 5 , kCLOCK_Sai3PreDivBy7 = 6 , kCLOCK_Sai3PreDivBy8 = 7 ,
  kCLOCK_Flexio2PreDivBy1 = 0 , kCLOCK_Flexio2PreDivBy2 = 1 , kCLOCK_Flexio2PreDivBy3 = 2 , kCLOCK_Flexio2PreDivBy4 = 3 ,
  kCLOCK_Flexio2PreDivBy5 = 4 , kCLOCK_Flexio2PreDivBy6 = 5 , kCLOCK_Flexio2PreDivBy7 = 6 , kCLOCK_Flexio2PreDivBy8 = 7 ,
  kCLOCK_Sai1PreDivBy1 = 0 , kCLOCK_Sai1PreDivBy2 = 1 , kCLOCK_Sai1PreDivBy3 = 2 , kCLOCK_Sai1PreDivBy4 = 3 ,
  kCLOCK_Sai1PreDivBy5 = 4 , kCLOCK_Sai1PreDivBy6 = 5 , kCLOCK_Sai1PreDivBy7 = 6 , kCLOCK_Sai1PreDivBy8 = 7 ,
  kCLOCK_Sai2PreDivBy1 = 0 , kCLOCK_Sai2PreDivBy2 = 1 , kCLOCK_Sai2PreDivBy3 = 2 , kCLOCK_Sai2PreDivBy4 = 3 ,
  kCLOCK_Sai2PreDivBy5 = 4 , kCLOCK_Sai2PreDivBy6 = 5 , kCLOCK_Sai2PreDivBy7 = 6 , kCLOCK_Sai2PreDivBy8 = 7 ,
  kCLOCK_Spdif0PreDivBy1 = 0 , kCLOCK_Spdif0PreDivBy2 = 1 , kCLOCK_Spdif0PreDivBy3 = 2 , kCLOCK_Spdif0PreDivBy4 = 3 ,
  kCLOCK_Spdif0PreDivBy5 = 4 , kCLOCK_Spdif0PreDivBy6 = 5 , kCLOCK_Spdif0PreDivBy7 = 6 , kCLOCK_Spdif0PreDivBy8 = 7 ,
  kCLOCK_Spdif0DivBy1 = 0 , kCLOCK_Spdif0DivBy2 = 1 , kCLOCK_Spdif0DivBy3 = 2 , kCLOCK_Spdif0DivBy4 = 3 ,
  kCLOCK_Spdif0DivBy5 = 4 , kCLOCK_Spdif0DivBy6 = 5 , kCLOCK_Spdif0DivBy7 = 6 , kCLOCK_Spdif0DivBy8 = 7 ,
  kCLOCK_Flexio1PreDivBy1 = 0 , kCLOCK_Flexio1PreDivBy2 = 1 , kCLOCK_Flexio1PreDivBy3 = 2 , kCLOCK_Flexio1PreDivBy4 = 3 ,
  kCLOCK_Flexio1PreDivBy5 = 4 , kCLOCK_Flexio1PreDivBy6 = 5 , kCLOCK_Flexio1PreDivBy7 = 6 , kCLOCK_Flexio1PreDivBy8 = 7 ,
  kCLOCK_Flexio1DivBy1 = 0 , kCLOCK_Flexio1DivBy2 = 1 , kCLOCK_Flexio1DivBy3 = 2 , kCLOCK_Flexio1DivBy4 = 3 ,
  kCLOCK_Flexio1DivBy5 = 4 , kCLOCK_Flexio1DivBy6 = 5 , kCLOCK_Flexio1DivBy7 = 6 , kCLOCK_Flexio1DivBy8 = 7 ,
  kCLOCK_LcdifPreDivBy1 = 0 , kCLOCK_LcdifPreDivBy2 = 1 , kCLOCK_LcdifPreDivBy3 = 2 , kCLOCK_LcdifPreDivBy4 = 3 ,
  kCLOCK_LcdifPreDivBy5 = 4 , kCLOCK_LcdifPreDivBy6 = 5 , kCLOCK_LcdifPreDivBy7 = 6 , kCLOCK_LcdifPreDivBy8 = 7 ,
  kCLOCK_CsiDivBy1 = 0 , kCLOCK_CsiDivBy2 = 1 , kCLOCK_CsiDivBy3 = 2 , kCLOCK_CsiDivBy4 = 3 ,
  kCLOCK_CsiDivBy5 = 4 , kCLOCK_CsiDivBy6 = 5 , kCLOCK_CsiDivBy7 = 6 , kCLOCK_CsiDivBy8 = 7 ,
  kCLOCK_MiscDivBy1 = 0 , kCLOCK_MiscDivBy2 = 1 , kCLOCK_MiscDivBy3 = 2 , kCLOCK_MiscDivBy4 = 3 ,
  kCLOCK_MiscDivBy5 = 4 , kCLOCK_MiscDivBy6 = 5 , kCLOCK_MiscDivBy7 = 6 , kCLOCK_MiscDivBy8 = 7 ,
  kCLOCK_MiscDivBy9 = 8 , kCLOCK_MiscDivBy10 = 9 , kCLOCK_MiscDivBy11 = 10 , kCLOCK_MiscDivBy12 = 11 ,
  kCLOCK_MiscDivBy13 = 12 , kCLOCK_MiscDivBy14 = 13 , kCLOCK_MiscDivBy15 = 14 , kCLOCK_MiscDivBy16 = 15 ,
  kCLOCK_MiscDivBy17 = 16 , kCLOCK_MiscDivBy18 = 17 , kCLOCK_MiscDivBy19 = 18 , kCLOCK_MiscDivBy20 = 19 ,
  kCLOCK_MiscDivBy21 = 20 , kCLOCK_MiscDivBy22 = 21 , kCLOCK_MiscDivBy23 = 22 , kCLOCK_MiscDivBy24 = 23 ,
  kCLOCK_MiscDivBy25 = 24 , kCLOCK_MiscDivBy26 = 25 , kCLOCK_MiscDivBy27 = 26 , kCLOCK_MiscDivBy28 = 27 ,
  kCLOCK_MiscDivBy29 = 28 , kCLOCK_MiscDivBy30 = 29 , kCLOCK_MiscDivBy31 = 30 , kCLOCK_MiscDivBy32 = 31 ,
  kCLOCK_MiscDivBy33 = 32 , kCLOCK_MiscDivBy34 = 33 , kCLOCK_MiscDivBy35 = 34 , kCLOCK_MiscDivBy36 = 35 ,
  kCLOCK_MiscDivBy37 = 36 , kCLOCK_MiscDivBy38 = 37 , kCLOCK_MiscDivBy39 = 38 , kCLOCK_MiscDivBy40 = 39 ,
  kCLOCK_MiscDivBy41 = 40 , kCLOCK_MiscDivBy42 = 41 , kCLOCK_MiscDivBy43 = 42 , kCLOCK_MiscDivBy44 = 43 ,
  kCLOCK_MiscDivBy45 = 44 , kCLOCK_MiscDivBy46 = 45 , kCLOCK_MiscDivBy47 = 46 , kCLOCK_MiscDivBy48 = 47 ,
  kCLOCK_MiscDivBy49 = 48 , kCLOCK_MiscDivBy50 = 49 , kCLOCK_MiscDivBy51 = 50 , kCLOCK_MiscDivBy52 = 51 ,
  kCLOCK_MiscDivBy53 = 52 , kCLOCK_MiscDivBy54 = 53 , kCLOCK_MiscDivBy55 = 54 , kCLOCK_MiscDivBy56 = 55 ,
  kCLOCK_MiscDivBy57 = 56 , kCLOCK_MiscDivBy58 = 57 , kCLOCK_MiscDivBy59 = 58 , kCLOCK_MiscDivBy60 = 59 ,
  kCLOCK_MiscDivBy61 = 60 , kCLOCK_MiscDivBy62 = 61 , kCLOCK_MiscDivBy63 = 62 , kCLOCK_MiscDivBy64 = 63
}
 Clock divider value. More...
 
enum  _clock_usb_src { kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU , kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
 USB clock source definition. More...
 
enum  _clock_usb_phy_src { kCLOCK_Usbphy480M = 0 , kCLOCK_Usbphy480M = 0 }
 Source of the USB HS PHY. More...
 
enum  _clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U , kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U }
 PLL clock source, bypass cloco source also. More...
 
enum  _clock_pll {
  kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT) , kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT) , kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT) , kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT) ,
  kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT) , kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT) , kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT) , kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT) ,
  kCLOCK_PllArm , kCLOCK_PllSys1 , kCLOCK_PllSys2 , kCLOCK_PllSys3 ,
  kCLOCK_PllAudio , kCLOCK_PllVideo , kCLOCK_PllInvalid = -1
}
 PLL name. More...
 
enum  _clock_pfd {
  kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U ,
  kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U
}
 PLL PFD name. More...
 
enum  _clock_output1_selection {
  kCLOCK_OutputPllUsb1 = 0U , kCLOCK_OutputPllSys = 1U , kCLOCK_OutputPllVideo = 3U , kCLOCK_OutputSemcClk = 5U ,
  kCLOCK_OutputLcdifPixClk = 0xAU , kCLOCK_OutputAhbClk = 0xBU , kCLOCK_OutputIpgClk = 0xCU , kCLOCK_OutputPerClk = 0xDU ,
  kCLOCK_OutputCkilSyncClk = 0xEU , kCLOCK_OutputPll4MainClk = 0xFU , kCLOCK_DisableClockOutput1 = 0x10U
}
 The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on. More...
 
enum  _clock_output2_selection {
  kCLOCK_OutputUsdhc1Clk = 3U , kCLOCK_OutputLpi2cClk = 6U , kCLOCK_OutputCsiClk = 0xBU , kCLOCK_OutputOscClk = 0xEU ,
  kCLOCK_OutputUsdhc2Clk = 0x11U , kCLOCK_OutputSai1Clk = 0x12U , kCLOCK_OutputSai2Clk = 0x13U , kCLOCK_OutputSai3Clk = 0x14U ,
  kCLOCK_OutputCanClk = 0x17U , kCLOCK_OutputFlexspiClk = 0x1BU , kCLOCK_OutputUartClk = 0x1CU , kCLOCK_OutputSpdif0Clk = 0x1DU ,
  kCLOCK_DisableClockOutput2 = 0x1FU
}
 The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on. More...
 
enum  _clock_output_divider {
  kCLOCK_DivideBy1 = 0U , kCLOCK_DivideBy2 , kCLOCK_DivideBy3 , kCLOCK_DivideBy4 ,
  kCLOCK_DivideBy5 , kCLOCK_DivideBy6 , kCLOCK_DivideBy7 , kCLOCK_DivideBy8
}
 The enumerator of clock output's divider. More...
 
enum  _clock_root {
  kCLOCK_Usdhc1ClkRoot = 0U , kCLOCK_Usdhc2ClkRoot , kCLOCK_FlexspiClkRoot , kCLOCK_CsiClkRoot ,
  kCLOCK_LpspiClkRoot , kCLOCK_TraceClkRoot , kCLOCK_Sai1ClkRoot , kCLOCK_Sai2ClkRoot ,
  kCLOCK_Sai3ClkRoot , kCLOCK_Lpi2cClkRoot , kCLOCK_CanClkRoot , kCLOCK_UartClkRoot ,
  kCLOCK_LcdifClkRoot , kCLOCK_SpdifClkRoot , kCLOCK_Flexio1ClkRoot , kCLOCK_Flexio2ClkRoot ,
  kCLOCK_Root_M7 = 0 , kCLOCK_Root_M4 = 1 , kCLOCK_Root_Bus = 2 , kCLOCK_Root_Bus_Lpsr = 3 ,
  kCLOCK_Root_Semc = 4 , kCLOCK_Root_Cssys = 5 , kCLOCK_Root_Cstrace = 6 , kCLOCK_Root_M4_Systick = 7 ,
  kCLOCK_Root_M7_Systick = 8 , kCLOCK_Root_Adc1 = 9 , kCLOCK_Root_Adc2 = 10 , kCLOCK_Root_Acmp = 11 ,
  kCLOCK_Root_Flexio1 = 12 , kCLOCK_Root_Flexio2 = 13 , kCLOCK_Root_Gpt1 = 14 , kCLOCK_Root_Gpt2 = 15 ,
  kCLOCK_Root_Gpt3 = 16 , kCLOCK_Root_Gpt4 = 17 , kCLOCK_Root_Gpt5 = 18 , kCLOCK_Root_Gpt6 = 19 ,
  kCLOCK_Root_Flexspi1 = 20 , kCLOCK_Root_Flexspi2 = 21 , kCLOCK_Root_Can1 = 22 , kCLOCK_Root_Can2 = 23 ,
  kCLOCK_Root_Can3 = 24 , kCLOCK_Root_Lpuart1 = 25 , kCLOCK_Root_Lpuart2 = 26 , kCLOCK_Root_Lpuart3 = 27 ,
  kCLOCK_Root_Lpuart4 = 28 , kCLOCK_Root_Lpuart5 = 29 , kCLOCK_Root_Lpuart6 = 30 , kCLOCK_Root_Lpuart7 = 31 ,
  kCLOCK_Root_Lpuart8 = 32 , kCLOCK_Root_Lpuart9 = 33 , kCLOCK_Root_Lpuart10 = 34 , kCLOCK_Root_Lpuart11 = 35 ,
  kCLOCK_Root_Lpuart12 = 36 , kCLOCK_Root_Lpi2c1 = 37 , kCLOCK_Root_Lpi2c2 = 38 , kCLOCK_Root_Lpi2c3 = 39 ,
  kCLOCK_Root_Lpi2c4 = 40 , kCLOCK_Root_Lpi2c5 = 41 , kCLOCK_Root_Lpi2c6 = 42 , kCLOCK_Root_Lpspi1 = 43 ,
  kCLOCK_Root_Lpspi2 = 44 , kCLOCK_Root_Lpspi3 = 45 , kCLOCK_Root_Lpspi4 = 46 , kCLOCK_Root_Lpspi5 = 47 ,
  kCLOCK_Root_Lpspi6 = 48 , kCLOCK_Root_Emv1 = 49 , kCLOCK_Root_Emv2 = 50 , kCLOCK_Root_Enet1 = 51 ,
  kCLOCK_Root_Enet2 = 52 , kCLOCK_Root_Enet_25m = 54 , kCLOCK_Root_Enet_Timer1 = 55 , kCLOCK_Root_Enet_Timer2 = 56 ,
  kCLOCK_Root_Usdhc1 = 58 , kCLOCK_Root_Usdhc2 = 59 , kCLOCK_Root_Asrc = 60 , kCLOCK_Root_Mqs = 61 ,
  kCLOCK_Root_Mic = 62 , kCLOCK_Root_Spdif = 63 , kCLOCK_Root_Sai1 = 64 , kCLOCK_Root_Sai2 = 65 ,
  kCLOCK_Root_Sai3 = 66 , kCLOCK_Root_Sai4 = 67 , kCLOCK_Root_Gc355 = 68 , kCLOCK_Root_Lcdif = 69 ,
  kCLOCK_Root_Lcdifv2 = 70 , kCLOCK_Root_Mipi_Ref = 71 , kCLOCK_Root_Mipi_Esc = 72 , kCLOCK_Root_Csi2 = 73 ,
  kCLOCK_Root_Csi2_Esc = 74 , kCLOCK_Root_Csi2_Ui = 75 , kCLOCK_Root_Csi = 76 , kCLOCK_Root_Cko1 = 77 ,
  kCLOCK_Root_Cko2 = 78
}
 The enumerator of clock root. More...
 
typedef enum _clock_name clock_name_t
 Clock name used to get clock frequency.
 
typedef enum _clock_ip_name clock_ip_name_t
 CCM CCGR gate control for each module independently.
 
typedef enum _clock_osc clock_osc_t
 OSC 24M sorce select.
 
typedef enum _clock_gate_value clock_gate_value_t
 Clock gate value.
 
typedef enum _clock_mode_t clock_mode_t
 System clock mode.
 
typedef enum _clock_mux clock_mux_t
 MUX control names for clock mux setting.
 
typedef enum _clock_div clock_div_t
 DIV control names for clock div setting.
 
typedef enum _clock_div_value clock_div_value_t
 Clock divider value.
 
typedef enum _clock_usb_src clock_usb_src_t
 USB clock source definition.
 
typedef enum _clock_usb_phy_src clock_usb_phy_src_t
 Source of the USB HS PHY.
 
typedef struct _clock_arm_pll_config clock_arm_pll_config_t
 PLL configuration for ARM.
 
typedef struct _clock_usb_pll_config clock_usb_pll_config_t
 PLL configuration for USB.
 
typedef struct _clock_sys_pll_config clock_sys_pll_config_t
 PLL configuration for System.
 
typedef struct _clock_audio_pll_config clock_audio_pll_config_t
 PLL configuration for AUDIO and VIDEO.
 
typedef struct _clock_video_pll_config clock_video_pll_config_t
 PLL configuration for AUDIO and VIDEO.
 
typedef struct _clock_enet_pll_config clock_enet_pll_config_t
 PLL configuration for ENET.
 
typedef enum _clock_pll clock_pll_t
 PLL name.
 
typedef enum _clock_pfd clock_pfd_t
 PLL PFD name.
 
typedef enum _clock_output1_selection clock_output1_selection_t
 The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
 
typedef enum _clock_output2_selection clock_output2_selection_t
 The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
 
typedef enum _clock_output_divider clock_output_divider_t
 The enumerator of clock output's divider.
 
typedef enum _clock_root clock_root_t
 The enumerator of clock root.
 
volatile uint32_t g_xtalFreq
 External XTAL (24M OSC/SYSOSC) clock frequency.
 
volatile uint32_t g_rtcXtalFreq
 External RTC XTAL (32K OSC) clock frequency.
 
uint32_t CLOCK_GetAhbFreq (void)
 Gets the AHB clock frequency.
 
uint32_t CLOCK_GetSemcFreq (void)
 Gets the SEMC clock frequency.
 
uint32_t CLOCK_GetIpgFreq (void)
 Gets the IPG clock frequency.
 
uint32_t CLOCK_GetPerClkFreq (void)
 Gets the PER clock frequency.
 
uint32_t CLOCK_GetFreq (clock_name_t name)
 Gets the clock frequency for a specific clock name.
 
uint32_t CLOCK_GetClockRootFreq (clock_root_t clockRoot)
 Gets the frequency of selected clock root.
 
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