RTEMS 6.1-rc2
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PLL configuration for AUDIO and VIDEO. More...
#include <fsl_clock.h>
Data Fields | |
uint8_t | loopDivider |
uint8_t | postDivider |
uint32_t | numerator |
uint32_t | denominator |
uint8_t | src |
PLL configuration for AUDIO and VIDEO.
uint32_t _clock_video_pll_config::denominator |
30 bit denominator of fractional loop divider
uint8_t _clock_video_pll_config::loopDivider |
PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
uint32_t _clock_video_pll_config::numerator |
30 bit numerator of fractional loop divider.
uint8_t _clock_video_pll_config::postDivider |
Divider after the PLL, should only be 1, 2, 4, 8, 16.
uint8_t _clock_video_pll_config::src |
Pll clock source, reference _clock_pll_clk_src