MIPS

MIPS Architecture Support. More...

Modules
	CPU Related Definitions
	RTEMS no cpu Build Information
	Register Structure

Data Structures
struct	Context_Control
	Thread register context. More...
struct	Context_Control_fp
	SPARC basic context. More...
struct	CPU_Interrupt_frame
	Interrupt stack frame (ISF). More...

Macros
#define	CPU_SIMPLE_VECTORED_INTERRUPTS   FALSE
#define	CPU_ISR_PASSES_FRAME_POINTER   TRUE
#define	CPU_HARDWARE_FP   FALSE
#define	CPU_ALL_TASKS_ARE_FP   CPU_HARDWARE_FP
#define	CPU_IDLE_TASK_IS_FP   FALSE
#define	CPU_USE_DEFERRED_FP_SWITCH   TRUE
#define	CPU_ENABLE_ROBUST_THREAD_DISPATCH   FALSE
#define	CPU_STACK_GROWS_UP   FALSE
#define	CPU_CACHE_LINE_BYTES   16
#define	CPU_STRUCTURE_ALIGNMENT   RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
#define	CPU_MODES_INTERRUPT_MASK   0x000000ff
#define	CPU_SIZEOF_POINTER   4
#define	CPU_MAXIMUM_PROCESSORS   32
#define	_CPU_Context_Get_SP(_context)    (uintptr_t) (_context)->sp
#define	CPU_CONTEXT_FP_SIZE   sizeof( Context_Control_fp )
#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   0
#define	CPU_STACK_MINIMUM_SIZE   (8 * 1024)
#define	CPU_ALIGNMENT   8
#define	CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
#define	CPU_STACK_ALIGNMENT   CPU_ALIGNMENT
#define	CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
#define	_CPU_ISR_Disable(_level)
#define	_CPU_ISR_Enable(_level)
#define	_CPU_ISR_Flash(_xlevel)
#define	_CPU_Context_Restart_self(_the_context)    _CPU_Context_restore( (_the_context) );
#define	_CPU_Context_Initialize_fp(_destination)
#define	CPU_USE_GENERIC_BITFIELD_CODE   TRUE
#define	CPU_USE_LIBC_INIT_FINI_ARRAY   FALSE
#define	CPU_swap_u16(value)    (((value&0xff) << 8) | ((value >> 8)&0xff))
#define	CPU_PER_CPU_CONTROL_SIZE   0
#define	CPU_THREAD_LOCAL_STORAGE_VARIANT   10

Typedefs
typedef CPU_Interrupt_frame	CPU_Exception_frame
typedef uint32_t	CPU_Counter_ticks
typedef uintptr_t	CPU_Uint32ptr

Functions
void	mips_vector_exceptions (CPU_Interrupt_frame *frame)
uint32_t	mips_interrupt_mask (void)
uint32_t	_CPU_ISR_Get_level (void)
void	_CPU_ISR_Set_level (uint32_t)
	Sets the hardware interrupt level by the level value.
void	_CPU_Context_Initialize (Context_Control *the_context, uintptr_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
void	mips_break (int error)
void	_CPU_Initialize (void)
	CPU initialization.
void *	_CPU_Thread_Idle_body (uintptr_t ignored)
void	_CPU_Context_switch (Context_Control *run, Context_Control *heir)
	CPU switch context.
RTEMS_NO_RETURN void	_CPU_Context_restore (Context_Control *new_context)
void	_CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
void	_CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)
uint32_t	_CPU_Counter_frequency (void)
CPU_Counter_ticks	_CPU_Counter_read (void)
RTEMS_NO_RETURN void	_CPU_Fatal_halt (uint32_t source, CPU_Uint32ptr error)

Variables
Context_Control_fp	_CPU_Null_fp_context

Detailed Description

MIPS Architecture Support.

Macro Definition Documentation

_CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp

(

_destination

)

Value:

  { \
   *(*(_destination)) = _CPU_Null_fp_context; \
  }

_CPU_ISR_Disable

#define _CPU_ISR_Disable

(

_level

)

Value:

  do { \
    unsigned int _scratch; \
    mips_get_sr( _scratch ); \
    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
  } while(0)

_CPU_ISR_Enable

#define _CPU_ISR_Enable

(

_level

)

Value:

  do { \
    unsigned int _scratch; \
    mips_get_sr( _scratch ); \
    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
  } while(0)

_CPU_ISR_Flash

#define _CPU_ISR_Flash

(

_xlevel

)

Value:

  do { \
    unsigned int _scratch2 = _xlevel; \
    _CPU_ISR_Enable( _scratch2 ); \
    _CPU_ISR_Disable( _scratch2 ); \
    _xlevel = _scratch2; \
  } while(0)

Typedef Documentation

CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.

Function Documentation

_CPU_Context_restore()

RTEMS_NO_RETURN void _CPU_Context_restore

(

Context_Control *

new_context

)

This routine is generally used only to restart self in an efficient manner. It may simply be a label in _CPU_Context_switch.

Parameters

[in]

new_context

points to the context to be restored.

Note

May be unnecessary to reload some registers.

Port Specific Information:

XXX document implementation including references if appropriate

_CPU_Context_switch()

void _CPU_Context_switch	(	Context_Control *	run,
		Context_Control *	heir
	)

CPU switch context.

This routine switches from the run context to the heir context.

Parameters

[in]	run	points to the context of the currently executing task
[in]	heir	points to the context of the heir task

Port Specific Information:

XXX document implementation including references if appropriate

_CPU_Exception_frame_print()

void _CPU_Exception_frame_print

(

const CPU_Exception_frame *

frame

)

This method prints the CPU exception frame.

Parameters

[in]

frame

points to the frame to be printed

_CPU_Fatal_halt()

RTEMS_NO_RETURN void _CPU_Fatal_halt	(	uint32_t	source,
		CPU_Uint32ptr	error
	)

COPYRIGHT (c) 2016. On-Line Applications Research Corporation (OAR).

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

_CPU_Initialize()

void _CPU_Initialize

(

void

)

CPU initialization.

CPU initialize. This routine performs CPU dependent initialization.

CPU initialize. This routine performs CPU dependent initialization.

CPU initialization.

_CPU_ISR_Get_level()

uint32_t _CPU_ISR_Get_level

(

void

)

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note

This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

_CPU_ISR_Set_level()

void _CPU_ISR_Set_level

(

uint32_t

level

)

Sets the hardware interrupt level by the level value.

Parameters

[in]

level

for or1k can only range over two values: 0 (enable interrupts) and 1 (disable interrupts). In future implementations if fast context switch is implemented, the level can range from 0 to 15.

See also

OpenRISC architecture manual.