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#define | LPC176X_IRQ_WDT 0U |
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#define | LPC176X_IRQ_TIMER_0 1U |
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#define | LPC176X_IRQ_TIMER_1 2U |
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#define | LPC176X_IRQ_TIMER_2 3U |
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#define | LPC176X_IRQ_TIMER_3 4U |
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#define | LPC176X_IRQ_UART_0 5U |
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#define | LPC176X_IRQ_UART_1 6U |
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#define | LPC176X_IRQ_UART_2 7U |
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#define | LPC176X_IRQ_UART_3 8U |
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#define | LPC176X_IRQ_PWM_1 9U |
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#define | LPC176X_IRQ_PLL 16U |
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#define | LPC176X_IRQ_RTC 17U |
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#define | LPC176X_IRQ_EINT_0 18U |
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#define | LPC176X_IRQ_EINT_1 19U |
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#define | LPC176X_IRQ_EINT_2 20U |
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#define | LPC176X_IRQ_EINT_3 21U |
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#define | LPC176X_IRQ_ADC_0 22U |
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#define | LPC176X_IRQ_BOD 23U |
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#define | LPC176X_IRQ_USB 24U |
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#define | LPC176X_IRQ_CAN 25U |
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#define | LPC176X_IRQ_DMA 26U |
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#define | LPC176X_IRQ_I2S 27U |
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#define | LPC176X_IRQ_SD_MMC 29U |
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#define | LPC176X_IRQ_MCPWM 30U |
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#define | LPC176X_IRQ_QEI 31U |
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#define | LPC176X_IRQ_PLL_ALT 32U |
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#define | LPC176X_IRQ_USB_ACTIVITY 33U |
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#define | LPC176X_IRQ_CAN_ACTIVITY 34U |
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#define | LPC176X_IRQ_UART_4 35U |
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#define | LPC176X_IRQ_GPIO 38U |
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#define | LPC176X_IRQ_PWM 39U |
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#define | LPC176X_IRQ_EEPROM 40U |
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#define | BSP_INTERRUPT_VECTOR_COUNT 41 |
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#define | LPC176X_IRQ_PRIORITY_VALUE_MIN 0U |
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#define | LPC176X_IRQ_PRIORITY_VALUE_MAX 31U |
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#define | LPC176X_IRQ_PRIORITY_COUNT ( LPC176X_IRQ_PRIORITY_VALUE_MAX + 1U ) |
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#define | LPC176X_IRQ_PRIORITY_HIGHEST LPC176X_IRQ_PRIORITY_VALUE_MIN |
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#define | LPC176X_IRQ_PRIORITY_LOWEST LPC176X_IRQ_PRIORITY_VALUE_MAX |
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#define | LPC24XX_IRQ_WDT 0 |
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#define | LPC24XX_IRQ_TIMER_0 1 |
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#define | LPC24XX_IRQ_TIMER_1 2 |
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#define | LPC24XX_IRQ_TIMER_2 3 |
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#define | LPC24XX_IRQ_TIMER_3 4 |
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#define | LPC24XX_IRQ_UART_0 5 |
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#define | LPC24XX_IRQ_UART_1 6 |
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#define | LPC24XX_IRQ_UART_2 7 |
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#define | LPC24XX_IRQ_UART_3 8 |
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#define | LPC24XX_IRQ_PWM_1 9 |
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#define | LPC24XX_IRQ_I2C_0 10 |
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#define | LPC24XX_IRQ_I2C_1 11 |
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#define | LPC24XX_IRQ_I2C_2 12 |
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#define | LPC24XX_IRQ_SPI_SSP_0 14 |
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#define | LPC24XX_IRQ_SSP_1 15 |
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#define | LPC24XX_IRQ_PLL 16 |
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#define | LPC24XX_IRQ_RTC 17 |
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#define | LPC24XX_IRQ_EINT_0 18 |
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#define | LPC24XX_IRQ_EINT_1 19 |
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#define | LPC24XX_IRQ_EINT_2 20 |
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#define | LPC24XX_IRQ_EINT_3 21 |
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#define | LPC24XX_IRQ_ADC_0 22 |
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#define | LPC24XX_IRQ_BOD 23 |
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#define | LPC24XX_IRQ_USB 24 |
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#define | LPC24XX_IRQ_CAN 25 |
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#define | LPC24XX_IRQ_DMA 26 |
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#define | LPC24XX_IRQ_I2S 27 |
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#define | LPC24XX_IRQ_ETHERNET 28 |
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#define | LPC24XX_IRQ_SD_MMC 29 |
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#define | LPC24XX_IRQ_MCPWM 30 |
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#define | LPC24XX_IRQ_QEI 31 |
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#define | LPC24XX_IRQ_PLL_ALT 32 |
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#define | LPC24XX_IRQ_USB_ACTIVITY 33 |
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#define | LPC24XX_IRQ_CAN_ACTIVITY 34 |
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#define | LPC24XX_IRQ_UART_4 35 |
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#define | LPC24XX_IRQ_SSP_2 36 |
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#define | LPC24XX_IRQ_LCD 37 |
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#define | LPC24XX_IRQ_GPIO 38 |
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#define | LPC24XX_IRQ_PWM 39 |
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#define | LPC24XX_IRQ_EEPROM 40 |
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#define | BSP_INTERRUPT_VECTOR_COUNT 41 |
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#define | LPC24XX_IRQ_PRIORITY_VALUE_MIN 0 |
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#define | LPC24XX_IRQ_PRIORITY_VALUE_MAX 31 |
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#define | LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1) |
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#define | LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN |
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#define | LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX |
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#define | BSP_INTERRUPT_VECTOR_COUNT 32 |
| Maximum vector number.
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#define | AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) |
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#define | AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) |
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#define | AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) |
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#define | AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) |
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#define | AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) |
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#define | AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) |
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#define | AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) |
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#define | AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) |
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#define | AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) |
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#define | AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) |
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#define | AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) |
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#define | AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) |
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#define | AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) |
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#define | AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) |
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#define | AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) |
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#define | AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) |
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#define | AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) |
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#define | AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) |
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#define | AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) |
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#define | AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) |
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#define | AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) |
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#define | AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) |
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#define | AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) |
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#define | AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) |
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#define | AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) |
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#define | AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) |
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#define | AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) |
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#define | AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) |
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#define | AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) |
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#define | AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) |
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#define | AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) |
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#define | AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) |
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#define | AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) |
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#define | AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) |
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#define | AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) |
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#define | AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) |
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#define | AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) |
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#define | AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) |
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#define | AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) |
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#define | AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) |
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#define | AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) |
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#define | AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) |
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#define | AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) |
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#define | AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) |
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#define | AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) |
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#define | AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) |
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#define | AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) |
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#define | AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) |
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#define | AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) |
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#define | AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) |
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#define | AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) |
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#define | AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) |
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#define | AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) |
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#define | AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) |
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#define | AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) |
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#define | AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) |
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#define | AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) |
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#define | AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) |
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#define | AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) |
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#define | AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) |
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#define | AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) |
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#define | AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) |
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#define | AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) |
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#define | AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) |
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#define | AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) |
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#define | AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) |
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#define | AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) |
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#define | AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) |
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#define | AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) |
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#define | AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) |
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#define | AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) |
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#define | AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) |
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#define | AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) |
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#define | AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) |
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#define | AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) |
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#define | BSP_INTERRUPT_VECTOR_COUNT (AU1X00_MAXIMUM_VECTORS + 1) |
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#define | RM5231_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE+8) |
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#define | BSP_INTERRUPT_VECTOR_COUNT (RM5231_MAXIMUM_VECTORS + 1) |
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#define | TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0 |
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#define | TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1 |
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#define | TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2 |
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#define | TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3 |
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#define | TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4 |
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#define | TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5 |
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#define | TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6 |
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#define | TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7 |
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#define | TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8 |
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#define | TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9 |
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#define | TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10 |
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#define | TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11 |
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#define | TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12 |
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#define | TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13 |
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#define | TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14 |
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#define | TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15 |
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#define | TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16 |
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#define | TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17 |
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#define | TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18 |
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#define | TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19 |
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#define | BSP_INTERRUPT_VECTOR_COUNT (TX3904_MAXIMUM_VECTORS + 1) |
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#define | MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0 |
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#define | MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0 |
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#define | MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1 |
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#define | MALTA_CPU_INT0 MALTA_CPU_INT_START+2 |
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#define | MALTA_CPU_INT1 MALTA_CPU_INT_START+3 |
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#define | MALTA_CPU_INT2 MALTA_CPU_INT_START+4 |
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#define | MALTA_CPU_INT3 MALTA_CPU_INT_START+5 |
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#define | MALTA_CPU_INT4 MALTA_CPU_INT_START+6 |
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#define | MALTA_CPU_INT5 MALTA_CPU_INT_START+7 |
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#define | MALTA_CPU_INT_LAST MALTA_CPU_INT5 |
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#define | MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1 |
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#define | MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0 |
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#define | MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1 |
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#define | MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2 |
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#define | MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3 |
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#define | MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4 |
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#define | MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5 |
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#define | MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6 |
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#define | MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7 |
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#define | MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8 |
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#define | MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9 |
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#define | MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10 |
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#define | MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11 |
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#define | MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12 |
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#define | MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13 |
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#define | MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14 |
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#define | MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15 |
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#define | MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15 |
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#define | MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1 |
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#define | MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0 |
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#define | MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1 |
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#define | MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2 |
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#define | MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3 |
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#define | MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4 |
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#define | MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5 |
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#define | MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6 |
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#define | MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7 |
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#define | MALTA_PCI_ADP_LAST MALTA_PCI_ADP31 |
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#define | BSP_INTERRUPT_VECTOR_COUNT (MALTA_PCI_ADP_LAST + 1) |
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#define | MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0 |
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#define | MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1 |
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#define | MALTA_INT_TTY2 MALTA_CPU_INT2 |
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#define | MALTA_INT_COREHI MALTA_CPU_INT3 |
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#define | MALTA_INT_CORELO MALTA_CPU_INT4 |
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#define | MALTA_INT_TICKER MALTA_CPU_INT5 |
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#define | MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0 |
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#define | MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1 |
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#define | MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2 |
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#define | MALTA_IRQ_TTY1 MALTA_SB_IRQ_3 |
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#define | MALTA_IRQ_TTY0 MALTA_SB_IRQ_4 |
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#define | MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5 |
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#define | MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6 |
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#define | MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7 |
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#define | MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8 |
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#define | MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9 |
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#define | MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10 |
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#define | MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11 |
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#define | MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12 |
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#define | MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13 |
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#define | MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14 |
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#define | MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15 |
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#define | MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20 |
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#define | MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B |
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#define | MALTA_IRQ_AUDIO MALTA_PCI_ADP22 |
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#define | MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27 |
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#define | MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28 |
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#define | MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29 |
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#define | MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30 |
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#define | MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31 |
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#define | TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0 |
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#define | TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1 |
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#define | TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2 |
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#define | TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3 |
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#define | TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4 |
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#define | TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5 |
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#define | TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6 |
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#define | TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7 |
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#define | TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8 |
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#define | TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9 |
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#define | TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10 |
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#define | TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11 |
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#define | TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12 |
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#define | TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13 |
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#define | TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14 |
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#define | TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15 |
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#define | TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16 |
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#define | TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17 |
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#define | TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18 |
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#define | TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19 |
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#define | TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20 |
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#define | TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21 |
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#define | TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22 |
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#define | TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23 |
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#define | TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24 |
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#define | TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25 |
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#define | TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26 |
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#define | TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 |
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#define | TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28 |
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#define | TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29 |
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#define | TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30 |
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#define | TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31 |
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#define | TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 |
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#define | TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 |
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#define | TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 |
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#define | BSP_INTERRUPT_VECTOR_COUNT (TX4925_MAXIMUM_VECTORS + 1) |
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#define | TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0 |
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#define | TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1 |
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#define | TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2 |
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#define | TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3 |
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#define | TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4 |
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#define | TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5 |
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#define | TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6 |
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#define | TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7 |
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#define | TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8 |
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#define | TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9 |
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#define | TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10 |
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#define | TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11 |
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#define | TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12 |
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#define | TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13 |
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#define | TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14 |
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#define | TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15 |
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#define | TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16 |
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#define | TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17 |
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#define | TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18 |
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#define | TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19 |
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#define | TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20 |
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#define | TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21 |
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#define | TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22 |
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#define | TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23 |
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#define | TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24 |
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#define | TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25 |
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#define | TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 |
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#define | TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26 |
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#define | TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28 |
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#define | TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29 |
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#define | TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30 |
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#define | TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31 |
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#define | TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 |
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#define | TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 |
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#define | TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 |
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#define | BSP_INTERRUPT_VECTOR_COUNT (TX4938_MAXIMUM_VECTORS + 1) |
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#define | BSP_INTERRUPT_VECTOR_COUNT (MPC55XX_IRQ_MAX + 1) |
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This group contains the Interrupt Manager implementation.
The Interrupt Manager implementation manages a sequence of interrupt vector numbers greater than or equal to zero and less than BSP_INTERRUPT_VECTOR_COUNT
. It provides methods to install, remove, and dispatch interrupt entries for each vector number, see bsp_interrupt_dispatch_entries().
The entry points to a list of interrupt entries are stored in a table (= dispatch table).
You have to configure the Interrupt Manager implementation in the <bsp/irq.h> file for each BSP. For a minimum configuration you have to provide BSP_INTERRUPT_VECTOR_COUNT
.
You have to provide some special routines in your BSP (follow the links for the details):
Optionally, the BSP may define the following macros to customize the vector installation after installing the first entry and the vector removal before removing the last entry: