RTEMS 6.1-rc1
stm32h7xx_hal_spi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_SPI_H
21#define STM32H7xx_HAL_SPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
47typedef struct
48{
49 uint32_t Mode;
52 uint32_t Direction;
55 uint32_t DataSize;
58 uint32_t CLKPolarity;
61 uint32_t CLKPhase;
64 uint32_t NSS;
69 uint32_t BaudRatePrescaler;
75 uint32_t FirstBit;
78 uint32_t TIMode;
81 uint32_t CRCCalculation;
84 uint32_t CRCPolynomial;
88 uint32_t CRCLength;
91 uint32_t NSSPMode;
97 uint32_t NSSPolarity;
101 uint32_t FifoThreshold;
104 uint32_t TxCRCInitializationPattern;
108 uint32_t RxCRCInitializationPattern;
112 uint32_t MasterSSIdleness;
117 uint32_t MasterInterDataIdleness;
122 uint32_t MasterReceiverAutoSusp;
126 uint32_t MasterKeepIOState;
129 uint32_t IOSwap;
131} SPI_InitTypeDef;
132
136typedef enum
137{
138 HAL_SPI_STATE_RESET = 0x00UL,
139 HAL_SPI_STATE_READY = 0x01UL,
140 HAL_SPI_STATE_BUSY = 0x02UL,
141 HAL_SPI_STATE_BUSY_TX = 0x03UL,
142 HAL_SPI_STATE_BUSY_RX = 0x04UL,
143 HAL_SPI_STATE_BUSY_TX_RX = 0x05UL,
144 HAL_SPI_STATE_ERROR = 0x06UL,
145 HAL_SPI_STATE_ABORT = 0x07UL
146} HAL_SPI_StateTypeDef;
147
148#if defined(USE_SPI_RELOAD_TRANSFER)
152typedef struct
153{
154 const uint8_t *pTxBuffPtr;
156 uint16_t TxXferSize;
158 uint8_t *pRxBuffPtr;
160 uint16_t RxXferSize;
162 uint32_t Requested;
164} SPI_ReloadTypeDef;
165#endif /* USE_SPI_RELOAD_TRANSFER */
166
170typedef struct __SPI_HandleTypeDef
171{
172 SPI_TypeDef *Instance;
174 SPI_InitTypeDef Init;
176 const uint8_t *pTxBuffPtr;
178 uint16_t TxXferSize;
180 __IO uint16_t TxXferCount;
182 uint8_t *pRxBuffPtr;
184 uint16_t RxXferSize;
186 __IO uint16_t RxXferCount;
188 uint32_t CRCSize;
190 void (*RxISR)(struct __SPI_HandleTypeDef *hspi);
192 void (*TxISR)(struct __SPI_HandleTypeDef *hspi);
194 DMA_HandleTypeDef *hdmatx;
196 DMA_HandleTypeDef *hdmarx;
198 HAL_LockTypeDef Lock;
200 __IO HAL_SPI_StateTypeDef State;
202 __IO uint32_t ErrorCode;
204#if defined(USE_SPI_RELOAD_TRANSFER)
205
206 SPI_ReloadTypeDef Reload;
208#endif /* USE_SPI_RELOAD_TRANSFER */
209
210#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
211 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
212 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
213 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
214 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
215 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
216 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
217 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);
218 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);
219 void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi);
220 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);
221 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);
223#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
224} SPI_HandleTypeDef;
225
226#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
230typedef enum
231{
232 HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL,
233 HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL,
234 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL,
235 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL,
236 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL,
237 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL,
238 HAL_SPI_ERROR_CB_ID = 0x06UL,
239 HAL_SPI_ABORT_CB_ID = 0x07UL,
240 HAL_SPI_SUSPEND_CB_ID = 0x08UL,
241 HAL_SPI_MSPINIT_CB_ID = 0x09UL,
242 HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL
244} HAL_SPI_CallbackIDTypeDef;
245
249typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi);
251#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
256/* Exported constants --------------------------------------------------------*/
257
267#define SPI_LOWEND_FIFO_SIZE 8UL
268#define SPI_HIGHEND_FIFO_SIZE 16UL
277#define HAL_SPI_ERROR_NONE (0x00000000UL)
278#define HAL_SPI_ERROR_MODF (0x00000001UL)
279#define HAL_SPI_ERROR_CRC (0x00000002UL)
280#define HAL_SPI_ERROR_OVR (0x00000004UL)
281#define HAL_SPI_ERROR_FRE (0x00000008UL)
282#define HAL_SPI_ERROR_DMA (0x00000010UL)
283#define HAL_SPI_ERROR_FLAG (0x00000020UL)
284#define HAL_SPI_ERROR_ABORT (0x00000040UL)
285#define HAL_SPI_ERROR_UDR (0x00000080UL)
286#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL)
287#define HAL_SPI_ERROR_UNKNOW (0x00000200UL)
288#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL)
289#define HAL_SPI_ERROR_RELOAD (0x00000800UL)
290#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
291#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL)
292#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
301#define SPI_MODE_SLAVE (0x00000000UL)
302#define SPI_MODE_MASTER SPI_CFG2_MASTER
311#define SPI_DIRECTION_2LINES (0x00000000UL)
312#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
313#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
314#define SPI_DIRECTION_1LINE SPI_CFG2_COMM
323#define SPI_DATASIZE_4BIT (0x00000003UL)
324#define SPI_DATASIZE_5BIT (0x00000004UL)
325#define SPI_DATASIZE_6BIT (0x00000005UL)
326#define SPI_DATASIZE_7BIT (0x00000006UL)
327#define SPI_DATASIZE_8BIT (0x00000007UL)
328#define SPI_DATASIZE_9BIT (0x00000008UL)
329#define SPI_DATASIZE_10BIT (0x00000009UL)
330#define SPI_DATASIZE_11BIT (0x0000000AUL)
331#define SPI_DATASIZE_12BIT (0x0000000BUL)
332#define SPI_DATASIZE_13BIT (0x0000000CUL)
333#define SPI_DATASIZE_14BIT (0x0000000DUL)
334#define SPI_DATASIZE_15BIT (0x0000000EUL)
335#define SPI_DATASIZE_16BIT (0x0000000FUL)
336#define SPI_DATASIZE_17BIT (0x00000010UL)
337#define SPI_DATASIZE_18BIT (0x00000011UL)
338#define SPI_DATASIZE_19BIT (0x00000012UL)
339#define SPI_DATASIZE_20BIT (0x00000013UL)
340#define SPI_DATASIZE_21BIT (0x00000014UL)
341#define SPI_DATASIZE_22BIT (0x00000015UL)
342#define SPI_DATASIZE_23BIT (0x00000016UL)
343#define SPI_DATASIZE_24BIT (0x00000017UL)
344#define SPI_DATASIZE_25BIT (0x00000018UL)
345#define SPI_DATASIZE_26BIT (0x00000019UL)
346#define SPI_DATASIZE_27BIT (0x0000001AUL)
347#define SPI_DATASIZE_28BIT (0x0000001BUL)
348#define SPI_DATASIZE_29BIT (0x0000001CUL)
349#define SPI_DATASIZE_30BIT (0x0000001DUL)
350#define SPI_DATASIZE_31BIT (0x0000001EUL)
351#define SPI_DATASIZE_32BIT (0x0000001FUL)
360#define SPI_POLARITY_LOW (0x00000000UL)
361#define SPI_POLARITY_HIGH SPI_CFG2_CPOL
370#define SPI_PHASE_1EDGE (0x00000000UL)
371#define SPI_PHASE_2EDGE SPI_CFG2_CPHA
380#define SPI_NSS_SOFT SPI_CFG2_SSM
381#define SPI_NSS_HARD_INPUT (0x00000000UL)
382#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
391#define SPI_NSS_PULSE_DISABLE (0x00000000UL)
392#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
401#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
402#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
403#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
404#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
405#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
406#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
407#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
408#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
417#define SPI_FIRSTBIT_MSB (0x00000000UL)
418#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
427#define SPI_TIMODE_DISABLE (0x00000000UL)
428#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
437#define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
438#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
447#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
448#define SPI_CRC_LENGTH_4BIT (0x00030000UL)
449#define SPI_CRC_LENGTH_5BIT (0x00040000UL)
450#define SPI_CRC_LENGTH_6BIT (0x00050000UL)
451#define SPI_CRC_LENGTH_7BIT (0x00060000UL)
452#define SPI_CRC_LENGTH_8BIT (0x00070000UL)
453#define SPI_CRC_LENGTH_9BIT (0x00080000UL)
454#define SPI_CRC_LENGTH_10BIT (0x00090000UL)
455#define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
456#define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
457#define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
458#define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
459#define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
460#define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
461#define SPI_CRC_LENGTH_17BIT (0x00100000UL)
462#define SPI_CRC_LENGTH_18BIT (0x00110000UL)
463#define SPI_CRC_LENGTH_19BIT (0x00120000UL)
464#define SPI_CRC_LENGTH_20BIT (0x00130000UL)
465#define SPI_CRC_LENGTH_21BIT (0x00140000UL)
466#define SPI_CRC_LENGTH_22BIT (0x00150000UL)
467#define SPI_CRC_LENGTH_23BIT (0x00160000UL)
468#define SPI_CRC_LENGTH_24BIT (0x00170000UL)
469#define SPI_CRC_LENGTH_25BIT (0x00180000UL)
470#define SPI_CRC_LENGTH_26BIT (0x00190000UL)
471#define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
472#define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
473#define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
474#define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
475#define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
476#define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
485#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
486#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
487#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
488#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
489#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
490#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
491#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
492#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
493#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
494#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
495#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
496#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
497#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
498#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
499#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
500#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
509#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
510#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
519#define SPI_NSS_POLARITY_LOW (0x00000000UL)
520#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
529#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
530#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
539#define SPI_IO_SWAP_DISABLE (0x00000000UL)
540#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
549#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
550#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
551#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
552#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
553#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
554#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
555#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
556#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
557#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
558#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
559#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
560#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
561#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
562#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
563#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
564#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
573#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
574#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
575#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
576#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
577#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
578#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
579#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
580#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
581#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
582#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
583#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
584#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
585#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
586#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
587#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
588#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
597#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
598#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
607#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
608#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
609#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
618#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
619#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
620#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
629#define SPI_IT_RXP SPI_IER_RXPIE
630#define SPI_IT_TXP SPI_IER_TXPIE
631#define SPI_IT_DXP SPI_IER_DXPIE
632#define SPI_IT_EOT SPI_IER_EOTIE
633#define SPI_IT_TXTF SPI_IER_TXTFIE
634#define SPI_IT_UDR SPI_IER_UDRIE
635#define SPI_IT_OVR SPI_IER_OVRIE
636#define SPI_IT_CRCERR SPI_IER_CRCEIE
637#define SPI_IT_FRE SPI_IER_TIFREIE
638#define SPI_IT_MODF SPI_IER_MODFIE
639#define SPI_IT_TSERF SPI_IER_TSERFIE
640#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
649#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
650#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
651#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
652#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
653#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
654#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
655#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
656#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
657#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
658#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
659#define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
660#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
661#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
662#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
663#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
672#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
673#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
674#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
675#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
684/* Exported macros -----------------------------------------------------------*/
695#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
696#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
697 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
698 (__HANDLE__)->MspInitCallback = NULL; \
699 (__HANDLE__)->MspDeInitCallback = NULL; \
700 } while(0)
701#else
702#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
703#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
704
724#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
725
745#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
746
766#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
767 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
768
791#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
792
797#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
798
803#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
804
809#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
810
815#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
816
821#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
822
827#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
828
833#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
834
839#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
840
845#define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
846
851#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
852
857#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
863/* Include SPI HAL Extension module */
864#include "stm32h7xx_hal_spi_ex.h"
865
866
867/* Exported functions --------------------------------------------------------*/
875/* Initialization/de-initialization functions ********************************/
876HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
877HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
878void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
879void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
880
881/* Callbacks Register/UnRegister functions ***********************************/
882#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
883HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
884 pSPI_CallbackTypeDef pCallback);
885HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
886#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
894/* I/O operation functions ***************************************************/
895HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
896HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
897HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
898 uint16_t Size, uint32_t Timeout);
899HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
900HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
901HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
902 uint16_t Size);
903
904HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
905HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
906HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
907 uint16_t Size);
908
909#if defined(USE_SPI_RELOAD_TRANSFER)
910HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
911HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
912HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData,
913 uint8_t *pRxData, uint16_t Size);
914#endif /* USE_SPI_RELOAD_TRANSFER */
915
916HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
917HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
918HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
919
920/* Transfer Abort functions */
921HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
922HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
923
924void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
925void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
926void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
927void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
928void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
929void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
930void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
931void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
932void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
933void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi);
942/* Peripheral State and Error functions ***************************************/
943HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
944uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
953/* Private macros ------------------------------------------------------------*/
964#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
965
971#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
972
978#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0)
979
985#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1)
986
992#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
993
994#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
995 ((MODE) == SPI_MODE_MASTER))
996
997#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
998 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
999 ((MODE) == SPI_DIRECTION_1LINE) || \
1000 ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
1001
1002#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
1003
1004#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
1005 ((MODE) == SPI_DIRECTION_1LINE) || \
1006 ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
1007
1008#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
1009 ((MODE) == SPI_DIRECTION_1LINE) || \
1010 ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
1011
1012#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
1013 ((DATASIZE) == SPI_DATASIZE_31BIT) || \
1014 ((DATASIZE) == SPI_DATASIZE_30BIT) || \
1015 ((DATASIZE) == SPI_DATASIZE_29BIT) || \
1016 ((DATASIZE) == SPI_DATASIZE_28BIT) || \
1017 ((DATASIZE) == SPI_DATASIZE_27BIT) || \
1018 ((DATASIZE) == SPI_DATASIZE_26BIT) || \
1019 ((DATASIZE) == SPI_DATASIZE_25BIT) || \
1020 ((DATASIZE) == SPI_DATASIZE_24BIT) || \
1021 ((DATASIZE) == SPI_DATASIZE_23BIT) || \
1022 ((DATASIZE) == SPI_DATASIZE_22BIT) || \
1023 ((DATASIZE) == SPI_DATASIZE_21BIT) || \
1024 ((DATASIZE) == SPI_DATASIZE_20BIT) || \
1025 ((DATASIZE) == SPI_DATASIZE_22BIT) || \
1026 ((DATASIZE) == SPI_DATASIZE_19BIT) || \
1027 ((DATASIZE) == SPI_DATASIZE_18BIT) || \
1028 ((DATASIZE) == SPI_DATASIZE_17BIT) || \
1029 ((DATASIZE) == SPI_DATASIZE_16BIT) || \
1030 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
1031 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
1032 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
1033 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
1034 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
1035 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
1036 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
1037 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
1038 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
1039 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
1040 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
1041 ((DATASIZE) == SPI_DATASIZE_4BIT))
1042
1043#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
1044 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
1045 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
1046 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
1047 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
1048 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
1049 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
1050 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
1051 ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
1052 ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
1053 ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
1054 ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
1055 ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
1056 ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
1057 ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
1058 ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
1059
1060#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
1061 ((CPOL) == SPI_POLARITY_HIGH))
1062
1063#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
1064 ((CPHA) == SPI_PHASE_2EDGE))
1065
1066#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
1067 ((NSS) == SPI_NSS_HARD_INPUT) || \
1068 ((NSS) == SPI_NSS_HARD_OUTPUT))
1069
1070#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
1071 ((NSSP) == SPI_NSS_PULSE_DISABLE))
1072
1073#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
1074 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
1075 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
1076 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
1077 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
1078 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
1079 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
1080 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
1081
1082#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
1083 ((BIT) == SPI_FIRSTBIT_LSB))
1084
1085#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
1086 ((MODE) == SPI_TIMODE_ENABLE))
1087
1088#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
1089 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
1090
1091#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
1092 ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
1093
1094#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
1095 ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
1096 ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
1097 ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
1098 ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
1099 ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
1100 ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
1101 ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
1102 ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
1103 ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
1104 ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
1105 ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
1106 ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
1107 ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
1108 ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
1109 ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
1110 ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
1111 ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
1112 ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
1113 ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
1114 ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
1115 ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
1116 ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
1117 ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
1118 ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
1119 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
1120 ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
1121 ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
1122 ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
1123 ((LENGTH) == SPI_CRC_LENGTH_4BIT))
1124
1125#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL)
1126
1127
1128#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
1129 ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
1130 ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
1131
1132#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
1133 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
1134 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
1135
1136#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \
1137 ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE))
1150#ifdef __cplusplus
1151}
1152#endif
1153
1154#endif /* STM32H7xx_HAL_SPI_H */
1155
__IO
#define __IO
Definition: core_cm4.h:239
HAL_SPI_StateTypeDef
HAL_SPI_StateTypeDef
HAL SPI State structure definition.
Definition: stm32h7xx_hal_spi.h:137
SPI_HandleTypeDef
struct __SPI_HandleTypeDef SPI_HandleTypeDef
SPI handle Structure definition.
HAL_SPI_STATE_BUSY
@ HAL_SPI_STATE_BUSY
Definition: stm32h7xx_hal_spi.h:140
HAL_SPI_STATE_ABORT
@ HAL_SPI_STATE_ABORT
Definition: stm32h7xx_hal_spi.h:145
HAL_SPI_STATE_ERROR
@ HAL_SPI_STATE_ERROR
Definition: stm32h7xx_hal_spi.h:144
HAL_SPI_STATE_BUSY_TX
@ HAL_SPI_STATE_BUSY_TX
Definition: stm32h7xx_hal_spi.h:141
HAL_SPI_STATE_BUSY_TX_RX
@ HAL_SPI_STATE_BUSY_TX_RX
Definition: stm32h7xx_hal_spi.h:143
HAL_SPI_STATE_READY
@ HAL_SPI_STATE_READY
Definition: stm32h7xx_hal_spi.h:139
HAL_SPI_STATE_RESET
@ HAL_SPI_STATE_RESET
Definition: stm32h7xx_hal_spi.h:138
HAL_SPI_STATE_BUSY_RX
@ HAL_SPI_STATE_BUSY_RX
Definition: stm32h7xx_hal_spi.h:142
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
stm32h7xx_hal_spi_ex.h
Header file of SPI HAL Extended module.
SPI_InitTypeDef
SPI Configuration Structure definition.
Definition: stm32h7xx_hal_spi.h:48
SPI_InitTypeDef::RxCRCInitializationPattern
uint32_t RxCRCInitializationPattern
Definition: stm32h7xx_hal_spi.h:108
SPI_InitTypeDef::MasterReceiverAutoSusp
uint32_t MasterReceiverAutoSusp
Definition: stm32h7xx_hal_spi.h:122
SPI_InitTypeDef::MasterSSIdleness
uint32_t MasterSSIdleness
Definition: stm32h7xx_hal_spi.h:112
SPI_InitTypeDef::BaudRatePrescaler
uint32_t BaudRatePrescaler
Definition: stm32h7xx_hal_spi.h:69
SPI_InitTypeDef::MasterKeepIOState
uint32_t MasterKeepIOState
Definition: stm32h7xx_hal_spi.h:126
SPI_InitTypeDef::DataSize
uint32_t DataSize
Definition: stm32h7xx_hal_spi.h:55
SPI_InitTypeDef::CRCCalculation
uint32_t CRCCalculation
Definition: stm32h7xx_hal_spi.h:81
SPI_InitTypeDef::Mode
uint32_t Mode
Definition: stm32h7xx_hal_spi.h:49
SPI_InitTypeDef::TIMode
uint32_t TIMode
Definition: stm32h7xx_hal_spi.h:78
SPI_InitTypeDef::FifoThreshold
uint32_t FifoThreshold
Definition: stm32h7xx_hal_spi.h:101
SPI_InitTypeDef::FirstBit
uint32_t FirstBit
Definition: stm32h7xx_hal_spi.h:75
SPI_InitTypeDef::CLKPolarity
uint32_t CLKPolarity
Definition: stm32h7xx_hal_spi.h:58
SPI_InitTypeDef::MasterInterDataIdleness
uint32_t MasterInterDataIdleness
Definition: stm32h7xx_hal_spi.h:117
SPI_InitTypeDef::NSSPMode
uint32_t NSSPMode
Definition: stm32h7xx_hal_spi.h:91
SPI_InitTypeDef::CLKPhase
uint32_t CLKPhase
Definition: stm32h7xx_hal_spi.h:61
SPI_InitTypeDef::CRCPolynomial
uint32_t CRCPolynomial
Definition: stm32h7xx_hal_spi.h:84
SPI_InitTypeDef::TxCRCInitializationPattern
uint32_t TxCRCInitializationPattern
Definition: stm32h7xx_hal_spi.h:104
SPI_InitTypeDef::CRCLength
uint32_t CRCLength
Definition: stm32h7xx_hal_spi.h:88
SPI_InitTypeDef::NSSPolarity
uint32_t NSSPolarity
Definition: stm32h7xx_hal_spi.h:97
SPI_InitTypeDef::Direction
uint32_t Direction
Definition: stm32h7xx_hal_spi.h:52
SPI_InitTypeDef::NSS
uint32_t NSS
Definition: stm32h7xx_hal_spi.h:64
SPI_InitTypeDef::IOSwap
uint32_t IOSwap
Definition: stm32h7xx_hal_spi.h:129
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138
__SPI_HandleTypeDef
SPI handle Structure definition.
Definition: stm32h7xx_hal_spi.h:171
__SPI_HandleTypeDef::hdmarx
DMA_HandleTypeDef * hdmarx
Definition: stm32h7xx_hal_spi.h:196
__SPI_HandleTypeDef::TxXferCount
__IO uint16_t TxXferCount
Definition: stm32h7xx_hal_spi.h:180
__SPI_HandleTypeDef::TxISR
void(* TxISR)(struct __SPI_HandleTypeDef *hspi)
Definition: stm32h7xx_hal_spi.h:192
__SPI_HandleTypeDef::Init
SPI_InitTypeDef Init
Definition: stm32h7xx_hal_spi.h:174
__SPI_HandleTypeDef::TxXferSize
uint16_t TxXferSize
Definition: stm32h7xx_hal_spi.h:178
__SPI_HandleTypeDef::RxISR
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)
Definition: stm32h7xx_hal_spi.h:190
__SPI_HandleTypeDef::RxXferCount
__IO uint16_t RxXferCount
Definition: stm32h7xx_hal_spi.h:186
__SPI_HandleTypeDef::Instance
SPI_TypeDef * Instance
Definition: stm32h7xx_hal_spi.h:172
__SPI_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32h7xx_hal_spi.h:198
__SPI_HandleTypeDef::hdmatx
DMA_HandleTypeDef * hdmatx
Definition: stm32h7xx_hal_spi.h:194
__SPI_HandleTypeDef::State
__IO HAL_SPI_StateTypeDef State
Definition: stm32h7xx_hal_spi.h:200
__SPI_HandleTypeDef::pRxBuffPtr
uint8_t * pRxBuffPtr
Definition: stm32h7xx_hal_spi.h:182
__SPI_HandleTypeDef::pTxBuffPtr
const uint8_t * pTxBuffPtr
Definition: stm32h7xx_hal_spi.h:176
__SPI_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32h7xx_hal_spi.h:202
__SPI_HandleTypeDef::RxXferSize
uint16_t RxXferSize
Definition: stm32h7xx_hal_spi.h:184
__SPI_HandleTypeDef::CRCSize
uint32_t CRCSize
Definition: stm32h7xx_hal_spi.h:188
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