RTEMS 6.1-rc1
Macros
SPI Private Macros
STM32H7xx_HAL_Driver | Board Support Packages » ARM » STM32H7 | Device Drivers » SPI

Macros

#define SPI_1LINE_TX(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
 Set the SPI transmit-only mode in 1Line configuration. More...
 
#define SPI_1LINE_RX(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
 Set the SPI receive-only mode in 1Line configuration. More...
 
#define SPI_2LINES_TX(__HANDLE__)   MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0)
 Set the SPI transmit-only mode in 2Lines configuration. More...
 
#define SPI_2LINES_RX(__HANDLE__)   MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1)
 Set the SPI receive-only mode in 2Lines configuration. More...
 
#define SPI_2LINES(__HANDLE__)   MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
 Set the SPI Transmit-Receive mode in 2Lines configuration. More...
 
#define IS_SPI_MODE(MODE)
 
#define IS_SPI_DIRECTION(MODE)
 
#define IS_SPI_DIRECTION_2LINES(MODE)   ((MODE) == SPI_DIRECTION_2LINES)
 
#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE)
 
#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE)
 
#define IS_SPI_DATASIZE(DATASIZE)
 
#define IS_SPI_FIFOTHRESHOLD(THRESHOLD)
 
#define IS_SPI_CPOL(CPOL)
 
#define IS_SPI_CPHA(CPHA)
 
#define IS_SPI_NSS(NSS)
 
#define IS_SPI_NSSP(NSSP)
 
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
 
#define IS_SPI_FIRST_BIT(BIT)
 
#define IS_SPI_TIMODE(MODE)
 
#define IS_SPI_CRC_CALCULATION(CALCULATION)
 
#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN)
 
#define IS_SPI_CRC_LENGTH(LENGTH)
 
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)   ((POLYNOMIAL) > 0x0UL)
 
#define IS_SPI_UNDERRUN_DETECTION(MODE)
 
#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE)
 
#define IS_SPI_MASTER_RX_AUTOSUSP(MODE)
 

Detailed Description

Macro Definition Documentation

◆ IS_SPI_BAUDRATE_PRESCALER

#define IS_SPI_BAUDRATE_PRESCALER (   PRESCALER)
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

◆ IS_SPI_CPHA

#define IS_SPI_CPHA (   CPHA)
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))

◆ IS_SPI_CPOL

#define IS_SPI_CPOL (   CPOL)
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))

◆ IS_SPI_CRC_CALCULATION

#define IS_SPI_CRC_CALCULATION (   CALCULATION)
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

◆ IS_SPI_CRC_INITIALIZATION_PATTERN

#define IS_SPI_CRC_INITIALIZATION_PATTERN (   PATTERN)
Value:
(((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))

◆ IS_SPI_CRC_LENGTH

#define IS_SPI_CRC_LENGTH (   LENGTH)
Value:
(((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
((LENGTH) == SPI_CRC_LENGTH_4BIT))

◆ IS_SPI_DATASIZE

#define IS_SPI_DATASIZE (   DATASIZE)
Value:
(((DATASIZE) == SPI_DATASIZE_32BIT) || \
((DATASIZE) == SPI_DATASIZE_31BIT) || \
((DATASIZE) == SPI_DATASIZE_30BIT) || \
((DATASIZE) == SPI_DATASIZE_29BIT) || \
((DATASIZE) == SPI_DATASIZE_28BIT) || \
((DATASIZE) == SPI_DATASIZE_27BIT) || \
((DATASIZE) == SPI_DATASIZE_26BIT) || \
((DATASIZE) == SPI_DATASIZE_25BIT) || \
((DATASIZE) == SPI_DATASIZE_24BIT) || \
((DATASIZE) == SPI_DATASIZE_23BIT) || \
((DATASIZE) == SPI_DATASIZE_22BIT) || \
((DATASIZE) == SPI_DATASIZE_21BIT) || \
((DATASIZE) == SPI_DATASIZE_20BIT) || \
((DATASIZE) == SPI_DATASIZE_22BIT) || \
((DATASIZE) == SPI_DATASIZE_19BIT) || \
((DATASIZE) == SPI_DATASIZE_18BIT) || \
((DATASIZE) == SPI_DATASIZE_17BIT) || \
((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_14BIT) || \
((DATASIZE) == SPI_DATASIZE_13BIT) || \
((DATASIZE) == SPI_DATASIZE_12BIT) || \
((DATASIZE) == SPI_DATASIZE_11BIT) || \
((DATASIZE) == SPI_DATASIZE_10BIT) || \
((DATASIZE) == SPI_DATASIZE_9BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT) || \
((DATASIZE) == SPI_DATASIZE_7BIT) || \
((DATASIZE) == SPI_DATASIZE_6BIT) || \
((DATASIZE) == SPI_DATASIZE_5BIT) || \
((DATASIZE) == SPI_DATASIZE_4BIT))

◆ IS_SPI_DIRECTION

#define IS_SPI_DIRECTION (   MODE)
Value:
(((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
((MODE) == SPI_DIRECTION_1LINE) || \
((MODE) == SPI_DIRECTION_2LINES_TXONLY))

◆ IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY

#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY (   MODE)
Value:
(((MODE) == SPI_DIRECTION_2LINES)|| \
((MODE) == SPI_DIRECTION_1LINE) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY))

◆ IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY

#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY (   MODE)
Value:
(((MODE) == SPI_DIRECTION_2LINES)|| \
((MODE) == SPI_DIRECTION_1LINE) || \
((MODE) == SPI_DIRECTION_2LINES_TXONLY))

◆ IS_SPI_FIFOTHRESHOLD

#define IS_SPI_FIFOTHRESHOLD (   THRESHOLD)
Value:
(((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))

◆ IS_SPI_FIRST_BIT

#define IS_SPI_FIRST_BIT (   BIT)
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
((BIT) == SPI_FIRSTBIT_LSB))

◆ IS_SPI_MASTER_RX_AUTOSUSP

#define IS_SPI_MASTER_RX_AUTOSUSP (   MODE)
Value:
(((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \
((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE))

◆ IS_SPI_MODE

#define IS_SPI_MODE (   MODE)
Value:
(((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))

◆ IS_SPI_NSS

#define IS_SPI_NSS (   NSS)
Value:
(((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))

◆ IS_SPI_NSSP

#define IS_SPI_NSSP (   NSSP)
Value:
(((NSSP) == SPI_NSS_PULSE_ENABLE) || \
((NSSP) == SPI_NSS_PULSE_DISABLE))

◆ IS_SPI_TIMODE

#define IS_SPI_TIMODE (   MODE)
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
((MODE) == SPI_TIMODE_ENABLE))

◆ IS_SPI_UNDERRUN_BEHAVIOUR

#define IS_SPI_UNDERRUN_BEHAVIOUR (   MODE)
Value:
(((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))

◆ IS_SPI_UNDERRUN_DETECTION

#define IS_SPI_UNDERRUN_DETECTION (   MODE)
Value:
(((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))

◆ SPI_1LINE_RX

#define SPI_1LINE_RX (   __HANDLE__)    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)

Set the SPI receive-only mode in 1Line configuration.

Parameters
__HANDLE__specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values
None

◆ SPI_1LINE_TX

#define SPI_1LINE_TX (   __HANDLE__)    SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)

Set the SPI transmit-only mode in 1Line configuration.

Parameters
__HANDLE__specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values
None

◆ SPI_2LINES

#define SPI_2LINES (   __HANDLE__)    MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)

Set the SPI Transmit-Receive mode in 2Lines configuration.

Parameters
__HANDLE__specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values
None

◆ SPI_2LINES_RX

#define SPI_2LINES_RX (   __HANDLE__)    MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1)

Set the SPI receive-only mode in 2Lines configuration.

Parameters
__HANDLE__specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values
None

◆ SPI_2LINES_TX

#define SPI_2LINES_TX (   __HANDLE__)    MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0)

Set the SPI transmit-only mode in 2Lines configuration.

Parameters
__HANDLE__specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values
None
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