ARM Architecture Support. More...

Modules
	AArch32 System Registers
	This group provides functions to read and write the AArch32 system registers.

	ARM Assembler Support
	ARM Assembler Support.

	ARM Co-Processor 15 Support
	ARM co-processor 15 (CP15) support.

	ARM Paravirtualization Support

	PMSAv8-32 Support
	This group provides support functions to manage an Arm PMSAv8-32 (Protected Memory System Architecture) based Memory Protection Unit (MPU).

Files
file	__aeabi_read_tp.c
	This source file contains the implementation of __aeabi_read_tp().

file	__tls_get_addr.c
	This source file contains the implementation of __tls_get_addr().

file	arm-exception-default.c
	This source file contains the implementation of _ARM_Exception_default().

file	arm-exception-frame-print.c
	This source file contains the implementation of _CPU_Exception_frame_print().

file	armv4-sync-synchronize.c
	This source file contains the implementation of __sync_synchronize().

file	armv7-thread-idle.c
	This source file contains the implementation of _CPU_Thread_Idle_body().

file	armv7m-context-initialize.c
	This source file contains the implementation of _CPU_Context_Initialize().

file	armv7m-context-restore.c
	This source file contains the implementation of _CPU_Context_restore().

file	armv7m-context-switch.c
	This source file contains the implementation of _CPU_Context_switch().

file	armv7m-exception-default.c
	This source file contains the implementation of _ARMV7M_Exception_default().

file	armv7m-exception-handler-get.c
	This source file contains the implementation of _ARMV7M_Get_exception_handler().

file	armv7m-exception-handler-set.c
	This source file contains the implementation of _ARMV7M_Set_exception_handler().

file	armv7m-exception-priority-get.c
	This source file contains the implementation of _ARMV7M_Get_exception_priority().

file	armv7m-exception-priority-handler.c
	This source file contains the implementation of _ARMV7M_Set_exception_priority_and_handler().

file	armv7m-exception-priority-set.c
	This source file contains the implementation of _ARMV7M_Set_exception_priority().

file	armv7m-initialize.c
	This source file contains the implementation of _CPU_Initialize().

file	armv7m-isr-dispatch.c
	This source file contains the implementation of _ARMV7M_Thread_dispatch().

file	armv7m-isr-enter-leave.c
	This source file contains the implementation of _ARMV7M_Interrupt_service_enter() and _ARMV7M_Interrupt_service_leave().

file	armv7m-isr-level-get.c
	This source file contains the implementation of _CPU_ISR_Get_level().

file	armv7m-isr-level-set.c
	This source file contains the implementation of _CPU_ISR_Set_level().

file	armv7m-isr-vector-install.c
	This source file contains the implementation of _CPU_ISR_install_vector().

file	armv7m-multitasking-start-stop.c
	This source file contains the implementation of _ARMV7M_Start_multitasking().

file	cpu.c
	This source file contains static assertions to ensure the consistency of interfaces used in C and assembler and it contains the ARM-specific implementation of _CPU_Initialize(), _CPU_ISR_Get_level(), _CPU_ISR_Set_level(), _CPU_ISR_install_vector(), _CPU_Context_Initialize(), and _CPU_Fatal_halt().

file	arm.h
	This header file provides defines derived from ARM multilib defines.

file	armv4.h
	This header file provides interfaces of the ARMv4 architecture support.

file	armv7m.h
	This header file provides interfaces of the ARMv7-M architecture support.

file	cpu.h
	This header file defines implementation interfaces pertaining to the port of the executive to the ARM architecture.

file	cpu_asm.h
	ARM Assembler Support API.

file	cpuimpl.h
	This header file defines implementation interfaces pertaining to the port of the executive to the ARM architecture.

Data Structures
struct	Context_Control
	Thread register context. More...

struct	ARM_VFP_context

struct	CPU_Exception_frame
	The set of registers that specifies the complete processor state. More...

Macros
#define	CPU_MODEL_NAME "ARMv4"

#define	ARM_MULTILIB_ARCH_V4

#define	CPU_NAME "ARM"

#define	CPU_SIMPLE_VECTORED_INTERRUPTS FALSE

#define	CPU_ISR_PASSES_FRAME_POINTER FALSE

#define	CPU_HARDWARE_FP FALSE

#define	CPU_SOFTWARE_FP FALSE

#define	CPU_ALL_TASKS_ARE_FP FALSE

#define	CPU_IDLE_TASK_IS_FP FALSE

#define	CPU_USE_DEFERRED_FP_SWITCH FALSE

#define	CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE

#define	CPU_STACK_GROWS_UP FALSE

#define	CPU_CACHE_LINE_BYTES 32

#define	CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )

#define	CPU_MODES_INTERRUPT_MASK 0x1

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

#define	CPU_STACK_MINIMUM_SIZE (1024 * 4)

#define	CPU_SIZEOF_POINTER 4

#define	CPU_ALIGNMENT 8

#define	CPU_HEAP_ALIGNMENT CPU_ALIGNMENT

#define	CPU_STACK_ALIGNMENT 8

#define	CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES

#define	CPU_USE_GENERIC_BITFIELD_CODE TRUE

#define	CPU_USE_LIBC_INIT_FINI_ARRAY TRUE

#define	CPU_MAXIMUM_PROCESSORS 32

#define	ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44

#define	ARM_EXCEPTION_FRAME_SIZE 80

#define	ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52

#define	ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72

#define	ARM_VFP_CONTEXT_SIZE 264

#define	_CPU_ISR_Disable(_isr_cookie)

#define	_CPU_ISR_Enable(_isr_cookie) arm_interrupt_enable( _isr_cookie )

#define	_CPU_ISR_Flash(_isr_cookie) arm_interrupt_flash( _isr_cookie )

#define	_CPU_Context_Get_SP(_context) (_context)->register_sp

#define	_CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) );

#define	_CPU_Context_Initialize_fp(_destination)

#define	CPU_PER_CPU_CONTROL_SIZE 0

#define	CPU_THREAD_LOCAL_STORAGE_VARIANT 11

Typedefs
typedef void(*	CPU_ISR_handler) (void)

typedef uint32_t	CPU_Counter_ticks

typedef uintptr_t	CPU_Uint32ptr

Functions
void	_CPU_ISR_Set_level (uint32_t level)
	Sets the hardware interrupt level by the level value. More...

uint32_t	_CPU_ISR_Get_level (void)

void	_CPU_Context_Initialize (Context_Control the_context, void stack_area_begin, size_t stack_area_size, uint32_t new_level, void(entry_point)(void), bool is_fp, void tls_area)

void	_CPU_Initialize (void)
	CPU initialization. More...

void	_CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)

void	_CPU_Context_switch (Context_Control run, Context_Control heir)
	CPU switch context.

RTEMS_NO_RETURN void	_CPU_Context_switch_no_return (Context_Control executing, Context_Control heir)

RTEMS_NO_RETURN void	_CPU_Context_restore (Context_Control *new_context)

uint32_t	_CPU_Counter_frequency (void)

CPU_Counter_ticks	_CPU_Counter_read (void)

void *	_CPU_Thread_Idle_body (uintptr_t ignored)

void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)

void	_ARM_Exception_default (CPU_Exception_frame *frame)

RTEMS_NO_RETURN void	_CPU_Fatal_halt (uint32_t source, CPU_Uint32ptr error)

void	_CPU_Context_volatile_clobber (uintptr_t pattern)

void	_CPU_Context_validate (uintptr_t pattern)

Detailed Description

ARM Architecture Support.

Macro Definition Documentation

◆ _CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp ( _destination )

Value:

  do { \
    *(*(_destination)) = _CPU_Null_fp_context; \
  } while (0)

◆ _CPU_ISR_Disable

#define _CPU_ISR_Disable ( _isr_cookie )

Value:

  do { \
    _isr_cookie = arm_interrupt_disable(); \
  } while (0)

Typedef Documentation

◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.

Function Documentation

◆ _CPU_Fatal_halt()

RTEMS_NO_RETURN void _CPU_Fatal_halt	(	uint32_t	source,
		CPU_Uint32ptr	error
	)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

◆ _CPU_Initialize()

void _CPU_Initialize ( void )

CPU initialization.

◆ _CPU_ISR_Set_level()

void _CPU_ISR_Set_level ( uint32_t level )

Sets the hardware interrupt level by the level value.

Parameters

[in] level for or1k can only range over two values: 0 (enable interrupts) and 1 (disable interrupts). In future implementations if fast context switch is implemented, the level can range from 0 to 15.

See also: OpenRISC architecture manual.

Modules

Files

Data Structures

Macros

Typedefs

Functions