RTEMS 6.1-rc1
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Type definitions for the Floating Point Unit (FPU) More...
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Core Debug Registers (CoreDebug) | |
Type definitions for the Core Debug Registers. | |
Type definitions for the Floating Point Unit (FPU)
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
#define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
#define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
#define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
#define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
#define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
#define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
#define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
#define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
#define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
#define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
#define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
#define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
#define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
#define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
#define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
#define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
#define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
#define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
#define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
#define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
#define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
#define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
#define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
#define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
#define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
#define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
#define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
#define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
#define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
#define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
#define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
#define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
#define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
#define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
#define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
#define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
#define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
#define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
#define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
#define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
#define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
#define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
#define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
#define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
#define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
#define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
#define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
#define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
#define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
#define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
#define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
#define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) |
MVFR2: VFP Misc bits Mask
#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) |
MVFR2: VFP Misc bits Mask
#define FPU_MVFR2_VFP_Misc_Pos 4U |
MVFR2: VFP Misc bits Position
#define FPU_MVFR2_VFP_Misc_Pos 4U |
MVFR2: VFP Misc bits Position