RTEMS 6.1-rc1
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Type definitions for the Instrumentation Trace Macrocell (ITM) More...
Modules | |
Data Watchpoint and Trace (DWT) | |
Type definitions for the Data Watchpoint and Trace (DWT) | |
Type definitions for the Instrumentation Trace Macrocell (ITM)
#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) |
ITM LSR: Access Mask
#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) |
ITM LSR: Access Mask
#define ITM_LSR_ACCESS_Pos 1U |
ITM LSR: Access Position
#define ITM_LSR_ACCESS_Pos 1U |
ITM LSR: Access Position
#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) |
ITM LSR: ByteAcc Mask
#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) |
ITM LSR: ByteAcc Mask
#define ITM_LSR_BYTEACC_Pos 2U |
ITM LSR: ByteAcc Position
#define ITM_LSR_BYTEACC_Pos 2U |
ITM LSR: ByteAcc Position
#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) |
ITM LSR: Present Mask
#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) |
ITM LSR: Present Mask
#define ITM_LSR_PRESENT_Pos 0U |
ITM LSR: Present Position
#define ITM_LSR_PRESENT_Pos 0U |
ITM LSR: Present Position
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
#define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
#define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
#define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
#define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
#define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
#define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
#define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
#define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
#define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
#define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
#define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
#define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
#define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
#define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
#define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
#define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPrescale Mask
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPrescale Mask
#define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPrescale Position
#define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPrescale Position
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
#define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
#define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position