Type definitions for the System Control Block Registers. More...

Modules
	System Controls not in SCB (SCnSCB)
	Type definitions for the System Control and ID Register not in the SCB.

Data Structures
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	SCB_ITCMCR_SZ_Pos 3U

#define	SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

#define	SCB_ITCMCR_RETEN_Pos 2U

#define	SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

#define	SCB_ITCMCR_RMW_Pos 1U

#define	SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

#define	SCB_ITCMCR_EN_Pos 0U

#define	SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/)

#define	SCB_DTCMCR_SZ_Pos 3U

#define	SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

#define	SCB_DTCMCR_RETEN_Pos 2U

#define	SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

#define	SCB_DTCMCR_RMW_Pos 1U

#define	SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

#define	SCB_DTCMCR_EN_Pos 0U

#define	SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/)

#define	SCB_AHBPCR_SZ_Pos 1U

#define	SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

#define	SCB_AHBPCR_EN_Pos 0U

#define	SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/)

#define	SCB_CACR_FORCEWT_Pos 2U

#define	SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

#define	SCB_CACR_ECCEN_Pos 1U

#define	SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

#define	SCB_CACR_ECCDIS_Pos 1U

#define	SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos)

#define	SCB_CACR_SIWT_Pos 0U

#define	SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/)

#define	SCB_AHBSCR_INITCOUNT_Pos 11U

#define	SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)

#define	SCB_AHBSCR_TPRI_Pos 2U

#define	SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos)

#define	SCB_AHBSCR_CTL_Pos 0U

#define	SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBSCR_CTL_Pos/)

#define	SCB_ABFSR_AXIMTYPE_Pos 8U

#define	SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

#define	SCB_ABFSR_EPPB_Pos 4U

#define	SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

#define	SCB_ABFSR_AXIM_Pos 3U

#define	SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

#define	SCB_ABFSR_AHBP_Pos 2U

#define	SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

#define	SCB_ABFSR_DTCM_Pos 1U

#define	SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

#define	SCB_ABFSR_ITCM_Pos 0U

#define	SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/)

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

◆ SCB_ABFSR_AHBP_Msk

#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

◆ SCB_ABFSR_AHBP_Pos

#define SCB_ABFSR_AHBP_Pos 2U

SCB ABFSR: AHBP Position

◆ SCB_ABFSR_AXIM_Msk

#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

◆ SCB_ABFSR_AXIM_Pos

#define SCB_ABFSR_AXIM_Pos 3U

SCB ABFSR: AXIM Position

◆ SCB_ABFSR_AXIMTYPE_Msk

#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

◆ SCB_ABFSR_AXIMTYPE_Pos

#define SCB_ABFSR_AXIMTYPE_Pos 8U

SCB ABFSR: AXIMTYPE Position

◆ SCB_ABFSR_DTCM_Msk

#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

◆ SCB_ABFSR_DTCM_Pos

#define SCB_ABFSR_DTCM_Pos 1U

SCB ABFSR: DTCM Position

◆ SCB_ABFSR_EPPB_Msk

#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

◆ SCB_ABFSR_EPPB_Pos

#define SCB_ABFSR_EPPB_Pos 4U

SCB ABFSR: EPPB Position

◆ SCB_ABFSR_ITCM_Msk

#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

◆ SCB_ABFSR_ITCM_Pos

#define SCB_ABFSR_ITCM_Pos 0U

SCB ABFSR: ITCM Position

◆ SCB_AHBPCR_EN_Msk

#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

◆ SCB_AHBPCR_EN_Pos

#define SCB_AHBPCR_EN_Pos 0U

SCB AHBPCR: EN Position

◆ SCB_AHBPCR_SZ_Msk

#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

◆ SCB_AHBPCR_SZ_Pos

#define SCB_AHBPCR_SZ_Pos 1U

SCB AHBPCR: SZ Position

◆ SCB_AHBSCR_CTL_Msk

#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

◆ SCB_AHBSCR_CTL_Pos

#define SCB_AHBSCR_CTL_Pos 0U

SCB AHBSCR: CTL Position

◆ SCB_AHBSCR_INITCOUNT_Msk

#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

◆ SCB_AHBSCR_INITCOUNT_Pos

#define SCB_AHBSCR_INITCOUNT_Pos 11U

SCB AHBSCR: INITCOUNT Position

◆ SCB_AHBSCR_TPRI_Msk

#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

◆ SCB_AHBSCR_TPRI_Pos

#define SCB_AHBSCR_TPRI_Pos 2U

SCB AHBSCR: TPRI Position

◆ SCB_AIRCR_ENDIANESS_Msk [1/2]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [2/2]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Pos [1/2]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [2/2]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_PRIGROUP_Msk [1/2]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [2/2]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Pos [1/2]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [2/2]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/2]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/2]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/2]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/2]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/2]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/2]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/2]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/2]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTKEY_Msk [1/2]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [2/2]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Pos [1/2]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [2/2]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/2]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/2]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/2]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/2]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTRESET_Msk [1/2]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [2/2]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Pos [1/2]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [2/2]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

◆ SCB_CACR_ECCDIS_Msk

#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos)

SCB CACR: ECCDIS Mask

◆ SCB_CACR_ECCDIS_Pos

#define SCB_CACR_ECCDIS_Pos 1U

SCB CACR: ECCDIS Position

◆ SCB_CACR_ECCEN_Msk

#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

Deprecated:: SCB CACR: ECCEN Mask

◆ SCB_CACR_ECCEN_Pos

#define SCB_CACR_ECCEN_Pos 1U

Deprecated:: SCB CACR: ECCEN Position

◆ SCB_CACR_FORCEWT_Msk

#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

◆ SCB_CACR_FORCEWT_Pos

#define SCB_CACR_FORCEWT_Pos 2U

SCB CACR: FORCEWT Position

◆ SCB_CACR_SIWT_Msk

#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

◆ SCB_CACR_SIWT_Pos

#define SCB_CACR_SIWT_Pos 0U

SCB CACR: SIWT Position

◆ SCB_CCR_BFHFNMIGN_Msk [1/2]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [2/2]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Pos [1/2]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [2/2]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BP_Msk

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Pos

#define SCB_CCR_BP_Pos 18U

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_DC_Msk

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Pos

#define SCB_CCR_DC_Pos 16U

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DIV_0_TRP_Msk [1/2]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [2/2]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Pos [1/2]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [2/2]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_IC_Msk

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Pos

#define SCB_CCR_IC_Pos 17U

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_NONBASETHRDENA_Msk [1/2]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [2/2]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Pos [1/2]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [2/2]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_STKALIGN_Msk [1/2]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [2/2]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Pos [1/2]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [2/2]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_UNALIGN_TRP_Msk [1/2]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [2/2]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Pos [1/2]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [2/2]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_USERSETMPEND_Msk [1/2]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [2/2]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Pos [1/2]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [2/2]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_LINESIZE_Msk

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Pos

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_NUMSETS_Msk

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Pos

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_RA_Msk

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Pos

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_WA_Msk

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Pos

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WB_Msk

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Pos

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WT_Msk

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Pos

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

◆ SCB_CFSR_BFARVALID_Msk [1/2]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [2/2]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Pos [1/2]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [2/2]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BUSFAULTSR_Msk [1/2]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [2/2]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Pos [1/2]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [2/2]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_DACCVIOL_Msk [1/2]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [2/2]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Pos [1/2]

#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [2/2]

#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DIVBYZERO_Msk [1/2]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [2/2]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Pos [1/2]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [2/2]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_IACCVIOL_Msk [1/2]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [2/2]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Pos [1/2]

#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [2/2]

#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IBUSERR_Msk [1/2]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [2/2]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Pos [1/2]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [2/2]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IMPRECISERR_Msk [1/2]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [2/2]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Pos [1/2]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [2/2]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_INVPC_Msk [1/2]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [2/2]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Pos [1/2]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [2/2]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVSTATE_Msk [1/2]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [2/2]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Pos [1/2]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [2/2]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_LSPERR_Msk [1/2]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [2/2]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Pos [1/2]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [2/2]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_MEMFAULTSR_Msk [1/2]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [2/2]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Pos [1/2]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [2/2]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MLSPERR_Msk [1/2]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [2/2]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Pos [1/2]

#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [2/2]

#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MMARVALID_Msk [1/2]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [2/2]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Pos [1/2]

#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [2/2]

#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MSTKERR_Msk [1/2]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [2/2]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Pos [1/2]

#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [2/2]

#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Msk [1/2]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [2/2]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Pos [1/2]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [2/2]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_NOCP_Msk [1/2]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [2/2]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Pos [1/2]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [2/2]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_PRECISERR_Msk [1/2]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [2/2]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Pos [1/2]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [2/2]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_STKERR_Msk [1/2]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [2/2]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Pos [1/2]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [2/2]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_UNALIGNED_Msk [1/2]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [2/2]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Pos [1/2]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [2/2]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNDEFINSTR_Msk [1/2]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [2/2]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Pos [1/2]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [2/2]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNSTKERR_Msk [1/2]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [2/2]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Pos [1/2]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [2/2]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_USGFAULTSR_Msk [1/2]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [2/2]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Pos [1/2]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [2/2]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CLIDR_LOC_Msk

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Pos

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOUU_Msk

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Pos

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

◆ SCB_CPUID_ARCHITECTURE_Msk [1/2]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [2/2]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Pos [1/2]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [2/2]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_IMPLEMENTER_Msk [1/2]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [2/2]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Pos [1/2]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [2/2]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_PARTNO_Msk [1/2]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [2/2]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Pos [1/2]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [2/2]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_REVISION_Msk [1/2]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [2/2]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Pos [1/2]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [2/2]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_VARIANT_Msk [1/2]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [2/2]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Pos [1/2]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [2/2]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

◆ SCB_CSSELR_IND_Msk

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Pos

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_LEVEL_Msk

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Pos

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

◆ SCB_CTR_CWG_Msk

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Pos

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

◆ SCB_CTR_DMINLINE_Msk

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Pos

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

◆ SCB_CTR_ERG_Msk

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Pos

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

◆ SCB_CTR_FORMAT_Msk

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Pos

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

◆ SCB_CTR_IMINLINE_Msk

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Pos

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

◆ SCB_DCCISW_SET_Msk

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Pos

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_WAY_Msk

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Pos

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

◆ SCB_DCCSW_SET_Msk

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Pos

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_WAY_Msk

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Pos

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

◆ SCB_DCISW_SET_Msk

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Pos

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

◆ SCB_DCISW_WAY_Msk

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Pos

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

◆ SCB_DFSR_BKPT_Msk [1/2]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [2/2]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Pos [1/2]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [2/2]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_DWTTRAP_Msk [1/2]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [2/2]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Pos [1/2]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [2/2]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_EXTERNAL_Msk [1/2]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [2/2]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Pos [1/2]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [2/2]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_HALTED_Msk [1/2]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [2/2]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Pos [1/2]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [2/2]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_VCATCH_Msk [1/2]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [2/2]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Pos [1/2]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [2/2]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

◆ SCB_DTCMCR_EN_Msk

#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

◆ SCB_DTCMCR_EN_Pos

#define SCB_DTCMCR_EN_Pos 0U

SCB DTCMCR: EN Position

◆ SCB_DTCMCR_RETEN_Msk

#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

◆ SCB_DTCMCR_RETEN_Pos

#define SCB_DTCMCR_RETEN_Pos 2U

SCB DTCMCR: RETEN Position

◆ SCB_DTCMCR_RMW_Msk

#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

◆ SCB_DTCMCR_RMW_Pos

#define SCB_DTCMCR_RMW_Pos 1U

SCB DTCMCR: RMW Position

◆ SCB_DTCMCR_SZ_Msk

#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

◆ SCB_DTCMCR_SZ_Pos

#define SCB_DTCMCR_SZ_Pos 3U

SCB DTCMCR: SZ Position

◆ SCB_HFSR_DEBUGEVT_Msk [1/2]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [2/2]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Pos [1/2]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [2/2]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_FORCED_Msk [1/2]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [2/2]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Pos [1/2]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [2/2]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_VECTTBL_Msk [1/2]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [2/2]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Pos [1/2]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [2/2]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

◆ SCB_ICSR_ISRPENDING_Msk [1/2]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [2/2]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Pos [1/2]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [2/2]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPREEMPT_Msk [1/2]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [2/2]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Pos [1/2]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [2/2]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_NMIPENDSET_Msk [1/2]

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [2/2]

#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Pos [1/2]

#define SCB_ICSR_NMIPENDSET_Pos 31U

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [2/2]

#define SCB_ICSR_NMIPENDSET_Pos 31U

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_PENDSTCLR_Msk [1/2]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [2/2]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Pos [1/2]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [2/2]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTSET_Msk [1/2]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [2/2]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Pos [1/2]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [2/2]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSVCLR_Msk [1/2]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [2/2]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Pos [1/2]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [2/2]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVSET_Msk [1/2]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [2/2]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Pos [1/2]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [2/2]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_RETTOBASE_Msk [1/2]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [2/2]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Pos [1/2]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [2/2]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_VECTACTIVE_Msk [1/2]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [2/2]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Pos [1/2]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [2/2]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTPENDING_Msk [1/2]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [2/2]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Pos [1/2]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [2/2]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

◆ SCB_ITCMCR_EN_Msk

#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

◆ SCB_ITCMCR_EN_Pos

#define SCB_ITCMCR_EN_Pos 0U

SCB ITCMCR: EN Position

◆ SCB_ITCMCR_RETEN_Msk

#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

◆ SCB_ITCMCR_RETEN_Pos

#define SCB_ITCMCR_RETEN_Pos 2U

SCB ITCMCR: RETEN Position

◆ SCB_ITCMCR_RMW_Msk

#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

◆ SCB_ITCMCR_RMW_Pos

#define SCB_ITCMCR_RMW_Pos 1U

SCB ITCMCR: RMW Position

◆ SCB_ITCMCR_SZ_Msk

#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

◆ SCB_ITCMCR_SZ_Pos

#define SCB_ITCMCR_SZ_Pos 3U

SCB ITCMCR: SZ Position

◆ SCB_SCR_SEVONPEND_Msk [1/2]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [2/2]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Pos [1/2]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [2/2]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SLEEPDEEP_Msk [1/2]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [2/2]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Pos [1/2]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [2/2]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPONEXIT_Msk [1/2]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [2/2]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Pos [1/2]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [2/2]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SHCSR_BUSFAULTACT_Msk [1/2]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [2/2]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Pos [1/2]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [2/2]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTENA_Msk [1/2]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [2/2]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Pos [1/2]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [2/2]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/2]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/2]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/2]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/2]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTACT_Msk [1/2]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [2/2]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Pos [1/2]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [2/2]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTENA_Msk [1/2]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [2/2]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Pos [1/2]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [2/2]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/2]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/2]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/2]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/2]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MONITORACT_Msk [1/2]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [2/2]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Pos [1/2]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [2/2]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_PENDSVACT_Msk [1/2]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [2/2]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Pos [1/2]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [2/2]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_SVCALLACT_Msk [1/2]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [2/2]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Pos [1/2]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [2/2]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLPENDED_Msk [1/2]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [2/2]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Pos [1/2]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [2/2]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SYSTICKACT_Msk [1/2]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [2/2]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Pos [1/2]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [2/2]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_USGFAULTACT_Msk [1/2]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [2/2]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Pos [1/2]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [2/2]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTENA_Msk [1/2]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [2/2]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Pos [1/2]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [2/2]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/2]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/2]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/2]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/2]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_STIR_INTID_Msk

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Pos

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

◆ SCB_VTOR_TBLOFF_Msk [1/2]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [2/2]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Pos [1/2]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [2/2]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Modules

Data Structures

Detailed Description

Macro Definition Documentation

◆ SCB_ABFSR_AHBP_Msk

◆ SCB_ABFSR_AHBP_Pos

◆ SCB_ABFSR_AXIM_Msk

◆ SCB_ABFSR_AXIM_Pos

◆ SCB_ABFSR_AXIMTYPE_Msk

◆ SCB_ABFSR_AXIMTYPE_Pos

◆ SCB_ABFSR_DTCM_Msk

◆ SCB_ABFSR_DTCM_Pos

◆ SCB_ABFSR_EPPB_Msk

◆ SCB_ABFSR_EPPB_Pos

◆ SCB_ABFSR_ITCM_Msk

◆ SCB_ABFSR_ITCM_Pos

◆ SCB_AHBPCR_EN_Msk

◆ SCB_AHBPCR_EN_Pos

◆ SCB_AHBPCR_SZ_Msk

◆ SCB_AHBPCR_SZ_Pos

◆ SCB_AHBSCR_CTL_Msk

◆ SCB_AHBSCR_CTL_Pos

◆ SCB_AHBSCR_INITCOUNT_Msk

◆ SCB_AHBSCR_INITCOUNT_Pos

◆ SCB_AHBSCR_TPRI_Msk

◆ SCB_AHBSCR_TPRI_Pos

◆ SCB_AIRCR_ENDIANESS_Msk [1/2]

◆ SCB_AIRCR_ENDIANESS_Msk [2/2]

◆ SCB_AIRCR_ENDIANESS_Pos [1/2]

◆ SCB_AIRCR_ENDIANESS_Pos [2/2]

◆ SCB_AIRCR_PRIGROUP_Msk [1/2]

◆ SCB_AIRCR_PRIGROUP_Msk [2/2]

◆ SCB_AIRCR_PRIGROUP_Pos [1/2]

◆ SCB_AIRCR_PRIGROUP_Pos [2/2]

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/2]

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/2]

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/2]

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/2]

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/2]

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/2]

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/2]

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/2]

◆ SCB_AIRCR_VECTKEY_Msk [1/2]

◆ SCB_AIRCR_VECTKEY_Msk [2/2]

◆ SCB_AIRCR_VECTKEY_Pos [1/2]

◆ SCB_AIRCR_VECTKEY_Pos [2/2]

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/2]

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/2]

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/2]

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/2]

◆ SCB_AIRCR_VECTRESET_Msk [1/2]

◆ SCB_AIRCR_VECTRESET_Msk [2/2]

◆ SCB_AIRCR_VECTRESET_Pos [1/2]

◆ SCB_AIRCR_VECTRESET_Pos [2/2]

◆ SCB_CACR_ECCDIS_Msk

◆ SCB_CACR_ECCDIS_Pos

◆ SCB_CACR_ECCEN_Msk

◆ SCB_CACR_ECCEN_Pos

◆ SCB_CACR_FORCEWT_Msk

◆ SCB_CACR_FORCEWT_Pos

◆ SCB_CACR_SIWT_Msk

◆ SCB_CACR_SIWT_Pos

◆ SCB_CCR_BFHFNMIGN_Msk [1/2]

◆ SCB_CCR_BFHFNMIGN_Msk [2/2]

◆ SCB_CCR_BFHFNMIGN_Pos [1/2]

◆ SCB_CCR_BFHFNMIGN_Pos [2/2]

◆ SCB_CCR_BP_Msk

◆ SCB_CCR_BP_Pos

◆ SCB_CCR_DC_Msk

◆ SCB_CCR_DC_Pos

◆ SCB_CCR_DIV_0_TRP_Msk [1/2]

◆ SCB_CCR_DIV_0_TRP_Msk [2/2]

◆ SCB_CCR_DIV_0_TRP_Pos [1/2]

◆ SCB_CCR_DIV_0_TRP_Pos [2/2]

◆ SCB_CCR_IC_Msk

◆ SCB_CCR_IC_Pos

◆ SCB_CCR_NONBASETHRDENA_Msk [1/2]

◆ SCB_CCR_NONBASETHRDENA_Msk [2/2]

◆ SCB_CCR_NONBASETHRDENA_Pos [1/2]

◆ SCB_CCR_NONBASETHRDENA_Pos [2/2]