RTEMS
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bsps
arm
lpc24xx
include
bsp
lpc24xx.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
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#define LIBBSP_ARM_LPC24XX_LPC24XX_H
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#include <rtems/score/cpu.h>
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#include <
bsp/utility.h
>
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#include <
bsp/lpc-i2s.h
>
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#ifdef ARM_MULTILIB_ARCH_V7M
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#include <
bsp/lpc17xx.h
>
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#endif
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#ifdef ARM_MULTILIB_ARCH_V4
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/* Vectored Interrupt Controller (VIC) */
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#define VIC_BASE_ADDR 0xFFFFF000
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#define VICIRQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
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#define VICFIQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004))
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#define VICRawIntr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008))
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#define VICIntSelect (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C))
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#define VICIntEnable (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010))
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#define VICIntEnClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014))
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#define VICSoftInt (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018))
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#define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C))
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#define VICProtection (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020))
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#define VICSWPrioMask (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024))
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#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
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#define VICVectAddr0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
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#define VICVectAddr1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104))
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#define VICVectAddr2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108))
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#define VICVectAddr3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C))
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#define VICVectAddr4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110))
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#define VICVectAddr5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114))
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#define VICVectAddr6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118))
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#define VICVectAddr7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C))
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#define VICVectAddr8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120))
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#define VICVectAddr9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124))
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#define VICVectAddr10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128))
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#define VICVectAddr11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C))
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#define VICVectAddr12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130))
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#define VICVectAddr13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134))
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#define VICVectAddr14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138))
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#define VICVectAddr15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C))
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#define VICVectAddr16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140))
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#define VICVectAddr17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144))
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#define VICVectAddr18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148))
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#define VICVectAddr19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C))
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#define VICVectAddr20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150))
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#define VICVectAddr21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154))
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#define VICVectAddr22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158))
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#define VICVectAddr23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C))
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#define VICVectAddr24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160))
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#define VICVectAddr25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164))
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#define VICVectAddr26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168))
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#define VICVectAddr27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C))
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#define VICVectAddr28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170))
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#define VICVectAddr29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174))
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#define VICVectAddr30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178))
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#define VICVectAddr31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C))
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#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
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#define VICVectPriority0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
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#define VICVectPriority1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204))
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#define VICVectPriority2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208))
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#define VICVectPriority3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C))
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#define VICVectPriority4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210))
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#define VICVectPriority5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214))
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#define VICVectPriority6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218))
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#define VICVectPriority7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C))
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#define VICVectPriority8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220))
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#define VICVectPriority9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224))
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#define VICVectPriority10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228))
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#define VICVectPriority11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C))
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#define VICVectPriority12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230))
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#define VICVectPriority13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234))
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#define VICVectPriority14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238))
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#define VICVectPriority15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C))
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#define VICVectPriority16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240))
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#define VICVectPriority17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244))
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#define VICVectPriority18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248))
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#define VICVectPriority19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C))
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#define VICVectPriority20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250))
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#define VICVectPriority21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254))
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#define VICVectPriority22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258))
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#define VICVectPriority23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C))
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#define VICVectPriority24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260))
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#define VICVectPriority25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264))
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#define VICVectPriority26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268))
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#define VICVectPriority27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C))
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#define VICVectPriority28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270))
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#define VICVectPriority29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274))
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#define VICVectPriority30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278))
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#define VICVectPriority31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C))
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#define VICVectAddr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
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#endif
/* ARM_MULTILIB_ARCH_V4 */
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/* Pin Connect Block */
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#ifdef ARM_MULTILIB_ARCH_V4
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#define PINSEL_BASE_ADDR 0xE002C000
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#else
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#define PINSEL_BASE_ADDR 0x4002C000
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#endif
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#ifdef ARM_MULTILIB_ARCH_V4
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#define PINSEL0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
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#define PINSEL1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
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#define PINSEL2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
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#define PINSEL3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C))
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#define PINSEL4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10))
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#define PINSEL5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14))
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#define PINSEL6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18))
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#define PINSEL7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C))
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#define PINSEL8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20))
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#define PINSEL9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24))
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#define PINSEL10 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28))
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#define PINSEL11 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C))
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#define PINMODE0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40))
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#define PINMODE1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44))
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#define PINMODE2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48))
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#define PINMODE3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C))
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#define PINMODE4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50))
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#define PINMODE5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54))
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#define PINMODE6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58))
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#define PINMODE7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C))
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#define PINMODE8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
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#define PINMODE9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
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#endif
/* ARM_MULTILIB_ARCH_V4 */
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/* General Purpose Input/Output (GPIO) */
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#ifdef ARM_MULTILIB_ARCH_V4
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#define GPIO_BASE_ADDR 0xE0028000
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#else
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#define GPIO_BASE_ADDR 0x40028000
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#endif
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#define IOPIN0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
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#define IOSET0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
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#define IODIR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
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#define IOCLR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C))
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#define IOPIN1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10))
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#define IOSET1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14))
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#define IODIR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18))
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#define IOCLR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C))
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/* GPIO Interrupt Registers */
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#define IO0_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
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#define IO0_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94))
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#define IO0_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84))
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#define IO0_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88))
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#define IO0_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C))
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#define IO2_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
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#define IO2_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4))
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#define IO2_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4))
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#define IO2_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8))
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#define IO2_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC))
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#define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
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#ifdef ARM_MULTILIB_ARCH_V4
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#define PARTCFG_BASE_ADDR 0x3FFF8000
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#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
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#endif
/* ARM_MULTILIB_ARCH_V4 */
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/* Fast I/O setup */
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#ifdef ARM_MULTILIB_ARCH_V4
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#define FIO_BASE_ADDR 0x3FFFC000
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#else
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#define FIO_BASE_ADDR 0x20098000
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#endif
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#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
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#define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
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#define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
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#define FIO0SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18))
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#define FIO0CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C))
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#define FIO1DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
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#define FIO1MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30))
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#define FIO1PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34))
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#define FIO1SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38))
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#define FIO1CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C))
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#define FIO2DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
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#define FIO2MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50))
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#define FIO2PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54))
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#define FIO2SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58))
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#define FIO2CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C))
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#define FIO3DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
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#define FIO3MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70))
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#define FIO3PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74))
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#define FIO3SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78))
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#define FIO3CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C))
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#define FIO4DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
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#define FIO4MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90))
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#define FIO4PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94))
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#define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
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#define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
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#ifdef ARM_MULTILIB_ARCH_V7M
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#define FIO5DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0))
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#define FIO5MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0))
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#define FIO5PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4))
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#define FIO5SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8))
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#define FIO5CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC))
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#endif
/* ARM_MULTILIB_ARCH_V7M */
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/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
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#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00))
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#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20))
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#define FIO2DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x40))
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#define FIO3DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x60))
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#define FIO4DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x80))
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#define FIO0DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
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#define FIO1DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
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#define FIO2DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
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#define FIO3DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
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#define FIO4DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
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#define FIO0DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
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#define FIO1DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
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#define FIO2DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
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#define FIO3DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
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#define FIO4DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
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#define FIO0DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
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#define FIO1DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
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#define FIO2DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
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#define FIO3DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
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#define FIO4DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
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#define FIO0DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
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#define FIO1DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
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#define FIO2DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
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#define FIO3DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
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#define FIO4DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
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#define FIO0DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
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#define FIO1DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
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#define FIO2DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
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#define FIO3DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
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#define FIO4DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
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#define FIO0MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
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#define FIO1MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
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#define FIO2MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
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#define FIO3MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
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#define FIO4MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
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#define FIO0MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
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#define FIO1MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
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#define FIO2MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
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#define FIO3MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
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#define FIO4MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
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#define FIO0MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
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#define FIO1MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
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#define FIO2MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
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#define FIO3MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
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#define FIO4MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
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#define FIO0MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
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#define FIO1MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
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#define FIO2MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
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#define FIO3MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
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#define FIO4MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
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#define FIO0MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
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#define FIO1MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
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#define FIO2MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
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#define FIO3MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
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#define FIO4MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
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#define FIO0MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
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#define FIO1MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
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#define FIO2MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
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#define FIO3MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
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#define FIO4MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
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#define FIO0PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
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#define FIO1PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
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#define FIO2PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
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#define FIO3PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
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#define FIO4PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
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#define FIO0PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
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#define FIO1PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
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#define FIO2PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
344
#define FIO3PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
345
#define FIO4PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
346
347
#define FIO0PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
348
#define FIO1PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
349
#define FIO2PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
350
#define FIO3PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
351
#define FIO4PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
352
353
#define FIO0PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
354
#define FIO1PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
355
#define FIO2PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
356
#define FIO3PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
357
#define FIO4PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
358
359
#define FIO0PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
360
#define FIO1PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
361
#define FIO2PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
362
#define FIO3PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
363
#define FIO4PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
364
365
#define FIO0PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
366
#define FIO1PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
367
#define FIO2PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
368
#define FIO3PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
369
#define FIO4PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
370
371
#define FIO0SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
372
#define FIO1SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
373
#define FIO2SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
374
#define FIO3SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
375
#define FIO4SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
376
377
#define FIO0SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
378
#define FIO1SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
379
#define FIO2SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
380
#define FIO3SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
381
#define FIO4SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
382
383
#define FIO0SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
384
#define FIO1SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
385
#define FIO2SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
386
#define FIO3SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
387
#define FIO4SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
388
389
#define FIO0SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
390
#define FIO1SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
391
#define FIO2SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
392
#define FIO3SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
393
#define FIO4SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
394
395
#define FIO0SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
396
#define FIO1SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
397
#define FIO2SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
398
#define FIO3SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
399
#define FIO4SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
400
401
#define FIO0SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
402
#define FIO1SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
403
#define FIO2SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
404
#define FIO3SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
405
#define FIO4SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
406
407
#define FIO0CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
408
#define FIO1CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
409
#define FIO2CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
410
#define FIO3CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
411
#define FIO4CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
412
413
#define FIO0CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
414
#define FIO1CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
415
#define FIO2CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
416
#define FIO3CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
417
#define FIO4CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
418
419
#define FIO0CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
420
#define FIO1CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
421
#define FIO2CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
422
#define FIO3CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
423
#define FIO4CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
424
425
#define FIO0CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
426
#define FIO1CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
427
#define FIO2CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
428
#define FIO3CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
429
#define FIO4CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
430
431
#define FIO0CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
432
#define FIO1CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
433
#define FIO2CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
434
#define FIO3CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
435
#define FIO4CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
436
437
#define FIO0CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
438
#define FIO1CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
439
#define FIO2CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
440
#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
441
#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
442
443
#ifdef ARM_MULTILIB_ARCH_V4
444
445
/* System Control Block(SCB) modules include Memory Accelerator Module,
446
Phase Locked Loop, VPB divider, Power Control, External Interrupt,
447
Reset, and Code Security/Debugging */
448
#define SCB_BASE_ADDR 0xE01FC000
449
450
/* Memory Accelerator Module (MAM) */
451
#define MAMCR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000))
452
#define MAMTIM (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004))
453
#define MEMMAP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040))
454
455
/* Phase Locked Loop (PLL) */
456
#define PLLCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080))
457
#define PLLCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084))
458
#define PLLSTAT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088))
459
#define PLLFEED (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C))
460
461
/* Power Control */
462
#define PCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0))
463
#define PCONP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4))
464
465
/* Clock Divider */
466
// #define APBDIV (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100))
467
#define CCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104))
468
#define USBCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108))
469
#define CLKSRCSEL (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C))
470
#define PCLKSEL0 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8))
471
#define PCLKSEL1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC))
472
473
/* External Interrupts */
474
#define EXTINT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140))
475
#define INTWAKE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144))
476
#define EXTMODE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148))
477
#define EXTPOLAR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C))
478
479
/* Reset, reset source identification */
480
#define RSIR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180))
481
482
/* RSID, code security protection */
483
#define CSPR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184))
484
485
/* AHB configuration */
486
#define AHBCFG1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188))
487
#define AHBCFG2 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C))
488
489
/* System Controls and Status */
490
#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
491
492
#endif
/* ARM_MULTILIB_ARCH_V4 */
493
494
/* External Memory Controller (EMC) */
495
#ifdef ARM_MULTILIB_ARCH_V4
496
#define EMC_BASE_ADDR 0xFFE08000
497
#else
498
#define EMC_BASE_ADDR 0x2009c000
499
#endif
500
#define EMC_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
501
#define EMC_STAT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
502
#define EMC_CONFIG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
503
504
/* Dynamic RAM access registers */
505
#define EMC_DYN_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020))
506
#define EMC_DYN_RFSH (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024))
507
#define EMC_DYN_RD_CFG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028))
508
#define EMC_DYN_RP (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030))
509
#define EMC_DYN_RAS (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034))
510
#define EMC_DYN_SREX (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038))
511
#define EMC_DYN_APR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C))
512
#define EMC_DYN_DAL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040))
513
#define EMC_DYN_WR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044))
514
#define EMC_DYN_RC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048))
515
#define EMC_DYN_RFC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C))
516
#define EMC_DYN_XSR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050))
517
#define EMC_DYN_RRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054))
518
#define EMC_DYN_MRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058))
519
520
#define EMC_DYN_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100))
521
#define EMC_DYN_RASCAS0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104))
522
#define EMC_DYN_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140))
523
#define EMC_DYN_RASCAS1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144))
524
#define EMC_DYN_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160))
525
#define EMC_DYN_RASCAS2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164))
526
#define EMC_DYN_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180))
527
#define EMC_DYN_RASCAS3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184))
528
529
/* static RAM access registers */
530
#define EMC_STA_BASE_0 ((uint32_t *) (EMC_BASE_ADDR + 0x200))
531
#define EMC_STA_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200))
532
#define EMC_STA_WAITWEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204))
533
#define EMC_STA_WAITOEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208))
534
#define EMC_STA_WAITRD0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C))
535
#define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210))
536
#define EMC_STA_WAITWR0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214))
537
#define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218))
538
539
#define EMC_STA_BASE_1 ((uint32_t *) (EMC_BASE_ADDR + 0x220))
540
#define EMC_STA_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220))
541
#define EMC_STA_WAITWEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224))
542
#define EMC_STA_WAITOEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228))
543
#define EMC_STA_WAITRD1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C))
544
#define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230))
545
#define EMC_STA_WAITWR1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234))
546
#define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238))
547
548
#define EMC_STA_BASE_2 ((uint32_t *) (EMC_BASE_ADDR + 0x240))
549
#define EMC_STA_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240))
550
#define EMC_STA_WAITWEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244))
551
#define EMC_STA_WAITOEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248))
552
#define EMC_STA_WAITRD2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C))
553
#define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250))
554
#define EMC_STA_WAITWR2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254))
555
#define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258))
556
557
#define EMC_STA_BASE_3 ((uint32_t *) (EMC_BASE_ADDR + 0x260))
558
#define EMC_STA_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260))
559
#define EMC_STA_WAITWEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264))
560
#define EMC_STA_WAITOEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268))
561
#define EMC_STA_WAITRD3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C))
562
#define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270))
563
#define EMC_STA_WAITWR3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274))
564
#define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278))
565
566
#define EMC_STA_EXT_WAIT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880))
567
568
569
/* Timer 0 */
570
#ifdef ARM_MULTILIB_ARCH_V4
571
#define TMR0_BASE_ADDR 0xE0004000
572
#else
573
#define TMR0_BASE_ADDR 0x40004000
574
#endif
575
#define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
576
#define T0TCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
577
#define T0TC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
578
#define T0PR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C))
579
#define T0PC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10))
580
#define T0MCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14))
581
#define T0MR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18))
582
#define T0MR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C))
583
#define T0MR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20))
584
#define T0MR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24))
585
#define T0CCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28))
586
#define T0CR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C))
587
#define T0CR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30))
588
#define T0CR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34))
589
#define T0CR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38))
590
#define T0EMR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C))
591
#define T0CTCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
592
593
/* Timer 1 */
594
#ifdef ARM_MULTILIB_ARCH_V4
595
#define TMR1_BASE_ADDR 0xE0008000
596
#else
597
#define TMR1_BASE_ADDR 0x40008000
598
#endif
599
#define T1IR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
600
#define T1TCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
601
#define T1TC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
602
#define T1PR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C))
603
#define T1PC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10))
604
#define T1MCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14))
605
#define T1MR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18))
606
#define T1MR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C))
607
#define T1MR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20))
608
#define T1MR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24))
609
#define T1CCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28))
610
#define T1CR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C))
611
#define T1CR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30))
612
#define T1CR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34))
613
#define T1CR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38))
614
#define T1EMR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C))
615
#define T1CTCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
616
617
/* Timer 2 */
618
#ifdef ARM_MULTILIB_ARCH_V4
619
#define TMR2_BASE_ADDR 0xE0070000
620
#else
621
#define TMR2_BASE_ADDR 0x40090000
622
#endif
623
#define T2IR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
624
#define T2TCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
625
#define T2TC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
626
#define T2PR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C))
627
#define T2PC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10))
628
#define T2MCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14))
629
#define T2MR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18))
630
#define T2MR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C))
631
#define T2MR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20))
632
#define T2MR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24))
633
#define T2CCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28))
634
#define T2CR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C))
635
#define T2CR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30))
636
#define T2CR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34))
637
#define T2CR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38))
638
#define T2EMR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C))
639
#define T2CTCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
640
641
/* Timer 3 */
642
#ifdef ARM_MULTILIB_ARCH_V4
643
#define TMR3_BASE_ADDR 0xE0074000
644
#else
645
#define TMR3_BASE_ADDR 0x40094000
646
#endif
647
#define T3IR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
648
#define T3TCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
649
#define T3TC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
650
#define T3PR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C))
651
#define T3PC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10))
652
#define T3MCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14))
653
#define T3MR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18))
654
#define T3MR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C))
655
#define T3MR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20))
656
#define T3MR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24))
657
#define T3CCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28))
658
#define T3CR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C))
659
#define T3CR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30))
660
#define T3CR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34))
661
#define T3CR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38))
662
#define T3EMR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C))
663
#define T3CTCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70))
664
665
666
/* Pulse Width Modulator (PWM) */
667
#ifdef ARM_MULTILIB_ARCH_V4
668
#define PWM0_BASE_ADDR 0xE0014000
669
#else
670
#define PWM0_BASE_ADDR 0x40014000
671
#endif
672
#define PWM0IR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
673
#define PWM0TCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
674
#define PWM0TC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
675
#define PWM0PR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C))
676
#define PWM0PC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10))
677
#define PWM0MCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14))
678
#define PWM0MR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18))
679
#define PWM0MR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C))
680
#define PWM0MR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20))
681
#define PWM0MR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24))
682
#define PWM0CCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28))
683
#define PWM0CR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C))
684
#define PWM0CR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30))
685
#define PWM0CR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34))
686
#define PWM0CR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38))
687
#define PWM0EMR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C))
688
#define PWM0MR4 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40))
689
#define PWM0MR5 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44))
690
#define PWM0MR6 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48))
691
#define PWM0PCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C))
692
#define PWM0LER (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
693
#define PWM0CTCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
694
695
#ifdef ARM_MULTILIB_ARCH_V4
696
#define PWM1_BASE_ADDR 0xE0018000
697
#else
698
#define PWM1_BASE_ADDR 0x40018000
699
#endif
700
#define PWM1IR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
701
#define PWM1TCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
702
#define PWM1TC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
703
#define PWM1PR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C))
704
#define PWM1PC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10))
705
#define PWM1MCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14))
706
#define PWM1MR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18))
707
#define PWM1MR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C))
708
#define PWM1MR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20))
709
#define PWM1MR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24))
710
#define PWM1CCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28))
711
#define PWM1CR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C))
712
#define PWM1CR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30))
713
#define PWM1CR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34))
714
#define PWM1CR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38))
715
#define PWM1EMR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C))
716
#define PWM1MR4 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40))
717
#define PWM1MR5 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44))
718
#define PWM1MR6 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48))
719
#define PWM1PCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C))
720
#define PWM1LER (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50))
721
#define PWM1CTCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70))
722
723
724
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
725
#ifdef ARM_MULTILIB_ARCH_V4
726
#define UART0_BASE_ADDR 0xE000C000
727
#else
728
#define UART0_BASE_ADDR 0x4000C000
729
#endif
730
#define U0RBR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
731
#define U0THR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
732
#define U0DLL (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
733
#define U0DLM (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
734
#define U0IER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
735
#define U0IIR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
736
#define U0FCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
737
#define U0LCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C))
738
#define U0LSR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14))
739
#define U0SCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C))
740
#define U0ACR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20))
741
#define U0ICR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24))
742
#define U0FDR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28))
743
#define U0TER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
744
745
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
746
#ifdef ARM_MULTILIB_ARCH_V4
747
#define UART1_BASE_ADDR 0xE0010000
748
#else
749
#define UART1_BASE_ADDR 0x40010000
750
#endif
751
#define U1RBR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
752
#define U1THR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
753
#define U1DLL (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
754
#define U1DLM (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
755
#define U1IER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
756
#define U1IIR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
757
#define U1FCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
758
#define U1LCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C))
759
#define U1MCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10))
760
#define U1LSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14))
761
#define U1MSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18))
762
#define U1SCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C))
763
#define U1ACR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20))
764
#define U1FDR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28))
765
#define U1TER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
766
767
/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
768
#ifdef ARM_MULTILIB_ARCH_V4
769
#define UART2_BASE_ADDR 0xE0078000
770
#else
771
#define UART2_BASE_ADDR 0x40098000
772
#endif
773
#define U2RBR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
774
#define U2THR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
775
#define U2DLL (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
776
#define U2DLM (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
777
#define U2IER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
778
#define U2IIR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
779
#define U2FCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
780
#define U2LCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C))
781
#define U2LSR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14))
782
#define U2SCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C))
783
#define U2ACR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20))
784
#define U2ICR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24))
785
#define U2FDR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28))
786
#define U2TER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
787
788
/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
789
#ifdef ARM_MULTILIB_ARCH_V4
790
#define UART3_BASE_ADDR 0xE007C000
791
#else
792
#define UART3_BASE_ADDR 0x4009C000
793
#endif
794
#define U3RBR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
795
#define U3THR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
796
#define U3DLL (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
797
#define U3DLM (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
798
#define U3IER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
799
#define U3IIR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
800
#define U3FCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
801
#define U3LCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C))
802
#define U3LSR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14))
803
#define U3SCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C))
804
#define U3ACR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20))
805
#define U3ICR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24))
806
#define U3FDR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28))
807
#define U3TER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
808
809
/* I2C Interface 0 */
810
#ifdef ARM_MULTILIB_ARCH_V4
811
#define I2C0_BASE_ADDR 0xE001C000
812
#else
813
#define I2C0_BASE_ADDR 0x4001C000
814
#endif
815
#define I20CONSET (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
816
#define I20STAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
817
#define I20DAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
818
#define I20ADR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C))
819
#define I20SCLH (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10))
820
#define I20SCLL (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14))
821
#define I20CONCLR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
822
823
/* I2C Interface 1 */
824
#ifdef ARM_MULTILIB_ARCH_V4
825
#define I2C1_BASE_ADDR 0xE005C000
826
#else
827
#define I2C1_BASE_ADDR 0x4005C000
828
#endif
829
#define I21CONSET (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
830
#define I21STAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
831
#define I21DAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
832
#define I21ADR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C))
833
#define I21SCLH (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10))
834
#define I21SCLL (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14))
835
#define I21CONCLR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
836
837
/* I2C Interface 2 */
838
#ifdef ARM_MULTILIB_ARCH_V4
839
#define I2C2_BASE_ADDR 0xE0080000
840
#else
841
#define I2C2_BASE_ADDR 0x400a0000
842
#endif
843
#define I22CONSET (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
844
#define I22STAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
845
#define I22DAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
846
#define I22ADR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C))
847
#define I22SCLH (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10))
848
#define I22SCLL (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14))
849
#define I22CONCLR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18))
850
851
/* SPI0 (Serial Peripheral Interface 0) */
852
#define SPI0_BASE_ADDR 0xE0020000
853
#define S0SPCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00))
854
#define S0SPSR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04))
855
#define S0SPDR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08))
856
#define S0SPCCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C))
857
#define S0SPINT (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
858
859
/* SSP0 Controller */
860
#ifdef ARM_MULTILIB_ARCH_V4
861
#define SSP0_BASE_ADDR 0xE0068000
862
#else
863
#define SSP0_BASE_ADDR 0x40088000
864
#endif
865
#define SSP0CR0 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
866
#define SSP0CR1 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
867
#define SSP0DR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
868
#define SSP0SR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C))
869
#define SSP0CPSR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10))
870
#define SSP0IMSC (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14))
871
#define SSP0RIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18))
872
#define SSP0MIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C))
873
#define SSP0ICR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20))
874
#define SSP0DMACR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
875
876
/* SSP1 Controller */
877
#ifdef ARM_MULTILIB_ARCH_V4
878
#define SSP1_BASE_ADDR 0xE0030000
879
#else
880
#define SSP1_BASE_ADDR 0x40030000
881
#endif
882
#define SSP1CR0 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
883
#define SSP1CR1 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
884
#define SSP1DR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
885
#define SSP1SR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C))
886
#define SSP1CPSR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10))
887
#define SSP1IMSC (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14))
888
#define SSP1RIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18))
889
#define SSP1MIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C))
890
#define SSP1ICR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
891
#define SSP1DMACR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
892
893
#ifdef ARM_MULTILIB_ARCH_V7M
894
895
/* SSP2 Controller */
896
#define SSP2_BASE_ADDR 0x400ac000
897
#define SSP2CR0 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00))
898
#define SSP2CR1 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04))
899
#define SSP2DR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08))
900
#define SSP2SR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C))
901
#define SSP2CPSR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10))
902
#define SSP2IMSC (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14))
903
#define SSP2RIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18))
904
#define SSP2MIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C))
905
#define SSP2ICR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20))
906
#define SSP2DMACR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24))
907
908
#endif
/* ARM_MULTILIB_ARCH_V4 */
909
910
/* Real Time Clock */
911
#ifdef ARM_MULTILIB_ARCH_V4
912
#define RTC_BASE_ADDR 0xE0024000
913
#else
914
#define RTC_BASE_ADDR 0x40024000
915
#endif
916
#define RTC_ILR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
917
#define RTC_CTC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
918
#define RTC_CCR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
919
#define RTC_CIIR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C))
920
#define RTC_AMR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10))
921
#define RTC_CTIME0 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14))
922
#define RTC_CTIME1 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18))
923
#define RTC_CTIME2 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C))
924
#define RTC_SEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20))
925
#define RTC_MIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24))
926
#define RTC_HOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28))
927
#define RTC_DOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C))
928
#define RTC_DOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30))
929
#define RTC_DOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34))
930
#define RTC_MONTH (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38))
931
#define RTC_YEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C))
932
#define RTC_CISS (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40))
933
#define RTC_ALSEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60))
934
#define RTC_ALMIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64))
935
#define RTC_ALHOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68))
936
#define RTC_ALDOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C))
937
#define RTC_ALDOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70))
938
#define RTC_ALDOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74))
939
#define RTC_ALMON (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78))
940
#define RTC_ALYEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C))
941
#define RTC_PREINT (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80))
942
#define RTC_PREFRAC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84))
943
944
945
/* A/D Converter 0 (AD0) */
946
#ifdef ARM_MULTILIB_ARCH_V4
947
#define AD0_BASE_ADDR 0xE0034000
948
#else
949
#define AD0_BASE_ADDR 0x40034000
950
#endif
951
#define AD0CR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
952
#define AD0GDR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
953
#define AD0INTEN (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
954
#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
955
#define AD0DR0 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
956
#define AD0DR1 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14))
957
#define AD0DR2 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18))
958
#define AD0DR3 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C))
959
#define AD0DR4 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20))
960
#define AD0DR5 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24))
961
#define AD0DR6 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28))
962
#define AD0DR7 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C))
963
#define AD0STAT (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30))
964
965
966
/* D/A Converter */
967
#ifdef ARM_MULTILIB_ARCH_V4
968
#define DAC_BASE_ADDR 0xE006C000
969
#else
970
#define DAC_BASE_ADDR 0x4008C000
971
#endif
972
#define DACR (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
973
974
975
/* Watchdog */
976
#ifdef ARM_MULTILIB_ARCH_V4
977
#define WDG_BASE_ADDR 0xE0000000
978
#else
979
#define WDG_BASE_ADDR 0x40000000
980
#endif
981
#define WDMOD (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
982
#define WDTC (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
983
#define WDFEED (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
984
#define WDTV (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C))
985
#define WDCLKSEL (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
986
987
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
988
#ifdef ARM_MULTILIB_ARCH_V4
989
#define CAN_ACCEPT_BASE_ADDR 0xE003C000
990
#else
991
#define CAN_ACCEPT_BASE_ADDR 0x4003C000
992
#endif
993
#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
994
#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
995
#define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
996
#define CAN_EFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C))
997
#define CAN_EFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))
998
#define CAN_EOT (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14))
999
#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
1000
#define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
1001
1002
#ifdef ARM_MULTILIB_ARCH_V4
1003
#define CAN_CENTRAL_BASE_ADDR 0xE0040000
1004
#else
1005
#define CAN_CENTRAL_BASE_ADDR 0x40040000
1006
#endif
1007
#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
1008
#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
1009
#define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
1010
1011
#ifdef ARM_MULTILIB_ARCH_V4
1012
#define CAN1_BASE_ADDR 0xE0044000
1013
#else
1014
#define CAN1_BASE_ADDR 0x40044000
1015
#endif
1016
#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
1017
#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
1018
#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
1019
#define CAN1ICR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))
1020
#define CAN1IER (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10))
1021
#define CAN1BTR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))
1022
#define CAN1EWL (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))
1023
#define CAN1SR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))
1024
#define CAN1RFS (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))
1025
#define CAN1RID (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24))
1026
#define CAN1RDA (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))
1027
#define CAN1RDB (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C))
1028
1029
#define CAN1TFI1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))
1030
#define CAN1TID1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))
1031
#define CAN1TDA1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38))
1032
#define CAN1TDB1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))
1033
#define CAN1TFI2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))
1034
#define CAN1TID2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))
1035
#define CAN1TDA2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))
1036
#define CAN1TDB2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C))
1037
#define CAN1TFI3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))
1038
#define CAN1TID3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))
1039
#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
1040
#define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
1041
1042
#ifdef ARM_MULTILIB_ARCH_V4
1043
#define CAN2_BASE_ADDR 0xE0048000
1044
#else
1045
#define CAN2_BASE_ADDR 0x40048000
1046
#endif
1047
#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
1048
#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
1049
#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
1050
#define CAN2ICR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))
1051
#define CAN2IER (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10))
1052
#define CAN2BTR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))
1053
#define CAN2EWL (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))
1054
#define CAN2SR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))
1055
#define CAN2RFS (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))
1056
#define CAN2RID (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24))
1057
#define CAN2RDA (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))
1058
#define CAN2RDB (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C))
1059
1060
#define CAN2TFI1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))
1061
#define CAN2TID1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))
1062
#define CAN2TDA1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38))
1063
#define CAN2TDB1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))
1064
#define CAN2TFI2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))
1065
#define CAN2TID2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))
1066
#define CAN2TDA2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))
1067
#define CAN2TDB2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C))
1068
#define CAN2TFI3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))
1069
#define CAN2TID3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))
1070
#define CAN2TDA3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))
1071
#define CAN2TDB3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C))
1072
1073
1074
/* MultiMedia Card Interface(MCI) Controller */
1075
#ifdef ARM_MULTILIB_ARCH_V4
1076
#define MCI_BASE_ADDR 0xE008C000
1077
#else
1078
#define MCI_BASE_ADDR 0x400c0000
1079
#endif
1080
#define MCI_POWER (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
1081
#define MCI_CLOCK (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
1082
#define MCI_ARGUMENT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
1083
#define MCI_COMMAND (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C))
1084
#define MCI_RESP_CMD (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10))
1085
#define MCI_RESP0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14))
1086
#define MCI_RESP1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18))
1087
#define MCI_RESP2 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C))
1088
#define MCI_RESP3 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20))
1089
#define MCI_DATA_TMR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24))
1090
#define MCI_DATA_LEN (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28))
1091
#define MCI_DATA_CTRL (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C))
1092
#define MCI_DATA_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30))
1093
#define MCI_STATUS (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34))
1094
#define MCI_CLEAR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38))
1095
#define MCI_MASK0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C))
1096
#define MCI_MASK1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40))
1097
#define MCI_FIFO_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48))
1098
#define MCI_FIFO (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80))
1099
1100
1101
/* I2S Interface Controller (I2S) */
1102
#ifdef ARM_MULTILIB_ARCH_V4
1103
#define I2S_BASE_ADDR 0xE0088000
1104
#else
1105
#define I2S_BASE_ADDR 0x400a8000
1106
#endif
1107
#define I2S_DAO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
1108
#define I2S_DAI (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
1109
#define I2S_TX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
1110
#define I2S_RX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C))
1111
#define I2S_STATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10))
1112
#define I2S_DMA1 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14))
1113
#define I2S_DMA2 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18))
1114
#define I2S_IRQ (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C))
1115
#define I2S_TXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20))
1116
#define I2S_RXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24))
1117
1118
1119
/* General-purpose DMA Controller */
1120
#ifdef ARM_MULTILIB_ARCH_V4
1121
#define DMA_BASE_ADDR 0xFFE04000
1122
#else
1123
#define DMA_BASE_ADDR 0x20080000
1124
#endif
1125
#define GPDMA_INT_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
1126
#define GPDMA_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
1127
#define GPDMA_INT_TCCLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
1128
#define GPDMA_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C))
1129
#define GPDMA_INT_ERR_CLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010))
1130
#define GPDMA_RAW_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014))
1131
#define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018))
1132
#define GPDMA_ENABLED_CHNS (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C))
1133
#define GPDMA_SOFT_BREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020))
1134
#define GPDMA_SOFT_SREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024))
1135
#define GPDMA_SOFT_LBREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028))
1136
#define GPDMA_SOFT_LSREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C))
1137
#define GPDMA_CONFIG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030))
1138
#define GPDMA_SYNC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034))
1139
1140
/* DMA channel 0 registers */
1141
#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
1142
#define GPDMA_CH0_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
1143
#define GPDMA_CH0_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
1144
#define GPDMA_CH0_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108))
1145
#define GPDMA_CH0_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C))
1146
#define GPDMA_CH0_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110))
1147
1148
/* DMA channel 1 registers */
1149
#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
1150
#define GPDMA_CH1_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
1151
#define GPDMA_CH1_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
1152
#define GPDMA_CH1_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128))
1153
#define GPDMA_CH1_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
1154
#define GPDMA_CH1_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
1155
1156
/* USB Controller */
1157
#ifdef ARM_MULTILIB_ARCH_V4
1158
#define USB_INT_BASE_ADDR 0xE01FC1C0
1159
#define USB_BASE_ADDR 0xFFE0C200
/* USB Base Address */
1160
#else
1161
#define USB_INT_BASE_ADDR 0x400fc1c0
1162
#define USB_BASE_ADDR 0x2008c200
1163
#endif
1164
1165
#define USB_INT_STAT (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
1166
1167
/* USB Device Interrupt Registers */
1168
#define DEV_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00))
1169
#define DEV_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04))
1170
#define DEV_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08))
1171
#define DEV_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C))
1172
#define DEV_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C))
1173
1174
/* USB Device Endpoint Interrupt Registers */
1175
#define EP_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30))
1176
#define EP_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34))
1177
#define EP_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38))
1178
#define EP_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C))
1179
#define EP_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40))
1180
1181
/* USB Device Endpoint Realization Registers */
1182
#define REALIZE_EP (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44))
1183
#define EP_INDEX (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48))
1184
#define MAXPACKET_SIZE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C))
1185
1186
/* USB Device Command Reagisters */
1187
#define CMD_CODE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10))
1188
#define CMD_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14))
1189
1190
/* USB Device Data Transfer Registers */
1191
#define RX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18))
1192
#define TX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C))
1193
#define RX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20))
1194
#define TX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24))
1195
#define USB_CTRL (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28))
1196
1197
/* USB Device DMA Registers */
1198
#define DMA_REQ_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50))
1199
#define DMA_REQ_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54))
1200
#define DMA_REQ_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58))
1201
#define UDCA_HEAD (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80))
1202
#define EP_DMA_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84))
1203
#define EP_DMA_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88))
1204
#define EP_DMA_DIS (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C))
1205
#define DMA_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90))
1206
#define DMA_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94))
1207
#define EOT_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0))
1208
#define EOT_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4))
1209
#define EOT_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8))
1210
#define NDD_REQ_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC))
1211
#define NDD_REQ_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0))
1212
#define NDD_REQ_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4))
1213
#define SYS_ERR_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8))
1214
#define SYS_ERR_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
1215
#define SYS_ERR_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
1216
1217
/* USB Host Controller */
1218
#ifdef ARM_MULTILIB_ARCH_V4
1219
#define USBHC_BASE_ADDR 0xFFE0C000
1220
#else
1221
#define USBHC_BASE_ADDR 0x2008c000
1222
#endif
1223
#define HC_REVISION (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
1224
#define HC_CONTROL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
1225
#define HC_CMD_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
1226
#define HC_INT_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C))
1227
#define HC_INT_EN (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10))
1228
#define HC_INT_DIS (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14))
1229
#define HC_HCCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18))
1230
#define HC_PERIOD_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C))
1231
#define HC_CTRL_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20))
1232
#define HC_CTRL_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24))
1233
#define HC_BULK_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28))
1234
#define HC_BULK_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C))
1235
#define HC_DONE_HEAD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30))
1236
#define HC_FM_INTERVAL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34))
1237
#define HC_FM_REMAINING (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38))
1238
#define HC_FM_NUMBER (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C))
1239
#define HC_PERIOD_START (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40))
1240
#define HC_LS_THRHLD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44))
1241
#define HC_RH_DESCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48))
1242
#define HC_RH_DESCB (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C))
1243
#define HC_RH_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50))
1244
#define HC_RH_PORT_STAT1 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54))
1245
#define HC_RH_PORT_STAT2 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
1246
1247
/* USB OTG Controller */
1248
#ifdef ARM_MULTILIB_ARCH_V4
1249
#define USBOTG_BASE_ADDR 0xFFE0C100
1250
#else
1251
#define USBOTG_BASE_ADDR 0x2008c100
1252
#endif
1253
#define OTG_INT_STAT (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
1254
#define OTG_INT_EN (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
1255
#define OTG_INT_SET (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
1256
#define OTG_INT_CLR (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C))
1257
#define OTG_STAT_CTRL (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
1258
#define OTG_TIMER (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
1259
1260
#ifdef ARM_MULTILIB_ARCH_V4
1261
#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1262
#else
1263
#define USBOTG_I2C_BASE_ADDR 0x2008c300
1264
#endif
1265
#define OTG_I2C_RX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1266
#define OTG_I2C_TX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1267
#define OTG_I2C_STS (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
1268
#define OTG_I2C_CTL (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08))
1269
#define OTG_I2C_CLKHI (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
1270
#define OTG_I2C_CLKLO (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
1271
1272
#ifdef ARM_MULTILIB_ARCH_V4
1273
#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1274
#else
1275
#define USBOTG_CLK_BASE_ADDR 0x2008cff0
1276
#endif
1277
#define OTG_CLK_CTRL (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
1278
#define OTG_CLK_STAT (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
1279
1280
/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1281
#ifdef ARM_MULTILIB_ARCH_V4
1282
#define MAC_BASE_ADDR 0xFFE00000
/* AHB Peripheral # 0 */
1283
#else
1284
#define MAC_BASE_ADDR 0x20084000
1285
#endif
1286
#define MAC_MAC1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000))
/* MAC config reg 1 */
1287
#define MAC_MAC2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004))
/* MAC config reg 2 */
1288
#define MAC_IPGT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008))
/* b2b InterPacketGap reg */
1289
#define MAC_IPGR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C))
/* non b2b InterPacketGap reg */
1290
#define MAC_CLRT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010))
/* CoLlision window/ReTry reg */
1291
#define MAC_MAXF (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014))
/* MAXimum Frame reg */
1292
#define MAC_SUPP (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018))
/* PHY SUPPort reg */
1293
#define MAC_TEST (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C))
/* TEST reg */
1294
#define MAC_MCFG (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020))
/* MII Mgmt ConFiG reg */
1295
#define MAC_MCMD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024))
/* MII Mgmt CoMmanD reg */
1296
#define MAC_MADR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028))
/* MII Mgmt ADdRess reg */
1297
#define MAC_MWTD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C))
/* MII Mgmt WriTe Data reg (WO) */
1298
#define MAC_MRDD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030))
/* MII Mgmt ReaD Data reg (RO) */
1299
#define MAC_MIND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034))
/* MII Mgmt INDicators reg (RO) */
1300
1301
#define MAC_SA0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040))
/* Station Address 0 reg */
1302
#define MAC_SA1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044))
/* Station Address 1 reg */
1303
#define MAC_SA2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048))
/* Station Address 2 reg */
1304
1305
#define MAC_COMMAND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100))
/* Command reg */
1306
#define MAC_STATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104))
/* Status reg (RO) */
1307
#define MAC_RXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108))
/* Rx descriptor base address reg */
1308
#define MAC_RXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C))
/* Rx status base address reg */
1309
#define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110))
/* Rx number of descriptors reg */
1310
#define MAC_RXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114))
/* Rx produce index reg (RO) */
1311
#define MAC_RXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118))
/* Rx consume index reg */
1312
#define MAC_TXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C))
/* Tx descriptor base address reg */
1313
#define MAC_TXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120))
/* Tx status base address reg */
1314
#define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124))
/* Tx number of descriptors reg */
1315
#define MAC_TXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128))
/* Tx produce index reg */
1316
#define MAC_TXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C))
/* Tx consume index reg (RO) */
1317
1318
#define MAC_TSV0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158))
/* Tx status vector 0 reg (RO) */
1319
#define MAC_TSV1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C))
/* Tx status vector 1 reg (RO) */
1320
#define MAC_RSV (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160))
/* Rx status vector reg (RO) */
1321
1322
#define MAC_FLOWCONTROLCNT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170))
/* Flow control counter reg */
1323
#define MAC_FLOWCONTROLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174))
/* Flow control status reg */
1324
1325
#define MAC_RXFILTERCTRL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200))
/* Rx filter ctrl reg */
1326
#define MAC_RXFILTERWOLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204))
/* Rx filter WoL status reg (RO) */
1327
#define MAC_RXFILTERWOLCLR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208))
/* Rx filter WoL clear reg (WO) */
1328
1329
#define MAC_HASHFILTERL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210))
/* Hash filter LSBs reg */
1330
#define MAC_HASHFILTERH (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214))
/* Hash filter MSBs reg */
1331
1332
#define MAC_INTSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0))
/* Interrupt status reg (RO) */
1333
#define MAC_INTENABLE (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4))
/* Interrupt enable reg */
1334
#define MAC_INTCLEAR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8))
/* Interrupt clear reg (WO) */
1335
#define MAC_INTSET (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC))
/* Interrupt set reg (WO) */
1336
1337
#define MAC_POWERDOWN (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4))
/* Power-down reg */
1338
#define MAC_MODULEID (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC))
/* Module ID reg (RO) */
1339
1340
/* LCD Controller */
1341
1342
#ifdef ARM_MULTILIB_ARCH_V4
1343
#define LCD_CFG (*(volatile uint32_t *) 0xE01FC1B8)
1344
#define LCD_BASE_ADDR 0xFFE10000
1345
#else
1346
#define LCD_CFG (*(volatile uint32_t *) 0x400FC1B8)
1347
#define LCD_BASE_ADDR 0x20088000
1348
#endif
1349
#define LCD_TIMH (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
1350
#define LCD_TIMV (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
1351
#define LCD_POL (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008))
1352
#define LCD_LE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C))
1353
#define LCD_UPBASE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010))
1354
#define LCD_LPBASE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014))
1355
#define LCD_CTRL (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018))
1356
#define LCD_INTMSK (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C))
1357
#define LCD_INTRAW (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020))
1358
#define LCD_INTSTAT (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024))
1359
#define LCD_INTCLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028))
1360
#define LCD_UPCURR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C))
1361
#define LCD_LPCURR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030))
1362
#define LCD_PAL_ADDR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200))
1363
#define CRSR_IMG (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800))
1364
#define CRSR_CTLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00))
1365
#define CRSR_CFG (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04))
1366
#define CRSR_PAL0 (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08))
1367
#define CRSR_PAL1 (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C))
1368
#define CRSR_XY (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10))
1369
#define CRSR_CLIP (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14))
1370
#define CRSR_INTMSK (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20))
1371
#define CRSR_INTCLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24))
1372
#define CRSR_INTRAW (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28))
1373
#define CRSR_INTSTAT (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C))
1374
1375
/* Register Fields */
1376
1377
#define GET_FIELD( val, mask, shift) \
1378
(((val) & (mask)) >> (shift))
1379
1380
#define SET_FIELD( val, field, mask, shift) \
1381
(((val) & ~(mask)) | (((field) << (shift)) & (mask)))
1382
1383
/* CLKSRCSEL */
1384
1385
#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
1386
1387
#define GET_CLKSRCSEL_CLKSRC(reg) \
1388
GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
1389
1390
#define SET_CLKSRCSEL_CLKSRC(reg, val) \
1391
SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
1392
1393
/* PLLCON */
1394
1395
#define PLLCON_PLLE 0x00000001U
1396
1397
#define PLLCON_PLLC 0x00000002U
1398
1399
/* PLLCFG */
1400
1401
#define PLLCFG_MSEL_MASK 0x00007fffU
1402
1403
#define GET_PLLCFG_MSEL(reg) \
1404
GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
1405
1406
#define SET_PLLCFG_MSEL(reg, val) \
1407
SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
1408
1409
#define PLLCFG_NSEL_MASK 0x00ff0000U
1410
1411
#define GET_PLLCFG_NSEL(reg) \
1412
GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
1413
1414
#define SET_PLLCFG_NSEL(reg, val) \
1415
SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
1416
1417
/* PLLSTAT */
1418
1419
#define PLLSTAT_MSEL_MASK 0x00007fffU
1420
1421
#define GET_PLLSTAT_MSEL(reg) \
1422
GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
1423
1424
#define SET_PLLSTAT_MSEL(reg, val) \
1425
SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
1426
1427
#define PLLSTAT_NSEL_MASK 0x00ff0000U
1428
1429
#define GET_PLLSTAT_NSEL(reg) \
1430
GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
1431
1432
#define SET_PLLSTAT_NSEL(reg, val) \
1433
SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
1434
1435
#define PLLSTAT_PLLE 0x01000000U
1436
1437
#define PLLSTAT_PLLC 0x02000000U
1438
1439
#define PLLSTAT_PLOCK 0x04000000U
1440
1441
/* CCLKCFG */
1442
1443
#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1444
1445
#define GET_CCLKCFG_CCLKSEL(reg) \
1446
GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
1447
1448
#define SET_CCLKCFG_CCLKSEL(reg, val) \
1449
SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
1450
1451
/* MEMMAP */
1452
1453
#define MEMMAP_MAP_MASK 0x00000003U
1454
1455
#define GET_MEMMAP_MAP(reg) \
1456
GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
1457
1458
#define SET_MEMMAP_MAP(reg, val) \
1459
SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
1460
1461
/* TIR */
1462
1463
#define TIR_MR0 0x00000001U
1464
1465
#define TIR_MR1 0x00000002U
1466
1467
#define TIR_MR2 0x00000004U
1468
1469
#define TIR_MR3 0x00000008U
1470
1471
#define TIR_CR0 0x00000010U
1472
1473
#define TIR_CR1 0x00000020U
1474
1475
#define TIR_CR2 0x00000040U
1476
1477
#define TIR_CR3 0x00000080U
1478
1479
/* TCR */
1480
1481
#define TCR_EN 0x00000001U
1482
1483
#define TCR_RST 0x00000002U
1484
1485
/* TMCR */
1486
1487
#define TMCR_MR0I 0x00000001U
1488
1489
#define TMCR_MR0R 0x00000002U
1490
1491
#define TMCR_MR0S 0x00000004U
1492
1493
#define TMCR_MR1I 0x00000008U
1494
1495
#define TMCR_MR1R 0x00000010U
1496
1497
#define TMCR_MR1S 0x00000020U
1498
1499
#define TMCR_MR2I 0x00000040U
1500
1501
#define TMCR_MR2R 0x00000080U
1502
1503
#define TMCR_MR2S 0x00000100U
1504
1505
#define TMCR_MR3I 0x00000200U
1506
1507
#define TMCR_MR3R 0x00000400U
1508
1509
#define TMCR_MR3S 0x00000800U
1510
1511
/* PCLKSEL0 */
1512
1513
#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1514
1515
#define GET_PCLKSEL0_PCLK_WDT(reg) \
1516
GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
1517
1518
#define SET_PCLKSEL0_PCLK_WDT(reg, val) \
1519
SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
1520
1521
#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1522
1523
#define GET_PCLKSEL0_PCLK_TIMER0(reg) \
1524
GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1525
1526
#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
1527
SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1528
1529
#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1530
1531
#define GET_PCLKSEL0_PCLK_TIMER1(reg) \
1532
GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1533
1534
#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
1535
SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1536
1537
#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1538
1539
#define GET_PCLKSEL0_PCLK_UART0(reg) \
1540
GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
1541
1542
#define SET_PCLKSEL0_PCLK_UART0(reg, val) \
1543
SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
1544
1545
#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1546
1547
#define GET_PCLKSEL0_PCLK_UART1(reg) \
1548
GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
1549
1550
#define SET_PCLKSEL0_PCLK_UART1(reg, val) \
1551
SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
1552
1553
#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1554
1555
#define GET_PCLKSEL0_PCLK_PWM0(reg) \
1556
GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
1557
1558
#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
1559
SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
1560
1561
#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1562
1563
#define GET_PCLKSEL0_PCLK_PWM1(reg) \
1564
GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
1565
1566
#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
1567
SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
1568
1569
#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1570
1571
#define GET_PCLKSEL0_PCLK_I2C0(reg) \
1572
GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
1573
1574
#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
1575
SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
1576
1577
#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1578
1579
#define GET_PCLKSEL0_PCLK_SPI(reg) \
1580
GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
1581
1582
#define SET_PCLKSEL0_PCLK_SPI(reg, val) \
1583
SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
1584
1585
#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1586
1587
#define GET_PCLKSEL0_PCLK_RTC(reg) \
1588
GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
1589
1590
#define SET_PCLKSEL0_PCLK_RTC(reg, val) \
1591
SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
1592
1593
#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1594
1595
#define GET_PCLKSEL0_PCLK_SSP1(reg) \
1596
GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
1597
1598
#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
1599
SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
1600
1601
#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1602
1603
#define GET_PCLKSEL0_PCLK_DAC(reg) \
1604
GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
1605
1606
#define SET_PCLKSEL0_PCLK_DAC(reg, val) \
1607
SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
1608
1609
#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1610
1611
#define GET_PCLKSEL0_PCLK_ADC(reg) \
1612
GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
1613
1614
#define SET_PCLKSEL0_PCLK_ADC(reg, val) \
1615
SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
1616
1617
#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1618
1619
#define GET_PCLKSEL0_PCLK_CAN1(reg) \
1620
GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
1621
1622
#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
1623
SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
1624
1625
#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1626
1627
#define GET_PCLKSEL0_PCLK_CAN2(reg) \
1628
GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
1629
1630
#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
1631
SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
1632
1633
/* PCLKSEL1 */
1634
1635
#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1636
1637
#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
1638
GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1639
1640
#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
1641
SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1642
1643
#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1644
1645
#define GET_PCLKSEL1_PCLK_GPIO(reg) \
1646
GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
1647
1648
#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
1649
SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
1650
1651
#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1652
1653
#define GET_PCLKSEL1_PCLK_PCB(reg) \
1654
GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
1655
1656
#define SET_PCLKSEL1_PCLK_PCB(reg, val) \
1657
SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
1658
1659
#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1660
1661
#define GET_PCLKSEL1_PCLK_I2C1(reg) \
1662
GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
1663
1664
#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
1665
SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
1666
1667
#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1668
1669
#define GET_PCLKSEL1_PCLK_SSP0(reg) \
1670
GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
1671
1672
#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
1673
SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
1674
1675
#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1676
1677
#define GET_PCLKSEL1_PCLK_TIMER2(reg) \
1678
GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1679
1680
#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
1681
SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1682
1683
#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1684
1685
#define GET_PCLKSEL1_PCLK_TIMER3(reg) \
1686
GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1687
1688
#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
1689
SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1690
1691
#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1692
1693
#define GET_PCLKSEL1_PCLK_UART2(reg) \
1694
GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
1695
1696
#define SET_PCLKSEL1_PCLK_UART2(reg, val) \
1697
SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
1698
1699
#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1700
1701
#define GET_PCLKSEL1_PCLK_UART3(reg) \
1702
GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
1703
1704
#define SET_PCLKSEL1_PCLK_UART3(reg, val) \
1705
SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
1706
1707
#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1708
1709
#define GET_PCLKSEL1_PCLK_I2C2(reg) \
1710
GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
1711
1712
#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
1713
SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
1714
1715
#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1716
1717
#define GET_PCLKSEL1_PCLK_I2S(reg) \
1718
GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
1719
1720
#define SET_PCLKSEL1_PCLK_I2S(reg, val) \
1721
SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
1722
1723
#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1724
1725
#define GET_PCLKSEL1_PCLK_MCI(reg) \
1726
GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
1727
1728
#define SET_PCLKSEL1_PCLK_MCI(reg, val) \
1729
SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
1730
1731
#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1732
1733
#define GET_PCLKSEL1_PCLK_SYSCON(reg) \
1734
GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1735
1736
#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
1737
SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1738
1739
/* RTC_ILR */
1740
1741
#define RTC_ILR_RTCCIF 0x00000001U
1742
1743
#define RTC_ILR_RTCALF 0x00000002U
1744
1745
#define RTC_ILR_RTSSF 0x00000004U
1746
1747
/* RTC_CCR */
1748
1749
#define RTC_CCR_CLKEN 0x00000001U
1750
1751
#define RTC_CCR_CTCRST 0x00000002U
1752
1753
#define RTC_CCR_CLKSRC 0x00000010U
1754
1755
/* SSP */
1756
1757
typedef
struct
{
1758
uint32_t cr0;
1759
uint32_t cr1;
1760
uint32_t dr;
1761
uint32_t sr;
1762
uint32_t cpsr;
1763
uint32_t imsc;
1764
uint32_t ris;
1765
uint32_t mis;
1766
uint32_t icr;
1767
uint32_t dmacr;
1768
}
lpc24xx_ssp
;
1769
1770
/* SSP_CR0 */
1771
1772
#define SSP_CR0_DSS_MASK 0x0000000fU
1773
1774
#define GET_SSP_CR0_DSS(reg) \
1775
GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
1776
1777
#define SET_SSP_CR0_DSS(reg, val) \
1778
SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
1779
1780
#define SSP_CR0_FRF_MASK 0x00000030U
1781
1782
#define GET_SSP_CR0_FRF(reg) \
1783
GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
1784
1785
#define SET_SSP_CR0_FRF(reg, val) \
1786
SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
1787
1788
#define SSP_CR0_CPOL 0x00000040U
1789
1790
#define SSP_CR0_CPHA 0x00000080U
1791
1792
#define SSP_CR0_SCR_MASK 0x0000ff00U
1793
1794
#define GET_SSP_CR0_SCR(reg) \
1795
GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
1796
1797
#define SET_SSP_CR0_SCR(reg, val) \
1798
SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
1799
1800
/* SSP_CR1 */
1801
1802
#define SSP_CR1_LBM 0x00000001U
1803
1804
#define SSP_CR1_SSE 0x00000002U
1805
1806
#define SSP_CR1_MS 0x00000004U
1807
1808
#define SSP_CR1_SOD 0x00000008U
1809
1810
/* SSP_SR */
1811
1812
#define SSP_SR_TFE 0x00000001U
1813
1814
#define SSP_SR_TNF 0x00000002U
1815
1816
#define SSP_SR_RNE 0x00000004U
1817
1818
#define SSP_SR_RFF 0x00000008U
1819
1820
#define SSP_SR_BSY 0x00000010U
1821
1822
/* SSP_IMSC */
1823
1824
#define SSP_IMSC_RORIM 0x00000001U
1825
1826
#define SSP_IMSC_RTIM 0x00000002U
1827
1828
#define SSP_IMSC_RXIM 0x00000004U
1829
1830
#define SSP_IMSC_TXIM 0x00000008U
1831
1832
/* SSP_RIS */
1833
1834
#define SSP_RIS_RORRIS 0x00000001U
1835
1836
#define SSP_RIS_RTRIS 0x00000002U
1837
1838
#define SSP_RIS_RXRIS 0x00000004U
1839
1840
#define SSP_RIS_TXRIS 0x00000008U
1841
1842
/* SSP_MIS */
1843
1844
#define SSP_MIS_RORRIS 0x00000001U
1845
1846
#define SSP_MIS_RTRIS 0x00000002U
1847
1848
#define SSP_MIS_RXRIS 0x00000004U
1849
1850
#define SSP_MIS_TXRIS 0x00000008U
1851
1852
/* SSP_ICR */
1853
1854
#define SSP_ICR_RORRIS 0x00000001U
1855
1856
#define SSP_ICR_RTRIS 0x00000002U
1857
1858
#define SSP_ICR_RXRIS 0x00000004U
1859
1860
#define SSP_ICR_TXRIS 0x00000008U
1861
1862
/* SSP_DMACR */
1863
1864
#define SSP_DMACR_RXDMAE 0x00000001U
1865
1866
#define SSP_DMACR_TXDMAE 0x00000002U
1867
1868
/* GPDMA */
1869
1870
typedef
struct
{
1871
uint32_t src;
1872
uint32_t dest;
1873
uint32_t lli;
1874
uint32_t ctrl;
1875
}
lpc24xx_dma_descriptor
;
1876
1877
typedef
struct
{
1878
lpc24xx_dma_descriptor
desc;
1879
uint32_t cfg;
1880
}
lpc24xx_dma_channel
;
1881
1882
#define GPDMA_CH_NUMBER 2
1883
1884
#define GPDMA_STATUS_CH_0 0x00000001U
1885
1886
#define GPDMA_STATUS_CH_1 0x00000002U
1887
1888
#define GPDMA_CH_BASE_ADDR(i) \
1889
((volatile lpc24xx_dma_channel *) \
1890
((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
1891
1892
/* GPDMA_CONFIG */
1893
1894
#define GPDMA_CONFIG_EN 0x00000001U
1895
1896
#define GPDMA_CONFIG_MODE 0x00000002U
1897
1898
/* GPDMA_ENABLED_CHNS */
1899
1900
#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1901
1902
#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1903
1904
/* GPDMA_CH_CTRL */
1905
1906
#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1907
1908
#define GET_GPDMA_CH_CTRL_TSZ(reg) \
1909
GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
1910
1911
#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
1912
SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
1913
1914
#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1915
1916
#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1917
1918
#define GET_GPDMA_CH_CTRL_SBSZ(reg) \
1919
GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1920
1921
#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
1922
SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1923
1924
#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1925
1926
#define GET_GPDMA_CH_CTRL_DBSZ(reg) \
1927
GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1928
1929
#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
1930
SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1931
1932
#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1933
1934
#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1935
1936
#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1937
1938
#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1939
1940
#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1941
1942
#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1943
1944
#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1945
1946
#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1947
1948
#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1949
1950
#define GET_GPDMA_CH_CTRL_SW(reg) \
1951
GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
1952
1953
#define SET_GPDMA_CH_CTRL_SW(reg, val) \
1954
SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
1955
1956
#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1957
1958
#define GET_GPDMA_CH_CTRL_DW(reg) \
1959
GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
1960
1961
#define SET_GPDMA_CH_CTRL_DW(reg, val) \
1962
SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
1963
1964
#define GPDMA_CH_CTRL_W_8 0x00000000U
1965
1966
#define GPDMA_CH_CTRL_W_16 0x00000001U
1967
1968
#define GPDMA_CH_CTRL_W_32 0x00000002U
1969
1970
#define GPDMA_CH_CTRL_SI 0x04000000U
1971
1972
#define GPDMA_CH_CTRL_DI 0x08000000U
1973
1974
#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1975
1976
#define GET_GPDMA_CH_CTRL_PROT(reg) \
1977
GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
1978
1979
#define SET_GPDMA_CH_CTRL_PROT(reg, val) \
1980
SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
1981
1982
#define GPDMA_CH_CTRL_ITC 0x80000000U
1983
1984
/* GPDMA_CH_CFG */
1985
1986
#define GPDMA_CH_CFG_EN 0x00000001U
1987
1988
#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1989
1990
#define GET_GPDMA_CH_CFG_SRCPER(reg) \
1991
GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
1992
1993
#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
1994
SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
1995
1996
#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1997
1998
#define GET_GPDMA_CH_CFG_DESTPER(reg) \
1999
GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
2000
2001
#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
2002
SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
2003
2004
#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
2005
2006
#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
2007
2008
#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
2009
2010
#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
2011
2012
#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
2013
2014
#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
2015
2016
#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
2017
2018
#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
2019
2020
#define GET_GPDMA_CH_CFG_FLOW(reg) \
2021
GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
2022
2023
#define SET_GPDMA_CH_CFG_FLOW(reg, val) \
2024
SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
2025
2026
#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
2027
2028
#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
2029
2030
#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
2031
2032
#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
2033
2034
#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
2035
2036
#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
2037
2038
#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
2039
2040
#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
2041
2042
#define GPDMA_CH_CFG_IE 0x00004000U
2043
2044
#define GPDMA_CH_CFG_ITC 0x00008000U
2045
2046
#define GPDMA_CH_CFG_LOCK 0x00010000U
2047
2048
#define GPDMA_CH_CFG_ACTIVE 0x00020000U
2049
2050
#define GPDMA_CH_CFG_HALT 0x00040000U
2051
2052
/* AHBCFG */
2053
2054
#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
2055
2056
#define AHBCFG_BREAK_BURST_MASK 0x00000006U
2057
2058
#define GET_AHBCFG_BREAK_BURST(reg) \
2059
GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
2060
2061
#define SET_AHBCFG_BREAK_BURST(reg, val) \
2062
SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
2063
2064
#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
2065
2066
#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
2067
2068
#define GET_AHBCFG_QUANTUM_SIZE(reg) \
2069
GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
2070
2071
#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
2072
SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
2073
2074
#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
2075
2076
#define GET_AHBCFG_DEFAULT_MASTER(reg) \
2077
GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
2078
2079
#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
2080
SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
2081
2082
#define AHBCFG_EP1_MASK 0x00007000U
2083
2084
#define GET_AHBCFG_EP1(reg) \
2085
GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
2086
2087
#define SET_AHBCFG_EP1(reg, val) \
2088
SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
2089
2090
#define AHBCFG_EP2_MASK 0x00070000U
2091
2092
#define GET_AHBCFG_EP2(reg) \
2093
GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
2094
2095
#define SET_AHBCFG_EP2(reg, val) \
2096
SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
2097
2098
#define AHBCFG_EP3_MASK 0x00700000U
2099
2100
#define GET_AHBCFG_EP3(reg) \
2101
GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
2102
2103
#define SET_AHBCFG_EP3(reg, val) \
2104
SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
2105
2106
#define AHBCFG_EP4_MASK 0x07000000U
2107
2108
#define GET_AHBCFG_EP4(reg) \
2109
GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
2110
2111
#define SET_AHBCFG_EP4(reg, val) \
2112
SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
2113
2114
#define AHBCFG_EP5_MASK 0x70000000U
2115
2116
#define GET_AHBCFG_EP5(reg) \
2117
GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
2118
2119
#define SET_AHBCFG_EP5(reg, val) \
2120
SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
2121
2122
/* I2C */
2123
2124
typedef
struct
{
2125
uint32_t conset;
2126
uint32_t stat;
2127
uint32_t dat;
2128
uint32_t adr;
2129
uint32_t sclh;
2130
uint32_t scll;
2131
uint32_t conclr;
2132
}
lpc24xx_i2c
;
2133
2134
#define LPC24XX_I2C_AA (1U << 2U)
2135
2136
#define LPC24XX_I2C_SI (1U << 3U)
2137
2138
#define LPC24XX_I2C_STO (1U << 4U)
2139
2140
#define LPC24XX_I2C_STA (1U << 5U)
2141
2142
#define LPC24XX_I2C_EN (1U << 6U)
2143
2144
/* IO */
2145
2146
#ifdef ARM_MULTILIB_ARCH_V4
2147
#define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
2148
#define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
2149
#else
2150
#define IOCON_FUNC(val) BSP_FLD32(val, 0, 2)
2151
#define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2)
2152
#define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
2153
#define IOCON_MODE(val) BSP_FLD32(val, 3, 4)
2154
#define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4)
2155
#define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
2156
#define IOCON_HYS BSP_BIT32(5)
2157
#define IOCON_INV BSP_BIT32(6)
2158
#define IOCON_ADMODE BSP_BIT32(7)
2159
#define IOCON_FILTER BSP_BIT32(8)
2160
#define IOCON_HS BSP_BIT32(8)
2161
#define IOCON_SLEW BSP_BIT32(9)
2162
#define IOCON_HIDRIVE BSP_BIT32(9)
2163
#define IOCON_OD BSP_BIT32(10)
2164
#define IOCON_DACEN BSP_BIT32(16)
2165
#define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR)
2166
#endif
2167
2168
typedef
struct
{
2169
uint32_t dir;
2170
uint32_t reserved [3];
2171
uint32_t mask;
2172
uint32_t pin;
2173
uint32_t set;
2174
uint32_t clr;
2175
}
lpc24xx_fio
;
2176
2177
#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
2178
2179
#ifdef ARM_MULTILIB_ARCH_V4
2180
2181
/* PCONP */
2182
2183
#define PCONP_GPDMA (1U << 29)
2184
#define PCONP_ETHERNET (1U << 30)
2185
#define PCONP_USB (1U << 31)
2186
2187
#endif
/* ARM_MULTILIB_ARCH_V4 */
2188
2189
/* I2S */
2190
2191
static
volatile
lpc_i2s
*
const
lpc24xx_i2s = (
lpc_i2s
*) I2S_BASE_ADDR;
2192
2193
/* ADC */
2194
2195
#define ADC_CR_SEL(val) BSP_FLD32(val, 0, 7)
2196
#define ADC_CR_SEL_GET(val) BSP_FLD32GET(val, 0, 7)
2197
#define ADC_CR_SEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
2198
#define ADC_CR_CLKDIV(val) BSP_FLD32(val, 8, 15)
2199
#define ADC_CR_CLKDIV_GET(reg) BSP_FLD32GET(reg, 8, 15)
2200
#define ADC_CR_CLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
2201
#define ADC_CR_BURST BSP_BIT32(16)
2202
#define ADC_CR_CLKS(val) BSP_FLD32(val, 17, 19)
2203
#define ADC_CR_PDN BSP_BIT32(21)
2204
#define ADC_CR_START(val) BSP_FLD32(val, 24, 26)
2205
#define ADC_CR_EDGE BSP_BIT32(27)
2206
2207
#define ADC_DR_VALUE(reg) BSP_FLD32GET(reg, 6, 15)
2208
#define ADC_DR_OVERRUN BSP_BIT32(30)
2209
#define ADC_DR_DONE BSP_BIT32(31)
2210
2211
/* DAC */
2212
2213
#define DAC_STEPS 1024
2214
#define DAC_VALUE(val) BSP_FLD32(val, 6, 15)
2215
#define DAC_BIAS BSP_BIT32(16)
2216
2218
2219
#endif
/* LIBBSP_ARM_LPC24XX_LPC24XX_H */
utility.h
This header file provides utility macros for BSPs.
lpc-i2s.h
I2S API.
lpc17xx.h
Register definitions.
lpc24xx_dma_channel
Definition
lpc24xx.h:1877
lpc24xx_dma_descriptor
Definition
lpc24xx.h:1870
lpc24xx_fio
Definition
lpc24xx.h:2168
lpc24xx_i2c
Definition
lpc24xx.h:2124
lpc24xx_ssp
Definition
lpc24xx.h:1757
lpc_i2s
I2S control block.
Definition
lpc-i2s.h:59
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