ARM Generic Interrupt Controller (GIC) Support

This group contains the Interrupt Manager implementation parts specific to the ARM Generic Interrupt Controller. More...

Files
file	bsps/aarch64/include/dev/irq/arm-gic-arch.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the AArch64 architecture.
file	bsps/arm/include/dev/irq/arm-gic-arch.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the Arm architecture.
file	bsps/include/dev/irq/arm-gic-irq.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
file	bsps/include/dev/irq/arm-gic-regs.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) memory-mapped registers.
file	bsps/include/dev/irq/arm-gic-tm27.h
	This header file provides the TM27 support for the ARM Generic Interrupt Controller (GIC).
file	bsps/include/dev/irq/arm-gic.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.
file	bsps/include/dev/irq/arm-gicv3.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the GICv3.
file	bsps/shared/dev/irq/arm-gicv2-get-attributes.c
	This source file contains the implementation of bsp_interrupt_get_attributes() for the GICv2.
file	bsps/shared/dev/irq/arm-gicv2-zynqmp.c
	This source file contains the implementation of bsp_interrupt_get_attributes() for the GICv2 of Xilinx Zynq UltraScale+ MPSoC and RFSoC devices.
file	bsps/shared/dev/irq/arm-gicv2.c
	This source file contains the implementation of the generic GICv2 support.
file	bsps/shared/dev/irq/arm-gicv3.c
	This source file contains the implementation of the generic GICv3 support.

Data Structures
struct	gic_cpuif
struct	gic_dist
struct	gic_redist
struct	gic_sgi_ppi

Macros
#define	ARM_GIC_IRQ_SGI_0   0
#define	ARM_GIC_IRQ_SGI_1   1
#define	ARM_GIC_IRQ_SGI_2   2
#define	ARM_GIC_IRQ_SGI_3   3
#define	ARM_GIC_IRQ_SGI_5   5
#define	ARM_GIC_IRQ_SGI_6   6
#define	ARM_GIC_IRQ_SGI_7   7
#define	ARM_GIC_IRQ_SGI_8   8
#define	ARM_GIC_IRQ_SGI_9   9
#define	ARM_GIC_IRQ_SGI_10   10
#define	ARM_GIC_IRQ_SGI_11   11
#define	ARM_GIC_IRQ_SGI_12   12
#define	ARM_GIC_IRQ_SGI_13   13
#define	ARM_GIC_IRQ_SGI_14   14
#define	ARM_GIC_IRQ_SGI_15   15
#define	ARM_GIC_IRQ_SGI_LAST   15
#define	ARM_GIC_IRQ_PPI_LAST   31
#define	ARM_GIC_DIST   ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
#define	GIC_ID_TO_ONE_BIT_REG_INDEX(id)
#define	GIC_ID_TO_ONE_BIT_REG_BIT(id)
#define	GIC_ID_TO_TWO_BITS_REG_INDEX(id)
#define	GIC_ID_TO_TWO_BITS_REG_OFFSET(id)
#define	PRIORITY_DEFAULT   127
#define	MPIDR_AFFINITY2(val)
#define	MPIDR_AFFINITY2_GET(reg)
#define	MPIDR_AFFINITY2_SET(reg, val)
#define	MPIDR_AFFINITY1(val)
#define	MPIDR_AFFINITY1_GET(reg)
#define	MPIDR_AFFINITY1_SET(reg, val)
#define	MPIDR_AFFINITY0(val)
#define	MPIDR_AFFINITY0_GET(reg)
#define	MPIDR_AFFINITY0_SET(reg, val)
#define	ICC_SGIR_AFFINITY3(val)
#define	ICC_SGIR_AFFINITY3_GET(reg)
#define	ICC_SGIR_AFFINITY3_SET(reg, val)
#define	ICC_SGIR_IRM   BSP_BIT32(40)
#define	ICC_SGIR_AFFINITY2(val)
#define	ICC_SGIR_AFFINITY2_GET(reg)
#define	ICC_SGIR_AFFINITY2_SET(reg, val)
#define	ICC_SGIR_INTID(val)
#define	ICC_SGIR_INTID_GET(reg)
#define	ICC_SGIR_INTID_SET(reg, val)
#define	ICC_SGIR_AFFINITY1(val)
#define	ICC_SGIR_AFFINITY1_GET(reg)
#define	ICC_SGIR_AFFINITY1_SET(reg, val)
#define	ICC_SGIR_CPU_TARGET_LIST(val)
#define	ICC_SGIR_CPU_TARGET_LIST_GET(reg)
#define	ICC_SGIR_CPU_TARGET_LIST_SET(reg, val)
#define	ICC_IGRPEN0_EL1   "S3_0_C12_C12_6, %0"
#define	ICC_IGRPEN1_EL1   "S3_0_C12_C12_7, %0"
#define	ICC_IGRPEN1_EL3   "S3_6_C12_C12_7, %0"
#define	ICC_IGRPEN0   ICC_IGRPEN0_EL1
#define	ICC_IGRPEN1   ICC_IGRPEN1_EL1
#define	ICC_PMR   "S3_0_C4_C6_0, %0"
#define	ICC_EOIR1   "S3_0_C12_C12_1, %0"
#define	ICC_SRE   "S3_0_C12_C12_5, %0"
#define	ICC_BPR0   "S3_0_C12_C8_3, %0"
#define	ICC_BPR1   "S3_0_C12_C12_3, %0"
#define	ICC_CTLR   "S3_0_C12_C12_4, %0"
#define	ICC_IAR1   "%0, S3_0_C12_C12_0"
#define	MPIDR   "%0, mpidr_el1"
#define	MPIDR_AFFINITY3(val)
#define	MPIDR_AFFINITY3_GET(reg)
#define	MPIDR_AFFINITY3_SET(reg, val)
#define	ICC_SGI1   "S3_0_C12_C11_5, %0"
#define	WRITE64_SR(SR_NAME, VALUE)
#define	WRITE_SR(SR_NAME, VALUE)
#define	READ_SR(SR_NAME)

Enumerations
enum	gic_group { GIC_GROUP_0 , GIC_GROUP_1 }
enum	gic_trigger_mode { GIC_LEVEL_SENSITIVE , GIC_EDGE_TRIGGERED }
enum	gic_handling_model { GIC_N_TO_N , GIC_1_TO_N }

Functions
rtems_status_code	arm_gic_irq_set_group (rtems_vector_number vector, gic_group group)
rtems_status_code	arm_gic_irq_get_group (rtems_vector_number vector, gic_group *group)
void	arm_gic_trigger_sgi (rtems_vector_number vector, uint32_t targets)

Detailed Description

This group contains the Interrupt Manager implementation parts specific to the ARM Generic Interrupt Controller.

Macro Definition Documentation

GIC_ID_TO_ONE_BIT_REG_BIT

#define GIC_ID_TO_ONE_BIT_REG_BIT

(

id

)

Value:

(1U << ((id) & 0x1fU))

GIC_ID_TO_ONE_BIT_REG_INDEX

#define GIC_ID_TO_ONE_BIT_REG_INDEX

(

id

)

Value:

((id) >> 5)

GIC_ID_TO_TWO_BITS_REG_INDEX

#define GIC_ID_TO_TWO_BITS_REG_INDEX

(

id

)

Value:

((id) >> 4)

GIC_ID_TO_TWO_BITS_REG_OFFSET

#define GIC_ID_TO_TWO_BITS_REG_OFFSET

(

id

)

Value:

(((id) & 0xfU) << 1)

ICC_SGIR_AFFINITY1

#define ICC_SGIR_AFFINITY1

(

val

)

Value:

BSP_FLD64(val, 16, 23)

ICC_SGIR_AFFINITY1_GET

#define ICC_SGIR_AFFINITY1_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 16, 23)

ICC_SGIR_AFFINITY1_SET

#define ICC_SGIR_AFFINITY1_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 16, 23)

ICC_SGIR_AFFINITY2

#define ICC_SGIR_AFFINITY2

(

val

)

Value:

BSP_FLD64(val, 32, 39)

ICC_SGIR_AFFINITY2_GET

#define ICC_SGIR_AFFINITY2_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 32, 39)

ICC_SGIR_AFFINITY2_SET

#define ICC_SGIR_AFFINITY2_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 32, 39)

ICC_SGIR_AFFINITY3

#define ICC_SGIR_AFFINITY3

(

val

)

Value:

BSP_FLD64(val, 48, 55)

ICC_SGIR_AFFINITY3_GET

#define ICC_SGIR_AFFINITY3_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 48, 55)

ICC_SGIR_AFFINITY3_SET

#define ICC_SGIR_AFFINITY3_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 48, 55)

ICC_SGIR_CPU_TARGET_LIST

#define ICC_SGIR_CPU_TARGET_LIST

(

val

)

Value:

BSP_FLD64(val, 0, 15)

ICC_SGIR_CPU_TARGET_LIST_GET

#define ICC_SGIR_CPU_TARGET_LIST_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 0, 15)

ICC_SGIR_CPU_TARGET_LIST_SET

#define ICC_SGIR_CPU_TARGET_LIST_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 0, 15)

ICC_SGIR_INTID

#define ICC_SGIR_INTID

(

val

)

Value:

BSP_FLD64(val, 24, 27)

ICC_SGIR_INTID_GET

#define ICC_SGIR_INTID_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 24, 27)

ICC_SGIR_INTID_SET

#define ICC_SGIR_INTID_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 24, 27)

MPIDR_AFFINITY0

#define MPIDR_AFFINITY0

(

val

)

Value:

BSP_FLD64(val, 0, 7)

MPIDR_AFFINITY0_GET

#define MPIDR_AFFINITY0_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 0, 7)

MPIDR_AFFINITY0_SET

#define MPIDR_AFFINITY0_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 0, 7)

MPIDR_AFFINITY1

#define MPIDR_AFFINITY1

(

val

)

Value:

BSP_FLD64(val, 8, 15)

MPIDR_AFFINITY1_GET

#define MPIDR_AFFINITY1_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 8, 15)

MPIDR_AFFINITY1_SET

#define MPIDR_AFFINITY1_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 8, 15)

MPIDR_AFFINITY2

#define MPIDR_AFFINITY2

(

val

)

Value:

BSP_FLD64(val, 16, 23)

MPIDR_AFFINITY2_GET

#define MPIDR_AFFINITY2_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 16, 23)

MPIDR_AFFINITY2_SET

#define MPIDR_AFFINITY2_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 16, 23)

MPIDR_AFFINITY3

#define MPIDR_AFFINITY3

(

val

)

Value:

BSP_FLD64(val, 32, 39)

MPIDR_AFFINITY3_GET

#define MPIDR_AFFINITY3_GET

(

reg

)

Value:

BSP_FLD64GET(reg, 32, 39)

MPIDR_AFFINITY3_SET

#define MPIDR_AFFINITY3_SET	(		reg,
			val )

Value:

BSP_FLD64SET(reg, val, 32, 39)

READ_SR

#define READ_SR

(

SR_NAME

)

Value:

({ \
  uint64_t value; \
  __asm__ volatile("mrs    " SR_NAME : "=&r" (value) ); \
  value; \
})

WRITE64_SR

#define WRITE64_SR	(		SR_NAME,
			VALUE )

Value:

__asm__ volatile("msr    " SR_NAME "  \n" : : "r" (VALUE) );

WRITE_SR

#define WRITE_SR	(		SR_NAME,
			VALUE )

Value:

WRITE64_SR(SR_NAME, VALUE)