MM

MM. More...

Files
file	cache_spec.h
file	frame.h
file	mmu.h
file	page.h
file	frame.h
file	mmu.h
file	page.h
file	tlb.h
file	tte.h
file	tlb.h
file	tte.h

Data Structures
union	tlb_context_reg
union	tlb_tag_read_reg
union	tlb_demap_addr
union	tlb_sfsr_reg
union	tte_tag
union	tte_data

Macros
#define	DCACHE_LINE_SIZE   32
#define	MMU_PAGE_WIDTH   MMU_FRAME_WIDTH
#define	MMU_PAGE_SIZE   MMU_FRAME_SIZE
#define	PAGE_WIDTH   FRAME_WIDTH
#define	PAGE_SIZE   FRAME_SIZE
#define	MMU_PAGES_PER_PAGE   (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH))
#define	MMU_FRAME_WIDTH   13 /* 8K */
#define	MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
#define	FRAME_WIDTH   14 /* 16K */
#define	FRAME_SIZE   (1 << FRAME_WIDTH)
#define	ASI_IMMU   0x50
#define	ASI_IMMU_TSB_8KB_PTR_REG   0x51
#define	ASI_IMMU_TSB_64KB_PTR_REG   0x52
#define	ASI_ITLB_DATA_IN_REG   0x54
#define	ASI_ITLB_DATA_ACCESS_REG   0x55
#define	ASI_ITLB_TAG_READ_REG   0x56
#define	ASI_IMMU_DEMAP   0x57
#define	VA_IMMU_TSB_TAG_TARGET   0x0
#define	VA_IMMU_SFSR   0x18
#define	VA_IMMU_TSB_BASE   0x28
#define	VA_IMMU_TAG_ACCESS   0x30
#define	ASI_DMMU   0x58
#define	ASI_DMMU_TSB_8KB_PTR_REG   0x59
#define	ASI_DMMU_TSB_64KB_PTR_REG   0x5a
#define	ASI_DMMU_TSB_DIRECT_PTR_REG   0x5b
#define	ASI_DTLB_DATA_IN_REG   0x5c
#define	ASI_DTLB_DATA_ACCESS_REG   0x5d
#define	ASI_DTLB_TAG_READ_REG   0x5e
#define	ASI_DMMU_DEMAP   0x5f
#define	VA_DMMU_TSB_TAG_TARGET   0x0
#define	VA_PRIMARY_CONTEXT_REG   0x8
#define	VA_SECONDARY_CONTEXT_REG   0x10
#define	VA_DMMU_SFSR   0x18
#define	VA_DMMU_SFAR   0x20
#define	VA_DMMU_TSB_BASE   0x28
#define	VA_DMMU_TAG_ACCESS   0x30
#define	VA_DMMU_VA_WATCHPOINT_REG   0x38
#define	VA_DMMU_PA_WATCHPOINT_REG   0x40
#define	MMU_PAGE_WIDTH   MMU_FRAME_WIDTH
#define	MMU_PAGE_SIZE   MMU_FRAME_SIZE
#define	PAGE_WIDTH   FRAME_WIDTH
#define	PAGE_SIZE   FRAME_SIZE
#define	MMU_PAGES_PER_PAGE   (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH))
#define	MEM_CONTEXT_KERNEL   0
#define	MEM_CONTEXT_TEMP   1
#define	PAGESIZE_8K   0
#define	PAGESIZE_64K   1
#define	PAGESIZE_512K   2
#define	PAGESIZE_4M   3
#define	KERNEL_PAGE_WIDTH   22 /* 4M */
#define	TLB_DEMAP_PAGE   0
#define	TLB_DEMAP_CONTEXT   1
#define	TLB_DEMAP_TYPE_SHIFT   6
#define	TLB_DEMAP_PRIMARY   0
#define	TLB_DEMAP_SECONDARY   1
#define	TLB_DEMAP_NUCLEUS   2
#define	TLB_DEMAP_CONTEXT_SHIFT   4
#define	TLB_TAG_ACCESS_CONTEXT_SHIFT   0
#define	TLB_TAG_ACCESS_CONTEXT_MASK   ((1 << 13) - 1)
#define	TLB_TAG_ACCESS_VPN_SHIFT   13
#define	TTE_G   (1 << 0)
#define	TTE_W   (1 << 1)
#define	TTE_P   (1 << 2)
#define	TTE_E   (1 << 3)
#define	TTE_CV   (1 << 4)
#define	TTE_CP   (1 << 5)
#define	TTE_L   (1 << 6)
#define	TTE_V_SHIFT   63
#define	TTE_SIZE_SHIFT   61
#define	VA_TAG_PAGE_SHIFT   22

Typedefs
typedef union tlb_context_reg	tlb_context_reg_t
typedef tte_data_t	tlb_data_t
typedef union tlb_tag_read_reg	tlb_tag_read_reg_t
typedef union tlb_tag_read_reg	tlb_tag_access_reg_t
typedef union tlb_demap_addr	tlb_demap_addr_t
typedef union tlb_sfsr_reg	tlb_sfsr_reg_t
typedef union tte_tag	tte_tag_t
typedef union tte_data	tte_data_t

Functions
void	fast_instruction_access_mmu_miss (unative_t, istate_t *)
void	fast_data_access_mmu_miss (tlb_tag_access_reg_t, istate_t *)
void	fast_data_access_protection (tlb_tag_access_reg_t, istate_t *)
void	dtlb_insert_mapping (uintptr_t, uintptr_t, int, bool, bool)
void	dump_sfsr_and_sfar (void)
void	describe_dmmu_fault (void)

Variables
union tte_tag	__attribute__

Detailed Description

MM.

Macro Definition Documentation

KERNEL_PAGE_WIDTH

#define KERNEL_PAGE_WIDTH   22 /* 4M */

Bit width of the TLB-locked portion of kernel address space.

MEM_CONTEXT_KERNEL

#define MEM_CONTEXT_KERNEL   0

TLB_DSMALL is the only of the three DMMUs that can hold locked entries.

PAGESIZE_8K

#define PAGESIZE_8K   0

Page sizes.

VA_DMMU_PA_WATCHPOINT_REG

#define VA_DMMU_PA_WATCHPOINT_REG   0x40

DMMU PA data watchpoint register.

VA_DMMU_SFAR

#define VA_DMMU_SFAR   0x20

DMMU sync fault address register.

VA_DMMU_SFSR

#define VA_DMMU_SFSR   0x18

DMMU sync fault status register.

VA_DMMU_TAG_ACCESS

#define VA_DMMU_TAG_ACCESS   0x30

DMMU TLB tag access register.

VA_DMMU_TSB_BASE

#define VA_DMMU_TSB_BASE   0x28

DMMU TSB base register.

VA_DMMU_TSB_TAG_TARGET

#define VA_DMMU_TSB_TAG_TARGET   0x0

DMMU TSB tag target register.

VA_DMMU_VA_WATCHPOINT_REG

#define VA_DMMU_VA_WATCHPOINT_REG   0x38

DMMU VA data watchpoint register.

VA_IMMU_SFSR

#define VA_IMMU_SFSR   0x18

IMMU sync fault status register.

VA_IMMU_TAG_ACCESS

#define VA_IMMU_TAG_ACCESS   0x30

IMMU TLB tag access register.

VA_IMMU_TSB_BASE

#define VA_IMMU_TSB_BASE   0x28

IMMU TSB base register.

VA_IMMU_TSB_TAG_TARGET

#define VA_IMMU_TSB_TAG_TARGET   0x0

IMMU TSB tag target register.

VA_PRIMARY_CONTEXT_REG

#define VA_PRIMARY_CONTEXT_REG   0x8

DMMU primary context register.

VA_SECONDARY_CONTEXT_REG

#define VA_SECONDARY_CONTEXT_REG   0x10

DMMU secondary context register.

Typedef Documentation

tlb_data_t

typedef tte_data_t tlb_data_t

I-/D-TLB Data In/Access Register type.