Type definitions for the Instrumentation Trace Macrocell (ITM) More...

Data Structures
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

Macros
#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_IWR_ATVALIDM_Pos 0U

#define	ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/)

#define	ITM_IRR_ATREADYM_Pos 0U

#define	ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/)

#define	ITM_IMCR_INTEGRATION_Pos 0U

#define	ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

Macro Definition Documentation

◆ ITM_IMCR_INTEGRATION_Msk

#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Pos

#define ITM_IMCR_INTEGRATION_Pos 0U

ITM IMCR: INTEGRATION Position

◆ ITM_IRR_ATREADYM_Msk

#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Pos

#define ITM_IRR_ATREADYM_Pos 0U

ITM IRR: ATREADYM Position

◆ ITM_IWR_ATVALIDM_Msk

#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Pos

#define ITM_IWR_ATVALIDM_Pos 0U

ITM IWR: ATVALIDM Position

◆ ITM_LSR_Access_Msk

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Pos

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

◆ ITM_LSR_ByteAcc_Msk

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Pos

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_Present_Msk

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Pos

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

◆ ITM_TCR_BUSY_Msk

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Pos

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

◆ ITM_TCR_DWTENA_Msk

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Pos

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

◆ ITM_TCR_GTSFREQ_Msk

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Pos

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_ITMENA_Msk

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Pos

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_SWOENA_Msk

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Pos

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SYNCENA_Msk

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Pos

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_TraceBusID_Msk

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TraceBusID_Pos

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

◆ ITM_TCR_TSENA_Msk

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Pos

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSPrescale_Msk

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

◆ ITM_TCR_TSPrescale_Pos

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

◆ ITM_TPR_PRIVMASK_Msk

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Pos

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Data Structures

Macros