RTEMS  5.1
armv4.h
1 /*
2  * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
3  *
4  * embedded brains GmbH
5  * Dornierstr. 4
6  * 82178 Puchheim
7  * Germany
8  * <rtems@embedded-brains.de>
9  *
10  * The license and distribution terms for this file may be
11  * found in the file LICENSE in this distribution or at
12  * http://www.rtems.org/license/LICENSE.
13  */
14 
15 #ifndef RTEMS_SCORE_ARMV4_H
16 #define RTEMS_SCORE_ARMV4_H
17 
18 #include <rtems/score/cpu.h>
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif /* __cplusplus */
23 
24 #ifdef ARM_MULTILIB_ARCH_V4
25 
26 void bsp_interrupt_dispatch( void );
27 
28 void _ARMV4_Exception_interrupt( void );
29 
30 typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame );
31 
32 void _ARMV4_Exception_data_abort_set_handler(
33  ARMV4_Exception_abort_handler handler
34 );
35 
36 void _ARMV4_Exception_data_abort( void );
37 
38 void _ARMV4_Exception_prefetch_abort_set_handler(
39  ARMV4_Exception_abort_handler handler
40 );
41 
42 void _ARMV4_Exception_prefetch_abort( void );
43 
44 void _ARMV4_Exception_undef_default( void );
45 
46 void _ARMV4_Exception_swi_default( void );
47 
48 void _ARMV4_Exception_data_abort_default( void );
49 
50 void _ARMV4_Exception_pref_abort_default( void );
51 
52 void _ARMV4_Exception_reserved_default( void );
53 
54 void _ARMV4_Exception_irq_default( void );
55 
56 void _ARMV4_Exception_fiq_default( void );
57 
58 static inline uint32_t _ARMV4_Status_irq_enable( void )
59 {
60  uint32_t arm_switch_reg;
61  uint32_t psr;
62 
64 
65  __asm__ volatile (
66  ARM_SWITCH_TO_ARM
67  "mrs %[psr], cpsr\n"
68  "bic %[arm_switch_reg], %[psr], #0x80\n"
69  "msr cpsr, %[arm_switch_reg]\n"
70  ARM_SWITCH_BACK
71  : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
72  );
73 
74  return psr;
75 }
76 
77 static inline void _ARMV4_Status_restore( uint32_t psr )
78 {
79  ARM_SWITCH_REGISTERS;
80 
81  __asm__ volatile (
82  ARM_SWITCH_TO_ARM
83  "msr cpsr, %[psr]\n"
84  ARM_SWITCH_BACK
85  : ARM_SWITCH_OUTPUT
86  : [psr] "r" (psr)
87  );
88 
90 }
91 
92 #endif /* ARM_MULTILIB_ARCH_V4 */
93 
94 #ifdef __cplusplus
95 }
96 #endif /* __cplusplus */
97 
98 #endif /* RTEMS_SCORE_ARMV4_H */
void bsp_interrupt_dispatch(void)
Interrupt dispatch.
Definition: irq.c:83
#define RTEMS_COMPILER_MEMORY_BARRIER()
Definition: basedefs.h:77
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
The set of registers that specifies the complete processor state.
Definition: cpu.h:629